1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2019 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32G4xx_HAL_H 22 #define STM32G4xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32g4xx_hal_conf.h" 30 31 /** @addtogroup STM32G4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /* Exported constants --------------------------------------------------------*/ 41 42 /** @defgroup HAL_Exported_Constants HAL Exported Constants 43 * @{ 44 */ 45 46 /** @defgroup HAL_TICK_FREQ Tick Frequency 47 * @{ 48 */ 49 #define HAL_TICK_FREQ_10HZ 100U 50 #define HAL_TICK_FREQ_100HZ 10U 51 #define HAL_TICK_FREQ_1KHZ 1U 52 #define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ 53 54 /** 55 * @} 56 */ 57 58 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 59 * @{ 60 */ 61 62 /** @defgroup SYSCFG_BootMode Boot Mode 63 * @{ 64 */ 65 #define SYSCFG_BOOT_MAINFLASH 0x00000000U 66 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMMEMRMP_MODE_0 67 68 #if defined (FMC_BANK1) 69 #define SYSCFG_BOOT_FMC SYSCFG_MEMMEMRMP_MODE_1 70 #endif /* FMC_BANK1 */ 71 72 #define SYSCFG_BOOT_SRAM (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0) 73 74 #if defined (QUADSPI) 75 #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMMEMRMP_MODE_2 | SYSCFG_MEMMEMRMP_MODE_1) 76 #endif /* QUADSPI */ 77 78 /** 79 * @} 80 */ 81 82 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 83 * @{ 84 */ 85 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 86 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 87 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 88 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 89 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 90 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 91 92 /** 93 * @} 94 */ 95 96 /** @defgroup SYSCFG_CCMSRAMWRP CCM Write protection 97 * @{ 98 */ 99 #define SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */ 100 #define SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */ 101 #define SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */ 102 #define SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */ 103 #define SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */ 104 #define SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */ 105 #define SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */ 106 #define SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */ 107 #define SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */ 108 #define SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */ 109 #define SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */ 110 #define SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */ 111 #define SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */ 112 #define SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */ 113 #define SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */ 114 #define SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */ 115 #define SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */ 116 #define SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */ 117 #define SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */ 118 #define SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */ 119 #define SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */ 120 #define SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */ 121 #define SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */ 122 #define SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */ 123 #define SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */ 124 #define SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */ 125 #define SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */ 126 #define SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */ 127 #define SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */ 128 #define SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */ 129 #define SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */ 130 #define SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */ 131 132 /** 133 * @} 134 */ 135 136 #if defined(VREFBUF) 137 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 138 * @{ 139 */ 140 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */ 141 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */ 142 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */ 143 144 /** 145 * @} 146 */ 147 148 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 149 * @{ 150 */ 151 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 152 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 153 154 /** 155 * @} 156 */ 157 #endif /* VREFBUF */ 158 159 /** @defgroup SYSCFG_flags_definition Flags 160 * @{ 161 */ 162 163 #define SYSCFG_FLAG_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM parity error (first 32kB of SRAM1 + CCM SRAM) */ 164 #define SYSCFG_FLAG_CCMSRAM_BUSY SYSCFG_SCSR_CCMBSY /*!< CCMSRAM busy by erase operation */ 165 166 /** 167 * @} 168 */ 169 170 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 171 * @{ 172 */ 173 174 /** @brief Fast-mode Plus driving capability on a specific GPIO 175 */ 176 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 177 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 178 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) 179 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 180 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ 181 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) 182 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 183 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ 184 185 /** 186 * @} 187 */ 188 189 /** 190 * @} 191 */ 192 193 /** 194 * @} 195 */ 196 197 /* Exported macros -----------------------------------------------------------*/ 198 199 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 200 * @{ 201 */ 202 203 /** @brief Freeze/Unfreeze Peripherals in Debug mode 204 */ 205 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 206 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 207 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 208 #endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ 209 210 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 211 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 212 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 213 #endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ 214 215 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 216 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 217 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 218 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ 219 220 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 221 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 222 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 223 #endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ 224 225 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 226 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 227 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 228 #endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ 229 230 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 231 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 232 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 233 #endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ 234 235 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) 236 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 237 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 238 #endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */ 239 240 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 241 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 242 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 243 #endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ 244 245 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 246 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 247 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 248 #endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ 249 250 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 251 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 252 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 253 #endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ 254 255 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 256 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 257 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 258 #endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ 259 260 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) 261 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 262 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 263 #endif /* DBGMCU_APB1FZR1_DBG_I2C3_STOP */ 264 265 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 266 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 267 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 268 #endif /* DBGMCU_APB1FZR1_DBG_LPTIM1_STOP */ 269 270 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) 271 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 272 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 273 #endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */ 274 275 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) 276 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 277 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 278 #endif /* DBGMCU_APB2FZ_DBG_TIM1_STOP */ 279 280 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) 281 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 282 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 283 #endif /* DBGMCU_APB2FZ_DBG_TIM8_STOP */ 284 285 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) 286 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 287 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 288 #endif /* DBGMCU_APB2FZ_DBG_TIM15_STOP */ 289 290 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) 291 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 292 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 293 #endif /* DBGMCU_APB2FZ_DBG_TIM16_STOP */ 294 295 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) 296 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 297 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 298 #endif /* DBGMCU_APB2FZ_DBG_TIM17_STOP */ 299 300 #if defined(DBGMCU_APB2FZ_DBG_TIM20_STOP) 301 #define __HAL_DBGMCU_FREEZE_TIM20() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP) 302 #define __HAL_DBGMCU_UNFREEZE_TIM20() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP) 303 #endif /* DBGMCU_APB2FZ_DBG_TIM20_STOP */ 304 305 #if defined(DBGMCU_APB2FZ_DBG_HRTIM1_STOP) 306 #define __HAL_DBGMCU_FREEZE_HRTIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP) 307 #define __HAL_DBGMCU_UNFREEZE_HRTIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP) 308 #endif /* DBGMCU_APB2FZ_DBG_HRTIM1_STOP */ 309 310 /** 311 * @} 312 */ 313 314 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 315 * @{ 316 */ 317 318 /** @brief Main Flash memory mapped at 0x00000000. 319 */ 320 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 321 322 /** @brief System Flash memory mapped at 0x00000000. 323 */ 324 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) 325 326 /** @brief Embedded SRAM mapped at 0x00000000. 327 */ 328 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) 329 330 #if defined (FMC_BANK1) 331 /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. 332 */ 333 #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) 334 #endif /* FMC_BANK1 */ 335 336 #if defined (QUADSPI) 337 /** @brief QUADSPI mapped at 0x00000000. 338 */ 339 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) 340 #endif /* QUADSPI */ 341 342 /** 343 * @brief Return the boot mode as configured by user. 344 * @retval The boot mode as configured by user. The returned value can be one 345 * of the following values: 346 * @arg @ref SYSCFG_BOOT_MAINFLASH 347 * @arg @ref SYSCFG_BOOT_SYSTEMFLASH 348 * @arg @ref SYSCFG_BOOT_FMC (*) 349 * @arg @ref SYSCFG_BOOT_QUADSPI (*) 350 * @arg @ref SYSCFG_BOOT_SRAM 351 * @note (*) availability depends on devices 352 */ 353 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 354 355 /** @brief CCMSRAM page write protection enable macro 356 * @param __CCMSRAMWRP__: This parameter can be a value of @ref SYSCFG_CCMSRAMWRP 357 * @note write protection can only be disabled by a system reset 358 * @retval None 359 */ 360 /* Legacy define */ 361 #define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE 362 #define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__) do {assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__)));\ 363 SET_BIT(SYSCFG->SWPR,(__CCMSRAMWRP__));\ 364 }while(0) 365 366 /** @brief CCMSRAM page write protection unlock prior to erase 367 * @note Writing a wrong key reactivates the write protection 368 */ 369 #define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ 370 SYSCFG->SKR = 0x53;\ 371 }while(0) 372 373 /** @brief CCMSRAM erase 374 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end of erase 375 */ 376 #define __HAL_SYSCFG_CCMSRAM_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER) 377 378 /** @brief Floating Point Unit interrupt enable/disable macros 379 * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts 380 */ 381 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 382 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 383 }while(0) 384 385 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 386 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 387 }while(0) 388 389 /** @brief SYSCFG Break ECC lock. 390 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 391 * @note The selected configuration is locked and can be unlocked only by system reset. 392 */ 393 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 394 395 /** @brief SYSCFG Break Cortex-M4 Lockup lock. 396 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 397 * @note The selected configuration is locked and can be unlocked only by system reset. 398 */ 399 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 400 401 /** @brief SYSCFG Break PVD lock. 402 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 403 * @note The selected configuration is locked and can be unlocked only by system reset. 404 */ 405 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 406 407 /** @brief SYSCFG Break SRAM parity lock. 408 * Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM SRAM) signal connection to TIM1/8/15/16/17 Break input. 409 * @note The selected configuration is locked and can be unlocked by system reset. 410 */ 411 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 412 413 /** @brief Check SYSCFG flag is set or not. 414 * @param __FLAG__: specifies the flag to check. 415 * This parameter can be one of the following values: 416 * @arg @ref SYSCFG_FLAG_SRAM_PE SRAM Parity Error Flag 417 * @arg @ref SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing 418 * @retval The new state of __FLAG__ (TRUE or FALSE). 419 */ 420 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\ 421 & (__FLAG__))!= 0U) ? 1U : 0U) 422 423 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 424 */ 425 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 426 427 /** @brief Fast-mode Plus driving capability enable/disable macros 428 * @param __FASTMODEPLUS__: This parameter can be a value of : 429 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 430 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 431 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 432 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 433 */ 434 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 435 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 436 }while(0) 437 438 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 439 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 440 }while(0) 441 442 /** 443 * @} 444 */ 445 446 /* Private macros ------------------------------------------------------------*/ 447 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 448 * @{ 449 */ 450 451 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 452 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 453 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 454 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 455 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 456 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 457 458 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 459 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 460 ((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY) || \ 461 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 462 463 #if (CCMSRAM_SIZE == 0x00008000UL) || (CCMSRAM_SIZE == 0x00004000UL) 464 #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) ((__PAGE__) > 0U) 465 #elif (CCMSRAM_SIZE == 0x00002800UL) 466 #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU)) 467 #endif /* CCMSRAM_SIZE */ 468 469 #if defined(VREFBUF) 470 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 471 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ 472 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2)) 473 474 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 475 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 476 477 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 478 #endif /* VREFBUF */ 479 480 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) 481 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 482 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 483 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 484 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 485 #elif defined(SYSCFG_FASTMODEPLUS_PB8) 486 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 487 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 488 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) 489 #elif defined(SYSCFG_FASTMODEPLUS_PB9) 490 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 491 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 492 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 493 #else 494 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 495 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) 496 #endif /* SYSCFG_FASTMODEPLUS_PB */ 497 /** 498 * @} 499 */ 500 501 /** @defgroup HAL_Private_Macros HAL Private Macros 502 * @{ 503 */ 504 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 505 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 506 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 507 /** 508 * @} 509 */ 510 511 /* Exported functions --------------------------------------------------------*/ 512 513 /** @addtogroup HAL_Exported_Functions 514 * @{ 515 */ 516 517 /** @addtogroup HAL_Exported_Functions_Group1 518 * @{ 519 */ 520 /* Initialization and Configuration functions ******************************/ 521 HAL_StatusTypeDef HAL_Init(void); 522 HAL_StatusTypeDef HAL_DeInit(void); 523 void HAL_MspInit(void); 524 void HAL_MspDeInit(void); 525 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 526 527 /** 528 * @} 529 */ 530 531 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions 532 * @{ 533 */ 534 535 /* Peripheral Control functions ************************************************/ 536 void HAL_IncTick(void); 537 void HAL_Delay(uint32_t Delay); 538 uint32_t HAL_GetTick(void); 539 uint32_t HAL_GetTickPrio(void); 540 HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); 541 uint32_t HAL_GetTickFreq(void); 542 void HAL_SuspendTick(void); 543 void HAL_ResumeTick(void); 544 uint32_t HAL_GetHalVersion(void); 545 uint32_t HAL_GetREVID(void); 546 uint32_t HAL_GetDEVID(void); 547 548 /** 549 * @} 550 */ 551 552 /** @addtogroup HAL_Exported_Functions_Group3 553 * @{ 554 */ 555 556 /* DBGMCU Peripheral Control functions *****************************************/ 557 void HAL_DBGMCU_EnableDBGSleepMode(void); 558 void HAL_DBGMCU_DisableDBGSleepMode(void); 559 void HAL_DBGMCU_EnableDBGStopMode(void); 560 void HAL_DBGMCU_DisableDBGStopMode(void); 561 void HAL_DBGMCU_EnableDBGStandbyMode(void); 562 void HAL_DBGMCU_DisableDBGStandbyMode(void); 563 564 /** 565 * @} 566 */ 567 568 /* Exported variables ---------------------------------------------------------*/ 569 /** @addtogroup HAL_Exported_Variables 570 * @{ 571 */ 572 extern __IO uint32_t uwTick; 573 extern uint32_t uwTickPrio; 574 extern uint32_t uwTickFreq; 575 /** 576 * @} 577 */ 578 579 /** @addtogroup HAL_Exported_Functions_Group4 580 * @{ 581 */ 582 583 /* SYSCFG Control functions ****************************************************/ 584 void HAL_SYSCFG_CCMSRAMErase(void); 585 void HAL_SYSCFG_EnableMemorySwappingBank(void); 586 void HAL_SYSCFG_DisableMemorySwappingBank(void); 587 588 #if defined(VREFBUF) 589 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 590 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 591 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 592 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 593 void HAL_SYSCFG_DisableVREFBUF(void); 594 #endif /* VREFBUF */ 595 596 void HAL_SYSCFG_EnableIOSwitchBooster(void); 597 void HAL_SYSCFG_DisableIOSwitchBooster(void); 598 void HAL_SYSCFG_EnableIOSwitchVDD(void); 599 void HAL_SYSCFG_DisableIOSwitchVDD(void); 600 601 void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page); 602 603 /** 604 * @} 605 */ 606 607 /** 608 * @} 609 */ 610 611 /** 612 * @} 613 */ 614 615 /** 616 * @} 617 */ 618 619 #ifdef __cplusplus 620 } 621 #endif 622 623 #endif /* STM32G4xx_HAL_H */ 624 625
