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Searched refs:SPI_CR1_CSTART (Results 1 – 25 of 68) sorted by relevance

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/hal_stm32-3.4.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_i2s.c855 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2S_Transmit()
976 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2S_Receive()
1093 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2SEx_TransmitReceive()
1246 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2S_Transmit_IT()
1321 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2S_Receive_IT()
1399 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2SEx_TransmitReceive_IT()
1486 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2S_Transmit_DMA()
1572 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2S_Receive_DMA()
1681 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2SEx_TransmitReceive_DMA()
1708 if (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) == 0UL) in HAL_I2S_DMAPause()
[all …]
Dstm32h7xx_hal_spi.c884 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Transmit()
1106 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Receive()
1307 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_TransmitReceive()
1535 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Transmit_IT()
1627 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Receive_IT()
1751 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_TransmitReceive_IT()
2104 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Transmit_DMA()
2255 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Receive_DMA()
2439 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_TransmitReceive_DMA()
2477 if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) in HAL_SPI_Abort()
[all …]
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_i2s.c846 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2S_Transmit()
967 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2S_Receive()
1084 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2SEx_TransmitReceive()
1237 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2S_Transmit_IT()
1312 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2S_Receive_IT()
1390 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2SEx_TransmitReceive_IT()
1520 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2S_Transmit_DMA()
1649 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2S_Receive_DMA()
1844 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); in HAL_I2SEx_TransmitReceive_DMA()
1871 if (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) == 0UL) in HAL_I2S_DMAPause()
[all …]
Dstm32h5xx_hal_spi.c898 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Transmit()
1120 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Receive()
1321 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_TransmitReceive()
1549 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Transmit_IT()
1641 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Receive_IT()
1764 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_TransmitReceive_IT()
1965 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Transmit_DMA()
2163 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Receive_DMA()
2440 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_TransmitReceive_DMA()
2478 if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) in HAL_SPI_Abort()
[all …]
/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_spi.c898 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Transmit()
1120 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Receive()
1321 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_TransmitReceive()
1549 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Transmit_IT()
1641 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Receive_IT()
1764 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_TransmitReceive_IT()
1965 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Transmit_DMA()
2163 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Receive_DMA()
2440 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_TransmitReceive_DMA()
2478 if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) in HAL_SPI_Abort()
[all …]
/hal_stm32-3.4.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_spi.c884 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Transmit()
1106 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Receive()
1307 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_TransmitReceive()
1535 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Transmit_IT()
1627 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Receive_IT()
1751 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_TransmitReceive_IT()
2104 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Transmit_DMA()
2255 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_Receive_DMA()
2449 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); in HAL_SPI_TransmitReceive_DMA()
2487 if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) in HAL_SPI_Abort()
[all …]
/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_spi.h1049 SET_BIT(SPIx->CR1, SPI_CR1_CSTART); in LL_SPI_StartMasterTransfer()
1060 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL); in LL_SPI_IsActiveMasterTransfer()
/hal_stm32-3.4.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_spi.h999 SET_BIT(SPIx->CR1, SPI_CR1_CSTART); in LL_SPI_StartMasterTransfer()
1010 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL); in LL_SPI_IsActiveMasterTransfer()
/hal_stm32-3.4.0/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_spi.h999 SET_BIT(SPIx->CR1, SPI_CR1_CSTART); in LL_SPI_StartMasterTransfer()
1010 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL); in LL_SPI_IsActiveMasterTransfer()
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_spi.h962 SET_BIT(SPIx->CR1, SPI_CR1_CSTART); in LL_SPI_StartMasterTransfer()
973 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL); in LL_SPI_IsActiveMasterTransfer()
/hal_stm32-3.4.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h12937 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master tran… macro
Dstm32h562xx.h19908 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master tran… macro
Dstm32h563xx.h22040 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master tran… macro
Dstm32h573xx.h22641 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master tran… macro
/hal_stm32-3.4.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h20100 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master tran… macro
Dstm32u545xx.h20610 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master tran… macro
Dstm32u575xx.h23112 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master tran… macro
/hal_stm32-3.4.0/stm32cube/stm32h7xx/soc/
Dstm32h7a3xxq.h16667 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer … macro
Dstm32h7a3xx.h16655 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer … macro
Dstm32h7b0xx.h17135 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer … macro
Dstm32h7b0xxq.h17147 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer … macro
Dstm32h7b3xx.h17142 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer … macro
Dstm32h7b3xxq.h17154 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer … macro
Dstm32h742xx.h17502 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer … macro
Dstm32h730xx.h18699 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer … macro

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