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Searched refs:RCC_PLL2_DIVP (Results 1 – 8 of 8) sorted by relevance

/hal_stm32-3.4.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_rcc_ex.c120 __HAL_RCC_PLL2CLKOUT_DISABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR); in RCCEx_PLL2_Config()
221 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR); in RCCEx_PLL2_Config()
226 __HAL_RCC_PLL2CLKOUT_DISABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR); in RCCEx_PLL2_Config()
/hal_stm32-3.4.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_rcc_ex.h471 #define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN macro
3965 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \
/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_rcc_ex.h480 #define RCC_PLL2_DIVP RCC_PLL2CFGR_PLL2PEN macro
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_rcc_ex.h540 #define RCC_PLL2_DIVP RCC_PLL2CFGR_PLL2PEN macro
/hal_stm32-3.4.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc_ex.c3756 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); in RCCEx_PLL2_Config()
/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc_ex.c1623 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U) in HAL_RCCEx_GetPLL2ClockFreq()
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc_ex.c2962 if (__HAL_RCC_GET_PLL2_CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U) in HAL_RCCEx_GetPLL2ClockFreq()
/hal_stm32-3.4.0/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_hal_rcc.h868 #define RCC_PLL2_DIVP RCC_PLL2CR_DIVPEN macro