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Searched refs:RCC_CFGR1_SWS_Pos (Results 1 – 12 of 12) sorted by relevance

/hal_stm32-3.4.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h8765 #define RCC_CFGR1_SWS_Pos (3U) macro
8766 #define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018…
8768 #define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008…
8769 #define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010…
Dstm32h562xx.h13103 #define RCC_CFGR1_SWS_Pos (3U) macro
13104 #define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018…
13106 #define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008…
13107 #define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010…
Dstm32h563xx.h15187 #define RCC_CFGR1_SWS_Pos (3U) macro
15188 #define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018…
15190 #define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008…
15191 #define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010…
Dstm32h573xx.h15708 #define RCC_CFGR1_SWS_Pos (3U) macro
15709 #define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018…
15711 #define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008…
15712 #define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010…
/hal_stm32-3.4.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h13900 #define RCC_CFGR1_SWS_Pos (2U) macro
13901 #define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C…
13903 #define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004…
13904 #define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008…
Dstm32u545xx.h14410 #define RCC_CFGR1_SWS_Pos (2U) macro
14411 #define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C…
14413 #define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004…
14414 #define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008…
Dstm32u575xx.h15271 #define RCC_CFGR1_SWS_Pos (2U) macro
15272 #define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C…
15274 #define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004…
15275 #define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008…
Dstm32u585xx.h15830 #define RCC_CFGR1_SWS_Pos (2U) macro
15831 #define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C…
15833 #define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004…
15834 #define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008…
Dstm32u5a5xx.h16856 #define RCC_CFGR1_SWS_Pos (2U) macro
16857 #define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C…
16859 #define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004…
16860 #define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008…
Dstm32u595xx.h16297 #define RCC_CFGR1_SWS_Pos (2U) macro
16298 #define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C…
16300 #define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004…
16301 #define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008…
Dstm32u599xx.h20016 #define RCC_CFGR1_SWS_Pos (2U) macro
20017 #define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C…
20019 #define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004…
20020 #define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008…
Dstm32u5a9xx.h20575 #define RCC_CFGR1_SWS_Pos (2U) macro
20576 #define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C…
20578 #define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004…
20579 #define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008…