RCC_CCIPR2_LPTIM1SEL_Pos (reference) in projects: hal_stm32-3.4.0

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Searched refs:RCC_CCIPR2_LPTIM1SEL_Pos (Results 1 – 5 of 5) sorted by relevance

/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/include/
D	stm32h5xx_ll_rcc.h	797 …E_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0x000000… 798 …E_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIP… 800 …E_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIP… 802 …E_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIP… 803 …E_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIP… 804 …E_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIP… 1073 …RCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0x000000…
/hal_stm32-3.4.0/stm32cube/stm32h5xx/soc/
D	stm32h503xx.h	`9615 #define RCC_CCIPR2_LPTIM1SEL_Pos (8U) macro 9616 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000700… 9618 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000100… 9619 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000200… 9620 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000400…`
D	stm32h562xx.h	`14506 #define RCC_CCIPR2_LPTIM1SEL_Pos (8U) macro 14507 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000700… 14509 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000100… 14510 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000200… 14511 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000400…`
D	stm32h563xx.h	`16599 #define RCC_CCIPR2_LPTIM1SEL_Pos (8U) macro 16600 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000700… 16602 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000100… 16603 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000200… 16604 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000400…`
D	stm32h573xx.h	`17156 #define RCC_CCIPR2_LPTIM1SEL_Pos (8U) macro 17157 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000700… 17159 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000100… 17160 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000200… 17161 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /!< 0x00000400…`

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TraceRecorderSource-3.4.0
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Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
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