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Searched refs:PLL1CFGR (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h3883 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ in LL_RCC_PLL1_ConfigDomain_SYS()
3911 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ in LL_RCC_PLL1_ConfigDomain_SAI()
3939 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ in LL_RCC_PLL1_ConfigDomain_48M()
3959 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source); in LL_RCC_PLL1_SetMainSource()
3974 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC)); in LL_RCC_PLL1_GetMainSource()
4079 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos); in LL_RCC_PLL1_SetDivider()
4090 return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL); in LL_RCC_PLL1_GetDivider()
4101 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); in LL_RCC_PLL1_EnableDomain_SAI()
4116 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); in LL_RCC_PLL1_DisableDomain_SAI()
4127 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == (RCC_PLL1CFGR_PLL1PEN)) ? 1UL : 0UL); in LL_RCC_PLL1_IsEnabledDomain_SAI()
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Dstm32u5xx_hal_rcc.h4359 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__))
4361 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__…
4374 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT…
4381 #define __HAL_RCC_PLL_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN)
4383 #define __HAL_RCC_PLL_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN)
4422 do{ MODIFY_REG(RCC->PLL1CFGR,(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M|\
4443 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLL1SOURCE__) MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1S…
4468 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__))
4478 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC))
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h4205 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); in LL_RCC_PLL1P_Enable()
4217 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); in LL_RCC_PLL1P_Disable()
4228 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); in LL_RCC_PLL1Q_Enable()
4240 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); in LL_RCC_PLL1Q_Disable()
4251 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); in LL_RCC_PLL1R_Enable()
4263 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); in LL_RCC_PLL1R_Disable()
4273 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == RCC_PLL1CFGR_PLL1PEN) ? 1UL : 0UL); in LL_RCC_PLL1P_IsEnabled()
4283 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == RCC_PLL1CFGR_PLL1QEN) ? 1UL : 0UL); in LL_RCC_PLL1Q_IsEnabled()
4293 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == RCC_PLL1CFGR_PLL1REN) ? 1UL : 0UL); in LL_RCC_PLL1R_IsEnabled()
4315 …MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | (PLL1M << RCC_PLL1CF… in LL_RCC_PLL1_ConfigDomain_SYS()
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Dstm32h5xx_hal_rcc.h4502 #define __HAL_RCC_PLL1_CLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__…
4504 #define __HAL_RCC_PLL1_CLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT…
4516 #define __HAL_RCC_GET_PLL1_CLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKO…
4523 #define __HAL_RCC_PLL1_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN)
4525 #define __HAL_RCC_PLL1_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN)
4562 do{ MODIFY_REG(RCC->PLL1CFGR, (RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M), \
4579 #define __HAL_RCC_PLL1_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1S…
4594 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos)
4624 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__))
4636 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
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/hal_stm32-3.4.0/stm32cube/stm32u5xx/soc/
Dsystem_stm32u5xx.c213 RCC->PLL1CFGR = 0U; in SystemInit()
310 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); in SystemCoreClockUpdate()
311 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in SystemCoreClockUpdate()
312 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); in SystemCoreClockUpdate()
Dsystem_stm32u5xx_s.c231 RCC->PLL1CFGR = 0U; in SystemInit()
333 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); in SystemCoreClockUpdate()
334 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in SystemCoreClockUpdate()
335 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); in SystemCoreClockUpdate()
Dstm32u535xx.h895 …__IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register … member
Dstm32u545xx.h961 …__IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register … member
Dstm32u575xx.h961 …__IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register … member
Dstm32u585xx.h1028 …__IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register … member
Dstm32u5a5xx.h1069 …__IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register … member
Dstm32u595xx.h1002 …__IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register … member
Dstm32u599xx.h1183 …__IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register … member
Dstm32u5a9xx.h1250 …__IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register … member
/hal_stm32-3.4.0/stm32cube/stm32h5xx/soc/
Dsystem_stm32h5xx.c226 RCC->PLL1CFGR = 0U; in SystemInit()
345 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); in SystemCoreClockUpdate()
346 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos); in SystemCoreClockUpdate()
347 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); in SystemCoreClockUpdate()
Dsystem_stm32h5xx_s.c239 RCC->PLL1CFGR = 0U; in SystemInit()
359 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); in SystemCoreClockUpdate()
360 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos); in SystemCoreClockUpdate()
361 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); in SystemCoreClockUpdate()
Dstm32h503xx.h716 …__IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register … member
Dstm32h562xx.h921 …__IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register … member
Dstm32h563xx.h1099 …__IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register … member
Dstm32h573xx.h1164 …__IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register … member
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc.c358 CLEAR_REG(RCC->PLL1CFGR); in HAL_RCC_DeInit()
923 …RCC->PLL1CFGR &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1PEN | RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CF… in HAL_RCC_OscConfig()
930 temp1_pllckcfg = RCC->PLL1CFGR; in HAL_RCC_OscConfig()
1402 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); in HAL_RCC_GetSysClockFreq()
1403 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); in HAL_RCC_GetSysClockFreq()
1404 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); in HAL_RCC_GetSysClockFreq()
1572 reg1val = RCC->PLL1CFGR; in HAL_RCC_GetOscConfig()
Dstm32h5xx_hal_rcc_ex.c2791 pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); in HAL_RCCEx_GetPLL1ClockFreq()
2792 pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); in HAL_RCCEx_GetPLL1ClockFreq()
2793 pll1fracen = RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN; in HAL_RCCEx_GetPLL1ClockFreq()
Dstm32h5xx_ll_rcc.c231 CLEAR_REG(RCC->PLL1CFGR); in LL_RCC_DeInit()
/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc.c471 CLEAR_REG(RCC->PLL1CFGR); in HAL_RCC_DeInit()
1279 …RCC->PLL1CFGR &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1PEN | RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CF… in HAL_RCC_OscConfig()
1286 temp1_pllckcfg = RCC->PLL1CFGR; in HAL_RCC_OscConfig()
1784 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); in HAL_RCC_GetSysClockFreq()
1785 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in HAL_RCC_GetSysClockFreq()
1786 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); in HAL_RCC_GetSysClockFreq()
1956 reg1val = RCC->PLL1CFGR; in HAL_RCC_GetOscConfig()
Dstm32u5xx_hal_rcc_ex.c1494 pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); in HAL_RCCEx_GetPLL1ClockFreq()
1495 pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in HAL_RCCEx_GetPLL1ClockFreq()
1496 pll1fracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); in HAL_RCCEx_GetPLL1ClockFreq()