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Searched refs:LPTIM_CFGR2_IN1SEL_Msk (Results 1 – 25 of 66) sorted by relevance

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/hal_stm32-3.4.0/stm32cube/stm32g0xx/soc/
Dstm32g031xx.h7011 #define LPTIM_CFGR2_IN1SEL_Msk (0xFUL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x0000000F */ macro
7012 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< CFGR2[3:0] bits…
Dstm32g041xx.h7315 #define LPTIM_CFGR2_IN1SEL_Msk (0xFUL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x0000000F */ macro
7316 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< CFGR2[3:0] bits…
Dstm32g051xx.h7429 #define LPTIM_CFGR2_IN1SEL_Msk (0xFUL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x0000000F */ macro
7430 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< CFGR2[3:0] bits…
Dstm32g061xx.h7733 #define LPTIM_CFGR2_IN1SEL_Msk (0xFUL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x0000000F */ macro
7734 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< CFGR2[3:0] bits…
Dstm32g081xx.h8117 #define LPTIM_CFGR2_IN1SEL_Msk (0xFUL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x0000000F */ macro
8118 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< CFGR2[3:0] bits…
Dstm32g071xx.h7813 #define LPTIM_CFGR2_IN1SEL_Msk (0xFUL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x0000000F */ macro
7814 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< CFGR2[3:0] bits…
Dstm32g0b1xx.h9397 #define LPTIM_CFGR2_IN1SEL_Msk (0xFUL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x0000000F */ macro
9398 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< CFGR2[3:0] bits…
Dstm32g0c1xx.h9701 #define LPTIM_CFGR2_IN1SEL_Msk (0xFUL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x0000000F */ macro
9702 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< CFGR2[3:0] bits…
/hal_stm32-3.4.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h8178 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003… macro
8179 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0…
Dstm32h562xx.h10864 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003… macro
10865 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0…
Dstm32h563xx.h12948 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003… macro
12949 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0…
Dstm32h573xx.h13359 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003… macro
13360 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0…
/hal_stm32-3.4.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h10912 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003… macro
10913 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0…
Dstm32u545xx.h11312 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003… macro
11313 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0…
Dstm32u575xx.h11935 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003… macro
11936 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0…
/hal_stm32-3.4.0/stm32cube/stm32h7xx/soc/
Dstm32h7a3xxq.h18621 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */ macro
18622 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bit…
Dstm32h7a3xx.h18609 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */ macro
18610 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bit…
Dstm32h7b0xx.h19089 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */ macro
19090 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bit…
Dstm32h7b0xxq.h19101 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */ macro
19102 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bit…
Dstm32h7b3xx.h19096 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */ macro
19097 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bit…
Dstm32h7b3xxq.h19108 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */ macro
19109 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bit…
Dstm32h742xx.h19699 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */ macro
19700 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bit…
Dstm32h730xx.h20767 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */ macro
20768 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bit…
Dstm32h733xx.h20767 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */ macro
20768 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bit…
Dstm32h735xx.h20779 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */ macro
20780 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bit…

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