1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32G0xx_LL_TIM_H
21 #define __STM32G0xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g0xx.h"
29
30 /** @addtogroup STM32G0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #if defined(COMP3)
120 #define TIM_POSITION_BRK_SOURCE \
121 ((Source == LL_TIM_BKIN_SOURCE_BKIN) ? 0U :\
122 (Source == LL_TIM_BKIN_SOURCE_BKCOMP1) ? 1U :\
123 (Source == LL_TIM_BKIN_SOURCE_BKCOMP2) ? 2U :3U)
124 #else
125 #define TIM_POSITION_BRK_SOURCE ((Source >> 1U) & 0x1FUL)
126 #endif
127
128 /* Generic bit definitions for TIMx_AF1 register */
129 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
130 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
131
132
133 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
134 #define DT_DELAY_1 ((uint8_t)0x7F)
135 #define DT_DELAY_2 ((uint8_t)0x3F)
136 #define DT_DELAY_3 ((uint8_t)0x1F)
137 #define DT_DELAY_4 ((uint8_t)0x1F)
138
139 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
140 #define DT_RANGE_1 ((uint8_t)0x00)
141 #define DT_RANGE_2 ((uint8_t)0x80)
142 #define DT_RANGE_3 ((uint8_t)0xC0)
143 #define DT_RANGE_4 ((uint8_t)0xE0)
144
145 /** Legacy definitions for compatibility purpose
146 @cond 0
147 */
148 /**
149 @endcond
150 */
151
152 #define OCREF_CLEAR_SELECT_Pos (16U)
153 #define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x00010000 */
154 /**
155 * @}
156 */
157
158 /* Private macros ------------------------------------------------------------*/
159 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
160 * @{
161 */
162 /** @brief Convert channel id into channel index.
163 * @param __CHANNEL__ This parameter can be one of the following values:
164 * @arg @ref LL_TIM_CHANNEL_CH1
165 * @arg @ref LL_TIM_CHANNEL_CH1N
166 * @arg @ref LL_TIM_CHANNEL_CH2
167 * @arg @ref LL_TIM_CHANNEL_CH2N
168 * @arg @ref LL_TIM_CHANNEL_CH3
169 * @arg @ref LL_TIM_CHANNEL_CH3N
170 * @arg @ref LL_TIM_CHANNEL_CH4
171 * @arg @ref LL_TIM_CHANNEL_CH5
172 * @arg @ref LL_TIM_CHANNEL_CH6
173 * @retval none
174 */
175 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
176 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
177 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
178 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
183 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
184
185 /** @brief Calculate the deadtime sampling period(in ps).
186 * @param __TIMCLK__ timer input clock frequency (in Hz).
187 * @param __CKD__ This parameter can be one of the following values:
188 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
189 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
190 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
191 * @retval none
192 */
193 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
194 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
195 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
196 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
197 /**
198 * @}
199 */
200
201
202 /* Exported types ------------------------------------------------------------*/
203 #if defined(USE_FULL_LL_DRIVER)
204 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
205 * @{
206 */
207
208 /**
209 * @brief TIM Time Base configuration structure definition.
210 */
211 typedef struct
212 {
213 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
214 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
215
216 This feature can be modified afterwards using unitary function
217 @ref LL_TIM_SetPrescaler().*/
218
219 uint32_t CounterMode; /*!< Specifies the counter mode.
220 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
221
222 This feature can be modified afterwards using unitary function
223 @ref LL_TIM_SetCounterMode().*/
224
225 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
226 Auto-Reload Register at the next update event.
227 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
228 Some timer instances may support 32 bits counters. In that case this parameter must
229 be a number between 0x0000 and 0xFFFFFFFF.
230
231 This feature can be modified afterwards using unitary function
232 @ref LL_TIM_SetAutoReload().*/
233
234 uint32_t ClockDivision; /*!< Specifies the clock division.
235 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
236
237 This feature can be modified afterwards using unitary function
238 @ref LL_TIM_SetClockDivision().*/
239
240 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
241 reaches zero, an update event is generated and counting restarts
242 from the RCR value (N).
243 This means in PWM mode that (N+1) corresponds to:
244 - the number of PWM periods in edge-aligned mode
245 - the number of half PWM period in center-aligned mode
246 GP timers: this parameter must be a number between Min_Data = 0x00 and
247 Max_Data = 0xFF.
248 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
249 Max_Data = 0xFFFF.
250
251 This feature can be modified afterwards using unitary function
252 @ref LL_TIM_SetRepetitionCounter().*/
253 } LL_TIM_InitTypeDef;
254
255 /**
256 * @brief TIM Output Compare configuration structure definition.
257 */
258 typedef struct
259 {
260 uint32_t OCMode; /*!< Specifies the output mode.
261 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
262
263 This feature can be modified afterwards using unitary function
264 @ref LL_TIM_OC_SetMode().*/
265
266 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
267 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
268
269 This feature can be modified afterwards using unitary functions
270 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
271
272 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
273 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
274
275 This feature can be modified afterwards using unitary functions
276 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
277
278 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
279 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
280
281 This feature can be modified afterwards using unitary function
282 LL_TIM_OC_SetCompareCHx (x=1..6).*/
283
284 uint32_t OCPolarity; /*!< Specifies the output polarity.
285 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
286
287 This feature can be modified afterwards using unitary function
288 @ref LL_TIM_OC_SetPolarity().*/
289
290 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
291 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
292
293 This feature can be modified afterwards using unitary function
294 @ref LL_TIM_OC_SetPolarity().*/
295
296
297 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
298 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
299
300 This feature can be modified afterwards using unitary function
301 @ref LL_TIM_OC_SetIdleState().*/
302
303 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
304 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
305
306 This feature can be modified afterwards using unitary function
307 @ref LL_TIM_OC_SetIdleState().*/
308 } LL_TIM_OC_InitTypeDef;
309
310 /**
311 * @brief TIM Input Capture configuration structure definition.
312 */
313
314 typedef struct
315 {
316
317 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
318 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
319
320 This feature can be modified afterwards using unitary function
321 @ref LL_TIM_IC_SetPolarity().*/
322
323 uint32_t ICActiveInput; /*!< Specifies the input.
324 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
325
326 This feature can be modified afterwards using unitary function
327 @ref LL_TIM_IC_SetActiveInput().*/
328
329 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
330 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
331
332 This feature can be modified afterwards using unitary function
333 @ref LL_TIM_IC_SetPrescaler().*/
334
335 uint32_t ICFilter; /*!< Specifies the input capture filter.
336 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
337
338 This feature can be modified afterwards using unitary function
339 @ref LL_TIM_IC_SetFilter().*/
340 } LL_TIM_IC_InitTypeDef;
341
342
343 /**
344 * @brief TIM Encoder interface configuration structure definition.
345 */
346 typedef struct
347 {
348 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
349 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
350
351 This feature can be modified afterwards using unitary function
352 @ref LL_TIM_SetEncoderMode().*/
353
354 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
355 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
356
357 This feature can be modified afterwards using unitary function
358 @ref LL_TIM_IC_SetPolarity().*/
359
360 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
361 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
362
363 This feature can be modified afterwards using unitary function
364 @ref LL_TIM_IC_SetActiveInput().*/
365
366 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
367 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
368
369 This feature can be modified afterwards using unitary function
370 @ref LL_TIM_IC_SetPrescaler().*/
371
372 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
373 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
374
375 This feature can be modified afterwards using unitary function
376 @ref LL_TIM_IC_SetFilter().*/
377
378 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
379 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
380
381 This feature can be modified afterwards using unitary function
382 @ref LL_TIM_IC_SetPolarity().*/
383
384 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
385 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
386
387 This feature can be modified afterwards using unitary function
388 @ref LL_TIM_IC_SetActiveInput().*/
389
390 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
391 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
392
393 This feature can be modified afterwards using unitary function
394 @ref LL_TIM_IC_SetPrescaler().*/
395
396 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
397 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
398
399 This feature can be modified afterwards using unitary function
400 @ref LL_TIM_IC_SetFilter().*/
401
402 } LL_TIM_ENCODER_InitTypeDef;
403
404 /**
405 * @brief TIM Hall sensor interface configuration structure definition.
406 */
407 typedef struct
408 {
409
410 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
411 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
412
413 This feature can be modified afterwards using unitary function
414 @ref LL_TIM_IC_SetPolarity().*/
415
416 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
417 Prescaler must be set to get a maximum counter period longer than the
418 time interval between 2 consecutive changes on the Hall inputs.
419 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
420
421 This feature can be modified afterwards using unitary function
422 @ref LL_TIM_IC_SetPrescaler().*/
423
424 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
425 This parameter can be a value of
426 @ref TIM_LL_EC_IC_FILTER.
427
428 This feature can be modified afterwards using unitary function
429 @ref LL_TIM_IC_SetFilter().*/
430
431 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
432 A positive pulse (TRGO event) is generated with a programmable delay every time
433 a change occurs on the Hall inputs.
434 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
435
436 This feature can be modified afterwards using unitary function
437 @ref LL_TIM_OC_SetCompareCH2().*/
438 } LL_TIM_HALLSENSOR_InitTypeDef;
439
440 /**
441 * @brief BDTR (Break and Dead Time) structure definition
442 */
443 typedef struct
444 {
445 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
446 This parameter can be a value of @ref TIM_LL_EC_OSSR
447
448 This feature can be modified afterwards using unitary function
449 @ref LL_TIM_SetOffStates()
450
451 @note This bit-field cannot be modified as long as LOCK level 2 has been
452 programmed. */
453
454 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
455 This parameter can be a value of @ref TIM_LL_EC_OSSI
456
457 This feature can be modified afterwards using unitary function
458 @ref LL_TIM_SetOffStates()
459
460 @note This bit-field cannot be modified as long as LOCK level 2 has been
461 programmed. */
462
463 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
464 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
465
466 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
467 register has been written, their content is frozen until the next reset.*/
468
469 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
470 switching-on of the outputs.
471 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
472
473 This feature can be modified afterwards using unitary function
474 @ref LL_TIM_OC_SetDeadTime()
475
476 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
477 programmed. */
478
479 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
480 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
481
482 This feature can be modified afterwards using unitary functions
483 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
484
485 @note This bit-field can not be modified as long as LOCK level 1 has been
486 programmed. */
487
488 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
489 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
490
491 This feature can be modified afterwards using unitary function
492 @ref LL_TIM_ConfigBRK()
493
494 @note This bit-field can not be modified as long as LOCK level 1 has been
495 programmed. */
496
497 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
498 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
499
500 This feature can be modified afterwards using unitary function
501 @ref LL_TIM_ConfigBRK()
502
503 @note This bit-field can not be modified as long as LOCK level 1 has been
504 programmed. */
505
506 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
507 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
508
509 This feature can be modified afterwards using unitary functions
510 @ref LL_TIM_ConfigBRK()
511
512 @note Bidirectional break input is only supported by advanced timers instances.
513
514 @note This bit-field can not be modified as long as LOCK level 1 has been
515 programmed. */
516
517 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
518 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
519
520 This feature can be modified afterwards using unitary functions
521 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
522
523 @note This bit-field can not be modified as long as LOCK level 1 has been
524 programmed. */
525
526 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
527 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
528
529 This feature can be modified afterwards using unitary function
530 @ref LL_TIM_ConfigBRK2()
531
532 @note This bit-field can not be modified as long as LOCK level 1 has been
533 programmed. */
534
535 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
536 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
537
538 This feature can be modified afterwards using unitary function
539 @ref LL_TIM_ConfigBRK2()
540
541 @note This bit-field can not be modified as long as LOCK level 1 has been
542 programmed. */
543
544 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
545 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
546
547 This feature can be modified afterwards using unitary functions
548 @ref LL_TIM_ConfigBRK2()
549
550 @note Bidirectional break input is only supported by advanced timers instances.
551
552 @note This bit-field can not be modified as long as LOCK level 1 has been
553 programmed. */
554
555 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
556 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
557
558 This feature can be modified afterwards using unitary functions
559 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
560
561 @note This bit-field can not be modified as long as LOCK level 1 has been
562 programmed. */
563 } LL_TIM_BDTR_InitTypeDef;
564
565 /**
566 * @}
567 */
568 #endif /* USE_FULL_LL_DRIVER */
569
570 /* Exported constants --------------------------------------------------------*/
571 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
572 * @{
573 */
574
575 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
576 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
577 * @{
578 */
579 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
580 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
581 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
582 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
583 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
584 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
585 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
586 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
587 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
588 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
589 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
590 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
591 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
592 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
593 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
594 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
595 /**
596 * @}
597 */
598
599 #if defined(USE_FULL_LL_DRIVER)
600 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
601 * @{
602 */
603 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
604 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
605 /**
606 * @}
607 */
608
609 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
610 * @{
611 */
612 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
613 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
614 /**
615 * @}
616 */
617
618 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
619 * @{
620 */
621 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
622 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
623 /**
624 * @}
625 */
626 #endif /* USE_FULL_LL_DRIVER */
627
628 /** @defgroup TIM_LL_EC_IT IT Defines
629 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
630 * @{
631 */
632 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
633 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
634 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
635 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
636 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
637 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
638 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
639 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
640 /**
641 * @}
642 */
643
644 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
645 * @{
646 */
647 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
648 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
649 /**
650 * @}
651 */
652
653 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
654 * @{
655 */
656 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
657 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
658 /**
659 * @}
660 */
661
662 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
663 * @{
664 */
665 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
666 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
667 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
668 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
669 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
670 /**
671 * @}
672 */
673
674 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
675 * @{
676 */
677 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
678 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
679 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
680 /**
681 * @}
682 */
683
684 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
685 * @{
686 */
687 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
688 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
689 /**
690 * @}
691 */
692
693 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
694 * @{
695 */
696 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
697 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
703 * @{
704 */
705 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
706 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
707 /**
708 * @}
709 */
710
711 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
712 * @{
713 */
714 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
715 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
716 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
717 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
718 /**
719 * @}
720 */
721
722 /** @defgroup TIM_LL_EC_CHANNEL Channel
723 * @{
724 */
725 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
726 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
727 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
728 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
729 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
730 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
731 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
732 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
733 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
734 /**
735 * @}
736 */
737
738 #if defined(USE_FULL_LL_DRIVER)
739 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
740 * @{
741 */
742 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
743 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
744 /**
745 * @}
746 */
747 #endif /* USE_FULL_LL_DRIVER */
748
749 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
750 * @{
751 */
752 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
753 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
754 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
755 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
756 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
757 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
758 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
759 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
760 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
761 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
762 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
763 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
764 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
765 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
766 /**
767 * @}
768 */
769
770 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
771 * @{
772 */
773 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
774 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
775 /**
776 * @}
777 */
778
779 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
780 * @{
781 */
782 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
783 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
784 /**
785 * @}
786 */
787
788 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
789 * @{
790 */
791 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
792 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
793 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
794 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
795 /**
796 * @}
797 */
798
799 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
800 * @{
801 */
802 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
803 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
804 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
805 /**
806 * @}
807 */
808
809 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
810 * @{
811 */
812 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
813 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
814 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
815 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
816 /**
817 * @}
818 */
819
820 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
821 * @{
822 */
823 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
824 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
825 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
826 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
827 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
828 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
829 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
830 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
831 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
832 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
833 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
834 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
835 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
836 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
837 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
838 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
839 /**
840 * @}
841 */
842
843 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
844 * @{
845 */
846 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
847 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
848 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
849 /**
850 * @}
851 */
852
853 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
854 * @{
855 */
856 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
857 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
858 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
859 /**
860 * @}
861 */
862
863 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
864 * @{
865 */
866 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
867 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
868 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
869 /**
870 * @}
871 */
872
873 /** @defgroup TIM_LL_EC_TRGO Trigger Output
874 * @{
875 */
876 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
877 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
878 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
879 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
880 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
881 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
882 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
883 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
884 /**
885 * @}
886 */
887
888 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
889 * @{
890 */
891 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
892 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
893 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
894 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
895 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
896 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
897 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
898 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
899 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
900 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
901 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
902 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
903 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
904 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
905 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
906 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
907 /**
908 * @}
909 */
910
911 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
912 * @{
913 */
914 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
915 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
916 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
917 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
918 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
919 /**
920 * @}
921 */
922
923 /** @defgroup TIM_LL_EC_TS Trigger Selection
924 * @{
925 */
926 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
927 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
928 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
929 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
930 #if defined(USB_BASE)
931 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
932 #endif /* USB_BASE */
933 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
934 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
935 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
936 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
937 /**
938 * @}
939 */
940
941 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
942 * @{
943 */
944 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
945 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
946 /**
947 * @}
948 */
949
950 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
951 * @{
952 */
953 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
954 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
955 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
956 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
957 /**
958 * @}
959 */
960
961 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
962 * @{
963 */
964 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
965 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
966 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
967 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
968 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
969 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
970 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
971 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
972 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
973 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
974 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
975 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
976 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
977 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
978 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
979 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
980 /**
981 * @}
982 */
983
984 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
985 * @{
986 */
987 #define LL_TIM_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
988 #if defined(COMP1) && defined(COMP2)
989 #define LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
990 #define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
991 #endif /* COMP1 && COMP2 */
992 #if defined(COMP3)
993 #define LL_TIM_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP3_OUT */
994 #endif /* COMP3 */
995 #define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */
996 #define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */
997 #define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */
998 #define LL_TIM_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
999 #define LL_TIM_ETRSOURCE_MCO TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to MCO */
1000 #define LL_TIM_ETRSOURCE_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MCO2 */
1001 /**
1002 * @}
1003 */
1004
1005 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1006 * @{
1007 */
1008 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1009 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1010 /**
1011 * @}
1012 */
1013
1014 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1015 * @{
1016 */
1017 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1018 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1019 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1020 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1021 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1022 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1023 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1024 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1025 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1026 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1027 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1028 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1029 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1030 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1031 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1032 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1033 /**
1034 * @}
1035 */
1036
1037 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1038 * @{
1039 */
1040 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1041 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1042 /**
1043 * @}
1044 */
1045
1046 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1047 * @{
1048 */
1049 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1050 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1051 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1052 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1053 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1054 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1055 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1056 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1057 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1058 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1059 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1060 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1061 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1062 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1063 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1064 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1065 /**
1066 * @}
1067 */
1068
1069 /** @defgroup TIM_LL_EC_OSSI OSSI
1070 * @{
1071 */
1072 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1073 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1074 /**
1075 * @}
1076 */
1077
1078 /** @defgroup TIM_LL_EC_OSSR OSSR
1079 * @{
1080 */
1081 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1082 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1083 /**
1084 * @}
1085 */
1086
1087 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1088 * @{
1089 */
1090 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1091 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1092 /**
1093 * @}
1094 */
1095
1096 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1097 * @{
1098 */
1099 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1100 #if defined(COMP1) && defined(COMP2)
1101 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1102 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1103 #endif /* COMP1 && COMP2 */
1104 #if defined(COMP3)
1105 #define LL_TIM_BKIN_SOURCE_BKCOMP3 TIM1_AF1_BKCMP3E /*!< internal signal: COMP3 output */
1106 #endif /* COMP3 */
1107 /**
1108 * @}
1109 */
1110
1111 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1112 * @{
1113 */
1114 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1115 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1116 /**
1117 * @}
1118 */
1119
1120 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1121 * @{
1122 */
1123 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1124 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1125 /**
1126 * @}
1127 */
1128
1129 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1130 * @{
1131 */
1132 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1133 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1134 /**
1135 * @}
1136 */
1137
1138 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1139 * @{
1140 */
1141 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1142 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1143 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1144 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1145 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1146 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1147 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1148 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1149 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1150 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1151 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1152 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1153 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1154 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1155 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1156 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1157 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1158 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1159 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
1160 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1161 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1162 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1163 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1164 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1165 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1166 /**
1167 * @}
1168 */
1169
1170 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1171 * @{
1172 */
1173 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1174 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1175 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1176 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1177 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1178 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1179 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1180 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1181 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1182 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1183 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1184 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1185 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1186 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1187 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1188 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1189 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1190 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1191 /**
1192 * @}
1193 */
1194
1195 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
1196 * @{
1197 */
1198 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
1199 #if defined(COMP1)
1200 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */
1201 #endif /* COMP1 */
1202 /**
1203 * @}
1204 */
1205
1206 /** @defgroup TIM_LL_EC_TIM1_TI2_RMP TIM1 Timer Input Ch2 Remap
1207 * @{
1208 */
1209 #define LL_TIM_TIM1_TI2_RMP_GPIO 0x00000000U /*!< TIM1 input 2 is connected to GPIO */
1210 #if defined(COMP2)
1211 #define LL_TIM_TIM1_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM1 input 2 is connected to COMP2_OUT */
1212 #endif /* COMP2 */
1213 /**
1214 * @}
1215 */
1216
1217 /** @defgroup TIM_LL_EC_TIM1_TI3_RMP TIM1 Timer Input Ch3 Remap
1218 * @{
1219 */
1220 #define LL_TIM_TIM1_TI3_RMP_GPIO 0x00000000U /*!< TIM1 input 3 is connected to GPIO */
1221 #if defined(COMP3)
1222 #define LL_TIM_TIM1_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM1 input 3 is connected to COMP3_OUT */
1223 #endif /* COMP3 */
1224 /**
1225 * @}
1226 */
1227
1228 #if defined(TIM2)
1229 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 Timer Input Ch1 Remap
1230 * @{
1231 */
1232 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U /*!< TIM2 input 1 is connected to GPIO */
1233 #define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */
1234 /**
1235 * @}
1236 */
1237
1238 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 Timer Input Ch2 Remap
1239 * @{
1240 */
1241 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U /*!< TIM2 input 2 is connected to GPIO */
1242 #define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP2_OUT */
1243 /**
1244 * @}
1245 */
1246
1247 /** @defgroup TIM_LL_EC_TIM2_TI3_RMP TIM2 Timer Input Ch3 Remap
1248 * @{
1249 */
1250 #define LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U /*!< TIM2 input 3 is connected to GPIO */
1251 #if defined(COMP3)
1252 #define LL_TIM_TIM2_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP3_OUT */
1253 #endif /* COMP3 */
1254 /**
1255 * @}
1256 */
1257 #endif /* TIM2 */
1258
1259 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
1260 * @{
1261 */
1262 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
1263 #if defined(COMP1)
1264 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */
1265 #endif /* COMP1 */
1266 /**
1267 * @}
1268 */
1269
1270 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 Timer Input Ch2 Remap
1271 * @{
1272 */
1273 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U /*!< TIM3 input 2 is connected to GPIO */
1274 #if defined(COMP2)
1275 #define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP2_OUT */
1276 #endif /* COMP2 */
1277 /**
1278 * @}
1279 */
1280
1281 /** @defgroup TIM_LL_EC_TIM3_TI3_RMP TIM3 Timer Input Ch3 Remap
1282 * @{
1283 */
1284 #define LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U /*!< TIM3 input 3 is connected to GPIO */
1285 #if defined(COMP3)
1286 #define LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */
1287 #endif /* COMP3 */
1288 /**
1289 * @}
1290 */
1291
1292 #if defined(TIM4)
1293 /** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 Timer Input Ch1 Remap
1294 * @{
1295 */
1296 #define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U /*!< TIM4 input 1 is connected to GPIO */
1297 #if defined(COMP1)
1298 #define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */
1299 #endif /* COMP1 */
1300 /**
1301 * @}
1302 */
1303
1304 /** @defgroup TIM_LL_EC_TIM4_TI2_RMP TIM4 Timer Input Ch2 Remap
1305 * @{
1306 */
1307 #define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U /*!< TIM4 input 2 is connected to GPIO */
1308 #if defined(COMP2)
1309 #define LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP2_OUT */
1310 #endif /* COMP2 */
1311 /**
1312 * @}
1313 */
1314
1315 /** @defgroup TIM_LL_EC_TIM4_TI3_RMP TIM4 Timer Input Ch3 Remap
1316 * @{
1317 */
1318 #define LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U /*!< TIM4 input 3 is connected to GPIO */
1319 #if defined(COMP3)
1320 #define LL_TIM_TIM4_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP3_OUT */
1321 #endif /* COMP3 */
1322 /**
1323 * @}
1324 */
1325 #endif /* TIM4 */
1326
1327 /** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input Ch1 Remap
1328 * @{
1329 */
1330 #define LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000U /*!< TIM14 input 1 is connected to GPIO */
1331 #define LL_TIM_TIM14_TI1_RMP_RTC_CLK TIM_TISEL_TI1SEL_0 /*!< TIM14 input 1 is connected to RTC clock */
1332 #define LL_TIM_TIM14_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /*!< TIM14 input 1 is connected to HSE/32 clock */
1333 #define LL_TIM_TIM14_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM14 input 1 is connected to MCO */
1334 #define LL_TIM_TIM14_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM14 input 1 is connected to MCO2 */
1335 /**
1336 * @}
1337 */
1338
1339 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
1340 * @{
1341 */
1342 #if defined(TIM15)
1343 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
1344 #if defined(TIM2)
1345 #define LL_TIM_TIM15_TI1_RMP_TIM2_IC1 TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to TIM2 input 1 */
1346 #endif /* TIM2 */
1347 #if defined(TIM3)
1348 #define LL_TIM_TIM15_TI1_RMP_TIM3_IC1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to TIM3 input 1 */
1349 #endif /* TIM3 */
1350 #endif /* TIM15 */
1351 /**
1352 * @}
1353 */
1354
1355 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
1356 * @{
1357 */
1358 #if defined(TIM15)
1359 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
1360 #if defined(TIM2)
1361 #define LL_TIM_TIM15_TI2_RMP_TIM2_IC2 TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to TIM2 input 2 */
1362 #endif /* TIM2 */
1363 #if defined(TIM3)
1364 #define LL_TIM_TIM15_TI2_RMP_TIM3_IC2 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 2 is connected to TIM3 input 2 */
1365 #endif /* TIM3 */
1366 #endif /* TIM15 */
1367 /**
1368 * @}
1369 */
1370
1371 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1372 * @{
1373 */
1374 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
1375 #define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to LSI */
1376 #define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to LSE */
1377 #define LL_TIM_TIM16_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to RTC_WAKEUP */
1378 #define LL_TIM_TIM16_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to MCO2 */
1379 /**
1380 * @}
1381 */
1382
1383 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1384 * @{
1385 */
1386 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
1387 #define LL_TIM_TIM17_TI1_RMP_HSI48 TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to HSI48/256 */
1388 #define LL_TIM_TIM17_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to HSE/32 clock */
1389 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to MCO */
1390 #define LL_TIM_TIM17_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to MCO2 */
1391 /**
1392 * @}
1393 */
1394
1395 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1396 * @{
1397 */
1398 #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk /*!< OCREF_CLR_INT is connected to ETRF */
1399 #if defined(COMP1) && defined(COMP2)
1400 #define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
1401 #if defined(COMP3)
1402 #define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_OR1_OCREF_CLR_0 /*!< OCREF clear input is connected to COMP2_OUT */
1403 #define LL_TIM_OCREF_CLR_INT_COMP3 TIM1_OR1_OCREF_CLR_1 /*!< OCREF clear input is connected to COMP3_OUT */
1404 #else
1405 #define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_OR1_OCREF_CLR /*!< OCREF clear input is connected to COMP2_OUT */
1406 #endif /* COMP3 */
1407 #endif /* COMP1 & COMP2 */
1408 /**
1409 * @}
1410 */
1411
1412 /** Legacy definitions for compatibility purpose
1413 @cond 0
1414 */
1415 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1416 /**
1417 @endcond
1418 */
1419 /**
1420 * @}
1421 */
1422
1423 /* Exported macro ------------------------------------------------------------*/
1424 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1425 * @{
1426 */
1427
1428 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1429 * @{
1430 */
1431 /**
1432 * @brief Write a value in TIM register.
1433 * @param __INSTANCE__ TIM Instance
1434 * @param __REG__ Register to be written
1435 * @param __VALUE__ Value to be written in the register
1436 * @retval None
1437 */
1438 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1439
1440 /**
1441 * @brief Read a value in TIM register.
1442 * @param __INSTANCE__ TIM Instance
1443 * @param __REG__ Register to be read
1444 * @retval Register value
1445 */
1446 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1447 /**
1448 * @}
1449 */
1450
1451 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1452 * @{
1453 */
1454
1455 /**
1456 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1457 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1458 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1459 * to TIMx_CNT register bit 31)
1460 * @param __CNT__ Counter value
1461 * @retval UIF status bit
1462 */
1463 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1464 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1465
1466 /**
1467 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1468 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1469 * @param __TIMCLK__ timer input clock frequency (in Hz)
1470 * @param __CKD__ This parameter can be one of the following values:
1471 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1472 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1473 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1474 * @param __DT__ deadtime duration (in ns)
1475 * @retval DTG[0:7]
1476 */
1477 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1478 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1479 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1480 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1481 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1482 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1483 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1484 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1485 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1486 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1487 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1488 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1489 0U)
1490
1491 /**
1492 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1493 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1494 * @param __TIMCLK__ timer input clock frequency (in Hz)
1495 * @param __CNTCLK__ counter clock frequency (in Hz)
1496 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1497 */
1498 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1499 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1500
1501 /**
1502 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1503 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1504 * @param __TIMCLK__ timer input clock frequency (in Hz)
1505 * @param __PSC__ prescaler
1506 * @param __FREQ__ output signal frequency (in Hz)
1507 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1508 */
1509 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1510 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1511
1512 /**
1513 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1514 * active/inactive delay.
1515 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1516 * @param __TIMCLK__ timer input clock frequency (in Hz)
1517 * @param __PSC__ prescaler
1518 * @param __DELAY__ timer output compare active/inactive delay (in us)
1519 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1520 */
1521 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1522 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1523 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1524
1525 /**
1526 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1527 * (when the timer operates in one pulse mode).
1528 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1529 * @param __TIMCLK__ timer input clock frequency (in Hz)
1530 * @param __PSC__ prescaler
1531 * @param __DELAY__ timer output compare active/inactive delay (in us)
1532 * @param __PULSE__ pulse duration (in us)
1533 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1534 */
1535 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1536 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1537 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1538
1539 /**
1540 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1541 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1542 * @param __ICPSC__ This parameter can be one of the following values:
1543 * @arg @ref LL_TIM_ICPSC_DIV1
1544 * @arg @ref LL_TIM_ICPSC_DIV2
1545 * @arg @ref LL_TIM_ICPSC_DIV4
1546 * @arg @ref LL_TIM_ICPSC_DIV8
1547 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1548 */
1549 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1550 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1551
1552
1553 /**
1554 * @}
1555 */
1556
1557
1558 /**
1559 * @}
1560 */
1561
1562 /* Exported functions --------------------------------------------------------*/
1563 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1564 * @{
1565 */
1566
1567 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1568 * @{
1569 */
1570 /**
1571 * @brief Enable timer counter.
1572 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1573 * @param TIMx Timer instance
1574 * @retval None
1575 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1576 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1577 {
1578 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1579 }
1580
1581 /**
1582 * @brief Disable timer counter.
1583 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1584 * @param TIMx Timer instance
1585 * @retval None
1586 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1587 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1588 {
1589 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1590 }
1591
1592 /**
1593 * @brief Indicates whether the timer counter is enabled.
1594 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1595 * @param TIMx Timer instance
1596 * @retval State of bit (1 or 0).
1597 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1598 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1599 {
1600 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1601 }
1602
1603 /**
1604 * @brief Enable update event generation.
1605 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1606 * @param TIMx Timer instance
1607 * @retval None
1608 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1609 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1610 {
1611 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1612 }
1613
1614 /**
1615 * @brief Disable update event generation.
1616 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1617 * @param TIMx Timer instance
1618 * @retval None
1619 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1620 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1621 {
1622 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1623 }
1624
1625 /**
1626 * @brief Indicates whether update event generation is enabled.
1627 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1628 * @param TIMx Timer instance
1629 * @retval Inverted state of bit (0 or 1).
1630 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1631 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1632 {
1633 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1634 }
1635
1636 /**
1637 * @brief Set update event source
1638 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1639 * generate an update interrupt or DMA request if enabled:
1640 * - Counter overflow/underflow
1641 * - Setting the UG bit
1642 * - Update generation through the slave mode controller
1643 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1644 * overflow/underflow generates an update interrupt or DMA request if enabled.
1645 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1646 * @param TIMx Timer instance
1647 * @param UpdateSource This parameter can be one of the following values:
1648 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1649 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1650 * @retval None
1651 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1652 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1653 {
1654 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1655 }
1656
1657 /**
1658 * @brief Get actual event update source
1659 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1660 * @param TIMx Timer instance
1661 * @retval Returned value can be one of the following values:
1662 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1663 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1664 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1665 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1666 {
1667 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1668 }
1669
1670 /**
1671 * @brief Set one pulse mode (one shot v.s. repetitive).
1672 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1673 * @param TIMx Timer instance
1674 * @param OnePulseMode This parameter can be one of the following values:
1675 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1676 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1677 * @retval None
1678 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1679 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1680 {
1681 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1682 }
1683
1684 /**
1685 * @brief Get actual one pulse mode.
1686 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1687 * @param TIMx Timer instance
1688 * @retval Returned value can be one of the following values:
1689 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1690 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1691 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1692 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1693 {
1694 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1695 }
1696
1697 /**
1698 * @brief Set the timer counter counting mode.
1699 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1700 * check whether or not the counter mode selection feature is supported
1701 * by a timer instance.
1702 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1703 * requires a timer reset to avoid unexpected direction
1704 * due to DIR bit readonly in center aligned mode.
1705 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1706 * CR1 CMS LL_TIM_SetCounterMode
1707 * @param TIMx Timer instance
1708 * @param CounterMode This parameter can be one of the following values:
1709 * @arg @ref LL_TIM_COUNTERMODE_UP
1710 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1711 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1712 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1713 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1714 * @retval None
1715 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1716 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1717 {
1718 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1719 }
1720
1721 /**
1722 * @brief Get actual counter mode.
1723 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1724 * check whether or not the counter mode selection feature is supported
1725 * by a timer instance.
1726 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1727 * CR1 CMS LL_TIM_GetCounterMode
1728 * @param TIMx Timer instance
1729 * @retval Returned value can be one of the following values:
1730 * @arg @ref LL_TIM_COUNTERMODE_UP
1731 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1732 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1733 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1734 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1735 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1736 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1737 {
1738 uint32_t counter_mode;
1739
1740 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1741
1742 if (counter_mode == 0U)
1743 {
1744 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1745 }
1746
1747 return counter_mode;
1748 }
1749
1750 /**
1751 * @brief Enable auto-reload (ARR) preload.
1752 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1753 * @param TIMx Timer instance
1754 * @retval None
1755 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1756 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1757 {
1758 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1759 }
1760
1761 /**
1762 * @brief Disable auto-reload (ARR) preload.
1763 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1764 * @param TIMx Timer instance
1765 * @retval None
1766 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1767 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1768 {
1769 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1770 }
1771
1772 /**
1773 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1774 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1775 * @param TIMx Timer instance
1776 * @retval State of bit (1 or 0).
1777 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1778 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1779 {
1780 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1781 }
1782
1783 /**
1784 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1785 * (when supported) and the digital filters.
1786 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1787 * whether or not the clock division feature is supported by the timer
1788 * instance.
1789 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1790 * @param TIMx Timer instance
1791 * @param ClockDivision This parameter can be one of the following values:
1792 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1793 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1794 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1795 * @retval None
1796 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1797 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1798 {
1799 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1800 }
1801
1802 /**
1803 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1804 * generators (when supported) and the digital filters.
1805 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1806 * whether or not the clock division feature is supported by the timer
1807 * instance.
1808 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1809 * @param TIMx Timer instance
1810 * @retval Returned value can be one of the following values:
1811 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1812 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1813 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1814 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1815 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1816 {
1817 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1818 }
1819
1820 /**
1821 * @brief Set the counter value.
1822 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1823 * whether or not a timer instance supports a 32 bits counter.
1824 * @rmtoll CNT CNT LL_TIM_SetCounter
1825 * @param TIMx Timer instance
1826 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1827 * @retval None
1828 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1829 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1830 {
1831 WRITE_REG(TIMx->CNT, Counter);
1832 }
1833
1834 /**
1835 * @brief Get the counter value.
1836 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1837 * whether or not a timer instance supports a 32 bits counter.
1838 * @rmtoll CNT CNT LL_TIM_GetCounter
1839 * @param TIMx Timer instance
1840 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1841 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1842 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1843 {
1844 return (uint32_t)(READ_REG(TIMx->CNT));
1845 }
1846
1847 /**
1848 * @brief Get the current direction of the counter
1849 * @rmtoll CR1 DIR LL_TIM_GetDirection
1850 * @param TIMx Timer instance
1851 * @retval Returned value can be one of the following values:
1852 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1853 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1854 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1855 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1856 {
1857 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1858 }
1859
1860 /**
1861 * @brief Set the prescaler value.
1862 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1863 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1864 * prescaler ratio is taken into account at the next update event.
1865 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1866 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1867 * @param TIMx Timer instance
1868 * @param Prescaler between Min_Data=0 and Max_Data=65535
1869 * @retval None
1870 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1871 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1872 {
1873 WRITE_REG(TIMx->PSC, Prescaler);
1874 }
1875
1876 /**
1877 * @brief Get the prescaler value.
1878 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1879 * @param TIMx Timer instance
1880 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1881 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1882 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1883 {
1884 return (uint32_t)(READ_REG(TIMx->PSC));
1885 }
1886
1887 /**
1888 * @brief Set the auto-reload value.
1889 * @note The counter is blocked while the auto-reload value is null.
1890 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1891 * whether or not a timer instance supports a 32 bits counter.
1892 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1893 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1894 * @param TIMx Timer instance
1895 * @param AutoReload between Min_Data=0 and Max_Data=65535
1896 * @retval None
1897 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1898 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1899 {
1900 WRITE_REG(TIMx->ARR, AutoReload);
1901 }
1902
1903 /**
1904 * @brief Get the auto-reload value.
1905 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1906 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1907 * whether or not a timer instance supports a 32 bits counter.
1908 * @param TIMx Timer instance
1909 * @retval Auto-reload value
1910 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1911 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1912 {
1913 return (uint32_t)(READ_REG(TIMx->ARR));
1914 }
1915
1916 /**
1917 * @brief Set the repetition counter value.
1918 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1919 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1920 * whether or not a timer instance supports a repetition counter.
1921 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1922 * @param TIMx Timer instance
1923 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1924 * @retval None
1925 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1926 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1927 {
1928 WRITE_REG(TIMx->RCR, RepetitionCounter);
1929 }
1930
1931 /**
1932 * @brief Get the repetition counter value.
1933 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1934 * whether or not a timer instance supports a repetition counter.
1935 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1936 * @param TIMx Timer instance
1937 * @retval Repetition counter value
1938 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1939 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1940 {
1941 return (uint32_t)(READ_REG(TIMx->RCR));
1942 }
1943
1944 /**
1945 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1946 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1947 * in an atomic way.
1948 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1949 * @param TIMx Timer instance
1950 * @retval None
1951 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1952 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1953 {
1954 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1955 }
1956
1957 /**
1958 * @brief Disable update interrupt flag (UIF) remapping.
1959 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1960 * @param TIMx Timer instance
1961 * @retval None
1962 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1963 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1964 {
1965 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1966 }
1967
1968 /**
1969 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1970 * @param Counter Counter value
1971 * @retval State of bit (1 or 0).
1972 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1973 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1974 {
1975 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1976 }
1977
1978 /**
1979 * @}
1980 */
1981
1982 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1983 * @{
1984 */
1985 /**
1986 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1987 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1988 * they are updated only when a commutation event (COM) occurs.
1989 * @note Only on channels that have a complementary output.
1990 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1991 * whether or not a timer instance is able to generate a commutation event.
1992 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1993 * @param TIMx Timer instance
1994 * @retval None
1995 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1996 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1997 {
1998 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1999 }
2000
2001 /**
2002 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2003 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2004 * whether or not a timer instance is able to generate a commutation event.
2005 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2006 * @param TIMx Timer instance
2007 * @retval None
2008 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)2009 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2010 {
2011 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2012 }
2013
2014 /**
2015 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2016 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2017 * whether or not a timer instance is able to generate a commutation event.
2018 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2019 * @param TIMx Timer instance
2020 * @param CCUpdateSource This parameter can be one of the following values:
2021 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2022 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2023 * @retval None
2024 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)2025 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2026 {
2027 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2028 }
2029
2030 /**
2031 * @brief Set the trigger of the capture/compare DMA request.
2032 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2033 * @param TIMx Timer instance
2034 * @param DMAReqTrigger This parameter can be one of the following values:
2035 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2036 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2037 * @retval None
2038 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)2039 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2040 {
2041 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2042 }
2043
2044 /**
2045 * @brief Get actual trigger of the capture/compare DMA request.
2046 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2047 * @param TIMx Timer instance
2048 * @retval Returned value can be one of the following values:
2049 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2050 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2051 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)2052 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
2053 {
2054 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2055 }
2056
2057 /**
2058 * @brief Set the lock level to freeze the
2059 * configuration of several capture/compare parameters.
2060 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2061 * the lock mechanism is supported by a timer instance.
2062 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2063 * @param TIMx Timer instance
2064 * @param LockLevel This parameter can be one of the following values:
2065 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2066 * @arg @ref LL_TIM_LOCKLEVEL_1
2067 * @arg @ref LL_TIM_LOCKLEVEL_2
2068 * @arg @ref LL_TIM_LOCKLEVEL_3
2069 * @retval None
2070 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)2071 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2072 {
2073 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2074 }
2075
2076 /**
2077 * @brief Enable capture/compare channels.
2078 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2079 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2080 * CCER CC2E LL_TIM_CC_EnableChannel\n
2081 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2082 * CCER CC3E LL_TIM_CC_EnableChannel\n
2083 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2084 * CCER CC4E LL_TIM_CC_EnableChannel\n
2085 * CCER CC5E LL_TIM_CC_EnableChannel\n
2086 * CCER CC6E LL_TIM_CC_EnableChannel
2087 * @param TIMx Timer instance
2088 * @param Channels This parameter can be a combination of the following values:
2089 * @arg @ref LL_TIM_CHANNEL_CH1
2090 * @arg @ref LL_TIM_CHANNEL_CH1N
2091 * @arg @ref LL_TIM_CHANNEL_CH2
2092 * @arg @ref LL_TIM_CHANNEL_CH2N
2093 * @arg @ref LL_TIM_CHANNEL_CH3
2094 * @arg @ref LL_TIM_CHANNEL_CH3N
2095 * @arg @ref LL_TIM_CHANNEL_CH4
2096 * @arg @ref LL_TIM_CHANNEL_CH5
2097 * @arg @ref LL_TIM_CHANNEL_CH6
2098 * @retval None
2099 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2100 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2101 {
2102 SET_BIT(TIMx->CCER, Channels);
2103 }
2104
2105 /**
2106 * @brief Disable capture/compare channels.
2107 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2108 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2109 * CCER CC2E LL_TIM_CC_DisableChannel\n
2110 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2111 * CCER CC3E LL_TIM_CC_DisableChannel\n
2112 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2113 * CCER CC4E LL_TIM_CC_DisableChannel\n
2114 * CCER CC5E LL_TIM_CC_DisableChannel\n
2115 * CCER CC6E LL_TIM_CC_DisableChannel
2116 * @param TIMx Timer instance
2117 * @param Channels This parameter can be a combination of the following values:
2118 * @arg @ref LL_TIM_CHANNEL_CH1
2119 * @arg @ref LL_TIM_CHANNEL_CH1N
2120 * @arg @ref LL_TIM_CHANNEL_CH2
2121 * @arg @ref LL_TIM_CHANNEL_CH2N
2122 * @arg @ref LL_TIM_CHANNEL_CH3
2123 * @arg @ref LL_TIM_CHANNEL_CH3N
2124 * @arg @ref LL_TIM_CHANNEL_CH4
2125 * @arg @ref LL_TIM_CHANNEL_CH5
2126 * @arg @ref LL_TIM_CHANNEL_CH6
2127 * @retval None
2128 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2129 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2130 {
2131 CLEAR_BIT(TIMx->CCER, Channels);
2132 }
2133
2134 /**
2135 * @brief Indicate whether channel(s) is(are) enabled.
2136 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2137 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2138 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2139 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2140 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2141 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2142 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2143 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2144 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2145 * @param TIMx Timer instance
2146 * @param Channels This parameter can be a combination of the following values:
2147 * @arg @ref LL_TIM_CHANNEL_CH1
2148 * @arg @ref LL_TIM_CHANNEL_CH1N
2149 * @arg @ref LL_TIM_CHANNEL_CH2
2150 * @arg @ref LL_TIM_CHANNEL_CH2N
2151 * @arg @ref LL_TIM_CHANNEL_CH3
2152 * @arg @ref LL_TIM_CHANNEL_CH3N
2153 * @arg @ref LL_TIM_CHANNEL_CH4
2154 * @arg @ref LL_TIM_CHANNEL_CH5
2155 * @arg @ref LL_TIM_CHANNEL_CH6
2156 * @retval State of bit (1 or 0).
2157 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)2158 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2159 {
2160 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2161 }
2162
2163 /**
2164 * @}
2165 */
2166
2167 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2168 * @{
2169 */
2170 /**
2171 * @brief Configure an output channel.
2172 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2173 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2174 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2175 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2176 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2177 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2178 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2179 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2180 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2181 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2182 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2183 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2184 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2185 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2186 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2187 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2188 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2189 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2190 * @param TIMx Timer instance
2191 * @param Channel This parameter can be one of the following values:
2192 * @arg @ref LL_TIM_CHANNEL_CH1
2193 * @arg @ref LL_TIM_CHANNEL_CH2
2194 * @arg @ref LL_TIM_CHANNEL_CH3
2195 * @arg @ref LL_TIM_CHANNEL_CH4
2196 * @arg @ref LL_TIM_CHANNEL_CH5
2197 * @arg @ref LL_TIM_CHANNEL_CH6
2198 * @param Configuration This parameter must be a combination of all the following values:
2199 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2200 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2201 * @retval None
2202 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2203 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2204 {
2205 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2206 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2207 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2208 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2209 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2210 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2211 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2212 }
2213
2214 /**
2215 * @brief Define the behavior of the output reference signal OCxREF from which
2216 * OCx and OCxN (when relevant) are derived.
2217 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2218 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2219 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2220 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2221 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2222 * CCMR3 OC6M LL_TIM_OC_SetMode
2223 * @param TIMx Timer instance
2224 * @param Channel This parameter can be one of the following values:
2225 * @arg @ref LL_TIM_CHANNEL_CH1
2226 * @arg @ref LL_TIM_CHANNEL_CH2
2227 * @arg @ref LL_TIM_CHANNEL_CH3
2228 * @arg @ref LL_TIM_CHANNEL_CH4
2229 * @arg @ref LL_TIM_CHANNEL_CH5
2230 * @arg @ref LL_TIM_CHANNEL_CH6
2231 * @param Mode This parameter can be one of the following values:
2232 * @arg @ref LL_TIM_OCMODE_FROZEN
2233 * @arg @ref LL_TIM_OCMODE_ACTIVE
2234 * @arg @ref LL_TIM_OCMODE_INACTIVE
2235 * @arg @ref LL_TIM_OCMODE_TOGGLE
2236 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2237 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2238 * @arg @ref LL_TIM_OCMODE_PWM1
2239 * @arg @ref LL_TIM_OCMODE_PWM2
2240 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2241 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2242 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2243 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2244 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2245 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2246 * @retval None
2247 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2248 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2249 {
2250 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2251 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2252 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2253 }
2254
2255 /**
2256 * @brief Get the output compare mode of an output channel.
2257 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2258 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2259 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2260 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2261 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2262 * CCMR3 OC6M LL_TIM_OC_GetMode
2263 * @param TIMx Timer instance
2264 * @param Channel This parameter can be one of the following values:
2265 * @arg @ref LL_TIM_CHANNEL_CH1
2266 * @arg @ref LL_TIM_CHANNEL_CH2
2267 * @arg @ref LL_TIM_CHANNEL_CH3
2268 * @arg @ref LL_TIM_CHANNEL_CH4
2269 * @arg @ref LL_TIM_CHANNEL_CH5
2270 * @arg @ref LL_TIM_CHANNEL_CH6
2271 * @retval Returned value can be one of the following values:
2272 * @arg @ref LL_TIM_OCMODE_FROZEN
2273 * @arg @ref LL_TIM_OCMODE_ACTIVE
2274 * @arg @ref LL_TIM_OCMODE_INACTIVE
2275 * @arg @ref LL_TIM_OCMODE_TOGGLE
2276 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2277 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2278 * @arg @ref LL_TIM_OCMODE_PWM1
2279 * @arg @ref LL_TIM_OCMODE_PWM2
2280 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2281 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2282 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2283 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2284 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2285 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2286 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2287 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2288 {
2289 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2290 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2291 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2292 }
2293
2294 /**
2295 * @brief Set the polarity of an output channel.
2296 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2297 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2298 * CCER CC2P LL_TIM_OC_SetPolarity\n
2299 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2300 * CCER CC3P LL_TIM_OC_SetPolarity\n
2301 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2302 * CCER CC4P LL_TIM_OC_SetPolarity\n
2303 * CCER CC5P LL_TIM_OC_SetPolarity\n
2304 * CCER CC6P LL_TIM_OC_SetPolarity
2305 * @param TIMx Timer instance
2306 * @param Channel This parameter can be one of the following values:
2307 * @arg @ref LL_TIM_CHANNEL_CH1
2308 * @arg @ref LL_TIM_CHANNEL_CH1N
2309 * @arg @ref LL_TIM_CHANNEL_CH2
2310 * @arg @ref LL_TIM_CHANNEL_CH2N
2311 * @arg @ref LL_TIM_CHANNEL_CH3
2312 * @arg @ref LL_TIM_CHANNEL_CH3N
2313 * @arg @ref LL_TIM_CHANNEL_CH4
2314 * @arg @ref LL_TIM_CHANNEL_CH5
2315 * @arg @ref LL_TIM_CHANNEL_CH6
2316 * @param Polarity This parameter can be one of the following values:
2317 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2318 * @arg @ref LL_TIM_OCPOLARITY_LOW
2319 * @retval None
2320 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2321 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2322 {
2323 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2324 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2325 }
2326
2327 /**
2328 * @brief Get the polarity of an output channel.
2329 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2330 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2331 * CCER CC2P LL_TIM_OC_GetPolarity\n
2332 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2333 * CCER CC3P LL_TIM_OC_GetPolarity\n
2334 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2335 * CCER CC4P LL_TIM_OC_GetPolarity\n
2336 * CCER CC5P LL_TIM_OC_GetPolarity\n
2337 * CCER CC6P LL_TIM_OC_GetPolarity
2338 * @param TIMx Timer instance
2339 * @param Channel This parameter can be one of the following values:
2340 * @arg @ref LL_TIM_CHANNEL_CH1
2341 * @arg @ref LL_TIM_CHANNEL_CH1N
2342 * @arg @ref LL_TIM_CHANNEL_CH2
2343 * @arg @ref LL_TIM_CHANNEL_CH2N
2344 * @arg @ref LL_TIM_CHANNEL_CH3
2345 * @arg @ref LL_TIM_CHANNEL_CH3N
2346 * @arg @ref LL_TIM_CHANNEL_CH4
2347 * @arg @ref LL_TIM_CHANNEL_CH5
2348 * @arg @ref LL_TIM_CHANNEL_CH6
2349 * @retval Returned value can be one of the following values:
2350 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2351 * @arg @ref LL_TIM_OCPOLARITY_LOW
2352 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2353 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2354 {
2355 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2356 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2357 }
2358
2359 /**
2360 * @brief Set the IDLE state of an output channel
2361 * @note This function is significant only for the timer instances
2362 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2363 * can be used to check whether or not a timer instance provides
2364 * a break input.
2365 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2366 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2367 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2368 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2369 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2370 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2371 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2372 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2373 * CR2 OIS6 LL_TIM_OC_SetIdleState
2374 * @param TIMx Timer instance
2375 * @param Channel This parameter can be one of the following values:
2376 * @arg @ref LL_TIM_CHANNEL_CH1
2377 * @arg @ref LL_TIM_CHANNEL_CH1N
2378 * @arg @ref LL_TIM_CHANNEL_CH2
2379 * @arg @ref LL_TIM_CHANNEL_CH2N
2380 * @arg @ref LL_TIM_CHANNEL_CH3
2381 * @arg @ref LL_TIM_CHANNEL_CH3N
2382 * @arg @ref LL_TIM_CHANNEL_CH4
2383 * @arg @ref LL_TIM_CHANNEL_CH5
2384 * @arg @ref LL_TIM_CHANNEL_CH6
2385 * @param IdleState This parameter can be one of the following values:
2386 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2387 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2388 * @retval None
2389 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2390 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2391 {
2392 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2393 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2394 }
2395
2396 /**
2397 * @brief Get the IDLE state of an output channel
2398 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2399 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2400 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2401 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2402 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2403 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2404 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2405 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2406 * CR2 OIS6 LL_TIM_OC_GetIdleState
2407 * @param TIMx Timer instance
2408 * @param Channel This parameter can be one of the following values:
2409 * @arg @ref LL_TIM_CHANNEL_CH1
2410 * @arg @ref LL_TIM_CHANNEL_CH1N
2411 * @arg @ref LL_TIM_CHANNEL_CH2
2412 * @arg @ref LL_TIM_CHANNEL_CH2N
2413 * @arg @ref LL_TIM_CHANNEL_CH3
2414 * @arg @ref LL_TIM_CHANNEL_CH3N
2415 * @arg @ref LL_TIM_CHANNEL_CH4
2416 * @arg @ref LL_TIM_CHANNEL_CH5
2417 * @arg @ref LL_TIM_CHANNEL_CH6
2418 * @retval Returned value can be one of the following values:
2419 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2420 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2421 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2422 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2423 {
2424 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2425 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2426 }
2427
2428 /**
2429 * @brief Enable fast mode for the output channel.
2430 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2431 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2432 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2433 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2434 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2435 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2436 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2437 * @param TIMx Timer instance
2438 * @param Channel This parameter can be one of the following values:
2439 * @arg @ref LL_TIM_CHANNEL_CH1
2440 * @arg @ref LL_TIM_CHANNEL_CH2
2441 * @arg @ref LL_TIM_CHANNEL_CH3
2442 * @arg @ref LL_TIM_CHANNEL_CH4
2443 * @arg @ref LL_TIM_CHANNEL_CH5
2444 * @arg @ref LL_TIM_CHANNEL_CH6
2445 * @retval None
2446 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2447 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2448 {
2449 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2450 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2451 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2452
2453 }
2454
2455 /**
2456 * @brief Disable fast mode for the output channel.
2457 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2458 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2459 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2460 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2461 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2462 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2463 * @param TIMx Timer instance
2464 * @param Channel This parameter can be one of the following values:
2465 * @arg @ref LL_TIM_CHANNEL_CH1
2466 * @arg @ref LL_TIM_CHANNEL_CH2
2467 * @arg @ref LL_TIM_CHANNEL_CH3
2468 * @arg @ref LL_TIM_CHANNEL_CH4
2469 * @arg @ref LL_TIM_CHANNEL_CH5
2470 * @arg @ref LL_TIM_CHANNEL_CH6
2471 * @retval None
2472 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2473 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2474 {
2475 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2476 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2477 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2478
2479 }
2480
2481 /**
2482 * @brief Indicates whether fast mode is enabled for the output channel.
2483 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2484 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2485 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2486 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2487 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2488 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2489 * @param TIMx Timer instance
2490 * @param Channel This parameter can be one of the following values:
2491 * @arg @ref LL_TIM_CHANNEL_CH1
2492 * @arg @ref LL_TIM_CHANNEL_CH2
2493 * @arg @ref LL_TIM_CHANNEL_CH3
2494 * @arg @ref LL_TIM_CHANNEL_CH4
2495 * @arg @ref LL_TIM_CHANNEL_CH5
2496 * @arg @ref LL_TIM_CHANNEL_CH6
2497 * @retval State of bit (1 or 0).
2498 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)2499 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2500 {
2501 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2502 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2503 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2504 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2505 }
2506
2507 /**
2508 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2509 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2510 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2511 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2512 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2513 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2514 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2515 * @param TIMx Timer instance
2516 * @param Channel This parameter can be one of the following values:
2517 * @arg @ref LL_TIM_CHANNEL_CH1
2518 * @arg @ref LL_TIM_CHANNEL_CH2
2519 * @arg @ref LL_TIM_CHANNEL_CH3
2520 * @arg @ref LL_TIM_CHANNEL_CH4
2521 * @arg @ref LL_TIM_CHANNEL_CH5
2522 * @arg @ref LL_TIM_CHANNEL_CH6
2523 * @retval None
2524 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2525 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2526 {
2527 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2528 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2529 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2530 }
2531
2532 /**
2533 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2534 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2535 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2536 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2537 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2538 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2539 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2540 * @param TIMx Timer instance
2541 * @param Channel This parameter can be one of the following values:
2542 * @arg @ref LL_TIM_CHANNEL_CH1
2543 * @arg @ref LL_TIM_CHANNEL_CH2
2544 * @arg @ref LL_TIM_CHANNEL_CH3
2545 * @arg @ref LL_TIM_CHANNEL_CH4
2546 * @arg @ref LL_TIM_CHANNEL_CH5
2547 * @arg @ref LL_TIM_CHANNEL_CH6
2548 * @retval None
2549 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2550 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2551 {
2552 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2553 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2554 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2555 }
2556
2557 /**
2558 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2559 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2560 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2561 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2562 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2563 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2564 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2565 * @param TIMx Timer instance
2566 * @param Channel This parameter can be one of the following values:
2567 * @arg @ref LL_TIM_CHANNEL_CH1
2568 * @arg @ref LL_TIM_CHANNEL_CH2
2569 * @arg @ref LL_TIM_CHANNEL_CH3
2570 * @arg @ref LL_TIM_CHANNEL_CH4
2571 * @arg @ref LL_TIM_CHANNEL_CH5
2572 * @arg @ref LL_TIM_CHANNEL_CH6
2573 * @retval State of bit (1 or 0).
2574 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)2575 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2576 {
2577 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2578 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2579 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2580 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2581 }
2582
2583 /**
2584 * @brief Enable clearing the output channel on an external event.
2585 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2586 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2587 * or not a timer instance can clear the OCxREF signal on an external event.
2588 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2589 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2590 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2591 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2592 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2593 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2594 * @param TIMx Timer instance
2595 * @param Channel This parameter can be one of the following values:
2596 * @arg @ref LL_TIM_CHANNEL_CH1
2597 * @arg @ref LL_TIM_CHANNEL_CH2
2598 * @arg @ref LL_TIM_CHANNEL_CH3
2599 * @arg @ref LL_TIM_CHANNEL_CH4
2600 * @arg @ref LL_TIM_CHANNEL_CH5
2601 * @arg @ref LL_TIM_CHANNEL_CH6
2602 * @retval None
2603 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2604 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2605 {
2606 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2607 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2608 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2609 }
2610
2611 /**
2612 * @brief Disable clearing the output channel on an external event.
2613 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2614 * or not a timer instance can clear the OCxREF signal on an external event.
2615 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2616 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2617 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2618 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2619 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2620 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2621 * @param TIMx Timer instance
2622 * @param Channel This parameter can be one of the following values:
2623 * @arg @ref LL_TIM_CHANNEL_CH1
2624 * @arg @ref LL_TIM_CHANNEL_CH2
2625 * @arg @ref LL_TIM_CHANNEL_CH3
2626 * @arg @ref LL_TIM_CHANNEL_CH4
2627 * @arg @ref LL_TIM_CHANNEL_CH5
2628 * @arg @ref LL_TIM_CHANNEL_CH6
2629 * @retval None
2630 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2631 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2632 {
2633 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2634 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2635 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2636 }
2637
2638 /**
2639 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2640 * @note This function enables clearing the output channel on an external event.
2641 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2642 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2643 * or not a timer instance can clear the OCxREF signal on an external event.
2644 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2645 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2646 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2647 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2648 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2649 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2650 * @param TIMx Timer instance
2651 * @param Channel This parameter can be one of the following values:
2652 * @arg @ref LL_TIM_CHANNEL_CH1
2653 * @arg @ref LL_TIM_CHANNEL_CH2
2654 * @arg @ref LL_TIM_CHANNEL_CH3
2655 * @arg @ref LL_TIM_CHANNEL_CH4
2656 * @arg @ref LL_TIM_CHANNEL_CH5
2657 * @arg @ref LL_TIM_CHANNEL_CH6
2658 * @retval State of bit (1 or 0).
2659 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)2660 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2661 {
2662 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2663 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2664 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2665 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2666 }
2667
2668 /**
2669 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2670 * the Ocx and OCxN signals).
2671 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2672 * dead-time insertion feature is supported by a timer instance.
2673 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2674 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2675 * @param TIMx Timer instance
2676 * @param DeadTime between Min_Data=0 and Max_Data=255
2677 * @retval None
2678 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2679 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2680 {
2681 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2682 }
2683
2684 /**
2685 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2686 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2687 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2688 * whether or not a timer instance supports a 32 bits counter.
2689 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2690 * output channel 1 is supported by a timer instance.
2691 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2692 * @param TIMx Timer instance
2693 * @param CompareValue between Min_Data=0 and Max_Data=65535
2694 * @retval None
2695 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2696 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2697 {
2698 WRITE_REG(TIMx->CCR1, CompareValue);
2699 }
2700
2701 /**
2702 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2703 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2704 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2705 * whether or not a timer instance supports a 32 bits counter.
2706 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2707 * output channel 2 is supported by a timer instance.
2708 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2709 * @param TIMx Timer instance
2710 * @param CompareValue between Min_Data=0 and Max_Data=65535
2711 * @retval None
2712 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2713 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2714 {
2715 WRITE_REG(TIMx->CCR2, CompareValue);
2716 }
2717
2718 /**
2719 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2720 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2721 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2722 * whether or not a timer instance supports a 32 bits counter.
2723 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2724 * output channel is supported by a timer instance.
2725 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2726 * @param TIMx Timer instance
2727 * @param CompareValue between Min_Data=0 and Max_Data=65535
2728 * @retval None
2729 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2730 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2731 {
2732 WRITE_REG(TIMx->CCR3, CompareValue);
2733 }
2734
2735 /**
2736 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2737 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2738 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2739 * whether or not a timer instance supports a 32 bits counter.
2740 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2741 * output channel 4 is supported by a timer instance.
2742 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2743 * @param TIMx Timer instance
2744 * @param CompareValue between Min_Data=0 and Max_Data=65535
2745 * @retval None
2746 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2747 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2748 {
2749 WRITE_REG(TIMx->CCR4, CompareValue);
2750 }
2751
2752 /**
2753 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2754 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2755 * output channel 5 is supported by a timer instance.
2756 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2757 * @param TIMx Timer instance
2758 * @param CompareValue between Min_Data=0 and Max_Data=65535
2759 * @retval None
2760 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2761 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2762 {
2763 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2764 }
2765
2766 /**
2767 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2768 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2769 * output channel 6 is supported by a timer instance.
2770 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2771 * @param TIMx Timer instance
2772 * @param CompareValue between Min_Data=0 and Max_Data=65535
2773 * @retval None
2774 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2775 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2776 {
2777 WRITE_REG(TIMx->CCR6, CompareValue);
2778 }
2779
2780 /**
2781 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2782 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2783 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2784 * whether or not a timer instance supports a 32 bits counter.
2785 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2786 * output channel 1 is supported by a timer instance.
2787 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2788 * @param TIMx Timer instance
2789 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2790 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2791 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2792 {
2793 return (uint32_t)(READ_REG(TIMx->CCR1));
2794 }
2795
2796 /**
2797 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2798 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2799 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2800 * whether or not a timer instance supports a 32 bits counter.
2801 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2802 * output channel 2 is supported by a timer instance.
2803 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2804 * @param TIMx Timer instance
2805 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2806 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2807 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2808 {
2809 return (uint32_t)(READ_REG(TIMx->CCR2));
2810 }
2811
2812 /**
2813 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2814 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2815 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2816 * whether or not a timer instance supports a 32 bits counter.
2817 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2818 * output channel 3 is supported by a timer instance.
2819 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2820 * @param TIMx Timer instance
2821 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2822 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2823 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2824 {
2825 return (uint32_t)(READ_REG(TIMx->CCR3));
2826 }
2827
2828 /**
2829 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2830 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2831 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2832 * whether or not a timer instance supports a 32 bits counter.
2833 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2834 * output channel 4 is supported by a timer instance.
2835 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2836 * @param TIMx Timer instance
2837 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2838 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2839 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2840 {
2841 return (uint32_t)(READ_REG(TIMx->CCR4));
2842 }
2843
2844 /**
2845 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2846 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2847 * output channel 5 is supported by a timer instance.
2848 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2849 * @param TIMx Timer instance
2850 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2851 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2852 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2853 {
2854 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2855 }
2856
2857 /**
2858 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2859 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2860 * output channel 6 is supported by a timer instance.
2861 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2862 * @param TIMx Timer instance
2863 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2864 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2865 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2866 {
2867 return (uint32_t)(READ_REG(TIMx->CCR6));
2868 }
2869
2870 /**
2871 * @brief Select on which reference signal the OC5REF is combined to.
2872 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2873 * whether or not a timer instance supports the combined 3-phase PWM mode.
2874 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2875 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2876 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2877 * @param TIMx Timer instance
2878 * @param GroupCH5 This parameter can be a combination of the following values:
2879 * @arg @ref LL_TIM_GROUPCH5_NONE
2880 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2881 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2882 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2883 * @retval None
2884 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2885 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2886 {
2887 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2888 }
2889
2890 /**
2891 * @}
2892 */
2893
2894 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2895 * @{
2896 */
2897 /**
2898 * @brief Configure input channel.
2899 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2900 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2901 * CCMR1 IC1F LL_TIM_IC_Config\n
2902 * CCMR1 CC2S LL_TIM_IC_Config\n
2903 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2904 * CCMR1 IC2F LL_TIM_IC_Config\n
2905 * CCMR2 CC3S LL_TIM_IC_Config\n
2906 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2907 * CCMR2 IC3F LL_TIM_IC_Config\n
2908 * CCMR2 CC4S LL_TIM_IC_Config\n
2909 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2910 * CCMR2 IC4F LL_TIM_IC_Config\n
2911 * CCER CC1P LL_TIM_IC_Config\n
2912 * CCER CC1NP LL_TIM_IC_Config\n
2913 * CCER CC2P LL_TIM_IC_Config\n
2914 * CCER CC2NP LL_TIM_IC_Config\n
2915 * CCER CC3P LL_TIM_IC_Config\n
2916 * CCER CC3NP LL_TIM_IC_Config\n
2917 * CCER CC4P LL_TIM_IC_Config\n
2918 * CCER CC4NP LL_TIM_IC_Config
2919 * @param TIMx Timer instance
2920 * @param Channel This parameter can be one of the following values:
2921 * @arg @ref LL_TIM_CHANNEL_CH1
2922 * @arg @ref LL_TIM_CHANNEL_CH2
2923 * @arg @ref LL_TIM_CHANNEL_CH3
2924 * @arg @ref LL_TIM_CHANNEL_CH4
2925 * @param Configuration This parameter must be a combination of all the following values:
2926 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2927 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2928 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2929 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2930 * @retval None
2931 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2932 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2933 {
2934 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2935 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2936 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2937 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2938 << SHIFT_TAB_ICxx[iChannel]);
2939 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2940 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2941 }
2942
2943 /**
2944 * @brief Set the active input.
2945 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2946 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2947 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2948 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2949 * @param TIMx Timer instance
2950 * @param Channel This parameter can be one of the following values:
2951 * @arg @ref LL_TIM_CHANNEL_CH1
2952 * @arg @ref LL_TIM_CHANNEL_CH2
2953 * @arg @ref LL_TIM_CHANNEL_CH3
2954 * @arg @ref LL_TIM_CHANNEL_CH4
2955 * @param ICActiveInput This parameter can be one of the following values:
2956 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2957 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2958 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2959 * @retval None
2960 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2961 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2962 {
2963 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2964 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2965 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2966 }
2967
2968 /**
2969 * @brief Get the current active input.
2970 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2971 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2972 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2973 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2974 * @param TIMx Timer instance
2975 * @param Channel This parameter can be one of the following values:
2976 * @arg @ref LL_TIM_CHANNEL_CH1
2977 * @arg @ref LL_TIM_CHANNEL_CH2
2978 * @arg @ref LL_TIM_CHANNEL_CH3
2979 * @arg @ref LL_TIM_CHANNEL_CH4
2980 * @retval Returned value can be one of the following values:
2981 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2982 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2983 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2984 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2985 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2986 {
2987 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2988 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2989 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2990 }
2991
2992 /**
2993 * @brief Set the prescaler of input channel.
2994 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2995 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2996 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2997 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2998 * @param TIMx Timer instance
2999 * @param Channel This parameter can be one of the following values:
3000 * @arg @ref LL_TIM_CHANNEL_CH1
3001 * @arg @ref LL_TIM_CHANNEL_CH2
3002 * @arg @ref LL_TIM_CHANNEL_CH3
3003 * @arg @ref LL_TIM_CHANNEL_CH4
3004 * @param ICPrescaler This parameter can be one of the following values:
3005 * @arg @ref LL_TIM_ICPSC_DIV1
3006 * @arg @ref LL_TIM_ICPSC_DIV2
3007 * @arg @ref LL_TIM_ICPSC_DIV4
3008 * @arg @ref LL_TIM_ICPSC_DIV8
3009 * @retval None
3010 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3011 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3012 {
3013 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3014 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3015 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3016 }
3017
3018 /**
3019 * @brief Get the current prescaler value acting on an input channel.
3020 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3021 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3022 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3023 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3024 * @param TIMx Timer instance
3025 * @param Channel This parameter can be one of the following values:
3026 * @arg @ref LL_TIM_CHANNEL_CH1
3027 * @arg @ref LL_TIM_CHANNEL_CH2
3028 * @arg @ref LL_TIM_CHANNEL_CH3
3029 * @arg @ref LL_TIM_CHANNEL_CH4
3030 * @retval Returned value can be one of the following values:
3031 * @arg @ref LL_TIM_ICPSC_DIV1
3032 * @arg @ref LL_TIM_ICPSC_DIV2
3033 * @arg @ref LL_TIM_ICPSC_DIV4
3034 * @arg @ref LL_TIM_ICPSC_DIV8
3035 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3036 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3037 {
3038 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3039 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3040 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3041 }
3042
3043 /**
3044 * @brief Set the input filter duration.
3045 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3046 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3047 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3048 * CCMR2 IC4F LL_TIM_IC_SetFilter
3049 * @param TIMx Timer instance
3050 * @param Channel This parameter can be one of the following values:
3051 * @arg @ref LL_TIM_CHANNEL_CH1
3052 * @arg @ref LL_TIM_CHANNEL_CH2
3053 * @arg @ref LL_TIM_CHANNEL_CH3
3054 * @arg @ref LL_TIM_CHANNEL_CH4
3055 * @param ICFilter This parameter can be one of the following values:
3056 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3057 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3058 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3059 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3060 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3061 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3062 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3063 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3064 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3065 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3066 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3067 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3068 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3069 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3070 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3071 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3072 * @retval None
3073 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3074 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3075 {
3076 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3077 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3078 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3079 }
3080
3081 /**
3082 * @brief Get the input filter duration.
3083 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3084 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3085 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3086 * CCMR2 IC4F LL_TIM_IC_GetFilter
3087 * @param TIMx Timer instance
3088 * @param Channel This parameter can be one of the following values:
3089 * @arg @ref LL_TIM_CHANNEL_CH1
3090 * @arg @ref LL_TIM_CHANNEL_CH2
3091 * @arg @ref LL_TIM_CHANNEL_CH3
3092 * @arg @ref LL_TIM_CHANNEL_CH4
3093 * @retval Returned value can be one of the following values:
3094 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3095 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3096 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3097 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3098 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3099 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3100 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3101 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3102 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3103 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3104 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3105 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3106 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3107 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3108 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3109 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3110 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3111 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3112 {
3113 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3114 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3115 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3116 }
3117
3118 /**
3119 * @brief Set the input channel polarity.
3120 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3121 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3122 * CCER CC2P LL_TIM_IC_SetPolarity\n
3123 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3124 * CCER CC3P LL_TIM_IC_SetPolarity\n
3125 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3126 * CCER CC4P LL_TIM_IC_SetPolarity\n
3127 * CCER CC4NP LL_TIM_IC_SetPolarity
3128 * @param TIMx Timer instance
3129 * @param Channel This parameter can be one of the following values:
3130 * @arg @ref LL_TIM_CHANNEL_CH1
3131 * @arg @ref LL_TIM_CHANNEL_CH2
3132 * @arg @ref LL_TIM_CHANNEL_CH3
3133 * @arg @ref LL_TIM_CHANNEL_CH4
3134 * @param ICPolarity This parameter can be one of the following values:
3135 * @arg @ref LL_TIM_IC_POLARITY_RISING
3136 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3137 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3138 * @retval None
3139 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3140 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3141 {
3142 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3143 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3144 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3145 }
3146
3147 /**
3148 * @brief Get the current input channel polarity.
3149 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3150 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3151 * CCER CC2P LL_TIM_IC_GetPolarity\n
3152 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3153 * CCER CC3P LL_TIM_IC_GetPolarity\n
3154 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3155 * CCER CC4P LL_TIM_IC_GetPolarity\n
3156 * CCER CC4NP LL_TIM_IC_GetPolarity
3157 * @param TIMx Timer instance
3158 * @param Channel This parameter can be one of the following values:
3159 * @arg @ref LL_TIM_CHANNEL_CH1
3160 * @arg @ref LL_TIM_CHANNEL_CH2
3161 * @arg @ref LL_TIM_CHANNEL_CH3
3162 * @arg @ref LL_TIM_CHANNEL_CH4
3163 * @retval Returned value can be one of the following values:
3164 * @arg @ref LL_TIM_IC_POLARITY_RISING
3165 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3166 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3167 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3168 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3169 {
3170 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3171 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3172 SHIFT_TAB_CCxP[iChannel]);
3173 }
3174
3175 /**
3176 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3177 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3178 * a timer instance provides an XOR input.
3179 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3180 * @param TIMx Timer instance
3181 * @retval None
3182 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3183 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3184 {
3185 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3186 }
3187
3188 /**
3189 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3190 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3191 * a timer instance provides an XOR input.
3192 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3193 * @param TIMx Timer instance
3194 * @retval None
3195 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3196 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3197 {
3198 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3199 }
3200
3201 /**
3202 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3203 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3204 * a timer instance provides an XOR input.
3205 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3206 * @param TIMx Timer instance
3207 * @retval State of bit (1 or 0).
3208 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)3209 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3210 {
3211 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3212 }
3213
3214 /**
3215 * @brief Get captured value for input channel 1.
3216 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3217 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3218 * whether or not a timer instance supports a 32 bits counter.
3219 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3220 * input channel 1 is supported by a timer instance.
3221 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3222 * @param TIMx Timer instance
3223 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3224 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3225 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3226 {
3227 return (uint32_t)(READ_REG(TIMx->CCR1));
3228 }
3229
3230 /**
3231 * @brief Get captured value for input channel 2.
3232 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3233 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3234 * whether or not a timer instance supports a 32 bits counter.
3235 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3236 * input channel 2 is supported by a timer instance.
3237 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3238 * @param TIMx Timer instance
3239 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3240 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3241 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3242 {
3243 return (uint32_t)(READ_REG(TIMx->CCR2));
3244 }
3245
3246 /**
3247 * @brief Get captured value for input channel 3.
3248 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3249 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3250 * whether or not a timer instance supports a 32 bits counter.
3251 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3252 * input channel 3 is supported by a timer instance.
3253 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3254 * @param TIMx Timer instance
3255 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3256 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3257 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3258 {
3259 return (uint32_t)(READ_REG(TIMx->CCR3));
3260 }
3261
3262 /**
3263 * @brief Get captured value for input channel 4.
3264 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3265 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3266 * whether or not a timer instance supports a 32 bits counter.
3267 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3268 * input channel 4 is supported by a timer instance.
3269 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3270 * @param TIMx Timer instance
3271 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3272 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3273 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3274 {
3275 return (uint32_t)(READ_REG(TIMx->CCR4));
3276 }
3277
3278 /**
3279 * @}
3280 */
3281
3282 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3283 * @{
3284 */
3285 /**
3286 * @brief Enable external clock mode 2.
3287 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3288 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3289 * whether or not a timer instance supports external clock mode2.
3290 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3291 * @param TIMx Timer instance
3292 * @retval None
3293 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3294 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3295 {
3296 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3297 }
3298
3299 /**
3300 * @brief Disable external clock mode 2.
3301 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3302 * whether or not a timer instance supports external clock mode2.
3303 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3304 * @param TIMx Timer instance
3305 * @retval None
3306 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3307 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3308 {
3309 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3310 }
3311
3312 /**
3313 * @brief Indicate whether external clock mode 2 is enabled.
3314 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3315 * whether or not a timer instance supports external clock mode2.
3316 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3317 * @param TIMx Timer instance
3318 * @retval State of bit (1 or 0).
3319 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3320 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3321 {
3322 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3323 }
3324
3325 /**
3326 * @brief Set the clock source of the counter clock.
3327 * @note when selected clock source is external clock mode 1, the timer input
3328 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3329 * function. This timer input must be configured by calling
3330 * the @ref LL_TIM_IC_Config() function.
3331 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3332 * whether or not a timer instance supports external clock mode1.
3333 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3334 * whether or not a timer instance supports external clock mode2.
3335 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3336 * SMCR ECE LL_TIM_SetClockSource
3337 * @param TIMx Timer instance
3338 * @param ClockSource This parameter can be one of the following values:
3339 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3340 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3341 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3342 * @retval None
3343 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3344 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3345 {
3346 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3347 }
3348
3349 /**
3350 * @brief Set the encoder interface mode.
3351 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3352 * whether or not a timer instance supports the encoder mode.
3353 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3354 * @param TIMx Timer instance
3355 * @param EncoderMode This parameter can be one of the following values:
3356 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3357 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3358 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3359 * @retval None
3360 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3361 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3362 {
3363 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3364 }
3365
3366 /**
3367 * @}
3368 */
3369
3370 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3371 * @{
3372 */
3373 /**
3374 * @brief Set the trigger output (TRGO) used for timer synchronization .
3375 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3376 * whether or not a timer instance can operate as a master timer.
3377 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3378 * @param TIMx Timer instance
3379 * @param TimerSynchronization This parameter can be one of the following values:
3380 * @arg @ref LL_TIM_TRGO_RESET
3381 * @arg @ref LL_TIM_TRGO_ENABLE
3382 * @arg @ref LL_TIM_TRGO_UPDATE
3383 * @arg @ref LL_TIM_TRGO_CC1IF
3384 * @arg @ref LL_TIM_TRGO_OC1REF
3385 * @arg @ref LL_TIM_TRGO_OC2REF
3386 * @arg @ref LL_TIM_TRGO_OC3REF
3387 * @arg @ref LL_TIM_TRGO_OC4REF
3388 * @retval None
3389 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3390 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3391 {
3392 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3393 }
3394
3395 /**
3396 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3397 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3398 * whether or not a timer instance can be used for ADC synchronization.
3399 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3400 * @param TIMx Timer Instance
3401 * @param ADCSynchronization This parameter can be one of the following values:
3402 * @arg @ref LL_TIM_TRGO2_RESET
3403 * @arg @ref LL_TIM_TRGO2_ENABLE
3404 * @arg @ref LL_TIM_TRGO2_UPDATE
3405 * @arg @ref LL_TIM_TRGO2_CC1F
3406 * @arg @ref LL_TIM_TRGO2_OC1
3407 * @arg @ref LL_TIM_TRGO2_OC2
3408 * @arg @ref LL_TIM_TRGO2_OC3
3409 * @arg @ref LL_TIM_TRGO2_OC4
3410 * @arg @ref LL_TIM_TRGO2_OC5
3411 * @arg @ref LL_TIM_TRGO2_OC6
3412 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3413 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3414 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3415 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3416 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3417 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3418 * @retval None
3419 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3420 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3421 {
3422 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3423 }
3424
3425 /**
3426 * @brief Set the synchronization mode of a slave timer.
3427 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3428 * a timer instance can operate as a slave timer.
3429 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3430 * @param TIMx Timer instance
3431 * @param SlaveMode This parameter can be one of the following values:
3432 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3433 * @arg @ref LL_TIM_SLAVEMODE_RESET
3434 * @arg @ref LL_TIM_SLAVEMODE_GATED
3435 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3436 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3437 * @retval None
3438 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3439 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3440 {
3441 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3442 }
3443
3444 /**
3445 * @brief Set the selects the trigger input to be used to synchronize the counter.
3446 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3447 * a timer instance can operate as a slave timer.
3448 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3449 * @param TIMx Timer instance
3450 * @param TriggerInput This parameter can be one of the following values:
3451 * @arg @ref LL_TIM_TS_ITR0
3452 * @arg @ref LL_TIM_TS_ITR1
3453 * @arg @ref LL_TIM_TS_ITR2
3454 * @arg @ref LL_TIM_TS_ITR3
3455 * @arg @ref LL_TIM_TS_ITR7 (*)
3456 * @arg @ref LL_TIM_TS_TI1F_ED
3457 * @arg @ref LL_TIM_TS_TI1FP1
3458 * @arg @ref LL_TIM_TS_TI2FP2
3459 * @arg @ref LL_TIM_TS_ETRF
3460 *
3461 * (*) Value not defined in all devices.
3462 * @retval None
3463 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3464 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3465 {
3466 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3467 }
3468
3469 /**
3470 * @brief Enable the Master/Slave mode.
3471 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3472 * a timer instance can operate as a slave timer.
3473 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3474 * @param TIMx Timer instance
3475 * @retval None
3476 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3477 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3478 {
3479 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3480 }
3481
3482 /**
3483 * @brief Disable the Master/Slave mode.
3484 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3485 * a timer instance can operate as a slave timer.
3486 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3487 * @param TIMx Timer instance
3488 * @retval None
3489 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3490 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3491 {
3492 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3493 }
3494
3495 /**
3496 * @brief Indicates whether the Master/Slave mode is enabled.
3497 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3498 * a timer instance can operate as a slave timer.
3499 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3500 * @param TIMx Timer instance
3501 * @retval State of bit (1 or 0).
3502 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3503 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3504 {
3505 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3506 }
3507
3508 /**
3509 * @brief Configure the external trigger (ETR) input.
3510 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3511 * a timer instance provides an external trigger input.
3512 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3513 * SMCR ETPS LL_TIM_ConfigETR\n
3514 * SMCR ETF LL_TIM_ConfigETR
3515 * @param TIMx Timer instance
3516 * @param ETRPolarity This parameter can be one of the following values:
3517 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3518 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3519 * @param ETRPrescaler This parameter can be one of the following values:
3520 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3521 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3522 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3523 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3524 * @param ETRFilter This parameter can be one of the following values:
3525 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3526 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3527 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3528 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3529 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3530 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3531 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3532 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3533 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3534 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3535 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3536 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3537 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3538 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3539 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3540 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3541 * @retval None
3542 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3543 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3544 uint32_t ETRFilter)
3545 {
3546 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3547 }
3548
3549 /**
3550 * @brief Select the external trigger (ETR) input source.
3551 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3552 * not a timer instance supports ETR source selection.
3553 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3554 * @param TIMx Timer instance
3555 * @param ETRSource This parameter can be one of the following values:
3556 * TIM1
3557 *
3558 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3559 * @arg @ref LL_TIM_ETRSOURCE_COMP1 (**)
3560 * @arg @ref LL_TIM_ETRSOURCE_COMP2 (**)
3561 * @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
3562 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
3563 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2
3564 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3
3565 *
3566 * TIM2 (*)
3567 *
3568 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3569 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3570 * @arg @ref LL_TIM_ETRSOURCE_COMP2
3571 * @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
3572 * @arg @ref LL_TIM_ETRSOURCE_LSE
3573 * @arg @ref LL_TIM_ETRSOURCE_MCO (**)
3574 * @arg @ref LL_TIM_ETRSOURCE_MCO2 (**)
3575 *
3576 * TIM3
3577 *
3578 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3579 * @arg @ref LL_TIM_ETRSOURCE_COMP1 (**)
3580 * @arg @ref LL_TIM_ETRSOURCE_COMP2 (**)
3581 * @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
3582 *
3583 * TIM4 (*)
3584 *
3585 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3586 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3587 * @arg @ref LL_TIM_ETRSOURCE_COMP2
3588 * @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
3589 *
3590 * (*) Timer instance not available on all devices \n
3591 * (**) Value not defined in all devices. \n
3592 *
3593 * @retval None
3594 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3595 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3596 {
3597 #if defined(COMP3)
3598 uint32_t etrsel_shift = ((ETRSource == LL_TIM_ETRSOURCE_COMP3) ? 1u : 0u);
3599 if ((TIMx == TIM1) || (TIMx == TIM2))
3600 {
3601 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3602 }
3603 else
3604 {
3605 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource >> etrsel_shift);
3606 }
3607 #else
3608 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3609 #endif /* COMP3 */
3610 }
3611
3612 /**
3613 * @}
3614 */
3615
3616 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3617 * @{
3618 */
3619 /**
3620 * @brief Enable the break function.
3621 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3622 * a timer instance provides a break input.
3623 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3624 * @param TIMx Timer instance
3625 * @retval None
3626 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3627 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3628 {
3629 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3630 }
3631
3632 /**
3633 * @brief Disable the break function.
3634 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3635 * @param TIMx Timer instance
3636 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3637 * a timer instance provides a break input.
3638 * @retval None
3639 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3640 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3641 {
3642 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3643 }
3644
3645 /**
3646 * @brief Configure the break input.
3647 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3648 * a timer instance provides a break input.
3649 * @note Bidirectional mode is only supported by advanced timer instances.
3650 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3651 * a timer instance is an advanced-control timer.
3652 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3653 * in input mode and in open drain output mode. Any active Break event will
3654 * assert a low logic level on the Break input to indicate an internal break
3655 * event to external devices.
3656 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3657 * LL_TIM_BREAK_AFMODE_INPUT.
3658 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3659 * BDTR BKF LL_TIM_ConfigBRK\n
3660 * BDTR BKBID LL_TIM_ConfigBRK
3661 * @param TIMx Timer instance
3662 * @param BreakPolarity This parameter can be one of the following values:
3663 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3664 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3665 * @param BreakFilter This parameter can be one of the following values:
3666 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3667 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3668 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3669 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3670 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3671 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3672 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3673 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3674 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3675 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3676 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3677 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3678 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3679 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3680 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3681 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3682 * @param BreakAFMode This parameter can be one of the following values:
3683 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3684 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3685 * @retval None
3686 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3687 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3688 uint32_t BreakAFMode)
3689 {
3690 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3691 }
3692
3693 /**
3694 * @brief Disarm the break input (when it operates in bidirectional mode).
3695 * @note The break input can be disarmed only when it is configured in
3696 * bidirectional mode and when when MOE is reset.
3697 * @note Purpose is to be able to have the input voltage back to high-state,
3698 * whatever the time constant on the output .
3699 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3700 * @param TIMx Timer instance
3701 * @retval None
3702 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3703 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3704 {
3705 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3706 }
3707
3708 /**
3709 * @brief Re-arm the break input (when it operates in bidirectional mode).
3710 * @note The Break input is automatically armed as soon as MOE bit is set.
3711 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
3712 * @param TIMx Timer instance
3713 * @retval None
3714 */
LL_TIM_ReArmBRK(TIM_TypeDef * TIMx)3715 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
3716 {
3717 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3718 }
3719
3720 /**
3721 * @brief Enable the break 2 function.
3722 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3723 * a timer instance provides a second break input.
3724 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3725 * @param TIMx Timer instance
3726 * @retval None
3727 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3728 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3729 {
3730 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3731 }
3732
3733 /**
3734 * @brief Disable the break 2 function.
3735 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3736 * a timer instance provides a second break input.
3737 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3738 * @param TIMx Timer instance
3739 * @retval None
3740 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3741 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3742 {
3743 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3744 }
3745
3746 /**
3747 * @brief Configure the break 2 input.
3748 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3749 * a timer instance provides a second break input.
3750 * @note Bidirectional mode is only supported by advanced timer instances.
3751 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3752 * a timer instance is an advanced-control timer.
3753 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3754 * in input mode and in open drain output mode. Any active Break event will
3755 * assert a low logic level on the Break 2 input to indicate an internal break
3756 * event to external devices.
3757 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3758 * LL_TIM_BREAK2_AFMODE_INPUT.
3759 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3760 * BDTR BK2F LL_TIM_ConfigBRK2\n
3761 * BDTR BK2BID LL_TIM_ConfigBRK2
3762 * @param TIMx Timer instance
3763 * @param Break2Polarity This parameter can be one of the following values:
3764 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3765 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3766 * @param Break2Filter This parameter can be one of the following values:
3767 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3768 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3769 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3770 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3771 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3772 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3773 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3774 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3775 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3776 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3777 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3778 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3779 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3780 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3781 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3782 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3783 * @param Break2AFMode This parameter can be one of the following values:
3784 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3785 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3786 * @retval None
3787 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)3788 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3789 uint32_t Break2AFMode)
3790 {
3791 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3792 }
3793
3794 /**
3795 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
3796 * @note The break 2 input can be disarmed only when it is configured in
3797 * bidirectional mode and when when MOE is reset.
3798 * @note Purpose is to be able to have the input voltage back to high-state,
3799 * whatever the time constant on the output.
3800 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3801 * @param TIMx Timer instance
3802 * @retval None
3803 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)3804 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3805 {
3806 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3807 }
3808
3809 /**
3810 * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
3811 * @note The Break 2 input is automatically armed as soon as MOE bit is set.
3812 * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
3813 * @param TIMx Timer instance
3814 * @retval None
3815 */
LL_TIM_ReArmBRK2(TIM_TypeDef * TIMx)3816 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
3817 {
3818 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3819 }
3820
3821 /**
3822 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3823 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3824 * a timer instance provides a break input.
3825 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3826 * BDTR OSSR LL_TIM_SetOffStates
3827 * @param TIMx Timer instance
3828 * @param OffStateIdle This parameter can be one of the following values:
3829 * @arg @ref LL_TIM_OSSI_DISABLE
3830 * @arg @ref LL_TIM_OSSI_ENABLE
3831 * @param OffStateRun This parameter can be one of the following values:
3832 * @arg @ref LL_TIM_OSSR_DISABLE
3833 * @arg @ref LL_TIM_OSSR_ENABLE
3834 * @retval None
3835 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3836 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3837 {
3838 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3839 }
3840
3841 /**
3842 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3843 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3844 * a timer instance provides a break input.
3845 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3846 * @param TIMx Timer instance
3847 * @retval None
3848 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3849 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3850 {
3851 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3852 }
3853
3854 /**
3855 * @brief Disable automatic output (MOE can be set only by software).
3856 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3857 * a timer instance provides a break input.
3858 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3859 * @param TIMx Timer instance
3860 * @retval None
3861 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3862 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3863 {
3864 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3865 }
3866
3867 /**
3868 * @brief Indicate whether automatic output is enabled.
3869 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3870 * a timer instance provides a break input.
3871 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3872 * @param TIMx Timer instance
3873 * @retval State of bit (1 or 0).
3874 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3875 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3876 {
3877 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3878 }
3879
3880 /**
3881 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3882 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3883 * software and is reset in case of break or break2 event
3884 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3885 * a timer instance provides a break input.
3886 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3887 * @param TIMx Timer instance
3888 * @retval None
3889 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3890 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3891 {
3892 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3893 }
3894
3895 /**
3896 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3897 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3898 * software and is reset in case of break or break2 event.
3899 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3900 * a timer instance provides a break input.
3901 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3902 * @param TIMx Timer instance
3903 * @retval None
3904 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3905 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3906 {
3907 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3908 }
3909
3910 /**
3911 * @brief Indicates whether outputs are enabled.
3912 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3913 * a timer instance provides a break input.
3914 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3915 * @param TIMx Timer instance
3916 * @retval State of bit (1 or 0).
3917 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3918 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3919 {
3920 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3921 }
3922
3923 /**
3924 * @brief Enable the signals connected to the designated timer break input.
3925 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3926 * or not a timer instance allows for break input selection.
3927 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3928 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
3929 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
3930 * AF1 BKCMP3E LL_TIM_EnableBreakInputSource\n
3931 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3932 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3933 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3934 * AF2 BK2CMP3E LL_TIM_EnableBreakInputSource
3935 * @param TIMx Timer instance
3936 * @param BreakInput This parameter can be one of the following values:
3937 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3938 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3939 * @param Source This parameter can be one of the following values:
3940 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3941 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3942 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3943 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
3944 *
3945 * (*) Value not defined in all devices. \n
3946 *
3947 * @retval None
3948 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3949 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3950 {
3951 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3952 SET_BIT(*pReg, Source);
3953 }
3954
3955 /**
3956 * @brief Disable the signals connected to the designated timer break input.
3957 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3958 * or not a timer instance allows for break input selection.
3959 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3960 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
3961 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
3962 * AF1 BKCMP3E LL_TIM_DisableBreakInputSource\n
3963 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3964 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3965 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3966 * AF2 BK2CMP3E LL_TIM_DisableBreakInputSource
3967 * @param TIMx Timer instance
3968 * @param BreakInput This parameter can be one of the following values:
3969 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3970 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3971 * @param Source This parameter can be one of the following values:
3972 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3973 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3974 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3975 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
3976 *
3977 * (*) Value not defined in all devices. \n
3978 *
3979 * @retval None
3980 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3981 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3982 {
3983 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3984 CLEAR_BIT(*pReg, Source);
3985 }
3986
3987 /**
3988 * @brief Set the polarity of the break signal for the timer break input.
3989 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3990 * or not a timer instance allows for break input selection.
3991 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3992 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3993 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3994 * AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity\n
3995 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3996 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3997 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity\n
3998 * AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity
3999 * @param TIMx Timer instance
4000 * @param BreakInput This parameter can be one of the following values:
4001 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4002 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4003 * @param Source This parameter can be one of the following values:
4004 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4005 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4006 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4007 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
4008 * @param Polarity This parameter can be one of the following values:
4009 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4010 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4011 *
4012 * (*) Value not defined in all devices. \n
4013 *
4014 * @retval None
4015 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)4016 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4017 uint32_t Polarity)
4018 {
4019 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4020 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4021 }
4022 /**
4023 * @}
4024 */
4025
4026 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4027 * @{
4028 */
4029 /**
4030 * @brief Configures the timer DMA burst feature.
4031 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4032 * not a timer instance supports the DMA burst mode.
4033 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4034 * DCR DBA LL_TIM_ConfigDMABurst
4035 * @param TIMx Timer instance
4036 * @param DMABurstBaseAddress This parameter can be one of the following values:
4037 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4038 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4039 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4040 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4041 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4042 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4043 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4044 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4045 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4046 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4047 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4048 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4049 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4050 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4051 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4052 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4053 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4054 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4055 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
4056 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4057 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4058 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4059 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4060 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4061 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4062 * @param DMABurstLength This parameter can be one of the following values:
4063 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4064 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4065 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4066 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4067 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4068 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4069 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4070 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4071 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4072 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4073 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4074 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4075 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4076 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4077 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4078 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4079 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4080 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4081 * @retval None
4082 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)4083 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
4084 {
4085 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
4086 }
4087
4088 /**
4089 * @}
4090 */
4091
4092 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
4093 * @{
4094 */
4095 /**
4096 * @brief Remap TIM inputs (input channel, internal/external triggers).
4097 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
4098 * a some timer inputs can be remapped.
4099 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
4100 * TIM1_TISEL TI2SEL LL_TIM_SetRemap\n
4101 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
4102 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
4103 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
4104 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
4105 * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
4106 * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
4107 * TIM4_TISEL TI3SEL LL_TIM_SetRemap\n
4108 * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n
4109 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
4110 * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
4111 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
4112 * TIM17_TISEL TI1SEL LL_TIM_SetRemap
4113 * @param TIMx Timer instance
4114 * @param Remap Remap param depends on the TIMx. Description available only
4115 * in CHM version of the User Manual (not in .pdf).
4116 * Otherwise see Reference Manual description of TISEL registers.
4117 *
4118 * Below description summarizes "Timer Instance" and "Remap" param combinations:
4119 *
4120 * TIM1: any combination of TI1_RMP and TI2_RMP where
4121 *
4122 * . . TI1_RMP can be one of the following values
4123 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
4124 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 (**)
4125 *
4126 * . . TI2_RMP can be one of the following values
4127 * @arg @ref LL_TIM_TIM1_TI2_RMP_GPIO
4128 * @arg @ref LL_TIM_TIM1_TI2_RMP_COMP2 (**)
4129 *
4130 * . . TI3_RMP can be one of the following values
4131 * @arg @ref LL_TIM_TIM1_TI3_RMP_GPIO
4132 * @arg @ref LL_TIM_TIM1_TI3_RMP_COMP3 (**)
4133 *
4134 * TIM2: any combination of TI1_RMP and TI2_RMP where
4135 *
4136 * . . TI1_RMP can be one of the following values
4137 * @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
4138 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1 (**)
4139 *
4140 * . . TI2_RMP can be one of the following values
4141 * @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
4142 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2 (**)
4143 *
4144 * . . TI3_RMP can be one of the following values
4145 * @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
4146 * @arg @ref LL_TIM_TIM2_TI3_RMP_COMP3 (**)
4147 *
4148 * TIM3: any combination of TI1_RMP and TI2_RMP where
4149 *
4150 * . . TI1_RMP can be one of the following values
4151 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
4152 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1 (**)
4153 *
4154 * . . TI2_RMP can be one of the following values
4155 * @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
4156 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2 (**)
4157 *
4158 * . . TI3_RMP can be one of the following values
4159 * @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
4160 * @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3 (**)
4161 *
4162 * TIM4: any combination of TI1_RMP, TI2_RMP and TI3_RMP where (*)
4163 *
4164 * . . TI1_RMP can be one of the following values
4165 * @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
4166 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1 (**)
4167 *
4168 * . . TI2_RMP can be one of the following values
4169 * @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
4170 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2 (**)
4171 *
4172 * . . TI3_RMP can be one of the following values
4173 * @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
4174 * @arg @ref LL_TIM_TIM4_TI3_RMP_COMP3 (**)
4175 *
4176 * TIM14: one of the following values
4177 *
4178 * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
4179 * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
4180 * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE_32
4181 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
4182 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO2 (**)
4183 *
4184 * TIM15: any combination of TI1_RMP and TI2_RMP where
4185 *
4186 * . . TI1_RMP can be one of the following values
4187 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
4188 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_IC1
4189 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_IC1
4190 *
4191 * . . TI2_RMP can be one of the following values
4192 * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
4193 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_IC2
4194 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_IC2
4195 *
4196 * TIM16: one of the following values
4197 *
4198 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
4199 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
4200 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
4201 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
4202 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO2(**)
4203 *
4204 * TIM17: one of the following values
4205 *
4206 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
4207 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
4208 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
4209 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSI48 (**)
4210 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO2(**)
4211 *
4212 * (*) Timer instance not available on all devices \n
4213 * (**) Value not defined in all devices. \n
4214 *
4215 * @retval None
4216 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4217 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4218 {
4219 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
4220 }
4221
4222 /**
4223 * @}
4224 */
4225
4226 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
4227 * @{
4228 */
4229 /**
4230 * @brief Set the OCREF clear input source
4231 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
4232 * @note This function can only be used in Output compare and PWM modes.
4233 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
4234 * @rmtoll OR1 OCREF_CLR LL_TIM_SetOCRefClearInputSource
4235 * @param TIMx Timer instance
4236 * @param OCRefClearInputSource This parameter can be one of the following values:
4237 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4238 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1 (*)
4239 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2 (*)
4240 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP3 (*)
4241 *
4242 * (*) Value not defined in all devices. \n
4243 *
4244 * @retval None
4245 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)4246 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4247 {
4248 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
4249 ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos);
4250 MODIFY_REG(TIMx->OR1, TIM1_OR1_OCREF_CLR, OCRefClearInputSource);
4251 }
4252 /**
4253 * @}
4254 */
4255
4256 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4257 * @{
4258 */
4259 /**
4260 * @brief Clear the update interrupt flag (UIF).
4261 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4262 * @param TIMx Timer instance
4263 * @retval None
4264 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4265 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4266 {
4267 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4268 }
4269
4270 /**
4271 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4272 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4273 * @param TIMx Timer instance
4274 * @retval State of bit (1 or 0).
4275 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4276 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4277 {
4278 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4279 }
4280
4281 /**
4282 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4283 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4284 * @param TIMx Timer instance
4285 * @retval None
4286 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4287 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4288 {
4289 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4290 }
4291
4292 /**
4293 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4294 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4295 * @param TIMx Timer instance
4296 * @retval State of bit (1 or 0).
4297 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4298 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4299 {
4300 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4301 }
4302
4303 /**
4304 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4305 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4306 * @param TIMx Timer instance
4307 * @retval None
4308 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4309 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4310 {
4311 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4312 }
4313
4314 /**
4315 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4316 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4317 * @param TIMx Timer instance
4318 * @retval State of bit (1 or 0).
4319 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4320 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4321 {
4322 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4323 }
4324
4325 /**
4326 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4327 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4328 * @param TIMx Timer instance
4329 * @retval None
4330 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4331 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4332 {
4333 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4334 }
4335
4336 /**
4337 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4338 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4339 * @param TIMx Timer instance
4340 * @retval State of bit (1 or 0).
4341 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4342 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4343 {
4344 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4345 }
4346
4347 /**
4348 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4349 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4350 * @param TIMx Timer instance
4351 * @retval None
4352 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4353 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4354 {
4355 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4356 }
4357
4358 /**
4359 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4360 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4361 * @param TIMx Timer instance
4362 * @retval State of bit (1 or 0).
4363 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4364 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4365 {
4366 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4367 }
4368
4369 /**
4370 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4371 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4372 * @param TIMx Timer instance
4373 * @retval None
4374 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4375 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4376 {
4377 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4378 }
4379
4380 /**
4381 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4382 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4383 * @param TIMx Timer instance
4384 * @retval State of bit (1 or 0).
4385 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4386 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4387 {
4388 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4389 }
4390
4391 /**
4392 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4393 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4394 * @param TIMx Timer instance
4395 * @retval None
4396 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4397 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4398 {
4399 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4400 }
4401
4402 /**
4403 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4404 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4405 * @param TIMx Timer instance
4406 * @retval State of bit (1 or 0).
4407 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4408 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4409 {
4410 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4411 }
4412
4413 /**
4414 * @brief Clear the commutation interrupt flag (COMIF).
4415 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4416 * @param TIMx Timer instance
4417 * @retval None
4418 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4419 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4420 {
4421 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4422 }
4423
4424 /**
4425 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4426 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4427 * @param TIMx Timer instance
4428 * @retval State of bit (1 or 0).
4429 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4430 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4431 {
4432 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4433 }
4434
4435 /**
4436 * @brief Clear the trigger interrupt flag (TIF).
4437 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4438 * @param TIMx Timer instance
4439 * @retval None
4440 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4441 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4442 {
4443 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4444 }
4445
4446 /**
4447 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4448 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4449 * @param TIMx Timer instance
4450 * @retval State of bit (1 or 0).
4451 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4452 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4453 {
4454 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4455 }
4456
4457 /**
4458 * @brief Clear the break interrupt flag (BIF).
4459 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4460 * @param TIMx Timer instance
4461 * @retval None
4462 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4463 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4464 {
4465 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4466 }
4467
4468 /**
4469 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4470 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4471 * @param TIMx Timer instance
4472 * @retval State of bit (1 or 0).
4473 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4474 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4475 {
4476 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4477 }
4478
4479 /**
4480 * @brief Clear the break 2 interrupt flag (B2IF).
4481 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4482 * @param TIMx Timer instance
4483 * @retval None
4484 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4485 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4486 {
4487 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4488 }
4489
4490 /**
4491 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4492 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4493 * @param TIMx Timer instance
4494 * @retval State of bit (1 or 0).
4495 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4496 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4497 {
4498 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4499 }
4500
4501 /**
4502 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4503 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4504 * @param TIMx Timer instance
4505 * @retval None
4506 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4507 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4508 {
4509 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4510 }
4511
4512 /**
4513 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4514 * (Capture/Compare 1 interrupt is pending).
4515 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4516 * @param TIMx Timer instance
4517 * @retval State of bit (1 or 0).
4518 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4519 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4520 {
4521 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4522 }
4523
4524 /**
4525 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4526 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4527 * @param TIMx Timer instance
4528 * @retval None
4529 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4530 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4531 {
4532 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4533 }
4534
4535 /**
4536 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4537 * (Capture/Compare 2 over-capture interrupt is pending).
4538 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4539 * @param TIMx Timer instance
4540 * @retval State of bit (1 or 0).
4541 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4542 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4543 {
4544 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4545 }
4546
4547 /**
4548 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4549 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4550 * @param TIMx Timer instance
4551 * @retval None
4552 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4553 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4554 {
4555 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4556 }
4557
4558 /**
4559 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4560 * (Capture/Compare 3 over-capture interrupt is pending).
4561 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4562 * @param TIMx Timer instance
4563 * @retval State of bit (1 or 0).
4564 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4565 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4566 {
4567 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4568 }
4569
4570 /**
4571 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4572 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4573 * @param TIMx Timer instance
4574 * @retval None
4575 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4576 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4577 {
4578 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4579 }
4580
4581 /**
4582 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4583 * (Capture/Compare 4 over-capture interrupt is pending).
4584 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4585 * @param TIMx Timer instance
4586 * @retval State of bit (1 or 0).
4587 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4588 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4589 {
4590 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4591 }
4592
4593 /**
4594 * @brief Clear the system break interrupt flag (SBIF).
4595 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4596 * @param TIMx Timer instance
4597 * @retval None
4598 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4599 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4600 {
4601 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4602 }
4603
4604 /**
4605 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4606 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4607 * @param TIMx Timer instance
4608 * @retval State of bit (1 or 0).
4609 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4610 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4611 {
4612 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4613 }
4614
4615 /**
4616 * @}
4617 */
4618
4619 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4620 * @{
4621 */
4622 /**
4623 * @brief Enable update interrupt (UIE).
4624 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4625 * @param TIMx Timer instance
4626 * @retval None
4627 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4628 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4629 {
4630 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4631 }
4632
4633 /**
4634 * @brief Disable update interrupt (UIE).
4635 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4636 * @param TIMx Timer instance
4637 * @retval None
4638 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4639 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4640 {
4641 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4642 }
4643
4644 /**
4645 * @brief Indicates whether the update interrupt (UIE) is enabled.
4646 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4647 * @param TIMx Timer instance
4648 * @retval State of bit (1 or 0).
4649 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4650 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4651 {
4652 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4653 }
4654
4655 /**
4656 * @brief Enable capture/compare 1 interrupt (CC1IE).
4657 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4658 * @param TIMx Timer instance
4659 * @retval None
4660 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4661 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4662 {
4663 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4664 }
4665
4666 /**
4667 * @brief Disable capture/compare 1 interrupt (CC1IE).
4668 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4669 * @param TIMx Timer instance
4670 * @retval None
4671 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4672 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4673 {
4674 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4675 }
4676
4677 /**
4678 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4679 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4680 * @param TIMx Timer instance
4681 * @retval State of bit (1 or 0).
4682 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4683 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4684 {
4685 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4686 }
4687
4688 /**
4689 * @brief Enable capture/compare 2 interrupt (CC2IE).
4690 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4691 * @param TIMx Timer instance
4692 * @retval None
4693 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4694 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4695 {
4696 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4697 }
4698
4699 /**
4700 * @brief Disable capture/compare 2 interrupt (CC2IE).
4701 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4702 * @param TIMx Timer instance
4703 * @retval None
4704 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4705 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4706 {
4707 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4708 }
4709
4710 /**
4711 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4712 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4713 * @param TIMx Timer instance
4714 * @retval State of bit (1 or 0).
4715 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4716 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4717 {
4718 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4719 }
4720
4721 /**
4722 * @brief Enable capture/compare 3 interrupt (CC3IE).
4723 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4724 * @param TIMx Timer instance
4725 * @retval None
4726 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4727 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4728 {
4729 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4730 }
4731
4732 /**
4733 * @brief Disable capture/compare 3 interrupt (CC3IE).
4734 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4735 * @param TIMx Timer instance
4736 * @retval None
4737 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4738 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4739 {
4740 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4741 }
4742
4743 /**
4744 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4745 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4746 * @param TIMx Timer instance
4747 * @retval State of bit (1 or 0).
4748 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4749 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4750 {
4751 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4752 }
4753
4754 /**
4755 * @brief Enable capture/compare 4 interrupt (CC4IE).
4756 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4757 * @param TIMx Timer instance
4758 * @retval None
4759 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4760 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4761 {
4762 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4763 }
4764
4765 /**
4766 * @brief Disable capture/compare 4 interrupt (CC4IE).
4767 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4768 * @param TIMx Timer instance
4769 * @retval None
4770 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4771 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4772 {
4773 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4774 }
4775
4776 /**
4777 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4778 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4779 * @param TIMx Timer instance
4780 * @retval State of bit (1 or 0).
4781 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4782 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4783 {
4784 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4785 }
4786
4787 /**
4788 * @brief Enable commutation interrupt (COMIE).
4789 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4790 * @param TIMx Timer instance
4791 * @retval None
4792 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4793 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4794 {
4795 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4796 }
4797
4798 /**
4799 * @brief Disable commutation interrupt (COMIE).
4800 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4801 * @param TIMx Timer instance
4802 * @retval None
4803 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4804 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4805 {
4806 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4807 }
4808
4809 /**
4810 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4811 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4812 * @param TIMx Timer instance
4813 * @retval State of bit (1 or 0).
4814 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4815 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4816 {
4817 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4818 }
4819
4820 /**
4821 * @brief Enable trigger interrupt (TIE).
4822 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4823 * @param TIMx Timer instance
4824 * @retval None
4825 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4826 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4827 {
4828 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4829 }
4830
4831 /**
4832 * @brief Disable trigger interrupt (TIE).
4833 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4834 * @param TIMx Timer instance
4835 * @retval None
4836 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4837 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4838 {
4839 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4840 }
4841
4842 /**
4843 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4844 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4845 * @param TIMx Timer instance
4846 * @retval State of bit (1 or 0).
4847 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4848 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4849 {
4850 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4851 }
4852
4853 /**
4854 * @brief Enable break interrupt (BIE).
4855 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4856 * @param TIMx Timer instance
4857 * @retval None
4858 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4859 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4860 {
4861 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4862 }
4863
4864 /**
4865 * @brief Disable break interrupt (BIE).
4866 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4867 * @param TIMx Timer instance
4868 * @retval None
4869 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4870 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4871 {
4872 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4873 }
4874
4875 /**
4876 * @brief Indicates whether the break interrupt (BIE) is enabled.
4877 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4878 * @param TIMx Timer instance
4879 * @retval State of bit (1 or 0).
4880 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4881 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4882 {
4883 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4884 }
4885
4886 /**
4887 * @}
4888 */
4889
4890 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4891 * @{
4892 */
4893 /**
4894 * @brief Enable update DMA request (UDE).
4895 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4896 * @param TIMx Timer instance
4897 * @retval None
4898 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4899 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4900 {
4901 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4902 }
4903
4904 /**
4905 * @brief Disable update DMA request (UDE).
4906 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4907 * @param TIMx Timer instance
4908 * @retval None
4909 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4910 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4911 {
4912 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4913 }
4914
4915 /**
4916 * @brief Indicates whether the update DMA request (UDE) is enabled.
4917 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4918 * @param TIMx Timer instance
4919 * @retval State of bit (1 or 0).
4920 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4921 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4922 {
4923 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4924 }
4925
4926 /**
4927 * @brief Enable capture/compare 1 DMA request (CC1DE).
4928 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4929 * @param TIMx Timer instance
4930 * @retval None
4931 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4932 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4933 {
4934 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4935 }
4936
4937 /**
4938 * @brief Disable capture/compare 1 DMA request (CC1DE).
4939 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4940 * @param TIMx Timer instance
4941 * @retval None
4942 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4943 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4944 {
4945 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4946 }
4947
4948 /**
4949 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4950 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4951 * @param TIMx Timer instance
4952 * @retval State of bit (1 or 0).
4953 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4954 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4955 {
4956 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4957 }
4958
4959 /**
4960 * @brief Enable capture/compare 2 DMA request (CC2DE).
4961 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4962 * @param TIMx Timer instance
4963 * @retval None
4964 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4965 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4966 {
4967 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4968 }
4969
4970 /**
4971 * @brief Disable capture/compare 2 DMA request (CC2DE).
4972 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4973 * @param TIMx Timer instance
4974 * @retval None
4975 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4976 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4977 {
4978 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4979 }
4980
4981 /**
4982 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4983 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4984 * @param TIMx Timer instance
4985 * @retval State of bit (1 or 0).
4986 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4987 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4988 {
4989 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4990 }
4991
4992 /**
4993 * @brief Enable capture/compare 3 DMA request (CC3DE).
4994 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4995 * @param TIMx Timer instance
4996 * @retval None
4997 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4998 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4999 {
5000 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
5001 }
5002
5003 /**
5004 * @brief Disable capture/compare 3 DMA request (CC3DE).
5005 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
5006 * @param TIMx Timer instance
5007 * @retval None
5008 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)5009 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
5010 {
5011 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
5012 }
5013
5014 /**
5015 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
5016 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
5017 * @param TIMx Timer instance
5018 * @retval State of bit (1 or 0).
5019 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)5020 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
5021 {
5022 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
5023 }
5024
5025 /**
5026 * @brief Enable capture/compare 4 DMA request (CC4DE).
5027 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
5028 * @param TIMx Timer instance
5029 * @retval None
5030 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)5031 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
5032 {
5033 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
5034 }
5035
5036 /**
5037 * @brief Disable capture/compare 4 DMA request (CC4DE).
5038 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
5039 * @param TIMx Timer instance
5040 * @retval None
5041 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)5042 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
5043 {
5044 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
5045 }
5046
5047 /**
5048 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
5049 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
5050 * @param TIMx Timer instance
5051 * @retval State of bit (1 or 0).
5052 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)5053 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
5054 {
5055 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
5056 }
5057
5058 /**
5059 * @brief Enable commutation DMA request (COMDE).
5060 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
5061 * @param TIMx Timer instance
5062 * @retval None
5063 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)5064 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
5065 {
5066 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
5067 }
5068
5069 /**
5070 * @brief Disable commutation DMA request (COMDE).
5071 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
5072 * @param TIMx Timer instance
5073 * @retval None
5074 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)5075 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
5076 {
5077 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
5078 }
5079
5080 /**
5081 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
5082 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
5083 * @param TIMx Timer instance
5084 * @retval State of bit (1 or 0).
5085 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)5086 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
5087 {
5088 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
5089 }
5090
5091 /**
5092 * @brief Enable trigger interrupt (TDE).
5093 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
5094 * @param TIMx Timer instance
5095 * @retval None
5096 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)5097 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
5098 {
5099 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
5100 }
5101
5102 /**
5103 * @brief Disable trigger interrupt (TDE).
5104 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
5105 * @param TIMx Timer instance
5106 * @retval None
5107 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)5108 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
5109 {
5110 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
5111 }
5112
5113 /**
5114 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
5115 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
5116 * @param TIMx Timer instance
5117 * @retval State of bit (1 or 0).
5118 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)5119 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
5120 {
5121 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
5122 }
5123
5124 /**
5125 * @}
5126 */
5127
5128 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
5129 * @{
5130 */
5131 /**
5132 * @brief Generate an update event.
5133 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
5134 * @param TIMx Timer instance
5135 * @retval None
5136 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)5137 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
5138 {
5139 SET_BIT(TIMx->EGR, TIM_EGR_UG);
5140 }
5141
5142 /**
5143 * @brief Generate Capture/Compare 1 event.
5144 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
5145 * @param TIMx Timer instance
5146 * @retval None
5147 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)5148 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
5149 {
5150 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
5151 }
5152
5153 /**
5154 * @brief Generate Capture/Compare 2 event.
5155 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
5156 * @param TIMx Timer instance
5157 * @retval None
5158 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)5159 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
5160 {
5161 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
5162 }
5163
5164 /**
5165 * @brief Generate Capture/Compare 3 event.
5166 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
5167 * @param TIMx Timer instance
5168 * @retval None
5169 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)5170 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
5171 {
5172 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
5173 }
5174
5175 /**
5176 * @brief Generate Capture/Compare 4 event.
5177 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
5178 * @param TIMx Timer instance
5179 * @retval None
5180 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)5181 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
5182 {
5183 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
5184 }
5185
5186 /**
5187 * @brief Generate commutation event.
5188 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
5189 * @param TIMx Timer instance
5190 * @retval None
5191 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)5192 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
5193 {
5194 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
5195 }
5196
5197 /**
5198 * @brief Generate trigger event.
5199 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
5200 * @param TIMx Timer instance
5201 * @retval None
5202 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)5203 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
5204 {
5205 SET_BIT(TIMx->EGR, TIM_EGR_TG);
5206 }
5207
5208 /**
5209 * @brief Generate break event.
5210 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
5211 * @param TIMx Timer instance
5212 * @retval None
5213 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)5214 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
5215 {
5216 SET_BIT(TIMx->EGR, TIM_EGR_BG);
5217 }
5218
5219 /**
5220 * @brief Generate break 2 event.
5221 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
5222 * @param TIMx Timer instance
5223 * @retval None
5224 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)5225 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
5226 {
5227 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
5228 }
5229
5230 /**
5231 * @}
5232 */
5233
5234 #if defined(USE_FULL_LL_DRIVER)
5235 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
5236 * @{
5237 */
5238
5239 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
5240 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
5241 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
5242 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5243 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5244 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
5245 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
5246 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5247 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5248 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5249 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5250 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5251 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5252 /**
5253 * @}
5254 */
5255 #endif /* USE_FULL_LL_DRIVER */
5256
5257 /**
5258 * @}
5259 */
5260
5261 /**
5262 * @}
5263 */
5264
5265 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
5266
5267 /**
5268 * @}
5269 */
5270
5271 #ifdef __cplusplus
5272 }
5273 #endif
5274
5275 #endif /* __STM32G0xx_LL_TIM_H */
5276
