1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef STM32L4xx_LL_RCC_H
20 #define STM32L4xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32l4xx.h"
28
29 /** @addtogroup STM32L4xx_LL_Driver
30 * @{
31 */
32
33 #if defined(RCC)
34
35 /** @defgroup RCC_LL RCC
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
43 * @{
44 */
45 /* Defines used to perform offsets*/
46 /* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
47 #define RCC_OFFSET_CCIPR 0U
48 #define RCC_OFFSET_CCIPR2 0x14U
49
50 /**
51 * @}
52 */
53
54 /* Private macros ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
57 * @{
58 */
59 /**
60 * @}
61 */
62 #endif /*USE_FULL_LL_DRIVER*/
63
64 /* Exported types ------------------------------------------------------------*/
65 #if defined(USE_FULL_LL_DRIVER)
66 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
67 * @{
68 */
69
70 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
71 * @{
72 */
73
74 /**
75 * @brief RCC Clocks Frequency Structure
76 */
77 typedef struct
78 {
79 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
80 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
81 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
82 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
83 } LL_RCC_ClocksTypeDef;
84
85 /**
86 * @}
87 */
88
89 /**
90 * @}
91 */
92 #endif /* USE_FULL_LL_DRIVER */
93
94 /* Exported constants --------------------------------------------------------*/
95 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
96 * @{
97 */
98
99 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
100 * @brief Defines used to adapt values of different oscillators
101 * @note These values could be modified in the user environment according to
102 * HW set-up.
103 * @{
104 */
105 #if !defined (HSE_VALUE)
106 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
107 #endif /* HSE_VALUE */
108
109 #if !defined (HSI_VALUE)
110 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
111 #endif /* HSI_VALUE */
112
113 #if !defined (LSE_VALUE)
114 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
115 #endif /* LSE_VALUE */
116
117 #if !defined (LSI_VALUE)
118 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
119 #endif /* LSI_VALUE */
120 #if defined(RCC_HSI48_SUPPORT)
121
122 #if !defined (HSI48_VALUE)
123 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
124 #endif /* HSI48_VALUE */
125 #endif /* RCC_HSI48_SUPPORT */
126
127 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
128 #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
129 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
130
131 #if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
132 #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */
133 #endif /* EXTERNAL_SAI2_CLOCK_VALUE */
134 /**
135 * @}
136 */
137
138 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
139 * @brief Flags defines which can be used with LL_RCC_WriteReg function
140 * @{
141 */
142 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
143 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
144 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
145 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
146 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
147 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
148 #if defined(RCC_HSI48_SUPPORT)
149 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
150 #endif /* RCC_HSI48_SUPPORT */
151 #if defined(RCC_PLLSAI1_SUPPORT)
152 #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
153 #endif /* RCC_PLLSAI1_SUPPORT */
154 #if defined(RCC_PLLSAI2_SUPPORT)
155 #define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */
156 #endif /* RCC_PLLSAI2_SUPPORT */
157 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
158 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
159 /**
160 * @}
161 */
162
163 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
164 * @brief Flags defines which can be used with LL_RCC_ReadReg function
165 * @{
166 */
167 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
168 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
169 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
170 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
171 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
172 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
173 #if defined(RCC_HSI48_SUPPORT)
174 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
175 #endif /* RCC_HSI48_SUPPORT */
176 #if defined(RCC_PLLSAI1_SUPPORT)
177 #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
178 #endif /* RCC_PLLSAI1_SUPPORT */
179 #if defined(RCC_PLLSAI2_SUPPORT)
180 #define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
181 #endif /* RCC_PLLSAI2_SUPPORT */
182 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
183 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
184 #define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */
185 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
186 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
187 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
188 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
189 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
190 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
191 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
192 /**
193 * @}
194 */
195
196 /** @defgroup RCC_LL_EC_IT IT Defines
197 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
198 * @{
199 */
200 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
201 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
202 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
203 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
204 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
205 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
206 #if defined(RCC_HSI48_SUPPORT)
207 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
208 #endif /* RCC_HSI48_SUPPORT */
209 #if defined(RCC_PLLSAI1_SUPPORT)
210 #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */
211 #endif /* RCC_PLLSAI1_SUPPORT */
212 #if defined(RCC_PLLSAI2_SUPPORT)
213 #define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /*!< PLLSAI2 Ready Interrupt Enable */
214 #endif /* RCC_PLLSAI2_SUPPORT */
215 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
216 /**
217 * @}
218 */
219
220 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
221 * @{
222 */
223 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
224 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
225 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
226 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
227 /**
228 * @}
229 */
230
231 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
232 * @{
233 */
234 #define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
235 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
236 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
237 #define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
238 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
239 #define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
240 #define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
241 #define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
242 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
243 #define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
244 #define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
245 #define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
246 /**
247 * @}
248 */
249
250 /** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
251 * @{
252 */
253 #define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /*!< MSI = 1 MHz */
254 #define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /*!< MSI = 2 MHz */
255 #define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /*!< MSI = 4 MHz */
256 #define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /*!< MSI = 8 MHz */
257 /**
258 * @}
259 */
260
261 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
262 * @{
263 */
264 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
265 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
266 /**
267 * @}
268 */
269
270 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
271 * @{
272 */
273 #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
274 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
275 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
276 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
277 /**
278 * @}
279 */
280
281 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
282 * @{
283 */
284 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
285 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
286 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
287 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
288 /**
289 * @}
290 */
291
292 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
293 * @{
294 */
295 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
296 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
297 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
298 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
299 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
300 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
301 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
302 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
303 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
304 /**
305 * @}
306 */
307
308 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
309 * @{
310 */
311 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
312 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
313 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
314 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
315 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
316 /**
317 * @}
318 */
319
320 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
321 * @{
322 */
323 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
324 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
325 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
326 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
327 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
328 /**
329 * @}
330 */
331
332 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
333 * @{
334 */
335 #define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
336 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
337 /**
338 * @}
339 */
340
341 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
342 * @{
343 */
344 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
345 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
346 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
347 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
348 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
349 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
350 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
351 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
352 #if defined(RCC_HSI48_SUPPORT)
353 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
354 #endif /* RCC_HSI48_SUPPORT */
355 /**
356 * @}
357 */
358
359 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
360 * @{
361 */
362 #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
363 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
364 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
365 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
366 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
367 /**
368 * @}
369 */
370
371 #if defined(USE_FULL_LL_DRIVER)
372 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
373 * @{
374 */
375 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
376 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
377 /**
378 * @}
379 */
380 #endif /* USE_FULL_LL_DRIVER */
381
382 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
383 * @{
384 */
385 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
386 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
387 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
388 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
389 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
390 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
391 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
392 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
393 #if defined(RCC_CCIPR_USART3SEL)
394 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */
395 #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
396 #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
397 #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
398 #endif /* RCC_CCIPR_USART3SEL */
399 /**
400 * @}
401 */
402
403 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
404 /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
405 * @{
406 */
407 #if defined(RCC_CCIPR_UART4SEL)
408 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */
409 #define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
410 #define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
411 #define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */
412 #endif /* RCC_CCIPR_UART4SEL */
413 #if defined(RCC_CCIPR_UART5SEL)
414 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */
415 #define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
416 #define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
417 #define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */
418 #endif /* RCC_CCIPR_UART5SEL */
419 /**
420 * @}
421 */
422 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
423
424 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
425 * @{
426 */
427 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */
428 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
429 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
430 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */
431 /**
432 * @}
433 */
434
435 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
436 * @{
437 */
438 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
439 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
440 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
441 #if defined(RCC_CCIPR_I2C2SEL)
442 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
443 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
444 #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
445 #endif /* RCC_CCIPR_I2C2SEL */
446 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
447 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
448 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
449 #if defined(RCC_CCIPR2_I2C4SEL)
450 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
451 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
452 #define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
453 #endif /* RCC_CCIPR2_I2C4SEL */
454 /**
455 * @}
456 */
457
458 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
459 * @{
460 */
461 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM1SEL /*!< PCLK1 clock used as LPTIM1 clock source */
462 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI clock used as LPTIM1 clock source */
463 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI clock used as LPTIM1 clock source */
464 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) /*!< LSE clock used as LPTIM1 clock source */
465 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM2SEL /*!< PCLK1 clock used as LPTIM2 clock source */
466 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI clock used as LPTIM2 clock source */
467 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI clock used as LPTIM2 clock source */
468 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) /*!< LSE clock used as LPTIM2 clock source */
469 /**
470 * @}
471 */
472
473 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
474 * @{
475 */
476 #if defined(RCC_CCIPR2_SAI1SEL)
477 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLLSAI1 (PLLSAI1CLK) clock used as SAI1 clock source */
478 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI2 (PLLSAI2CLK) clock used as SAI1 clock source */
479 #define LL_RCC_SAI1_CLKSOURCE_PLL ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLL (PLLSAI3CLK) clock used as SAI1 clock source */
480 #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */
481 #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */
482 #elif defined(RCC_CCIPR_SAI1SEL)
483 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /*!< PLLSAI1 clock used as SAI1 clock source */
484 #if defined(RCC_PLLSAI2_SUPPORT)
485 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI1 clock source */
486 #endif /* RCC_PLLSAI2_SUPPORT */
487 #define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16U)) /*!< PLL clock used as SAI1 clock source */
488 #define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16U)) /*!< External input clock used as SAI1 clock source */
489 #endif /* RCC_CCIPR2_SAI1SEL */
490
491 #if defined(RCC_CCIPR2_SAI2SEL)
492 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLLSAI1 (PLLSAI1CLK) clock used as SAI2 clock source */
493 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI2 (PLLSAI2CLK) clock used as SAI2 clock source */
494 #define LL_RCC_SAI2_CLKSOURCE_PLL ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLL (PLLSAI3CLK) clock used as SAI2 clock source */
495 #define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */
496 #define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */
497 #elif defined(RCC_CCIPR_SAI2SEL)
498 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /*!< PLLSAI1 clock used as SAI2 clock source */
499 #if defined(RCC_PLLSAI2_SUPPORT)
500 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI2 clock source */
501 #endif /* RCC_PLLSAI2_SUPPORT */
502 #define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16U)) /*!< PLL clock used as SAI2 clock source */
503 #define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16U)) /*!< External input clock used as SAI2 clock source */
504 #endif /* RCC_CCIPR2_SAI2SEL */
505 /**
506 * @}
507 */
508
509 #if defined(RCC_CCIPR2_SDMMCSEL)
510 /** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection
511 * @{
512 */
513 #define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */
514 #define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLLSAI3CLK clock used as SDMMC1 clock source */
515 /**
516 * @}
517 */
518 #endif /* RCC_CCIPR2_SDMMCSEL */
519
520 #if defined(SDMMC1)
521 /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
522 * @{
523 */
524 #if defined(RCC_HSI48_SUPPORT)
525 #define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1 clock source */
526 #else
527 #define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U /*!< No clock used as SDMMC1 clock source */
528 #endif
529 #if defined(RCC_PLLSAI1_SUPPORT)
530 #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source */
531 #endif /* RCC_PLLSAI1_SUPPORT */
532 #define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as SDMMC1 clock source */
533 #define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as SDMMC1 clock source */
534 /**
535 * @}
536 */
537 #endif /* SDMMC1 */
538
539 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
540 * @{
541 */
542 #if defined(RCC_HSI48_SUPPORT)
543 #define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */
544 #else
545 #define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock source */
546 #endif
547 #if defined(RCC_PLLSAI1_SUPPORT)
548 #define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as RNG clock source */
549 #endif /* RCC_PLLSAI1_SUPPORT */
550 #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */
551 #define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as RNG clock source */
552 /**
553 * @}
554 */
555
556 #if defined(USB_OTG_FS) || defined(USB)
557 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
558 * @{
559 */
560 #if defined(RCC_HSI48_SUPPORT)
561 #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
562 #else
563 #define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /*!< No clock used as USB clock source */
564 #endif
565 #if defined(RCC_PLLSAI1_SUPPORT)
566 #define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as USB clock source */
567 #endif /* RCC_PLLSAI1_SUPPORT */
568 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */
569 #define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as USB clock source */
570 /**
571 * @}
572 */
573
574 #endif /* USB_OTG_FS || USB */
575
576 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
577 * @{
578 */
579 #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as ADC clock source */
580 #if defined(RCC_PLLSAI1_SUPPORT)
581 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */
582 #endif /* RCC_PLLSAI1_SUPPORT */
583 #if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC)
584 #define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /*!< PLLSAI2 clock used as ADC clock source */
585 #endif /* RCC_PLLSAI2_SUPPORT */
586 #if defined(RCC_CCIPR_ADCSEL)
587 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK clock used as ADC clock source */
588 #else
589 #define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x30000000U /*!< SYSCLK clock used as ADC clock source */
590 #endif
591 /**
592 * @}
593 */
594
595 #if defined(SWPMI1)
596 /** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI1 clock source selection
597 * @{
598 */
599 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 used as SWPMI1 clock source */
600 #define LL_RCC_SWPMI1_CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /*!< HSI used as SWPMI1 clock source */
601 /**
602 * @}
603 */
604 #endif /* SWPMI1 */
605
606 #if defined(DFSDM1_Channel0)
607 #if defined(RCC_CCIPR2_ADFSDM1SEL)
608 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM1 Audio clock source selection
609 * @{
610 */
611 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */
612 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 /*!< HSI clock used as DFSDM1 Audio clock */
613 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /*!< MSI clock used as DFSDM1 Audio clock */
614 /**
615 * @}
616 */
617 #endif /* RCC_CCIPR2_ADFSDM1SEL */
618
619 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection
620 * @{
621 */
622 #if defined(RCC_CCIPR2_DFSDM1SEL)
623 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */
624 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */
625 #else
626 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */
627 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */
628 #endif /* RCC_CCIPR2_DFSDM1SEL */
629 /**
630 * @}
631 */
632 #endif /* DFSDM1_Channel0 */
633
634 #if defined(DSI)
635 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
636 * @{
637 */
638 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
639 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */
640 /**
641 * @}
642 */
643 #endif /* DSI */
644
645 #if defined(LTDC)
646 /** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection
647 * @{
648 */
649 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U /*!< PLLSAI2DIVR divided by 2 used as LTDC clock source */
650 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2DIVR divided by 4 used as LTDC clock source */
651 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2DIVR divided by 8 used as LTDC clock source */
652 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR /*!< PLLSAI2DIVR divided by 16 used as LTDC clock source */
653 /**
654 * @}
655 */
656 #endif /* LTDC */
657
658 #if defined(OCTOSPI1)
659 /** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
660 * @{
661 */
662 #define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as OctoSPI clock source */
663 #define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI used as OctoSPI clock source */
664 #define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL used as OctoSPI clock source */
665 /**
666 * @}
667 */
668 #endif /* OCTOSPI1 */
669
670 /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
671 * @{
672 */
673 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
674 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
675 #if defined(RCC_CCIPR_USART3SEL)
676 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
677 #endif /* RCC_CCIPR_USART3SEL */
678 /**
679 * @}
680 */
681
682 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
683 /** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
684 * @{
685 */
686 #if defined(RCC_CCIPR_UART4SEL)
687 #define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
688 #endif /* RCC_CCIPR_UART4SEL */
689 #if defined(RCC_CCIPR_UART5SEL)
690 #define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
691 #endif /* RCC_CCIPR_UART5SEL */
692 /**
693 * @}
694 */
695 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
696
697 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
698 * @{
699 */
700 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
701 /**
702 * @}
703 */
704
705 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
706 * @{
707 */
708 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
709 #if defined(RCC_CCIPR_I2C2SEL)
710 #define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
711 #endif /* RCC_CCIPR_I2C2SEL */
712 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
713 #if defined(RCC_CCIPR2_I2C4SEL)
714 #define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
715 #endif /* RCC_CCIPR2_I2C4SEL */
716 /**
717 * @}
718 */
719
720 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
721 * @{
722 */
723 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
724 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */
725 /**
726 * @}
727 */
728
729 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
730 /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
731 * @{
732 */
733 #if defined(RCC_CCIPR2_SAI1SEL)
734 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */
735 #else
736 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
737 #endif /* RCC_CCIPR2_SAI1SEL */
738 #if defined(RCC_CCIPR2_SAI2SEL)
739 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */
740 #elif defined(RCC_CCIPR_SAI2SEL)
741 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */
742 #endif /* RCC_CCIPR2_SAI2SEL */
743 /**
744 * @}
745 */
746 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */
747
748 #if defined(SDMMC1)
749 #if defined(RCC_CCIPR2_SDMMCSEL)
750 /** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source
751 * @{
752 */
753 #define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Kernel Clock source selection */
754 /**
755 * @}
756 */
757 #endif /* RCC_CCIPR2_SDMMCSEL */
758
759 /** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source
760 * @{
761 */
762 #define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< SDMMC1 Clock source selection */
763 /**
764 * @}
765 */
766 #endif /* SDMMC1 */
767
768 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
769 * @{
770 */
771 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
772 /**
773 * @}
774 */
775
776 #if defined(USB_OTG_FS) || defined(USB)
777 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
778 * @{
779 */
780 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
781 /**
782 * @}
783 */
784 #endif /* USB_OTG_FS || USB */
785
786 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
787 * @{
788 */
789 #if defined(RCC_CCIPR_ADCSEL)
790 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */
791 #else
792 #define LL_RCC_ADC_CLKSOURCE 0x30000000U /*!< ADC Clock source selection */
793 #endif
794 /**
795 * @}
796 */
797
798 #if defined(SWPMI1)
799 /** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI1 get clock source
800 * @{
801 */
802 #define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /*!< SWPMI1 Clock source selection */
803 /**
804 * @}
805 */
806 #endif /* SWPMI1 */
807
808 #if defined(DFSDM1_Channel0)
809 #if defined(RCC_CCIPR2_ADFSDM1SEL)
810 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO Peripheral DFSDM1 Audio get clock source
811 * @{
812 */
813 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */
814 /**
815 * @}
816 */
817
818 #endif /* RCC_CCIPR2_ADFSDM1SEL */
819 /** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source
820 * @{
821 */
822 #if defined(RCC_CCIPR2_DFSDM1SEL)
823 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL /*!< DFSDM1 Clock source selection */
824 #else
825 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */
826 #endif /* RCC_CCIPR2_DFSDM1SEL */
827 /**
828 * @}
829 */
830 #endif /* DFSDM1_Channel0 */
831
832 #if defined(DSI)
833 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
834 * @{
835 */
836 #define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL /*!< DSI Clock source selection */
837 /**
838 * @}
839 */
840 #endif /* DSI */
841
842 #if defined(LTDC)
843 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
844 * @{
845 */
846 #define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR /*!< LTDC Clock source selection */
847 /**
848 * @}
849 */
850 #endif /* LTDC */
851
852 #if defined(OCTOSPI1)
853 /** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
854 * @{
855 */
856 #define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /*!< OctoSPI Clock source selection */
857 /**
858 * @}
859 */
860 #endif /* OCTOSPI1 */
861
862
863 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
864 * @{
865 */
866 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
867 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
868 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
869 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
870 /**
871 * @}
872 */
873
874
875 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source
876 * @{
877 */
878 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
879 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */
880 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
881 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
882 /**
883 * @}
884 */
885
886 /** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
887 * @{
888 */
889 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< Main PLL division factor for PLLM input by 1 */
890 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 2 */
891 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 3 */
892 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 4 */
893 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 5 */
894 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 6 */
895 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 7 */
896 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 8 */
897 #if defined(RCC_PLLM_DIV_1_16_SUPPORT)
898 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /*!< Main PLL division factor for PLLM input by 9 */
899 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 10 */
900 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 11 */
901 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 12 */
902 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 13 */
903 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 14 */
904 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 15 */
905 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 16 */
906 #endif /* RCC_PLLM_DIV_1_16_SUPPORT */
907 /**
908 * @}
909 */
910
911 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
912 * @{
913 */
914 #define LL_RCC_PLLR_DIV_2 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
915 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
916 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
917 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
918 /**
919 * @}
920 */
921
922 #if defined(RCC_PLLP_SUPPORT)
923 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
924 * @{
925 */
926 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
927 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */
928 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */
929 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */
930 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */
931 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */
932 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */
933 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */
934 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */
935 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */
936 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */
937 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */
938 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */
939 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */
940 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */
941 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */
942 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */
943 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */
944 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */
945 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */
946 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */
947 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */
948 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */
949 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */
950 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */
951 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */
952 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */
953 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */
954 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */
955 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */
956 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */
957 #else
958 #define LL_RCC_PLLP_DIV_7 0x00000000U /*!< Main PLL division factor for PLLP output by 7 */
959 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /*!< Main PLL division factor for PLLP output by 17 */
960 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
961 /**
962 * @}
963 */
964 #endif /* RCC_PLLP_SUPPORT */
965
966 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
967 * @{
968 */
969 #define LL_RCC_PLLQ_DIV_2 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */
970 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
971 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
972 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
973 /**
974 * @}
975 */
976
977 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
978 /** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M)
979 * @{
980 */
981 #define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */
982 #define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 2 */
983 #define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 3 */
984 #define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 4 */
985 #define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 5 */
986 #define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 6 */
987 #define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 7 */
988 #define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 8 */
989 #define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /*!< PLLSAI1 division factor for PLLSAI1M input by 9 */
990 #define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 10 */
991 #define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 11 */
992 #define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 12 */
993 #define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 13 */
994 #define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 14 */
995 #define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 15 */
996 #define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 16 */
997 /**
998 * @}
999 */
1000 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
1001
1002 #if defined(RCC_PLLSAI1_SUPPORT)
1003 /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
1004 * @{
1005 */
1006 #define LL_RCC_PLLSAI1Q_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
1007 #define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
1008 #define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
1009 #define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
1010 /**
1011 * @}
1012 */
1013
1014 /** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P)
1015 * @{
1016 */
1017 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
1018 #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */
1019 #define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */
1020 #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */
1021 #define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */
1022 #define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */
1023 #define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
1024 #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */
1025 #define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */
1026 #define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */
1027 #define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */
1028 #define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */
1029 #define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */
1030 #define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */
1031 #define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */
1032 #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */
1033 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
1034 #define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */
1035 #define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */
1036 #define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */
1037 #define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */
1038 #define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */
1039 #define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */
1040 #define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */
1041 #define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */
1042 #define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */
1043 #define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */
1044 #define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */
1045 #define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */
1046 #define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */
1047 #define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
1048 #else
1049 #define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
1050 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
1051 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
1052 /**
1053 * @}
1054 */
1055
1056 /** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R)
1057 * @{
1058 */
1059 #define LL_RCC_PLLSAI1R_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
1060 #define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
1061 #define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
1062 #define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
1063 /**
1064 * @}
1065 */
1066 #endif /* RCC_PLLSAI1_SUPPORT */
1067
1068 #if defined(RCC_PLLSAI2_SUPPORT)
1069 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1070 /** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI1 division factor (PLLSAI2M)
1071 * @{
1072 */
1073 #define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */
1074 #define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 2 */
1075 #define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 3 */
1076 #define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 4 */
1077 #define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 5 */
1078 #define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 6 */
1079 #define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 7 */
1080 #define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 8 */
1081 #define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /*!< PLLSAI2 division factor for PLLSAI2M input by 9 */
1082 #define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 10 */
1083 #define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 11 */
1084 #define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 12 */
1085 #define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 13 */
1086 #define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 14 */
1087 #define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 15 */
1088 #define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 16 */
1089 /**
1090 * @}
1091 */
1092 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
1093
1094 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
1095 /** @defgroup RCC_LL_EC_PLLSAI2Q PLLSAI2 division factor (PLLSAI2Q)
1096 * @{
1097 */
1098 #define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2Q output by 2 */
1099 #define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /*!< PLLSAI2 division factor for PLLSAI2Q output by 4 */
1100 #define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /*!< PLLSAI2 division factor for PLLSAI2Q output by 6 */
1101 #define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q) /*!< PLLSAI2 division factor for PLLSAI2Q output by 8 */
1102 /**
1103 * @}
1104 */
1105 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
1106
1107 /** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P)
1108 * @{
1109 */
1110 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
1111 #define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 2 */
1112 #define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 3 */
1113 #define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 4 */
1114 #define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 5 */
1115 #define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 6 */
1116 #define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */
1117 #define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 8 */
1118 #define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 9 */
1119 #define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 10 */
1120 #define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 1 */
1121 #define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 12 */
1122 #define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 13 */
1123 #define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 14 */
1124 #define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 15 */
1125 #define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /*!< PLLSAI2 division factor for PLLSAI2P output by 16 */
1126 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */
1127 #define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 18 */
1128 #define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 19 */
1129 #define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 20 */
1130 #define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division fctor for PLLSAI2P output by 21 */
1131 #define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 22 */
1132 #define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 23 */
1133 #define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 24 */
1134 #define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 25 */
1135 #define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 26 */
1136 #define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 27 */
1137 #define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 28 */
1138 #define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 29 */
1139 #define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 30 */
1140 #define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
1141 #else
1142 #define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */
1143 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */
1144 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
1145 /**
1146 * @}
1147 */
1148
1149 /** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R)
1150 * @{
1151 */
1152 #define LL_RCC_PLLSAI2R_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2R output by 2 */
1153 #define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /*!< PLLSAI2 division factor for PLLSAI2R output by 4 */
1154 #define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /*!< PLLSAI2 division factor for PLLSAI2R output by 6 */
1155 #define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /*!< PLLSAI2 division factor for PLLSAI2R output by 8 */
1156 /**
1157 * @}
1158 */
1159
1160 #if defined(RCC_CCIPR2_PLLSAI2DIVR)
1161 /** @defgroup RCC_LL_EC_PLLSAI2DIVR PLLSAI2DIVR division factor (PLLSAI2DIVR)
1162 * @{
1163 */
1164 #define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 */
1165 #define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 */
1166 #define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 */
1167 #define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 | RCC_CCIPR2_PLLSAI2DIVR_0) /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 */
1168 /**
1169 * @}
1170 */
1171 #endif /* RCC_CCIPR2_PLLSAI2DIVR */
1172 #endif /* RCC_PLLSAI2_SUPPORT */
1173
1174 /** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
1175 * @{
1176 */
1177 #define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */
1178 #define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */
1179 /**
1180 * @}
1181 */
1182
1183 #if defined(RCC_CSR_LSIPREDIV)
1184 /** @defgroup RCC_LL_EC_LSIPREDIV LSI division factor
1185 * @{
1186 */
1187 #define LL_RCC_LSI_PREDIV_1 0x00000000U /*!< LSI division factor by 1 */
1188 #define LL_RCC_LSI_PREDIV_128 RCC_CSR_LSIPREDIV /*!< LSI division factor by 128 */
1189 /**
1190 * @}
1191 */
1192 #endif /* RCC_CSR_LSIPREDIV */
1193
1194 /** Legacy definitions for compatibility purpose
1195 @cond 0
1196 */
1197 #if defined(DFSDM1_Channel0)
1198 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
1199 #define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
1200 #define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
1201 #define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE
1202 #endif /* DFSDM1_Channel0 */
1203 #if defined(SWPMI1)
1204 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK LL_RCC_SWPMI1_CLKSOURCE_PCLK1
1205 #endif /* SWPMI1 */
1206 /**
1207 @endcond
1208 */
1209
1210 /**
1211 * @}
1212 */
1213
1214 /* Exported macro ------------------------------------------------------------*/
1215 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1216 * @{
1217 */
1218
1219 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1220 * @{
1221 */
1222
1223 /**
1224 * @brief Write a value in RCC register
1225 * @param __REG__ Register to be written
1226 * @param __VALUE__ Value to be written in the register
1227 * @retval None
1228 */
1229 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1230
1231 /**
1232 * @brief Read a value in RCC register
1233 * @param __REG__ Register to be read
1234 * @retval Register value
1235 */
1236 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1237 /**
1238 * @}
1239 */
1240
1241 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1242 * @{
1243 */
1244
1245 /**
1246 * @brief Helper macro to calculate the PLLCLK frequency on system domain
1247 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1248 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1249 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1250 * @param __PLLM__ This parameter can be one of the following values:
1251 * @arg @ref LL_RCC_PLLM_DIV_1
1252 * @arg @ref LL_RCC_PLLM_DIV_2
1253 * @arg @ref LL_RCC_PLLM_DIV_3
1254 * @arg @ref LL_RCC_PLLM_DIV_4
1255 * @arg @ref LL_RCC_PLLM_DIV_5
1256 * @arg @ref LL_RCC_PLLM_DIV_6
1257 * @arg @ref LL_RCC_PLLM_DIV_7
1258 * @arg @ref LL_RCC_PLLM_DIV_8
1259 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
1260 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
1261 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
1262 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
1263 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
1264 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
1265 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
1266 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
1267 *
1268 * (*) value not defined in all devices.
1269 * @param __PLLN__ Between 8 and 86 or 127 depending on devices
1270 * @param __PLLR__ This parameter can be one of the following values:
1271 * @arg @ref LL_RCC_PLLR_DIV_2
1272 * @arg @ref LL_RCC_PLLR_DIV_4
1273 * @arg @ref LL_RCC_PLLR_DIV_6
1274 * @arg @ref LL_RCC_PLLR_DIV_8
1275 * @retval PLL clock frequency (in Hz)
1276 */
1277 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1278 ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
1279
1280 #if defined(RCC_PLLSAI1_SUPPORT)
1281 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
1282 /**
1283 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
1284 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1285 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1286 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1287 * @param __PLLM__ This parameter can be one of the following values:
1288 * @arg @ref LL_RCC_PLLM_DIV_1
1289 * @arg @ref LL_RCC_PLLM_DIV_2
1290 * @arg @ref LL_RCC_PLLM_DIV_3
1291 * @arg @ref LL_RCC_PLLM_DIV_4
1292 * @arg @ref LL_RCC_PLLM_DIV_5
1293 * @arg @ref LL_RCC_PLLM_DIV_6
1294 * @arg @ref LL_RCC_PLLM_DIV_7
1295 * @arg @ref LL_RCC_PLLM_DIV_8
1296 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
1297 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
1298 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
1299 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
1300 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
1301 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
1302 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
1303 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
1304 *
1305 * (*) value not defined in all devices.
1306 * @param __PLLN__ Between 8 and 86 or 127 depending on devices
1307 * @param __PLLP__ This parameter can be one of the following values:
1308 * @arg @ref LL_RCC_PLLP_DIV_2
1309 * @arg @ref LL_RCC_PLLP_DIV_3
1310 * @arg @ref LL_RCC_PLLP_DIV_4
1311 * @arg @ref LL_RCC_PLLP_DIV_5
1312 * @arg @ref LL_RCC_PLLP_DIV_6
1313 * @arg @ref LL_RCC_PLLP_DIV_7
1314 * @arg @ref LL_RCC_PLLP_DIV_8
1315 * @arg @ref LL_RCC_PLLP_DIV_9
1316 * @arg @ref LL_RCC_PLLP_DIV_10
1317 * @arg @ref LL_RCC_PLLP_DIV_11
1318 * @arg @ref LL_RCC_PLLP_DIV_12
1319 * @arg @ref LL_RCC_PLLP_DIV_13
1320 * @arg @ref LL_RCC_PLLP_DIV_14
1321 * @arg @ref LL_RCC_PLLP_DIV_15
1322 * @arg @ref LL_RCC_PLLP_DIV_16
1323 * @arg @ref LL_RCC_PLLP_DIV_17
1324 * @arg @ref LL_RCC_PLLP_DIV_18
1325 * @arg @ref LL_RCC_PLLP_DIV_19
1326 * @arg @ref LL_RCC_PLLP_DIV_20
1327 * @arg @ref LL_RCC_PLLP_DIV_21
1328 * @arg @ref LL_RCC_PLLP_DIV_22
1329 * @arg @ref LL_RCC_PLLP_DIV_23
1330 * @arg @ref LL_RCC_PLLP_DIV_24
1331 * @arg @ref LL_RCC_PLLP_DIV_25
1332 * @arg @ref LL_RCC_PLLP_DIV_26
1333 * @arg @ref LL_RCC_PLLP_DIV_27
1334 * @arg @ref LL_RCC_PLLP_DIV_28
1335 * @arg @ref LL_RCC_PLLP_DIV_29
1336 * @arg @ref LL_RCC_PLLP_DIV_30
1337 * @arg @ref LL_RCC_PLLP_DIV_31
1338 * @retval PLL clock frequency (in Hz)
1339 */
1340 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1341 ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
1342
1343 #else
1344 /**
1345 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
1346 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1347 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1348 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1349 * @param __PLLM__ This parameter can be one of the following values:
1350 * @arg @ref LL_RCC_PLLM_DIV_1
1351 * @arg @ref LL_RCC_PLLM_DIV_2
1352 * @arg @ref LL_RCC_PLLM_DIV_3
1353 * @arg @ref LL_RCC_PLLM_DIV_4
1354 * @arg @ref LL_RCC_PLLM_DIV_5
1355 * @arg @ref LL_RCC_PLLM_DIV_6
1356 * @arg @ref LL_RCC_PLLM_DIV_7
1357 * @arg @ref LL_RCC_PLLM_DIV_8
1358 * @param __PLLN__ Between 8 and 86
1359 * @param __PLLP__ This parameter can be one of the following values:
1360 * @arg @ref LL_RCC_PLLP_DIV_7
1361 * @arg @ref LL_RCC_PLLP_DIV_17
1362 * @retval PLL clock frequency (in Hz)
1363 */
1364 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1365 (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U))
1366
1367 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
1368 #endif /* RCC_PLLSAI1_SUPPORT */
1369
1370 /**
1371 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
1372 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1373 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1374 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1375 * @param __PLLM__ This parameter can be one of the following values:
1376 * @arg @ref LL_RCC_PLLM_DIV_1
1377 * @arg @ref LL_RCC_PLLM_DIV_2
1378 * @arg @ref LL_RCC_PLLM_DIV_3
1379 * @arg @ref LL_RCC_PLLM_DIV_4
1380 * @arg @ref LL_RCC_PLLM_DIV_5
1381 * @arg @ref LL_RCC_PLLM_DIV_6
1382 * @arg @ref LL_RCC_PLLM_DIV_7
1383 * @arg @ref LL_RCC_PLLM_DIV_8
1384 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
1385 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
1386 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
1387 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
1388 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
1389 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
1390 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
1391 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
1392 *
1393 * (*) value not defined in all devices.
1394 * @param __PLLN__ Between 8 and 86 or 127 depending on devices
1395 * @param __PLLQ__ This parameter can be one of the following values:
1396 * @arg @ref LL_RCC_PLLQ_DIV_2
1397 * @arg @ref LL_RCC_PLLQ_DIV_4
1398 * @arg @ref LL_RCC_PLLQ_DIV_6
1399 * @arg @ref LL_RCC_PLLQ_DIV_8
1400 * @retval PLL clock frequency (in Hz)
1401 */
1402 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1403 ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
1404
1405 #if defined(RCC_PLLSAI1_SUPPORT)
1406 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
1407 /**
1408 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
1409 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
1410 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
1411 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1412 * @param __PLLSAI1M__ This parameter can be one of the following values:
1413 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
1414 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
1415 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
1416 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
1417 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
1418 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
1419 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
1420 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
1421 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
1422 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
1423 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
1424 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
1425 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
1426 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
1427 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
1428 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
1429 * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices
1430 * @param __PLLSAI1P__ This parameter can be one of the following values:
1431 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
1432 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
1433 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
1434 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
1435 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
1436 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
1437 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
1438 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
1439 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
1440 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
1441 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
1442 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
1443 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
1444 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
1445 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
1446 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
1447 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
1448 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
1449 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
1450 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
1451 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
1452 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
1453 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
1454 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
1455 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
1456 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
1457 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
1458 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
1459 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
1460 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
1461 * @retval PLLSAI1 clock frequency (in Hz)
1462 */
1463 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \
1464 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
1465 ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
1466
1467 #elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
1468 /**
1469 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
1470 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1471 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
1472 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1473 * @param __PLLM__ This parameter can be one of the following values:
1474 * @arg @ref LL_RCC_PLLM_DIV_1
1475 * @arg @ref LL_RCC_PLLM_DIV_2
1476 * @arg @ref LL_RCC_PLLM_DIV_3
1477 * @arg @ref LL_RCC_PLLM_DIV_4
1478 * @arg @ref LL_RCC_PLLM_DIV_5
1479 * @arg @ref LL_RCC_PLLM_DIV_6
1480 * @arg @ref LL_RCC_PLLM_DIV_7
1481 * @arg @ref LL_RCC_PLLM_DIV_8
1482 * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices
1483 * @param __PLLSAI1P__ This parameter can be one of the following values:
1484 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
1485 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
1486 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
1487 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
1488 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
1489 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
1490 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
1491 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
1492 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
1493 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
1494 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
1495 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
1496 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
1497 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
1498 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
1499 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
1500 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
1501 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
1502 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
1503 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
1504 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
1505 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
1506 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
1507 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
1508 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
1509 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
1510 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
1511 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
1512 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
1513 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
1514 * @retval PLLSAI1 clock frequency (in Hz)
1515 */
1516 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
1517 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
1518 ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
1519
1520 #else
1521 /**
1522 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
1523 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1524 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
1525 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1526 * @param __PLLM__ This parameter can be one of the following values:
1527 * @arg @ref LL_RCC_PLLM_DIV_1
1528 * @arg @ref LL_RCC_PLLM_DIV_2
1529 * @arg @ref LL_RCC_PLLM_DIV_3
1530 * @arg @ref LL_RCC_PLLM_DIV_4
1531 * @arg @ref LL_RCC_PLLM_DIV_5
1532 * @arg @ref LL_RCC_PLLM_DIV_6
1533 * @arg @ref LL_RCC_PLLM_DIV_7
1534 * @arg @ref LL_RCC_PLLM_DIV_8
1535 * @param __PLLSAI1N__ Between 8 and 86
1536 * @param __PLLSAI1P__ This parameter can be one of the following values:
1537 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
1538 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
1539 * @retval PLLSAI1 clock frequency (in Hz)
1540 */
1541 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
1542 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
1543 (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U))
1544
1545 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
1546
1547 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
1548 /**
1549 * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
1550 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
1551 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
1552 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1553 * @param __PLLSAI1M__ This parameter can be one of the following values:
1554 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
1555 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
1556 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
1557 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
1558 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
1559 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
1560 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
1561 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
1562 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
1563 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
1564 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
1565 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
1566 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
1567 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
1568 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
1569 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
1570 * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices
1571 * @param __PLLSAI1Q__ This parameter can be one of the following values:
1572 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
1573 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
1574 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
1575 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
1576 * @retval PLLSAI1 clock frequency (in Hz)
1577 */
1578 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \
1579 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
1580 ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
1581
1582 #else
1583 /**
1584 * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
1585 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1586 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
1587 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1588 * @param __PLLM__ This parameter can be one of the following values:
1589 * @arg @ref LL_RCC_PLLM_DIV_1
1590 * @arg @ref LL_RCC_PLLM_DIV_2
1591 * @arg @ref LL_RCC_PLLM_DIV_3
1592 * @arg @ref LL_RCC_PLLM_DIV_4
1593 * @arg @ref LL_RCC_PLLM_DIV_5
1594 * @arg @ref LL_RCC_PLLM_DIV_6
1595 * @arg @ref LL_RCC_PLLM_DIV_7
1596 * @arg @ref LL_RCC_PLLM_DIV_8
1597 * @param __PLLSAI1N__ Between 8 and 86
1598 * @param __PLLSAI1Q__ This parameter can be one of the following values:
1599 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
1600 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
1601 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
1602 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
1603 * @retval PLLSAI1 clock frequency (in Hz)
1604 */
1605 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
1606 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
1607 ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
1608
1609 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
1610
1611 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
1612 /**
1613 * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
1614 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
1615 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
1616 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1617 * @param __PLLSAI1M__ This parameter can be one of the following values:
1618 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
1619 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
1620 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
1621 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
1622 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
1623 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
1624 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
1625 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
1626 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
1627 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
1628 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
1629 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
1630 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
1631 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
1632 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
1633 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
1634 * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices
1635 * @param __PLLSAI1R__ This parameter can be one of the following values:
1636 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
1637 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
1638 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
1639 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
1640 * @retval PLLSAI1 clock frequency (in Hz)
1641 */
1642 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \
1643 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
1644 ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
1645
1646 #else
1647 /**
1648 * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
1649 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1650 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
1651 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1652 * @param __PLLM__ This parameter can be one of the following values:
1653 * @arg @ref LL_RCC_PLLM_DIV_1
1654 * @arg @ref LL_RCC_PLLM_DIV_2
1655 * @arg @ref LL_RCC_PLLM_DIV_3
1656 * @arg @ref LL_RCC_PLLM_DIV_4
1657 * @arg @ref LL_RCC_PLLM_DIV_5
1658 * @arg @ref LL_RCC_PLLM_DIV_6
1659 * @arg @ref LL_RCC_PLLM_DIV_7
1660 * @arg @ref LL_RCC_PLLM_DIV_8
1661 * @param __PLLSAI1N__ Between 8 and 86
1662 * @param __PLLSAI1R__ This parameter can be one of the following values:
1663 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
1664 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
1665 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
1666 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
1667 * @retval PLLSAI1 clock frequency (in Hz)
1668 */
1669 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
1670 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
1671 ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
1672
1673 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
1674 #endif /* RCC_PLLSAI1_SUPPORT */
1675
1676 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
1677 /**
1678 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
1679 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
1680 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
1681 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1682 * @param __PLLSAI2M__ This parameter can be one of the following values:
1683 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
1684 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
1685 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
1686 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
1687 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
1688 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
1689 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
1690 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
1691 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
1692 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
1693 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
1694 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
1695 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
1696 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
1697 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
1698 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
1699 * @param __PLLSAI2N__ Between 8 and 86 or 127 depending on devices
1700 * @param __PLLSAI2P__ This parameter can be one of the following values:
1701 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
1702 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
1703 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
1704 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
1705 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
1706 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
1707 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
1708 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
1709 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
1710 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
1711 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
1712 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
1713 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
1714 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
1715 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
1716 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
1717 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
1718 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
1719 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
1720 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
1721 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
1722 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
1723 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
1724 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
1725 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
1726 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
1727 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
1728 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
1729 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
1730 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
1731 * @retval PLLSAI2 clock frequency (in Hz)
1732 */
1733 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \
1734 ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
1735 ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
1736
1737 #elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
1738 /**
1739 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
1740 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1741 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
1742 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1743 * @param __PLLM__ This parameter can be one of the following values:
1744 * @arg @ref LL_RCC_PLLM_DIV_1
1745 * @arg @ref LL_RCC_PLLM_DIV_2
1746 * @arg @ref LL_RCC_PLLM_DIV_3
1747 * @arg @ref LL_RCC_PLLM_DIV_4
1748 * @arg @ref LL_RCC_PLLM_DIV_5
1749 * @arg @ref LL_RCC_PLLM_DIV_6
1750 * @arg @ref LL_RCC_PLLM_DIV_7
1751 * @arg @ref LL_RCC_PLLM_DIV_8
1752 * @param __PLLSAI2N__ Between 8 and 86 or 127 depending on devices
1753 * @param __PLLSAI2P__ This parameter can be one of the following values:
1754 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
1755 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
1756 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
1757 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
1758 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
1759 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
1760 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
1761 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
1762 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
1763 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
1764 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
1765 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
1766 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
1767 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
1768 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
1769 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
1770 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
1771 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
1772 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
1773 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
1774 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
1775 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
1776 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
1777 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
1778 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
1779 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
1780 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
1781 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
1782 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
1783 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
1784 * @retval PLLSAI2 clock frequency (in Hz)
1785 */
1786 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
1787 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
1788 ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
1789
1790 #else
1791 /**
1792 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
1793 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1794 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
1795 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1796 * @param __PLLM__ This parameter can be one of the following values:
1797 * @arg @ref LL_RCC_PLLM_DIV_1
1798 * @arg @ref LL_RCC_PLLM_DIV_2
1799 * @arg @ref LL_RCC_PLLM_DIV_3
1800 * @arg @ref LL_RCC_PLLM_DIV_4
1801 * @arg @ref LL_RCC_PLLM_DIV_5
1802 * @arg @ref LL_RCC_PLLM_DIV_6
1803 * @arg @ref LL_RCC_PLLM_DIV_7
1804 * @arg @ref LL_RCC_PLLM_DIV_8
1805 * @param __PLLSAI2N__ Between 8 and 86
1806 * @param __PLLSAI2P__ This parameter can be one of the following values:
1807 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
1808 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
1809 * @retval PLLSAI2 clock frequency (in Hz)
1810 */
1811 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
1812 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \
1813 (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))
1814
1815 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
1816
1817 #if defined(LTDC)
1818 /**
1819 * @brief Helper macro to calculate the PLLSAI2 frequency used for LTDC domain
1820 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
1821 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ());
1822 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
1823 * @param __PLLSAI2M__ This parameter can be one of the following values:
1824 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
1825 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
1826 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
1827 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
1828 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
1829 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
1830 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
1831 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
1832 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
1833 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
1834 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
1835 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
1836 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
1837 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
1838 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
1839 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
1840 * @param __PLLSAI2N__ Between 8 and 127
1841 * @param __PLLSAI2R__ This parameter can be one of the following values:
1842 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
1843 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
1844 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
1845 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
1846 * @param __PLLSAI2DIVR__ This parameter can be one of the following values:
1847 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
1848 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
1849 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
1850 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
1851 * @retval PLLSAI2 clock frequency (in Hz)
1852 */
1853 #define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \
1854 (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
1855 (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (2UL << ((__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos))))
1856 #elif defined(RCC_PLLSAI2_SUPPORT)
1857 /**
1858 * @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain
1859 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1860 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ());
1861 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1862 * @param __PLLM__ This parameter can be one of the following values:
1863 * @arg @ref LL_RCC_PLLM_DIV_1
1864 * @arg @ref LL_RCC_PLLM_DIV_2
1865 * @arg @ref LL_RCC_PLLM_DIV_3
1866 * @arg @ref LL_RCC_PLLM_DIV_4
1867 * @arg @ref LL_RCC_PLLM_DIV_5
1868 * @arg @ref LL_RCC_PLLM_DIV_6
1869 * @arg @ref LL_RCC_PLLM_DIV_7
1870 * @arg @ref LL_RCC_PLLM_DIV_8
1871 * @param __PLLSAI2N__ Between 8 and 86
1872 * @param __PLLSAI2R__ This parameter can be one of the following values:
1873 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
1874 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
1875 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
1876 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
1877 * @retval PLLSAI2 clock frequency (in Hz)
1878 */
1879 #define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \
1880 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
1881 ((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U))
1882
1883 #endif /* LTDC */
1884
1885 #if defined(DSI)
1886 /**
1887 * @brief Helper macro to calculate the PLLDSICLK frequency used on DSI
1888 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
1889 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ());
1890 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
1891 * @param __PLLSAI2M__ This parameter can be one of the following values:
1892 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
1893 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
1894 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
1895 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
1896 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
1897 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
1898 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
1899 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
1900 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
1901 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
1902 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
1903 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
1904 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
1905 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
1906 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
1907 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
1908 * @param __PLLSAI2N__ Between 8 and 127
1909 * @param __PLLSAI2Q__ This parameter can be one of the following values:
1910 * @arg @ref LL_RCC_PLLSAI2Q_DIV_2
1911 * @arg @ref LL_RCC_PLLSAI2Q_DIV_4
1912 * @arg @ref LL_RCC_PLLSAI2Q_DIV_6
1913 * @arg @ref LL_RCC_PLLSAI2Q_DIV_8
1914 * @retval PLL clock frequency (in Hz)
1915 */
1916 #define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \
1917 ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
1918 ((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U))
1919 #endif /* DSI */
1920
1921
1922
1923 /**
1924 * @brief Helper macro to calculate the HCLK frequency
1925 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
1926 * @param __AHBPRESCALER__ This parameter can be one of the following values:
1927 * @arg @ref LL_RCC_SYSCLK_DIV_1
1928 * @arg @ref LL_RCC_SYSCLK_DIV_2
1929 * @arg @ref LL_RCC_SYSCLK_DIV_4
1930 * @arg @ref LL_RCC_SYSCLK_DIV_8
1931 * @arg @ref LL_RCC_SYSCLK_DIV_16
1932 * @arg @ref LL_RCC_SYSCLK_DIV_64
1933 * @arg @ref LL_RCC_SYSCLK_DIV_128
1934 * @arg @ref LL_RCC_SYSCLK_DIV_256
1935 * @arg @ref LL_RCC_SYSCLK_DIV_512
1936 * @retval HCLK clock frequency (in Hz)
1937 */
1938 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
1939
1940 /**
1941 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1942 * @param __HCLKFREQ__ HCLK frequency
1943 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1944 * @arg @ref LL_RCC_APB1_DIV_1
1945 * @arg @ref LL_RCC_APB1_DIV_2
1946 * @arg @ref LL_RCC_APB1_DIV_4
1947 * @arg @ref LL_RCC_APB1_DIV_8
1948 * @arg @ref LL_RCC_APB1_DIV_16
1949 * @retval PCLK1 clock frequency (in Hz)
1950 */
1951 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
1952
1953 /**
1954 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1955 * @param __HCLKFREQ__ HCLK frequency
1956 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1957 * @arg @ref LL_RCC_APB2_DIV_1
1958 * @arg @ref LL_RCC_APB2_DIV_2
1959 * @arg @ref LL_RCC_APB2_DIV_4
1960 * @arg @ref LL_RCC_APB2_DIV_8
1961 * @arg @ref LL_RCC_APB2_DIV_16
1962 * @retval PCLK2 clock frequency (in Hz)
1963 */
1964 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
1965
1966 /**
1967 * @brief Helper macro to calculate the MSI frequency (in Hz)
1968 * @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
1969 * @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
1970 * __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
1971 * else by LL_RCC_MSI_GetRange()
1972 * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1973 * (LL_RCC_MSI_IsEnabledRangeSelect()?
1974 * LL_RCC_MSI_GetRange():
1975 * LL_RCC_MSI_GetRangeAfterStandby()))
1976 * @param __MSISEL__ This parameter can be one of the following values:
1977 * @arg @ref LL_RCC_MSIRANGESEL_STANDBY
1978 * @arg @ref LL_RCC_MSIRANGESEL_RUN
1979 * @param __MSIRANGE__ This parameter can be one of the following values:
1980 * @arg @ref LL_RCC_MSIRANGE_0
1981 * @arg @ref LL_RCC_MSIRANGE_1
1982 * @arg @ref LL_RCC_MSIRANGE_2
1983 * @arg @ref LL_RCC_MSIRANGE_3
1984 * @arg @ref LL_RCC_MSIRANGE_4
1985 * @arg @ref LL_RCC_MSIRANGE_5
1986 * @arg @ref LL_RCC_MSIRANGE_6
1987 * @arg @ref LL_RCC_MSIRANGE_7
1988 * @arg @ref LL_RCC_MSIRANGE_8
1989 * @arg @ref LL_RCC_MSIRANGE_9
1990 * @arg @ref LL_RCC_MSIRANGE_10
1991 * @arg @ref LL_RCC_MSIRANGE_11
1992 * @arg @ref LL_RCC_MSISRANGE_4
1993 * @arg @ref LL_RCC_MSISRANGE_5
1994 * @arg @ref LL_RCC_MSISRANGE_6
1995 * @arg @ref LL_RCC_MSISRANGE_7
1996 * @retval MSI clock frequency (in Hz)
1997 */
1998 #define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
1999 (MSIRangeTable[(__MSIRANGE__) >> 8U]) : \
2000 (MSIRangeTable[(__MSIRANGE__) >> 4U]))
2001
2002 /**
2003 * @}
2004 */
2005
2006 /**
2007 * @}
2008 */
2009
2010 /* Exported functions --------------------------------------------------------*/
2011 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
2012 * @{
2013 */
2014
2015 /** @defgroup RCC_LL_EF_HSE HSE
2016 * @{
2017 */
2018
2019 /**
2020 * @brief Enable the Clock Security System.
2021 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
2022 * @retval None
2023 */
LL_RCC_HSE_EnableCSS(void)2024 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
2025 {
2026 SET_BIT(RCC->CR, RCC_CR_CSSON);
2027 }
2028
2029 /**
2030 * @brief Enable HSE external oscillator (HSE Bypass)
2031 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
2032 * @retval None
2033 */
LL_RCC_HSE_EnableBypass(void)2034 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
2035 {
2036 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
2037 }
2038
2039 /**
2040 * @brief Disable HSE external oscillator (HSE Bypass)
2041 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
2042 * @retval None
2043 */
LL_RCC_HSE_DisableBypass(void)2044 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
2045 {
2046 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
2047 }
2048
2049 /**
2050 * @brief Enable HSE crystal oscillator (HSE ON)
2051 * @rmtoll CR HSEON LL_RCC_HSE_Enable
2052 * @retval None
2053 */
LL_RCC_HSE_Enable(void)2054 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
2055 {
2056 SET_BIT(RCC->CR, RCC_CR_HSEON);
2057 }
2058
2059 /**
2060 * @brief Disable HSE crystal oscillator (HSE ON)
2061 * @rmtoll CR HSEON LL_RCC_HSE_Disable
2062 * @retval None
2063 */
LL_RCC_HSE_Disable(void)2064 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
2065 {
2066 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
2067 }
2068
2069 /**
2070 * @brief Check if HSE oscillator Ready
2071 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
2072 * @retval State of bit (1 or 0).
2073 */
LL_RCC_HSE_IsReady(void)2074 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
2075 {
2076 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
2077 }
2078
2079 /**
2080 * @}
2081 */
2082
2083 /** @defgroup RCC_LL_EF_HSI HSI
2084 * @{
2085 */
2086
2087 /**
2088 * @brief Enable HSI even in stop mode
2089 * @note HSI oscillator is forced ON even in Stop mode
2090 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
2091 * @retval None
2092 */
LL_RCC_HSI_EnableInStopMode(void)2093 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
2094 {
2095 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
2096 }
2097
2098 /**
2099 * @brief Disable HSI in stop mode
2100 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
2101 * @retval None
2102 */
LL_RCC_HSI_DisableInStopMode(void)2103 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
2104 {
2105 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
2106 }
2107
2108 /**
2109 * @brief Check if HSI is enabled in stop mode
2110 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
2111 * @retval State of bit (1 or 0).
2112 */
LL_RCC_HSI_IsEnabledInStopMode(void)2113 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
2114 {
2115 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL);
2116 }
2117
2118 /**
2119 * @brief Enable HSI oscillator
2120 * @rmtoll CR HSION LL_RCC_HSI_Enable
2121 * @retval None
2122 */
LL_RCC_HSI_Enable(void)2123 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
2124 {
2125 SET_BIT(RCC->CR, RCC_CR_HSION);
2126 }
2127
2128 /**
2129 * @brief Disable HSI oscillator
2130 * @rmtoll CR HSION LL_RCC_HSI_Disable
2131 * @retval None
2132 */
LL_RCC_HSI_Disable(void)2133 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
2134 {
2135 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
2136 }
2137
2138 /**
2139 * @brief Check if HSI clock is ready
2140 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
2141 * @retval State of bit (1 or 0).
2142 */
LL_RCC_HSI_IsReady(void)2143 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
2144 {
2145 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
2146 }
2147
2148 /**
2149 * @brief Enable HSI Automatic from stop mode
2150 * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
2151 * @retval None
2152 */
LL_RCC_HSI_EnableAutoFromStop(void)2153 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
2154 {
2155 SET_BIT(RCC->CR, RCC_CR_HSIASFS);
2156 }
2157
2158 /**
2159 * @brief Disable HSI Automatic from stop mode
2160 * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
2161 * @retval None
2162 */
LL_RCC_HSI_DisableAutoFromStop(void)2163 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
2164 {
2165 CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
2166 }
2167 /**
2168 * @brief Get HSI Calibration value
2169 * @note When HSITRIM is written, HSICAL is updated with the sum of
2170 * HSITRIM and the factory trim value
2171 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
2172 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
2173 */
LL_RCC_HSI_GetCalibration(void)2174 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
2175 {
2176 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
2177 }
2178
2179 /**
2180 * @brief Set HSI Calibration trimming
2181 * @note user-programmable trimming value that is added to the HSICAL
2182 * @note Default value is 16 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or 64 on other devices,
2183 * which, when added to the HSICAL value, should trim the HSI to 16 MHz +/- 1 %
2184 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
2185 * @param Value Between Min_Data = 0 and Max_Data = 31 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or
2186 * between Min_Data = 0 and Max_Data = 127 on other devices
2187 * @retval None
2188 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)2189 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
2190 {
2191 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
2192 }
2193
2194 /**
2195 * @brief Get HSI Calibration trimming
2196 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
2197 * @retval Between Min_Data = 0 and Max_Data = 31 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or
2198 * between Min_Data = 0 and Max_Data = 127 on other devices
2199 */
LL_RCC_HSI_GetCalibTrimming(void)2200 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
2201 {
2202 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
2203 }
2204
2205 /**
2206 * @}
2207 */
2208
2209 #if defined(RCC_HSI48_SUPPORT)
2210 /** @defgroup RCC_LL_EF_HSI48 HSI48
2211 * @{
2212 */
2213
2214 /**
2215 * @brief Enable HSI48
2216 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
2217 * @retval None
2218 */
LL_RCC_HSI48_Enable(void)2219 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
2220 {
2221 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
2222 }
2223
2224 /**
2225 * @brief Disable HSI48
2226 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
2227 * @retval None
2228 */
LL_RCC_HSI48_Disable(void)2229 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
2230 {
2231 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
2232 }
2233
2234 /**
2235 * @brief Check if HSI48 oscillator Ready
2236 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
2237 * @retval State of bit (1 or 0).
2238 */
LL_RCC_HSI48_IsReady(void)2239 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
2240 {
2241 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY) ? 1UL : 0UL);
2242 }
2243
2244 /**
2245 * @brief Get HSI48 Calibration value
2246 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
2247 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
2248 */
LL_RCC_HSI48_GetCalibration(void)2249 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
2250 {
2251 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
2252 }
2253
2254 /**
2255 * @}
2256 */
2257 #endif /* RCC_HSI48_SUPPORT */
2258
2259 /** @defgroup RCC_LL_EF_LSE LSE
2260 * @{
2261 */
2262
2263 /**
2264 * @brief Enable Low Speed External (LSE) crystal.
2265 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
2266 * @retval None
2267 */
LL_RCC_LSE_Enable(void)2268 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
2269 {
2270 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2271 }
2272
2273 /**
2274 * @brief Disable Low Speed External (LSE) crystal.
2275 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
2276 * @retval None
2277 */
LL_RCC_LSE_Disable(void)2278 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
2279 {
2280 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2281 }
2282
2283 /**
2284 * @brief Enable external clock source (LSE bypass).
2285 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
2286 * @retval None
2287 */
LL_RCC_LSE_EnableBypass(void)2288 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
2289 {
2290 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2291 }
2292
2293 /**
2294 * @brief Disable external clock source (LSE bypass).
2295 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
2296 * @retval None
2297 */
LL_RCC_LSE_DisableBypass(void)2298 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
2299 {
2300 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2301 }
2302
2303 /**
2304 * @brief Set LSE oscillator drive capability
2305 * @note The oscillator is in Xtal mode when it is not in bypass mode.
2306 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
2307 * @param LSEDrive This parameter can be one of the following values:
2308 * @arg @ref LL_RCC_LSEDRIVE_LOW
2309 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2310 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2311 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2312 * @retval None
2313 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)2314 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
2315 {
2316 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
2317 }
2318
2319 /**
2320 * @brief Get LSE oscillator drive capability
2321 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
2322 * @retval Returned value can be one of the following values:
2323 * @arg @ref LL_RCC_LSEDRIVE_LOW
2324 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2325 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2326 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2327 */
LL_RCC_LSE_GetDriveCapability(void)2328 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2329 {
2330 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
2331 }
2332
2333 /**
2334 * @brief Enable Clock security system on LSE.
2335 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
2336 * @retval None
2337 */
LL_RCC_LSE_EnableCSS(void)2338 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
2339 {
2340 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2341 }
2342
2343 /**
2344 * @brief Disable Clock security system on LSE.
2345 * @note Clock security system can be disabled only after a LSE
2346 * failure detection. In that case it MUST be disabled by software.
2347 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
2348 * @retval None
2349 */
LL_RCC_LSE_DisableCSS(void)2350 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
2351 {
2352 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2353 }
2354
2355 /**
2356 * @brief Check if LSE oscillator Ready
2357 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
2358 * @retval State of bit (1 or 0).
2359 */
LL_RCC_LSE_IsReady(void)2360 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
2361 {
2362 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
2363 }
2364
2365 /**
2366 * @brief Check if CSS on LSE failure Detection
2367 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
2368 * @retval State of bit (1 or 0).
2369 */
LL_RCC_LSE_IsCSSDetected(void)2370 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
2371 {
2372 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL);
2373 }
2374
2375 #if defined(RCC_BDCR_LSESYSDIS)
2376 /**
2377 * @brief Disable LSE oscillator propagation
2378 * @note LSE clock is not propagated to any peripheral except to RTC which remains clocked
2379 * @note A 2 LSE-clock delay is needed for LSESYSDIS setting to be taken into account
2380 * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_DisablePropagation
2381 * @retval None
2382 */
LL_RCC_LSE_DisablePropagation(void)2383 __STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
2384 {
2385 SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
2386 }
2387
2388 /**
2389 * @brief Enable LSE oscillator propagation
2390 * @note A 2 LSE-clock delay is needed for LSESYSDIS resetting to be taken into account
2391 * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_EnablePropagation
2392 * @retval None
2393 */
LL_RCC_LSE_EnablePropagation(void)2394 __STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
2395 {
2396 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
2397 }
2398
2399 /**
2400 * @brief Check if LSE oscillator propagation is enabled
2401 * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_IsPropagationEnabled
2402 * @retval State of bit (1 or 0).
2403 */
LL_RCC_LSE_IsPropagationEnabled(void)2404 __STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationEnabled(void)
2405 {
2406 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS) == 0U) ? 1UL : 0UL);
2407 }
2408 #endif /* RCC_BDCR_LSESYSDIS */
2409 /**
2410 * @}
2411 */
2412
2413 /** @defgroup RCC_LL_EF_LSI LSI
2414 * @{
2415 */
2416
2417 /**
2418 * @brief Enable LSI Oscillator
2419 * @rmtoll CSR LSION LL_RCC_LSI_Enable
2420 * @retval None
2421 */
LL_RCC_LSI_Enable(void)2422 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2423 {
2424 SET_BIT(RCC->CSR, RCC_CSR_LSION);
2425 }
2426
2427 /**
2428 * @brief Disable LSI Oscillator
2429 * @rmtoll CSR LSION LL_RCC_LSI_Disable
2430 * @retval None
2431 */
LL_RCC_LSI_Disable(void)2432 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2433 {
2434 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
2435 }
2436
2437 /**
2438 * @brief Check if LSI is Ready
2439 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
2440 * @retval State of bit (1 or 0).
2441 */
LL_RCC_LSI_IsReady(void)2442 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2443 {
2444 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL);
2445 }
2446
2447 #if defined(RCC_CSR_LSIPREDIV)
2448 /**
2449 * @brief Set LSI division factor
2450 * @rmtoll CSR LSIPREDIV LL_RCC_LSI_SetPrediv
2451 * @param LSI_PREDIV This parameter can be one of the following values:
2452 * @arg @ref LL_RCC_LSI_PREDIV_1
2453 * @arg @ref LL_RCC_LSI_PREDIV_128
2454 * @retval None
2455 */
LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV)2456 __STATIC_INLINE void LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV)
2457 {
2458 MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, LSI_PREDIV);
2459 }
2460
2461 /**
2462 * @brief Get LSI division factor
2463 * @rmtoll CSR LSIPREDIV LL_RCC_LSI_GetPrediv
2464 * @retval Returned value can be one of the following values:
2465 * @arg @ref LL_RCC_LSI_PREDIV_1
2466 * @arg @ref LL_RCC_LSI_PREDIV_128
2467 */
LL_RCC_LSI_GetPrediv(void)2468 __STATIC_INLINE uint32_t LL_RCC_LSI_GetPrediv(void)
2469 {
2470 return (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV));
2471 }
2472 #endif /* RCC_CSR_LSIPREDIV */
2473
2474 /**
2475 * @}
2476 */
2477
2478 /** @defgroup RCC_LL_EF_MSI MSI
2479 * @{
2480 */
2481
2482 /**
2483 * @brief Enable MSI oscillator
2484 * @rmtoll CR MSION LL_RCC_MSI_Enable
2485 * @retval None
2486 */
LL_RCC_MSI_Enable(void)2487 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
2488 {
2489 SET_BIT(RCC->CR, RCC_CR_MSION);
2490 }
2491
2492 /**
2493 * @brief Disable MSI oscillator
2494 * @rmtoll CR MSION LL_RCC_MSI_Disable
2495 * @retval None
2496 */
LL_RCC_MSI_Disable(void)2497 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
2498 {
2499 CLEAR_BIT(RCC->CR, RCC_CR_MSION);
2500 }
2501
2502 /**
2503 * @brief Check if MSI oscillator Ready
2504 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
2505 * @retval State of bit (1 or 0).
2506 */
LL_RCC_MSI_IsReady(void)2507 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
2508 {
2509 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
2510 }
2511
2512 /**
2513 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
2514 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
2515 * and ready (LSERDY set by hardware)
2516 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
2517 * ready
2518 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
2519 * @retval None
2520 */
LL_RCC_MSI_EnablePLLMode(void)2521 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
2522 {
2523 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
2524 }
2525
2526 /**
2527 * @brief Disable MSI-PLL mode
2528 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
2529 * the Clock Security System on LSE detects a LSE failure
2530 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
2531 * @retval None
2532 */
LL_RCC_MSI_DisablePLLMode(void)2533 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
2534 {
2535 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
2536 }
2537
2538 /**
2539 * @brief Enable MSI clock range selection with MSIRANGE register
2540 * @note Write 0 has no effect. After a standby or a reset
2541 * MSIRGSEL is at 0 and the MSI range value is provided by
2542 * MSISRANGE
2543 * @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
2544 * @retval None
2545 */
LL_RCC_MSI_EnableRangeSelection(void)2546 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
2547 {
2548 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
2549 }
2550
2551 /**
2552 * @brief Check if MSI clock range is selected with MSIRANGE register
2553 * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
2554 * @retval State of bit (1 or 0).
2555 */
LL_RCC_MSI_IsEnabledRangeSelect(void)2556 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
2557 {
2558 return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RCC_CR_MSIRGSEL) ? 1UL : 0UL);
2559 }
2560
2561 /**
2562 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
2563 * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
2564 * @param Range This parameter can be one of the following values:
2565 * @arg @ref LL_RCC_MSIRANGE_0
2566 * @arg @ref LL_RCC_MSIRANGE_1
2567 * @arg @ref LL_RCC_MSIRANGE_2
2568 * @arg @ref LL_RCC_MSIRANGE_3
2569 * @arg @ref LL_RCC_MSIRANGE_4
2570 * @arg @ref LL_RCC_MSIRANGE_5
2571 * @arg @ref LL_RCC_MSIRANGE_6
2572 * @arg @ref LL_RCC_MSIRANGE_7
2573 * @arg @ref LL_RCC_MSIRANGE_8
2574 * @arg @ref LL_RCC_MSIRANGE_9
2575 * @arg @ref LL_RCC_MSIRANGE_10
2576 * @arg @ref LL_RCC_MSIRANGE_11
2577 * @retval None
2578 */
LL_RCC_MSI_SetRange(uint32_t Range)2579 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
2580 {
2581 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
2582 }
2583
2584 /**
2585 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
2586 * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
2587 * @retval Returned value can be one of the following values:
2588 * @arg @ref LL_RCC_MSIRANGE_0
2589 * @arg @ref LL_RCC_MSIRANGE_1
2590 * @arg @ref LL_RCC_MSIRANGE_2
2591 * @arg @ref LL_RCC_MSIRANGE_3
2592 * @arg @ref LL_RCC_MSIRANGE_4
2593 * @arg @ref LL_RCC_MSIRANGE_5
2594 * @arg @ref LL_RCC_MSIRANGE_6
2595 * @arg @ref LL_RCC_MSIRANGE_7
2596 * @arg @ref LL_RCC_MSIRANGE_8
2597 * @arg @ref LL_RCC_MSIRANGE_9
2598 * @arg @ref LL_RCC_MSIRANGE_10
2599 * @arg @ref LL_RCC_MSIRANGE_11
2600 */
LL_RCC_MSI_GetRange(void)2601 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
2602 {
2603 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
2604 }
2605
2606 /**
2607 * @brief Configure MSI range used after standby
2608 * @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
2609 * @param Range This parameter can be one of the following values:
2610 * @arg @ref LL_RCC_MSISRANGE_4
2611 * @arg @ref LL_RCC_MSISRANGE_5
2612 * @arg @ref LL_RCC_MSISRANGE_6
2613 * @arg @ref LL_RCC_MSISRANGE_7
2614 * @retval None
2615 */
LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)2616 __STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
2617 {
2618 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
2619 }
2620
2621 /**
2622 * @brief Get MSI range used after standby
2623 * @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
2624 * @retval Returned value can be one of the following values:
2625 * @arg @ref LL_RCC_MSISRANGE_4
2626 * @arg @ref LL_RCC_MSISRANGE_5
2627 * @arg @ref LL_RCC_MSISRANGE_6
2628 * @arg @ref LL_RCC_MSISRANGE_7
2629 */
LL_RCC_MSI_GetRangeAfterStandby(void)2630 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
2631 {
2632 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
2633 }
2634
2635 /**
2636 * @brief Get MSI Calibration value
2637 * @note When MSITRIM is written, MSICAL is updated with the sum of
2638 * MSITRIM and the factory trim value
2639 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
2640 * @retval Between Min_Data = 0 and Max_Data = 255
2641 */
LL_RCC_MSI_GetCalibration(void)2642 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
2643 {
2644 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
2645 }
2646
2647 /**
2648 * @brief Set MSI Calibration trimming
2649 * @note user-programmable trimming value that is added to the MSICAL
2650 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
2651 * @param Value Between Min_Data = 0 and Max_Data = 255
2652 * @retval None
2653 */
LL_RCC_MSI_SetCalibTrimming(uint32_t Value)2654 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
2655 {
2656 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
2657 }
2658
2659 /**
2660 * @brief Get MSI Calibration trimming
2661 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
2662 * @retval Between 0 and 255
2663 */
LL_RCC_MSI_GetCalibTrimming(void)2664 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
2665 {
2666 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
2667 }
2668
2669 /**
2670 * @}
2671 */
2672
2673 /** @defgroup RCC_LL_EF_LSCO LSCO
2674 * @{
2675 */
2676
2677 /**
2678 * @brief Enable Low speed clock
2679 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
2680 * @retval None
2681 */
LL_RCC_LSCO_Enable(void)2682 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
2683 {
2684 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2685 }
2686
2687 /**
2688 * @brief Disable Low speed clock
2689 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
2690 * @retval None
2691 */
LL_RCC_LSCO_Disable(void)2692 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
2693 {
2694 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2695 }
2696
2697 /**
2698 * @brief Configure Low speed clock selection
2699 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
2700 * @param Source This parameter can be one of the following values:
2701 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2702 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2703 * @retval None
2704 */
LL_RCC_LSCO_SetSource(uint32_t Source)2705 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
2706 {
2707 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
2708 }
2709
2710 /**
2711 * @brief Get Low speed clock selection
2712 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
2713 * @retval Returned value can be one of the following values:
2714 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2715 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2716 */
LL_RCC_LSCO_GetSource(void)2717 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
2718 {
2719 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
2720 }
2721
2722 /**
2723 * @}
2724 */
2725
2726 /** @defgroup RCC_LL_EF_System System
2727 * @{
2728 */
2729
2730 /**
2731 * @brief Configure the system clock source
2732 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
2733 * @param Source This parameter can be one of the following values:
2734 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
2735 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2736 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2737 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
2738 * @retval None
2739 */
LL_RCC_SetSysClkSource(uint32_t Source)2740 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2741 {
2742 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2743 }
2744
2745 /**
2746 * @brief Get the system clock source
2747 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2748 * @retval Returned value can be one of the following values:
2749 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
2750 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2751 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2752 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
2753 */
LL_RCC_GetSysClkSource(void)2754 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2755 {
2756 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2757 }
2758
2759 /**
2760 * @brief Set AHB prescaler
2761 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
2762 * @param Prescaler This parameter can be one of the following values:
2763 * @arg @ref LL_RCC_SYSCLK_DIV_1
2764 * @arg @ref LL_RCC_SYSCLK_DIV_2
2765 * @arg @ref LL_RCC_SYSCLK_DIV_4
2766 * @arg @ref LL_RCC_SYSCLK_DIV_8
2767 * @arg @ref LL_RCC_SYSCLK_DIV_16
2768 * @arg @ref LL_RCC_SYSCLK_DIV_64
2769 * @arg @ref LL_RCC_SYSCLK_DIV_128
2770 * @arg @ref LL_RCC_SYSCLK_DIV_256
2771 * @arg @ref LL_RCC_SYSCLK_DIV_512
2772 * @retval None
2773 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)2774 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2775 {
2776 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
2777 }
2778
2779 /**
2780 * @brief Set APB1 prescaler
2781 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
2782 * @param Prescaler This parameter can be one of the following values:
2783 * @arg @ref LL_RCC_APB1_DIV_1
2784 * @arg @ref LL_RCC_APB1_DIV_2
2785 * @arg @ref LL_RCC_APB1_DIV_4
2786 * @arg @ref LL_RCC_APB1_DIV_8
2787 * @arg @ref LL_RCC_APB1_DIV_16
2788 * @retval None
2789 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2790 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2791 {
2792 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
2793 }
2794
2795 /**
2796 * @brief Set APB2 prescaler
2797 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
2798 * @param Prescaler This parameter can be one of the following values:
2799 * @arg @ref LL_RCC_APB2_DIV_1
2800 * @arg @ref LL_RCC_APB2_DIV_2
2801 * @arg @ref LL_RCC_APB2_DIV_4
2802 * @arg @ref LL_RCC_APB2_DIV_8
2803 * @arg @ref LL_RCC_APB2_DIV_16
2804 * @retval None
2805 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2806 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2807 {
2808 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
2809 }
2810
2811 /**
2812 * @brief Get AHB prescaler
2813 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
2814 * @retval Returned value can be one of the following values:
2815 * @arg @ref LL_RCC_SYSCLK_DIV_1
2816 * @arg @ref LL_RCC_SYSCLK_DIV_2
2817 * @arg @ref LL_RCC_SYSCLK_DIV_4
2818 * @arg @ref LL_RCC_SYSCLK_DIV_8
2819 * @arg @ref LL_RCC_SYSCLK_DIV_16
2820 * @arg @ref LL_RCC_SYSCLK_DIV_64
2821 * @arg @ref LL_RCC_SYSCLK_DIV_128
2822 * @arg @ref LL_RCC_SYSCLK_DIV_256
2823 * @arg @ref LL_RCC_SYSCLK_DIV_512
2824 */
LL_RCC_GetAHBPrescaler(void)2825 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2826 {
2827 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
2828 }
2829
2830 /**
2831 * @brief Get APB1 prescaler
2832 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
2833 * @retval Returned value can be one of the following values:
2834 * @arg @ref LL_RCC_APB1_DIV_1
2835 * @arg @ref LL_RCC_APB1_DIV_2
2836 * @arg @ref LL_RCC_APB1_DIV_4
2837 * @arg @ref LL_RCC_APB1_DIV_8
2838 * @arg @ref LL_RCC_APB1_DIV_16
2839 */
LL_RCC_GetAPB1Prescaler(void)2840 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2841 {
2842 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
2843 }
2844
2845 /**
2846 * @brief Get APB2 prescaler
2847 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
2848 * @retval Returned value can be one of the following values:
2849 * @arg @ref LL_RCC_APB2_DIV_1
2850 * @arg @ref LL_RCC_APB2_DIV_2
2851 * @arg @ref LL_RCC_APB2_DIV_4
2852 * @arg @ref LL_RCC_APB2_DIV_8
2853 * @arg @ref LL_RCC_APB2_DIV_16
2854 */
LL_RCC_GetAPB2Prescaler(void)2855 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2856 {
2857 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
2858 }
2859
2860 /**
2861 * @brief Set Clock After Wake-Up From Stop mode
2862 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
2863 * @param Clock This parameter can be one of the following values:
2864 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
2865 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
2866 * @retval None
2867 */
LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)2868 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
2869 {
2870 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
2871 }
2872
2873 /**
2874 * @brief Get Clock After Wake-Up From Stop mode
2875 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
2876 * @retval Returned value can be one of the following values:
2877 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
2878 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
2879 */
LL_RCC_GetClkAfterWakeFromStop(void)2880 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
2881 {
2882 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
2883 }
2884
2885 /**
2886 * @}
2887 */
2888
2889 /** @defgroup RCC_LL_EF_MCO MCO
2890 * @{
2891 */
2892
2893 /**
2894 * @brief Configure MCOx
2895 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
2896 * CFGR MCOPRE LL_RCC_ConfigMCO
2897 * @param MCOxSource This parameter can be one of the following values:
2898 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
2899 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
2900 * @arg @ref LL_RCC_MCO1SOURCE_MSI
2901 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2902 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2903 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
2904 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
2905 * @arg @ref LL_RCC_MCO1SOURCE_LSI
2906 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2907 *
2908 * (*) value not defined in all devices.
2909 * @param MCOxPrescaler This parameter can be one of the following values:
2910 * @arg @ref LL_RCC_MCO1_DIV_1
2911 * @arg @ref LL_RCC_MCO1_DIV_2
2912 * @arg @ref LL_RCC_MCO1_DIV_4
2913 * @arg @ref LL_RCC_MCO1_DIV_8
2914 * @arg @ref LL_RCC_MCO1_DIV_16
2915 * @retval None
2916 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2917 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2918 {
2919 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
2920 }
2921
2922 /**
2923 * @}
2924 */
2925
2926 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2927 * @{
2928 */
2929
2930 /**
2931 * @brief Configure USARTx clock source
2932 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
2933 * @param USARTxSource This parameter can be one of the following values:
2934 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2935 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2936 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2937 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2938 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2939 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2940 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2941 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2942 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
2943 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
2944 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
2945 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
2946 *
2947 * (*) value not defined in all devices.
2948 * @retval None
2949 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)2950 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2951 {
2952 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
2953 }
2954
2955 #if defined(UART4) || defined(UART5)
2956 /**
2957 * @brief Configure UARTx clock source
2958 * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
2959 * @param UARTxSource This parameter can be one of the following values:
2960 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2961 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
2962 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2963 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2964 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2965 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
2966 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2967 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2968 * @retval None
2969 */
LL_RCC_SetUARTClockSource(uint32_t UARTxSource)2970 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
2971 {
2972 MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
2973 }
2974 #endif /* UART4 || UART5 */
2975
2976 /**
2977 * @brief Configure LPUART1x clock source
2978 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
2979 * @param LPUARTxSource This parameter can be one of the following values:
2980 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2981 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2982 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2983 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2984 * @retval None
2985 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)2986 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
2987 {
2988 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
2989 }
2990
2991 /**
2992 * @brief Configure I2Cx clock source
2993 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
2994 * @param I2CxSource This parameter can be one of the following values:
2995 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2996 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2997 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2998 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
2999 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
3000 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
3001 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
3002 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
3003 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
3004 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
3005 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
3006 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
3007 *
3008 * (*) value not defined in all devices.
3009 * @retval None
3010 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)3011 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
3012 {
3013 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
3014 MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U)));
3015 }
3016
3017 /**
3018 * @brief Configure LPTIMx clock source
3019 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
3020 * @param LPTIMxSource This parameter can be one of the following values:
3021 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3022 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3023 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3024 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3025 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
3026 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3027 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
3028 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3029 * @retval None
3030 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)3031 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
3032 {
3033 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
3034 }
3035
3036 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
3037 /**
3038 * @brief Configure SAIx clock source
3039 @if STM32L4S9xx
3040 * @rmtoll CCIPR2 SAIxSEL LL_RCC_SetSAIClockSource
3041 @else
3042 * @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource
3043 @endif
3044 * @param SAIxSource This parameter can be one of the following values:
3045 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
3046 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
3047 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
3048 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
3049 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
3050 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
3051 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3052 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
3053 *
3054 * (*) value not defined in all devices.
3055 * @retval None
3056 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)3057 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
3058 {
3059 #if defined(RCC_CCIPR2_SAI1SEL)
3060 MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
3061 #else
3062 MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
3063 #endif /* RCC_CCIPR2_SAI1SEL */
3064 }
3065 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */
3066
3067 #if defined(RCC_CCIPR2_SDMMCSEL)
3068 /**
3069 * @brief Configure SDMMC1 kernel clock source
3070 * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource
3071 * @param SDMMCxSource This parameter can be one of the following values:
3072 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
3073 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*)
3074 *
3075 * (*) value not defined in all devices.
3076 * @retval None
3077 */
LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)3078 __STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
3079 {
3080 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
3081 }
3082 #endif /* RCC_CCIPR2_SDMMCSEL */
3083
3084 /**
3085 * @brief Configure SDMMC1 clock source
3086 * @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource
3087 * @param SDMMCxSource This parameter can be one of the following values:
3088 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
3089 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
3090 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
3091 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
3092 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
3093 *
3094 * (*) value not defined in all devices.
3095 * @retval None
3096 */
LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)3097 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
3098 {
3099 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
3100 }
3101
3102 /**
3103 * @brief Configure RNG clock source
3104 * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
3105 * @param RNGxSource This parameter can be one of the following values:
3106 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
3107 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
3108 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*)
3109 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3110 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
3111 *
3112 * (*) value not defined in all devices.
3113 * @retval None
3114 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)3115 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
3116 {
3117 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
3118 }
3119
3120 #if defined(USB_OTG_FS) || defined(USB)
3121 /**
3122 * @brief Configure USB clock source
3123 * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
3124 * @param USBxSource This parameter can be one of the following values:
3125 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
3126 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
3127 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*)
3128 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3129 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
3130 *
3131 * (*) value not defined in all devices.
3132 * @retval None
3133 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)3134 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
3135 {
3136 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
3137 }
3138 #endif /* USB_OTG_FS || USB */
3139
3140 #if defined(RCC_CCIPR_ADCSEL)
3141 /**
3142 * @brief Configure ADC clock source
3143 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
3144 * @param ADCxSource This parameter can be one of the following values:
3145 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
3146 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
3147 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
3148 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
3149 *
3150 * (*) value not defined in all devices.
3151 * @retval None
3152 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)3153 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
3154 {
3155 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
3156 }
3157 #endif /* RCC_CCIPR_ADCSEL */
3158
3159 #if defined(SWPMI1)
3160 /**
3161 * @brief Configure SWPMI clock source
3162 * @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource
3163 * @param SWPMIxSource This parameter can be one of the following values:
3164 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
3165 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
3166 * @retval None
3167 */
LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)3168 __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
3169 {
3170 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
3171 }
3172 #endif /* SWPMI1 */
3173
3174 #if defined(DFSDM1_Channel0)
3175 #if defined(RCC_CCIPR2_ADFSDM1SEL)
3176 /**
3177 * @brief Configure DFSDM Audio clock source
3178 * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
3179 * @param Source This parameter can be one of the following values:
3180 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
3181 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
3182 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
3183 * @retval None
3184 */
LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)3185 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
3186 {
3187 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source);
3188 }
3189 #endif /* RCC_CCIPR2_ADFSDM1SEL */
3190
3191 /**
3192 * @brief Configure DFSDM Kernel clock source
3193 @if STM32L4S9xx
3194 * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource
3195 @else
3196 * @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource
3197 @endif
3198 * @param DFSDMxSource This parameter can be one of the following values:
3199 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3200 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3201 * @retval None
3202 */
LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)3203 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
3204 {
3205 #if defined(RCC_CCIPR2_DFSDM1SEL)
3206 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource);
3207 #else
3208 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
3209 #endif /* RCC_CCIPR2_DFSDM1SEL */
3210 }
3211 #endif /* DFSDM1_Channel0 */
3212
3213 #if defined(DSI)
3214 /**
3215 * @brief Configure DSI clock source
3216 * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource
3217 * @param Source This parameter can be one of the following values:
3218 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3219 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3220 * @retval None
3221 */
LL_RCC_SetDSIClockSource(uint32_t Source)3222 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
3223 {
3224 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source);
3225 }
3226 #endif /* DSI */
3227
3228 #if defined(LTDC)
3229 /**
3230 * @brief Configure LTDC Clock Source
3231 * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource
3232 * @param Source This parameter can be one of the following values:
3233 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
3234 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
3235 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
3236 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
3237 * @retval None
3238 */
LL_RCC_SetLTDCClockSource(uint32_t Source)3239 __STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source)
3240 {
3241 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source);
3242 }
3243 #endif /* LTDC */
3244
3245 #if defined(OCTOSPI1)
3246 /**
3247 * @brief Configure OCTOSPI clock source
3248 * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource
3249 * @param Source This parameter can be one of the following values:
3250 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
3251 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
3252 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
3253 * @retval None
3254 */
LL_RCC_SetOCTOSPIClockSource(uint32_t Source)3255 __STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)
3256 {
3257 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source);
3258 }
3259 #endif /* OCTOSPI1 */
3260
3261 /**
3262 * @brief Get USARTx clock source
3263 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
3264 * @param USARTx This parameter can be one of the following values:
3265 * @arg @ref LL_RCC_USART1_CLKSOURCE
3266 * @arg @ref LL_RCC_USART2_CLKSOURCE
3267 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
3268 *
3269 * (*) value not defined in all devices.
3270 * @retval Returned value can be one of the following values:
3271 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
3272 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
3273 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
3274 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
3275 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
3276 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
3277 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
3278 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
3279 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
3280 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
3281 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
3282 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
3283 *
3284 * (*) value not defined in all devices.
3285 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)3286 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
3287 {
3288 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
3289 }
3290
3291 #if defined(UART4) || defined(UART5)
3292 /**
3293 * @brief Get UARTx clock source
3294 * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
3295 * @param UARTx This parameter can be one of the following values:
3296 * @arg @ref LL_RCC_UART4_CLKSOURCE
3297 * @arg @ref LL_RCC_UART5_CLKSOURCE
3298 * @retval Returned value can be one of the following values:
3299 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
3300 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
3301 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
3302 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
3303 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
3304 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
3305 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
3306 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
3307 */
LL_RCC_GetUARTClockSource(uint32_t UARTx)3308 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
3309 {
3310 return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
3311 }
3312 #endif /* UART4 || UART5 */
3313
3314 /**
3315 * @brief Get LPUARTx clock source
3316 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
3317 * @param LPUARTx This parameter can be one of the following values:
3318 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
3319 * @retval Returned value can be one of the following values:
3320 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
3321 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
3322 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3323 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3324 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)3325 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
3326 {
3327 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
3328 }
3329
3330 /**
3331 * @brief Get I2Cx clock source
3332 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
3333 * @param I2Cx This parameter can be one of the following values:
3334 * @arg @ref LL_RCC_I2C1_CLKSOURCE
3335 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
3336 * @arg @ref LL_RCC_I2C3_CLKSOURCE
3337 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
3338 *
3339 * (*) value not defined in all devices.
3340 * @retval Returned value can be one of the following values:
3341 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
3342 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
3343 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
3344 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
3345 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
3346 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
3347 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
3348 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
3349 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
3350 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
3351 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
3352 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
3353 *
3354 * (*) value not defined in all devices.
3355 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)3356 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
3357 {
3358 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
3359 return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
3360 }
3361
3362 /**
3363 * @brief Get LPTIMx clock source
3364 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
3365 * @param LPTIMx This parameter can be one of the following values:
3366 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3367 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3368 * @retval Returned value can be one of the following values:
3369 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3370 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3371 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3372 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3373 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
3374 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3375 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
3376 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3377 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)3378 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
3379 {
3380 return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx);
3381 }
3382
3383 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
3384 /**
3385 * @brief Get SAIx clock source
3386 @if STM32L4S9xx
3387 * @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource
3388 @else
3389 * @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource
3390 @endif
3391 * @param SAIx This parameter can be one of the following values:
3392 * @arg @ref LL_RCC_SAI1_CLKSOURCE
3393 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
3394 *
3395 * (*) value not defined in all devices.
3396 * @retval Returned value can be one of the following values:
3397 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
3398 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
3399 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
3400 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
3401 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
3402 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
3403 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3404 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
3405 *
3406 * (*) value not defined in all devices.
3407 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)3408 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
3409 {
3410 #if defined(RCC_CCIPR2_SAI1SEL)
3411 return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U));
3412 #else
3413 return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx);
3414 #endif /* RCC_CCIPR2_SAI1SEL */
3415 }
3416 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */
3417
3418 #if defined(SDMMC1)
3419 #if defined(RCC_CCIPR2_SDMMCSEL)
3420 /**
3421 * @brief Get SDMMCx kernel clock source
3422 * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource
3423 * @param SDMMCx This parameter can be one of the following values:
3424 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
3425 * @retval Returned value can be one of the following values:
3426 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
3427 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*)
3428 *
3429 * (*) value not defined in all devices.
3430 */
LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)3431 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
3432 {
3433 return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
3434 }
3435 #endif /* RCC_CCIPR2_SDMMCSEL */
3436
3437 /**
3438 * @brief Get SDMMCx clock source
3439 * @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource
3440 * @param SDMMCx This parameter can be one of the following values:
3441 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
3442 * @retval Returned value can be one of the following values:
3443 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
3444 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
3445 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
3446 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
3447 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
3448 *
3449 * (*) value not defined in all devices.
3450 */
LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)3451 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
3452 {
3453 return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
3454 }
3455 #endif /* SDMMC1 */
3456
3457 /**
3458 * @brief Get RNGx clock source
3459 * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
3460 * @param RNGx This parameter can be one of the following values:
3461 * @arg @ref LL_RCC_RNG_CLKSOURCE
3462 * @retval Returned value can be one of the following values:
3463 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
3464 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
3465 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*)
3466 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3467 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
3468 *
3469 * (*) value not defined in all devices.
3470 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)3471 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
3472 {
3473 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
3474 }
3475
3476 #if defined(USB_OTG_FS) || defined(USB)
3477 /**
3478 * @brief Get USBx clock source
3479 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
3480 * @param USBx This parameter can be one of the following values:
3481 * @arg @ref LL_RCC_USB_CLKSOURCE
3482 * @retval Returned value can be one of the following values:
3483 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
3484 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
3485 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*)
3486 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3487 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
3488 *
3489 * (*) value not defined in all devices.
3490 */
LL_RCC_GetUSBClockSource(uint32_t USBx)3491 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
3492 {
3493 return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
3494 }
3495 #endif /* USB_OTG_FS || USB */
3496
3497 /**
3498 * @brief Get ADCx clock source
3499 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
3500 * @param ADCx This parameter can be one of the following values:
3501 * @arg @ref LL_RCC_ADC_CLKSOURCE
3502 * @retval Returned value can be one of the following values:
3503 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
3504 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
3505 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
3506 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
3507 *
3508 * (*) value not defined in all devices.
3509 */
LL_RCC_GetADCClockSource(uint32_t ADCx)3510 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
3511 {
3512 #if defined(RCC_CCIPR_ADCSEL)
3513 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
3514 #else
3515 (void)ADCx; /* unused */
3516 return ((READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) ? LL_RCC_ADC_CLKSOURCE_SYSCLK : LL_RCC_ADC_CLKSOURCE_NONE);
3517 #endif /* RCC_CCIPR_ADCSEL */
3518 }
3519
3520 #if defined(SWPMI1)
3521 /**
3522 * @brief Get SWPMIx clock source
3523 * @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource
3524 * @param SPWMIx This parameter can be one of the following values:
3525 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE
3526 * @retval Returned value can be one of the following values:
3527 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
3528 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
3529 */
LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)3530 __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
3531 {
3532 return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
3533 }
3534 #endif /* SWPMI1 */
3535
3536 #if defined(DFSDM1_Channel0)
3537 #if defined(RCC_CCIPR2_ADFSDM1SEL)
3538 /**
3539 * @brief Get DFSDM Audio Clock Source
3540 * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
3541 * @param DFSDMx This parameter can be one of the following values:
3542 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
3543 * @retval Returned value can be one of the following values:
3544 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
3545 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
3546 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
3547 */
LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)3548 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
3549 {
3550 return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
3551 }
3552 #endif /* RCC_CCIPR2_ADFSDM1SEL */
3553
3554 /**
3555 * @brief Get DFSDMx Kernel clock source
3556 @if STM32L4S9xx
3557 * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource
3558 @else
3559 * @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource
3560 @endif
3561 * @param DFSDMx This parameter can be one of the following values:
3562 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
3563 * @retval Returned value can be one of the following values:
3564 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3565 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3566 */
LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)3567 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
3568 {
3569 #if defined(RCC_CCIPR2_DFSDM1SEL)
3570 return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
3571 #else
3572 return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
3573 #endif /* RCC_CCIPR2_DFSDM1SEL */
3574 }
3575 #endif /* DFSDM1_Channel0 */
3576
3577 #if defined(DSI)
3578 /**
3579 * @brief Get DSI Clock Source
3580 * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource
3581 * @param DSIx This parameter can be one of the following values:
3582 * @arg @ref LL_RCC_DSI_CLKSOURCE
3583 * @retval Returned value can be one of the following values:
3584 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3585 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3586 */
LL_RCC_GetDSIClockSource(uint32_t DSIx)3587 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
3588 {
3589 return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx));
3590 }
3591 #endif /* DSI */
3592
3593 #if defined(LTDC)
3594 /**
3595 * @brief Get LTDC Clock Source
3596 * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource
3597 * @param LTDCx This parameter can be one of the following values:
3598 * @arg @ref LL_RCC_LTDC_CLKSOURCE
3599 * @retval Returned value can be one of the following values:
3600 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
3601 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
3602 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
3603 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
3604 */
LL_RCC_GetLTDCClockSource(uint32_t LTDCx)3605 __STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx)
3606 {
3607 return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx));
3608 }
3609 #endif /* LTDC */
3610
3611 #if defined(OCTOSPI1)
3612 /**
3613 * @brief Get OCTOSPI clock source
3614 * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource
3615 * @param OCTOSPIx This parameter can be one of the following values:
3616 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
3617 * @retval Returned value can be one of the following values:
3618 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
3619 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
3620 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
3621 */
LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)3622 __STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
3623 {
3624 return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx));
3625 }
3626 #endif /* OCTOSPI1 */
3627 /**
3628 * @}
3629 */
3630
3631 /** @defgroup RCC_LL_EF_RTC RTC
3632 * @{
3633 */
3634
3635 /**
3636 * @brief Set RTC Clock Source
3637 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3638 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3639 * set). The BDRST bit can be used to reset them.
3640 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3641 * @param Source This parameter can be one of the following values:
3642 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3643 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3644 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3645 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
3646 * @retval None
3647 */
LL_RCC_SetRTCClockSource(uint32_t Source)3648 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3649 {
3650 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
3651 }
3652
3653 /**
3654 * @brief Get RTC Clock Source
3655 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
3656 * @retval Returned value can be one of the following values:
3657 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3658 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3659 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3660 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
3661 */
LL_RCC_GetRTCClockSource(void)3662 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
3663 {
3664 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
3665 }
3666
3667 /**
3668 * @brief Enable RTC
3669 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
3670 * @retval None
3671 */
LL_RCC_EnableRTC(void)3672 __STATIC_INLINE void LL_RCC_EnableRTC(void)
3673 {
3674 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3675 }
3676
3677 /**
3678 * @brief Disable RTC
3679 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
3680 * @retval None
3681 */
LL_RCC_DisableRTC(void)3682 __STATIC_INLINE void LL_RCC_DisableRTC(void)
3683 {
3684 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3685 }
3686
3687 /**
3688 * @brief Check if RTC has been enabled or not
3689 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
3690 * @retval State of bit (1 or 0).
3691 */
LL_RCC_IsEnabledRTC(void)3692 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
3693 {
3694 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL);
3695 }
3696
3697 /**
3698 * @brief Force the Backup domain reset
3699 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
3700 * @retval None
3701 */
LL_RCC_ForceBackupDomainReset(void)3702 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
3703 {
3704 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
3705 }
3706
3707 /**
3708 * @brief Release the Backup domain reset
3709 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
3710 * @retval None
3711 */
LL_RCC_ReleaseBackupDomainReset(void)3712 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
3713 {
3714 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
3715 }
3716
3717 /**
3718 * @}
3719 */
3720
3721
3722 /** @defgroup RCC_LL_EF_PLL PLL
3723 * @{
3724 */
3725
3726 /**
3727 * @brief Enable PLL
3728 * @rmtoll CR PLLON LL_RCC_PLL_Enable
3729 * @retval None
3730 */
LL_RCC_PLL_Enable(void)3731 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
3732 {
3733 SET_BIT(RCC->CR, RCC_CR_PLLON);
3734 }
3735
3736 /**
3737 * @brief Disable PLL
3738 * @note Cannot be disabled if the PLL clock is used as the system clock
3739 * @rmtoll CR PLLON LL_RCC_PLL_Disable
3740 * @retval None
3741 */
LL_RCC_PLL_Disable(void)3742 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
3743 {
3744 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
3745 }
3746
3747 /**
3748 * @brief Check if PLL Ready
3749 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
3750 * @retval State of bit (1 or 0).
3751 */
LL_RCC_PLL_IsReady(void)3752 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
3753 {
3754 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
3755 }
3756
3757 /**
3758 * @brief Configure PLL used for SYSCLK Domain
3759 * @note PLL Source and PLLM Divider can be written only when PLL,
3760 * PLLSAI1 and PLLSAI2 (*) are disabled.
3761 * @note PLLN/PLLR can be written only when PLL is disabled.
3762 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
3763 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
3764 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
3765 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
3766 * @param Source This parameter can be one of the following values:
3767 * @arg @ref LL_RCC_PLLSOURCE_NONE
3768 * @arg @ref LL_RCC_PLLSOURCE_MSI
3769 * @arg @ref LL_RCC_PLLSOURCE_HSI
3770 * @arg @ref LL_RCC_PLLSOURCE_HSE
3771 * @param PLLM This parameter can be one of the following values:
3772 * @arg @ref LL_RCC_PLLM_DIV_1
3773 * @arg @ref LL_RCC_PLLM_DIV_2
3774 * @arg @ref LL_RCC_PLLM_DIV_3
3775 * @arg @ref LL_RCC_PLLM_DIV_4
3776 * @arg @ref LL_RCC_PLLM_DIV_5
3777 * @arg @ref LL_RCC_PLLM_DIV_6
3778 * @arg @ref LL_RCC_PLLM_DIV_7
3779 * @arg @ref LL_RCC_PLLM_DIV_8
3780 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
3781 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
3782 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
3783 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
3784 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
3785 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
3786 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
3787 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
3788 *
3789 * (*) value not defined in all devices.
3790 * @param PLLN Between 8 and 86 or 127 depending on devices
3791 * @param PLLR This parameter can be one of the following values:
3792 * @arg @ref LL_RCC_PLLR_DIV_2
3793 * @arg @ref LL_RCC_PLLR_DIV_4
3794 * @arg @ref LL_RCC_PLLR_DIV_6
3795 * @arg @ref LL_RCC_PLLR_DIV_8
3796 * @retval None
3797 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)3798 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
3799 {
3800 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
3801 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
3802 }
3803
3804 #if defined(RCC_PLLP_SUPPORT)
3805 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
3806 /**
3807 * @brief Configure PLL used for SAI domain clock
3808 * @note PLL Source and PLLM Divider can be written only when PLL,
3809 * PLLSAI1 and PLLSAI2 (*) are disabled.
3810 * @note PLLN/PLLP can be written only when PLL is disabled.
3811 * @note This can be selected for SAI1 or SAI2 (*)
3812 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
3813 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
3814 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
3815 * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI
3816 * @param Source This parameter can be one of the following values:
3817 * @arg @ref LL_RCC_PLLSOURCE_NONE
3818 * @arg @ref LL_RCC_PLLSOURCE_MSI
3819 * @arg @ref LL_RCC_PLLSOURCE_HSI
3820 * @arg @ref LL_RCC_PLLSOURCE_HSE
3821 * @param PLLM This parameter can be one of the following values:
3822 * @arg @ref LL_RCC_PLLM_DIV_1
3823 * @arg @ref LL_RCC_PLLM_DIV_2
3824 * @arg @ref LL_RCC_PLLM_DIV_3
3825 * @arg @ref LL_RCC_PLLM_DIV_4
3826 * @arg @ref LL_RCC_PLLM_DIV_5
3827 * @arg @ref LL_RCC_PLLM_DIV_6
3828 * @arg @ref LL_RCC_PLLM_DIV_7
3829 * @arg @ref LL_RCC_PLLM_DIV_8
3830 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
3831 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
3832 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
3833 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
3834 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
3835 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
3836 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
3837 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
3838 *
3839 * (*) value not defined in all devices.
3840 * @param PLLN Between 8 and 86 or 127 depending on devices
3841 * @param PLLP This parameter can be one of the following values:
3842 * @arg @ref LL_RCC_PLLP_DIV_2
3843 * @arg @ref LL_RCC_PLLP_DIV_3
3844 * @arg @ref LL_RCC_PLLP_DIV_4
3845 * @arg @ref LL_RCC_PLLP_DIV_5
3846 * @arg @ref LL_RCC_PLLP_DIV_6
3847 * @arg @ref LL_RCC_PLLP_DIV_7
3848 * @arg @ref LL_RCC_PLLP_DIV_8
3849 * @arg @ref LL_RCC_PLLP_DIV_9
3850 * @arg @ref LL_RCC_PLLP_DIV_10
3851 * @arg @ref LL_RCC_PLLP_DIV_11
3852 * @arg @ref LL_RCC_PLLP_DIV_12
3853 * @arg @ref LL_RCC_PLLP_DIV_13
3854 * @arg @ref LL_RCC_PLLP_DIV_14
3855 * @arg @ref LL_RCC_PLLP_DIV_15
3856 * @arg @ref LL_RCC_PLLP_DIV_16
3857 * @arg @ref LL_RCC_PLLP_DIV_17
3858 * @arg @ref LL_RCC_PLLP_DIV_18
3859 * @arg @ref LL_RCC_PLLP_DIV_19
3860 * @arg @ref LL_RCC_PLLP_DIV_20
3861 * @arg @ref LL_RCC_PLLP_DIV_21
3862 * @arg @ref LL_RCC_PLLP_DIV_22
3863 * @arg @ref LL_RCC_PLLP_DIV_23
3864 * @arg @ref LL_RCC_PLLP_DIV_24
3865 * @arg @ref LL_RCC_PLLP_DIV_25
3866 * @arg @ref LL_RCC_PLLP_DIV_26
3867 * @arg @ref LL_RCC_PLLP_DIV_27
3868 * @arg @ref LL_RCC_PLLP_DIV_28
3869 * @arg @ref LL_RCC_PLLP_DIV_29
3870 * @arg @ref LL_RCC_PLLP_DIV_30
3871 * @arg @ref LL_RCC_PLLP_DIV_31
3872 * @retval None
3873 */
3874 #else
3875 /**
3876 * @brief Configure PLL used for SAI domain clock
3877 * @note PLL Source and PLLM Divider can be written only when PLL,
3878 * PLLSAI1 and PLLSAI2 (*) are disabled.
3879 * @note PLLN/PLLP can be written only when PLL is disabled.
3880 * @note This can be selected for SAI1 or SAI2 (*)
3881 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
3882 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
3883 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
3884 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
3885 * @param Source This parameter can be one of the following values:
3886 * @arg @ref LL_RCC_PLLSOURCE_NONE
3887 * @arg @ref LL_RCC_PLLSOURCE_MSI
3888 * @arg @ref LL_RCC_PLLSOURCE_HSI
3889 * @arg @ref LL_RCC_PLLSOURCE_HSE
3890 * @param PLLM This parameter can be one of the following values:
3891 * @arg @ref LL_RCC_PLLM_DIV_1
3892 * @arg @ref LL_RCC_PLLM_DIV_2
3893 * @arg @ref LL_RCC_PLLM_DIV_3
3894 * @arg @ref LL_RCC_PLLM_DIV_4
3895 * @arg @ref LL_RCC_PLLM_DIV_5
3896 * @arg @ref LL_RCC_PLLM_DIV_6
3897 * @arg @ref LL_RCC_PLLM_DIV_7
3898 * @arg @ref LL_RCC_PLLM_DIV_8
3899 * @param PLLN Between 8 and 86
3900 * @param PLLP This parameter can be one of the following values:
3901 * @arg @ref LL_RCC_PLLP_DIV_7
3902 * @arg @ref LL_RCC_PLLP_DIV_17
3903 * @retval None
3904 */
3905 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3906 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3907 {
3908 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
3909 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
3910 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3911 #else
3912 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
3913 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3914 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
3915 }
3916 #endif /* RCC_PLLP_SUPPORT */
3917
3918 /**
3919 * @brief Configure PLL used for 48Mhz domain clock
3920 * @note PLL Source and PLLM Divider can be written only when PLL,
3921 * PLLSAI1 and PLLSAI2 (*) are disabled.
3922 * @note PLLN/PLLQ can be written only when PLL is disabled.
3923 * @note This can be selected for USB, RNG, SDMMC
3924 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
3925 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
3926 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
3927 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
3928 * @param Source This parameter can be one of the following values:
3929 * @arg @ref LL_RCC_PLLSOURCE_NONE
3930 * @arg @ref LL_RCC_PLLSOURCE_MSI
3931 * @arg @ref LL_RCC_PLLSOURCE_HSI
3932 * @arg @ref LL_RCC_PLLSOURCE_HSE
3933 * @param PLLM This parameter can be one of the following values:
3934 * @arg @ref LL_RCC_PLLM_DIV_1
3935 * @arg @ref LL_RCC_PLLM_DIV_2
3936 * @arg @ref LL_RCC_PLLM_DIV_3
3937 * @arg @ref LL_RCC_PLLM_DIV_4
3938 * @arg @ref LL_RCC_PLLM_DIV_5
3939 * @arg @ref LL_RCC_PLLM_DIV_6
3940 * @arg @ref LL_RCC_PLLM_DIV_7
3941 * @arg @ref LL_RCC_PLLM_DIV_8
3942 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
3943 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
3944 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
3945 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
3946 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
3947 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
3948 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
3949 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
3950 *
3951 * (*) value not defined in all devices.
3952 * @param PLLN Between 8 and 86 or 127 depending on devices
3953 * @param PLLQ This parameter can be one of the following values:
3954 * @arg @ref LL_RCC_PLLQ_DIV_2
3955 * @arg @ref LL_RCC_PLLQ_DIV_4
3956 * @arg @ref LL_RCC_PLLQ_DIV_6
3957 * @arg @ref LL_RCC_PLLQ_DIV_8
3958 * @retval None
3959 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)3960 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3961 {
3962 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
3963 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
3964 }
3965
3966 /**
3967 * @brief Configure PLL clock source
3968 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
3969 * @param PLLSource This parameter can be one of the following values:
3970 * @arg @ref LL_RCC_PLLSOURCE_NONE
3971 * @arg @ref LL_RCC_PLLSOURCE_MSI
3972 * @arg @ref LL_RCC_PLLSOURCE_HSI
3973 * @arg @ref LL_RCC_PLLSOURCE_HSE
3974 * @retval None
3975 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)3976 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
3977 {
3978 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
3979 }
3980
3981 /**
3982 * @brief Get the oscillator used as PLL clock source.
3983 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
3984 * @retval Returned value can be one of the following values:
3985 * @arg @ref LL_RCC_PLLSOURCE_NONE
3986 * @arg @ref LL_RCC_PLLSOURCE_MSI
3987 * @arg @ref LL_RCC_PLLSOURCE_HSI
3988 * @arg @ref LL_RCC_PLLSOURCE_HSE
3989 */
LL_RCC_PLL_GetMainSource(void)3990 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
3991 {
3992 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
3993 }
3994
3995 /**
3996 * @brief Get Main PLL multiplication factor for VCO
3997 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
3998 * @retval Between 8 and 86 or 127 depending on devices
3999 */
LL_RCC_PLL_GetN(void)4000 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
4001 {
4002 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
4003 }
4004
4005 #if defined(RCC_PLLP_SUPPORT)
4006 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
4007 /**
4008 * @brief Get Main PLL division factor for PLLP
4009 * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
4010 * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP
4011 * @retval Returned value can be one of the following values:
4012 * @arg @ref LL_RCC_PLLP_DIV_2
4013 * @arg @ref LL_RCC_PLLP_DIV_3
4014 * @arg @ref LL_RCC_PLLP_DIV_4
4015 * @arg @ref LL_RCC_PLLP_DIV_5
4016 * @arg @ref LL_RCC_PLLP_DIV_6
4017 * @arg @ref LL_RCC_PLLP_DIV_7
4018 * @arg @ref LL_RCC_PLLP_DIV_8
4019 * @arg @ref LL_RCC_PLLP_DIV_9
4020 * @arg @ref LL_RCC_PLLP_DIV_10
4021 * @arg @ref LL_RCC_PLLP_DIV_11
4022 * @arg @ref LL_RCC_PLLP_DIV_12
4023 * @arg @ref LL_RCC_PLLP_DIV_13
4024 * @arg @ref LL_RCC_PLLP_DIV_14
4025 * @arg @ref LL_RCC_PLLP_DIV_15
4026 * @arg @ref LL_RCC_PLLP_DIV_16
4027 * @arg @ref LL_RCC_PLLP_DIV_17
4028 * @arg @ref LL_RCC_PLLP_DIV_18
4029 * @arg @ref LL_RCC_PLLP_DIV_19
4030 * @arg @ref LL_RCC_PLLP_DIV_20
4031 * @arg @ref LL_RCC_PLLP_DIV_21
4032 * @arg @ref LL_RCC_PLLP_DIV_22
4033 * @arg @ref LL_RCC_PLLP_DIV_23
4034 * @arg @ref LL_RCC_PLLP_DIV_24
4035 * @arg @ref LL_RCC_PLLP_DIV_25
4036 * @arg @ref LL_RCC_PLLP_DIV_26
4037 * @arg @ref LL_RCC_PLLP_DIV_27
4038 * @arg @ref LL_RCC_PLLP_DIV_28
4039 * @arg @ref LL_RCC_PLLP_DIV_29
4040 * @arg @ref LL_RCC_PLLP_DIV_30
4041 * @arg @ref LL_RCC_PLLP_DIV_31
4042 */
LL_RCC_PLL_GetP(void)4043 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
4044 {
4045 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
4046 }
4047 #else
4048 /**
4049 * @brief Get Main PLL division factor for PLLP
4050 * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
4051 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
4052 * @retval Returned value can be one of the following values:
4053 * @arg @ref LL_RCC_PLLP_DIV_7
4054 * @arg @ref LL_RCC_PLLP_DIV_17
4055 */
LL_RCC_PLL_GetP(void)4056 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
4057 {
4058 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
4059 }
4060 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
4061 #endif /* RCC_PLLP_SUPPORT */
4062
4063 /**
4064 * @brief Get Main PLL division factor for PLLQ
4065 * @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
4066 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
4067 * @retval Returned value can be one of the following values:
4068 * @arg @ref LL_RCC_PLLQ_DIV_2
4069 * @arg @ref LL_RCC_PLLQ_DIV_4
4070 * @arg @ref LL_RCC_PLLQ_DIV_6
4071 * @arg @ref LL_RCC_PLLQ_DIV_8
4072 */
LL_RCC_PLL_GetQ(void)4073 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
4074 {
4075 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
4076 }
4077
4078 /**
4079 * @brief Get Main PLL division factor for PLLR
4080 * @note Used for PLLCLK (system clock)
4081 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
4082 * @retval Returned value can be one of the following values:
4083 * @arg @ref LL_RCC_PLLR_DIV_2
4084 * @arg @ref LL_RCC_PLLR_DIV_4
4085 * @arg @ref LL_RCC_PLLR_DIV_6
4086 * @arg @ref LL_RCC_PLLR_DIV_8
4087 */
LL_RCC_PLL_GetR(void)4088 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
4089 {
4090 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
4091 }
4092
4093 /**
4094 * @brief Get Division factor for the main PLL and other PLL
4095 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
4096 * @retval Returned value can be one of the following values:
4097 * @arg @ref LL_RCC_PLLM_DIV_1
4098 * @arg @ref LL_RCC_PLLM_DIV_2
4099 * @arg @ref LL_RCC_PLLM_DIV_3
4100 * @arg @ref LL_RCC_PLLM_DIV_4
4101 * @arg @ref LL_RCC_PLLM_DIV_5
4102 * @arg @ref LL_RCC_PLLM_DIV_6
4103 * @arg @ref LL_RCC_PLLM_DIV_7
4104 * @arg @ref LL_RCC_PLLM_DIV_8
4105 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
4106 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
4107 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
4108 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
4109 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
4110 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
4111 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
4112 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
4113 *
4114 * (*) value not defined in all devices.
4115 */
LL_RCC_PLL_GetDivider(void)4116 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
4117 {
4118 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
4119 }
4120
4121 #if defined(RCC_PLLP_SUPPORT)
4122 /**
4123 * @brief Enable PLL output mapped on SAI domain clock
4124 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
4125 * @retval None
4126 */
LL_RCC_PLL_EnableDomain_SAI(void)4127 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
4128 {
4129 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
4130 }
4131
4132 /**
4133 * @brief Disable PLL output mapped on SAI domain clock
4134 * @note Cannot be disabled if the PLL clock is used as the system
4135 * clock
4136 * @note In order to save power, when the PLLCLK of the PLL is
4137 * not used, should be 0
4138 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
4139 * @retval None
4140 */
LL_RCC_PLL_DisableDomain_SAI(void)4141 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
4142 {
4143 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
4144 }
4145
4146 /**
4147 * @brief Check if PLL output mapped on SAI domain clock is enabled
4148 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_SAI
4149 * @retval State of bit (1 or 0).
4150 */
LL_RCC_PLL_IsEnabledDomain_SAI(void)4151 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SAI(void)
4152 {
4153 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
4154 }
4155
4156 #endif /* RCC_PLLP_SUPPORT */
4157
4158 /**
4159 * @brief Enable PLL output mapped on 48MHz domain clock
4160 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
4161 * @retval None
4162 */
LL_RCC_PLL_EnableDomain_48M(void)4163 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
4164 {
4165 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
4166 }
4167
4168 /**
4169 * @brief Disable PLL output mapped on 48MHz domain clock
4170 * @note Cannot be disabled if the PLL clock is used as the system
4171 * clock
4172 * @note In order to save power, when the PLLCLK of the PLL is
4173 * not used, should be 0
4174 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
4175 * @retval None
4176 */
LL_RCC_PLL_DisableDomain_48M(void)4177 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
4178 {
4179 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
4180 }
4181
4182 /**
4183 * @brief Check if PLL output mapped on 48MHz domain clock is enabled
4184 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M
4185 * @retval State of bit (1 or 0).
4186 */
LL_RCC_PLL_IsEnabledDomain_48M(void)4187 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void)
4188 {
4189 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
4190 }
4191
4192 /**
4193 * @brief Enable PLL output mapped on SYSCLK domain
4194 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
4195 * @retval None
4196 */
LL_RCC_PLL_EnableDomain_SYS(void)4197 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
4198 {
4199 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
4200 }
4201
4202 /**
4203 * @brief Disable PLL output mapped on SYSCLK domain
4204 * @note Cannot be disabled if the PLL clock is used as the system
4205 * clock
4206 * @note In order to save power, when the PLLCLK of the PLL is
4207 * not used, Main PLL should be 0
4208 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
4209 * @retval None
4210 */
LL_RCC_PLL_DisableDomain_SYS(void)4211 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
4212 {
4213 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
4214 }
4215
4216 /**
4217 * @brief Check if PLL output mapped on SYSCLK domain clock is enabled
4218 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
4219 * @retval State of bit (1 or 0).
4220 */
LL_RCC_PLL_IsEnabledDomain_SYS(void)4221 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
4222 {
4223 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
4224 }
4225
4226 /**
4227 * @}
4228 */
4229
4230 #if defined(RCC_PLLSAI1_SUPPORT)
4231 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
4232 * @{
4233 */
4234
4235 /**
4236 * @brief Enable PLLSAI1
4237 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
4238 * @retval None
4239 */
LL_RCC_PLLSAI1_Enable(void)4240 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
4241 {
4242 SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
4243 }
4244
4245 /**
4246 * @brief Disable PLLSAI1
4247 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
4248 * @retval None
4249 */
LL_RCC_PLLSAI1_Disable(void)4250 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
4251 {
4252 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
4253 }
4254
4255 /**
4256 * @brief Check if PLLSAI1 Ready
4257 * @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
4258 * @retval State of bit (1 or 0).
4259 */
LL_RCC_PLLSAI1_IsReady(void)4260 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
4261 {
4262 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RCC_CR_PLLSAI1RDY) ? 1UL : 0UL);
4263 }
4264
4265 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
4266 /**
4267 * @brief Configure PLLSAI1 used for 48Mhz domain clock
4268 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
4269 * @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
4270 * @note This can be selected for USB, RNG, SDMMC
4271 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
4272 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n
4273 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
4274 * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
4275 * @param Source This parameter can be one of the following values:
4276 * @arg @ref LL_RCC_PLLSOURCE_NONE
4277 * @arg @ref LL_RCC_PLLSOURCE_MSI
4278 * @arg @ref LL_RCC_PLLSOURCE_HSI
4279 * @arg @ref LL_RCC_PLLSOURCE_HSE
4280 * @param PLLM This parameter can be one of the following values:
4281 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
4282 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
4283 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
4284 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
4285 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
4286 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
4287 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
4288 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
4289 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
4290 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
4291 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
4292 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
4293 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
4294 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
4295 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
4296 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
4297 * @param PLLN Between 8 and 86 or 127 depending on devices
4298 * @param PLLQ This parameter can be one of the following values:
4299 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
4300 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
4301 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
4302 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
4303 * @retval None
4304 */
LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)4305 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
4306 {
4307 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4308 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
4309 PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLQ);
4310 }
4311 #else
4312 /**
4313 * @brief Configure PLLSAI1 used for 48Mhz domain clock
4314 * @note PLL Source and PLLM Divider can be written only when PLL,
4315 * PLLSAI1 and PLLSAI2 (*) are disabled.
4316 * @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
4317 * @note This can be selected for USB, RNG, SDMMC
4318 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
4319 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
4320 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
4321 * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
4322 * @param Source This parameter can be one of the following values:
4323 * @arg @ref LL_RCC_PLLSOURCE_NONE
4324 * @arg @ref LL_RCC_PLLSOURCE_MSI
4325 * @arg @ref LL_RCC_PLLSOURCE_HSI
4326 * @arg @ref LL_RCC_PLLSOURCE_HSE
4327 * @param PLLM This parameter can be one of the following values:
4328 * @arg @ref LL_RCC_PLLM_DIV_1
4329 * @arg @ref LL_RCC_PLLM_DIV_2
4330 * @arg @ref LL_RCC_PLLM_DIV_3
4331 * @arg @ref LL_RCC_PLLM_DIV_4
4332 * @arg @ref LL_RCC_PLLM_DIV_5
4333 * @arg @ref LL_RCC_PLLM_DIV_6
4334 * @arg @ref LL_RCC_PLLM_DIV_7
4335 * @arg @ref LL_RCC_PLLM_DIV_8
4336 * @param PLLN Between 8 and 86 or 127 depending on devices
4337 * @param PLLQ This parameter can be one of the following values:
4338 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
4339 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
4340 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
4341 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
4342 * @retval None
4343 */
LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)4344 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
4345 {
4346 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4347 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ);
4348 }
4349 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
4350
4351 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
4352 /**
4353 * @brief Configure PLLSAI1 used for SAI domain clock
4354 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
4355 * @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
4356 * @note This can be selected for SAI1 or SAI2
4357 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4358 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4359 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4360 * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
4361 * @param Source This parameter can be one of the following values:
4362 * @arg @ref LL_RCC_PLLSOURCE_NONE
4363 * @arg @ref LL_RCC_PLLSOURCE_MSI
4364 * @arg @ref LL_RCC_PLLSOURCE_HSI
4365 * @arg @ref LL_RCC_PLLSOURCE_HSE
4366 * @param PLLM This parameter can be one of the following values:
4367 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
4368 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
4369 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
4370 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
4371 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
4372 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
4373 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
4374 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
4375 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
4376 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
4377 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
4378 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
4379 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
4380 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
4381 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
4382 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
4383 * @param PLLN Between 8 and 86 or 127 depending on devices
4384 * @param PLLP This parameter can be one of the following values:
4385 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
4386 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
4387 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
4388 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
4389 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
4390 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
4391 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
4392 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
4393 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
4394 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
4395 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
4396 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
4397 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
4398 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
4399 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
4400 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
4401 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
4402 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
4403 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
4404 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
4405 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
4406 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
4407 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
4408 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
4409 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
4410 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
4411 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
4412 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
4413 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
4414 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
4415 * @retval None
4416 */
LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4417 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4418 {
4419 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4420 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
4421 PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLP);
4422 }
4423 #elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
4424 /**
4425 * @brief Configure PLLSAI1 used for SAI domain clock
4426 * @note PLL Source and PLLM Divider can be written only when PLL,
4427 * PLLSAI1 and PLLSAI2 (*) are disabled.
4428 * @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
4429 * @note This can be selected for SAI1 or SAI2 (*)
4430 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4431 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4432 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4433 * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
4434 * @param Source This parameter can be one of the following values:
4435 * @arg @ref LL_RCC_PLLSOURCE_NONE
4436 * @arg @ref LL_RCC_PLLSOURCE_MSI
4437 * @arg @ref LL_RCC_PLLSOURCE_HSI
4438 * @arg @ref LL_RCC_PLLSOURCE_HSE
4439 * @param PLLM This parameter can be one of the following values:
4440 * @arg @ref LL_RCC_PLLM_DIV_1
4441 * @arg @ref LL_RCC_PLLM_DIV_2
4442 * @arg @ref LL_RCC_PLLM_DIV_3
4443 * @arg @ref LL_RCC_PLLM_DIV_4
4444 * @arg @ref LL_RCC_PLLM_DIV_5
4445 * @arg @ref LL_RCC_PLLM_DIV_6
4446 * @arg @ref LL_RCC_PLLM_DIV_7
4447 * @arg @ref LL_RCC_PLLM_DIV_8
4448 * @param PLLN Between 8 and 86 or 127 depending on devices
4449 * @param PLLP This parameter can be one of the following values:
4450 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
4451 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
4452 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
4453 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
4454 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
4455 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
4456 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
4457 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
4458 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
4459 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
4460 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
4461 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
4462 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
4463 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
4464 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
4465 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
4466 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
4467 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
4468 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
4469 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
4470 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
4471 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
4472 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
4473 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
4474 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
4475 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
4476 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
4477 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
4478 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
4479 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
4480 * @retval None
4481 */
LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4482 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4483 {
4484 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4485 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
4486 PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
4487 }
4488 #else
4489 /**
4490 * @brief Configure PLLSAI1 used for SAI domain clock
4491 * @note PLL Source and PLLM Divider can be written only when PLL,
4492 * PLLSAI1 and PLLSAI2 (*) are disabled.
4493 * @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled.
4494 * @note This can be selected for SAI1 or SAI2 (*)
4495 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4496 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4497 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4498 * PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI
4499 * @param Source This parameter can be one of the following values:
4500 * @arg @ref LL_RCC_PLLSOURCE_NONE
4501 * @arg @ref LL_RCC_PLLSOURCE_MSI
4502 * @arg @ref LL_RCC_PLLSOURCE_HSI
4503 * @arg @ref LL_RCC_PLLSOURCE_HSE
4504 * @param PLLM This parameter can be one of the following values:
4505 * @arg @ref LL_RCC_PLLM_DIV_1
4506 * @arg @ref LL_RCC_PLLM_DIV_2
4507 * @arg @ref LL_RCC_PLLM_DIV_3
4508 * @arg @ref LL_RCC_PLLM_DIV_4
4509 * @arg @ref LL_RCC_PLLM_DIV_5
4510 * @arg @ref LL_RCC_PLLM_DIV_6
4511 * @arg @ref LL_RCC_PLLM_DIV_7
4512 * @arg @ref LL_RCC_PLLM_DIV_8
4513 * @param PLLN Between 8 and 86
4514 * @param PLLP This parameter can be one of the following values:
4515 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
4516 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
4517 * @retval None
4518 */
LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4519 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4520 {
4521 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4522 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
4523 }
4524 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */
4525
4526 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
4527 /**
4528 * @brief Configure PLLSAI1 used for ADC domain clock
4529 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
4530 * @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled.
4531 * @note This can be selected for ADC
4532 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
4533 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n
4534 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
4535 * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
4536 * @param Source This parameter can be one of the following values:
4537 * @arg @ref LL_RCC_PLLSOURCE_NONE
4538 * @arg @ref LL_RCC_PLLSOURCE_MSI
4539 * @arg @ref LL_RCC_PLLSOURCE_HSI
4540 * @arg @ref LL_RCC_PLLSOURCE_HSE
4541 * @param PLLM This parameter can be one of the following values:
4542 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
4543 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
4544 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
4545 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
4546 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
4547 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
4548 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
4549 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
4550 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
4551 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
4552 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
4553 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
4554 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
4555 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
4556 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
4557 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
4558 * @param PLLN Between 8 and 86 or 127 depending on devices
4559 * @param PLLR This parameter can be one of the following values:
4560 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
4561 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
4562 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
4563 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
4564 * @retval None
4565 */
LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4566 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4567 {
4568 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4569 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
4570 PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLR);
4571 }
4572 #else
4573 /**
4574 * @brief Configure PLLSAI1 used for ADC domain clock
4575 * @note PLL Source and PLLM Divider can be written only when PLL,
4576 * PLLSAI1 and PLLSAI2 (*) are disabled.
4577 * @note PLLN/PLLR can be written only when PLLSAI1 is disabled.
4578 * @note This can be selected for ADC
4579 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
4580 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
4581 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
4582 * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
4583 * @param Source This parameter can be one of the following values:
4584 * @arg @ref LL_RCC_PLLSOURCE_NONE
4585 * @arg @ref LL_RCC_PLLSOURCE_MSI
4586 * @arg @ref LL_RCC_PLLSOURCE_HSI
4587 * @arg @ref LL_RCC_PLLSOURCE_HSE
4588 * @param PLLM This parameter can be one of the following values:
4589 * @arg @ref LL_RCC_PLLM_DIV_1
4590 * @arg @ref LL_RCC_PLLM_DIV_2
4591 * @arg @ref LL_RCC_PLLM_DIV_3
4592 * @arg @ref LL_RCC_PLLM_DIV_4
4593 * @arg @ref LL_RCC_PLLM_DIV_5
4594 * @arg @ref LL_RCC_PLLM_DIV_6
4595 * @arg @ref LL_RCC_PLLM_DIV_7
4596 * @arg @ref LL_RCC_PLLM_DIV_8
4597 * @param PLLN Between 8 and 86 or 127 depending on devices
4598 * @param PLLR This parameter can be one of the following values:
4599 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
4600 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
4601 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
4602 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
4603 * @retval None
4604 */
LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4605 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4606 {
4607 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4608 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR);
4609 }
4610 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
4611
4612 /**
4613 * @brief Get SAI1PLL multiplication factor for VCO
4614 * @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN
4615 * @retval Between 8 and 86 or 127 depending on devices
4616 */
LL_RCC_PLLSAI1_GetN(void)4617 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
4618 {
4619 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
4620 }
4621
4622 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
4623 /**
4624 * @brief Get SAI1PLL division factor for PLLSAI1P
4625 * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
4626 * @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP
4627 * @retval Returned value can be one of the following values:
4628 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
4629 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
4630 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
4631 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
4632 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
4633 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
4634 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
4635 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
4636 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
4637 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
4638 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
4639 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
4640 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
4641 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
4642 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
4643 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
4644 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
4645 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
4646 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
4647 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
4648 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
4649 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
4650 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
4651 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
4652 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
4653 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
4654 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
4655 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
4656 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
4657 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
4658 */
LL_RCC_PLLSAI1_GetP(void)4659 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
4660 {
4661 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
4662 }
4663 #else
4664 /**
4665 * @brief Get SAI1PLL division factor for PLLSAI1P
4666 * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
4667 * @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
4668 * @retval Returned value can be one of the following values:
4669 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
4670 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
4671 */
LL_RCC_PLLSAI1_GetP(void)4672 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
4673 {
4674 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
4675 }
4676 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
4677
4678 /**
4679 * @brief Get SAI1PLL division factor for PLLSAI1Q
4680 * @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
4681 * @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
4682 * @retval Returned value can be one of the following values:
4683 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
4684 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
4685 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
4686 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
4687 */
LL_RCC_PLLSAI1_GetQ(void)4688 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
4689 {
4690 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
4691 }
4692
4693 /**
4694 * @brief Get PLLSAI1 division factor for PLLSAIR
4695 * @note Used for PLLADC1CLK (ADC clock)
4696 * @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
4697 * @retval Returned value can be one of the following values:
4698 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
4699 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
4700 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
4701 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
4702 */
LL_RCC_PLLSAI1_GetR(void)4703 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
4704 {
4705 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
4706 }
4707
4708 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
4709 /**
4710 * @brief Get Division factor for the PLLSAI1
4711 * @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider
4712 * @retval Returned value can be one of the following values:
4713 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
4714 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
4715 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
4716 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
4717 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
4718 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
4719 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
4720 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
4721 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
4722 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
4723 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
4724 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
4725 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
4726 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
4727 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
4728 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
4729 */
LL_RCC_PLLSAI1_GetDivider(void)4730 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void)
4731 {
4732 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M));
4733 }
4734 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
4735
4736 /**
4737 * @brief Enable PLLSAI1 output mapped on SAI domain clock
4738 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
4739 * @retval None
4740 */
LL_RCC_PLLSAI1_EnableDomain_SAI(void)4741 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
4742 {
4743 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
4744 }
4745
4746 /**
4747 * @brief Disable PLLSAI1 output mapped on SAI domain clock
4748 * @note In order to save power, when of the PLLSAI1 is
4749 * not used, should be 0
4750 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
4751 * @retval None
4752 */
LL_RCC_PLLSAI1_DisableDomain_SAI(void)4753 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
4754 {
4755 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
4756 }
4757
4758 /**
4759 * @brief Check if PLLSAI1 output mapped on SAI domain clock is enabled
4760 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_IsEnabledDomain_SAI
4761 * @retval State of bit (1 or 0).
4762 */
LL_RCC_PLLSAI1_IsEnabledDomain_SAI(void)4763 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_SAI(void)
4764 {
4765 return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN) == (RCC_PLLSAI1CFGR_PLLSAI1PEN)) ? 1UL : 0UL);
4766 }
4767
4768 /**
4769 * @brief Enable PLLSAI1 output mapped on 48MHz domain clock
4770 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
4771 * @retval None
4772 */
LL_RCC_PLLSAI1_EnableDomain_48M(void)4773 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
4774 {
4775 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
4776 }
4777
4778 /**
4779 * @brief Disable PLLSAI1 output mapped on 48MHz domain clock
4780 * @note In order to save power, when of the PLLSAI1 is
4781 * not used, should be 0
4782 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
4783 * @retval None
4784 */
LL_RCC_PLLSAI1_DisableDomain_48M(void)4785 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
4786 {
4787 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
4788 }
4789
4790 /**
4791 * @brief Check if PLLSAI1 output mapped on SAI domain clock is enabled
4792 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_IsEnabledDomain_48M
4793 * @retval State of bit (1 or 0).
4794 */
LL_RCC_PLLSAI1_IsEnabledDomain_48M(void)4795 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_48M(void)
4796 {
4797 return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN) == (RCC_PLLSAI1CFGR_PLLSAI1QEN)) ? 1UL : 0UL);
4798 }
4799
4800 /**
4801 * @brief Enable PLLSAI1 output mapped on ADC domain clock
4802 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
4803 * @retval None
4804 */
LL_RCC_PLLSAI1_EnableDomain_ADC(void)4805 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
4806 {
4807 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
4808 }
4809
4810 /**
4811 * @brief Disable PLLSAI1 output mapped on ADC domain clock
4812 * @note In order to save power, when of the PLLSAI1 is
4813 * not used, Main PLLSAI1 should be 0
4814 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
4815 * @retval None
4816 */
LL_RCC_PLLSAI1_DisableDomain_ADC(void)4817 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
4818 {
4819 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
4820 }
4821
4822 /**
4823 * @brief Check if PLLSAI1 output mapped on ADC domain clock is enabled
4824 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_IsEnabledDomain_ADC
4825 * @retval State of bit (1 or 0).
4826 */
LL_RCC_PLLSAI1_IsEnabledDomain_ADC(void)4827 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_ADC(void)
4828 {
4829 return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN) == (RCC_PLLSAI1CFGR_PLLSAI1REN)) ? 1UL : 0UL);
4830 }
4831
4832 /**
4833 * @}
4834 */
4835 #endif /* RCC_PLLSAI1_SUPPORT */
4836
4837 #if defined(RCC_PLLSAI2_SUPPORT)
4838 /** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
4839 * @{
4840 */
4841
4842 /**
4843 * @brief Enable PLLSAI2
4844 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable
4845 * @retval None
4846 */
LL_RCC_PLLSAI2_Enable(void)4847 __STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
4848 {
4849 SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
4850 }
4851
4852 /**
4853 * @brief Disable PLLSAI2
4854 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable
4855 * @retval None
4856 */
LL_RCC_PLLSAI2_Disable(void)4857 __STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
4858 {
4859 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
4860 }
4861
4862 /**
4863 * @brief Check if PLLSAI2 Ready
4864 * @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady
4865 * @retval State of bit (1 or 0).
4866 */
LL_RCC_PLLSAI2_IsReady(void)4867 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
4868 {
4869 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY) ? 1UL : 0UL);
4870 }
4871
4872 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
4873 /**
4874 * @brief Configure PLLSAI2 used for SAI domain clock
4875 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
4876 * @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
4877 * @note This can be selected for SAI1 or SAI2
4878 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4879 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4880 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4881 * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
4882 * @param Source This parameter can be one of the following values:
4883 * @arg @ref LL_RCC_PLLSOURCE_NONE
4884 * @arg @ref LL_RCC_PLLSOURCE_MSI
4885 * @arg @ref LL_RCC_PLLSOURCE_HSI
4886 * @arg @ref LL_RCC_PLLSOURCE_HSE
4887 * @param PLLM This parameter can be one of the following values:
4888 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
4889 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
4890 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
4891 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
4892 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
4893 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
4894 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
4895 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
4896 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
4897 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
4898 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
4899 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
4900 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
4901 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
4902 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
4903 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
4904 * @param PLLN Between 8 and 86 or 127 depending on devices
4905 * @param PLLP This parameter can be one of the following values:
4906 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
4907 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
4908 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
4909 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
4910 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
4911 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
4912 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
4913 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
4914 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
4915 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
4916 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
4917 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
4918 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
4919 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
4920 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
4921 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
4922 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
4923 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
4924 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
4925 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
4926 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
4927 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
4928 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
4929 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
4930 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
4931 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
4932 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
4933 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
4934 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
4935 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
4936 * @retval None
4937 */
LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4938 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4939 {
4940 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4941 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
4942 PLLM | (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLP);
4943 }
4944 #elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
4945 /**
4946 * @brief Configure PLLSAI2 used for SAI domain clock
4947 * @note PLL Source and PLLM Divider can be written only when PLL,
4948 * PLLSAI1 and PLLSAI2 are disabled.
4949 * @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
4950 * @note This can be selected for SAI1 or SAI2
4951 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4952 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4953 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4954 * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
4955 * @param Source This parameter can be one of the following values:
4956 * @arg @ref LL_RCC_PLLSOURCE_NONE
4957 * @arg @ref LL_RCC_PLLSOURCE_MSI
4958 * @arg @ref LL_RCC_PLLSOURCE_HSI
4959 * @arg @ref LL_RCC_PLLSOURCE_HSE
4960 * @param PLLM This parameter can be one of the following values:
4961 * @arg @ref LL_RCC_PLLM_DIV_1
4962 * @arg @ref LL_RCC_PLLM_DIV_2
4963 * @arg @ref LL_RCC_PLLM_DIV_3
4964 * @arg @ref LL_RCC_PLLM_DIV_4
4965 * @arg @ref LL_RCC_PLLM_DIV_5
4966 * @arg @ref LL_RCC_PLLM_DIV_6
4967 * @arg @ref LL_RCC_PLLM_DIV_7
4968 * @arg @ref LL_RCC_PLLM_DIV_8
4969 * @param PLLN Between 8 and 86 or 127 depending on devices
4970 * @param PLLP This parameter can be one of the following values:
4971 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
4972 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
4973 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
4974 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
4975 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
4976 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
4977 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
4978 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
4979 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
4980 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
4981 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
4982 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
4983 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
4984 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
4985 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
4986 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
4987 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
4988 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
4989 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
4990 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
4991 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
4992 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
4993 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
4994 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
4995 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
4996 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
4997 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
4998 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
4999 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
5000 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
5001 * @retval None
5002 */
LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)5003 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
5004 {
5005 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
5006 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
5007 }
5008 #else
5009 /**
5010 * @brief Configure PLLSAI2 used for SAI domain clock
5011 * @note PLL Source and PLLM Divider can be written only when PLL,
5012 * PLLSAI2 and PLLSAI2 are disabled.
5013 * @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled.
5014 * @note This can be selected for SAI1 or SAI2
5015 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
5016 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
5017 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
5018 * PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI
5019 * @param Source This parameter can be one of the following values:
5020 * @arg @ref LL_RCC_PLLSOURCE_NONE
5021 * @arg @ref LL_RCC_PLLSOURCE_MSI
5022 * @arg @ref LL_RCC_PLLSOURCE_HSI
5023 * @arg @ref LL_RCC_PLLSOURCE_HSE
5024 * @param PLLM This parameter can be one of the following values:
5025 * @arg @ref LL_RCC_PLLM_DIV_1
5026 * @arg @ref LL_RCC_PLLM_DIV_2
5027 * @arg @ref LL_RCC_PLLM_DIV_3
5028 * @arg @ref LL_RCC_PLLM_DIV_4
5029 * @arg @ref LL_RCC_PLLM_DIV_5
5030 * @arg @ref LL_RCC_PLLM_DIV_6
5031 * @arg @ref LL_RCC_PLLM_DIV_7
5032 * @arg @ref LL_RCC_PLLM_DIV_8
5033 * @param PLLN Between 8 and 86
5034 * @param PLLP This parameter can be one of the following values:
5035 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
5036 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
5037 * @retval None
5038 */
LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)5039 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
5040 {
5041 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
5042 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
5043 }
5044 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */
5045
5046 #if defined(DSI)
5047 /**
5048 * @brief Configure PLLSAI2 used for DSI domain clock
5049 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
5050 * @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled.
5051 * @note This can be selected for DSI
5052 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI\n
5053 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI\n
5054 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI\n
5055 * PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI
5056 * @param Source This parameter can be one of the following values:
5057 * @arg @ref LL_RCC_PLLSOURCE_NONE
5058 * @arg @ref LL_RCC_PLLSOURCE_MSI
5059 * @arg @ref LL_RCC_PLLSOURCE_HSI
5060 * @arg @ref LL_RCC_PLLSOURCE_HSE
5061 * @param PLLM This parameter can be one of the following values:
5062 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
5063 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
5064 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
5065 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
5066 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
5067 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
5068 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
5069 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
5070 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
5071 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
5072 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
5073 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
5074 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
5075 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
5076 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
5077 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
5078 * @param PLLN Between 8 and 127
5079 * @param PLLQ This parameter can be one of the following values:
5080 * @arg @ref LL_RCC_PLLSAI2Q_DIV_2
5081 * @arg @ref LL_RCC_PLLSAI2Q_DIV_4
5082 * @arg @ref LL_RCC_PLLSAI2Q_DIV_6
5083 * @arg @ref LL_RCC_PLLSAI2Q_DIV_8
5084 * @retval None
5085 */
LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)5086 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
5087 {
5088 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5089 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q,
5090 (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLQ | PLLM);
5091 }
5092 #endif /* DSI */
5093
5094 #if defined(LTDC)
5095 /**
5096 * @brief Configure PLLSAI2 used for LTDC domain clock
5097 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
5098 * @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
5099 * @note This can be selected for LTDC
5100 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
5101 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
5102 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
5103 * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
5104 * CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC
5105 * @param Source This parameter can be one of the following values:
5106 * @arg @ref LL_RCC_PLLSOURCE_NONE
5107 * @arg @ref LL_RCC_PLLSOURCE_MSI
5108 * @arg @ref LL_RCC_PLLSOURCE_HSI
5109 * @arg @ref LL_RCC_PLLSOURCE_HSE
5110 * @param PLLM This parameter can be one of the following values:
5111 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
5112 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
5113 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
5114 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
5115 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
5116 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
5117 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
5118 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
5119 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
5120 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
5121 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
5122 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
5123 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
5124 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
5125 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
5126 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
5127 * @param PLLN Between 8 and 127
5128 * @param PLLR This parameter can be one of the following values:
5129 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
5130 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
5131 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
5132 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
5133 * @param PLLDIVR This parameter can be one of the following values:
5134 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
5135 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
5136 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
5137 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
5138 * @retval None
5139 */
LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR,uint32_t PLLDIVR)5140 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
5141 {
5142 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5143 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R,
5144 (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLR | PLLM);
5145 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR);
5146 }
5147 #else
5148 /**
5149 * @brief Configure PLLSAI2 used for ADC domain clock
5150 * @note PLL Source and PLLM Divider can be written only when PLL,
5151 * PLLSAI2 and PLLSAI2 are disabled.
5152 * @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
5153 * @note This can be selected for ADC
5154 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n
5155 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n
5156 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n
5157 * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC
5158 * @param Source This parameter can be one of the following values:
5159 * @arg @ref LL_RCC_PLLSOURCE_NONE
5160 * @arg @ref LL_RCC_PLLSOURCE_MSI
5161 * @arg @ref LL_RCC_PLLSOURCE_HSI
5162 * @arg @ref LL_RCC_PLLSOURCE_HSE
5163 * @param PLLM This parameter can be one of the following values:
5164 * @arg @ref LL_RCC_PLLM_DIV_1
5165 * @arg @ref LL_RCC_PLLM_DIV_2
5166 * @arg @ref LL_RCC_PLLM_DIV_3
5167 * @arg @ref LL_RCC_PLLM_DIV_4
5168 * @arg @ref LL_RCC_PLLM_DIV_5
5169 * @arg @ref LL_RCC_PLLM_DIV_6
5170 * @arg @ref LL_RCC_PLLM_DIV_7
5171 * @arg @ref LL_RCC_PLLM_DIV_8
5172 * @param PLLN Between 8 and 86
5173 * @param PLLR This parameter can be one of the following values:
5174 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
5175 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
5176 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
5177 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
5178 * @retval None
5179 */
LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)5180 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
5181 {
5182 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
5183 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR);
5184 }
5185 #endif /* LTDC */
5186
5187 /**
5188 * @brief Get SAI2PLL multiplication factor for VCO
5189 * @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN
5190 * @retval Between 8 and 86 or 127 depending on devices
5191 */
LL_RCC_PLLSAI2_GetN(void)5192 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
5193 {
5194 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
5195 }
5196
5197 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
5198 /**
5199 * @brief Get SAI2PLL division factor for PLLSAI2P
5200 * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
5201 * @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP
5202 * @retval Returned value can be one of the following values:
5203 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
5204 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
5205 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
5206 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
5207 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
5208 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
5209 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
5210 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
5211 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
5212 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
5213 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
5214 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
5215 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
5216 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
5217 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
5218 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
5219 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
5220 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
5221 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
5222 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
5223 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
5224 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
5225 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
5226 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
5227 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
5228 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
5229 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
5230 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
5231 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
5232 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
5233 */
LL_RCC_PLLSAI2_GetP(void)5234 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
5235 {
5236 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV));
5237 }
5238 #else
5239 /**
5240 * @brief Get SAI2PLL division factor for PLLSAI2P
5241 * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
5242 * @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
5243 * @retval Returned value can be one of the following values:
5244 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
5245 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
5246 */
LL_RCC_PLLSAI2_GetP(void)5247 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
5248 {
5249 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
5250 }
5251 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
5252
5253 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
5254 /**
5255 * @brief Get division factor for PLLSAI2Q
5256 * @note Used for PLLDSICLK (DSI clock)
5257 * @rmtoll PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ
5258 * @retval Returned value can be one of the following values:
5259 * @arg @ref LL_RCC_PLLSAI2Q_DIV_2
5260 * @arg @ref LL_RCC_PLLSAI2Q_DIV_4
5261 * @arg @ref LL_RCC_PLLSAI2Q_DIV_6
5262 * @arg @ref LL_RCC_PLLSAI2Q_DIV_8
5263 */
LL_RCC_PLLSAI2_GetQ(void)5264 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void)
5265 {
5266 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q));
5267 }
5268 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
5269
5270 /**
5271 * @brief Get SAI2PLL division factor for PLLSAI2R
5272 * @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices
5273 * @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
5274 * @retval Returned value can be one of the following values:
5275 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
5276 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
5277 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
5278 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
5279 */
LL_RCC_PLLSAI2_GetR(void)5280 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
5281 {
5282 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
5283 }
5284
5285 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
5286 /**
5287 * @brief Get Division factor for the PLLSAI2
5288 * @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider
5289 * @retval Returned value can be one of the following values:
5290 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
5291 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
5292 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
5293 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
5294 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
5295 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
5296 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
5297 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
5298 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
5299 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
5300 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
5301 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
5302 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
5303 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
5304 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
5305 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
5306 */
LL_RCC_PLLSAI2_GetDivider(void)5307 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void)
5308 {
5309 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M));
5310 }
5311 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
5312
5313 #if defined(RCC_CCIPR2_PLLSAI2DIVR)
5314 /**
5315 * @brief Get PLLSAI2 division factor for PLLSAI2DIVR
5316 * @note Used for LTDC domain clock
5317 * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR
5318 * @retval Returned value can be one of the following values:
5319 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
5320 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
5321 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
5322 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
5323 */
LL_RCC_PLLSAI2_GetDIVR(void)5324 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void)
5325 {
5326 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR));
5327 }
5328 #endif /* RCC_CCIPR2_PLLSAI2DIVR */
5329
5330 /**
5331 * @brief Enable PLLSAI2 output mapped on SAI domain clock
5332 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
5333 * @retval None
5334 */
LL_RCC_PLLSAI2_EnableDomain_SAI(void)5335 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
5336 {
5337 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
5338 }
5339
5340 /**
5341 * @brief Disable PLLSAI2 output mapped on SAI domain clock
5342 * @note In order to save power, when of the PLLSAI2 is
5343 * not used, should be 0
5344 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
5345 * @retval None
5346 */
LL_RCC_PLLSAI2_DisableDomain_SAI(void)5347 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
5348 {
5349 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
5350 }
5351
5352 /**
5353 * @brief Check if PLLSAI2 output mapped on SAI domain clock is enabled
5354 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_IsEnabledDomain_SAI
5355 * @retval State of bit (1 or 0).
5356 */
LL_RCC_PLLSAI2_IsEnabledDomain_SAI(void)5357 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_SAI(void)
5358 {
5359 return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN) == (RCC_PLLSAI2CFGR_PLLSAI2PEN)) ? 1UL : 0UL);
5360 }
5361
5362 #if defined(DSI)
5363 /**
5364 * @brief Enable PLLSAI2 output mapped on DSI domain clock
5365 * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI
5366 * @retval None
5367 */
LL_RCC_PLLSAI2_EnableDomain_DSI(void)5368 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void)
5369 {
5370 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
5371 }
5372
5373 /**
5374 * @brief Disable PLLSAI2 output mapped on DSI domain clock
5375 * @note In order to save power, when of the PLLSAI2 is
5376 * not used, Main PLLSAI2 should be 0
5377 * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI
5378 * @retval None
5379 */
LL_RCC_PLLSAI2_DisableDomain_DSI(void)5380 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void)
5381 {
5382 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
5383 }
5384
5385 /**
5386 * @brief Check if PLLSAI2 output mapped on DSI domain clock is enabled
5387 * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_IsEnabledDomain_DSI
5388 * @retval State of bit (1 or 0).
5389 */
LL_RCC_PLLSAI2_IsEnabledDomain_DSI(void)5390 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_DSI(void)
5391 {
5392 return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN) == (RCC_PLLSAI2CFGR_PLLSAI2QEN)) ? 1UL : 0UL);
5393 }
5394 #endif /* DSI */
5395
5396 #if defined(LTDC)
5397 /**
5398 * @brief Enable PLLSAI2 output mapped on LTDC domain clock
5399 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC
5400 * @retval None
5401 */
LL_RCC_PLLSAI2_EnableDomain_LTDC(void)5402 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void)
5403 {
5404 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5405 }
5406
5407 /**
5408 * @brief Disable PLLSAI2 output mapped on LTDC domain clock
5409 * @note In order to save power, when of the PLLSAI2 is
5410 * not used, Main PLLSAI2 should be 0
5411 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC
5412 * @retval None
5413 */
LL_RCC_PLLSAI2_DisableDomain_LTDC(void)5414 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void)
5415 {
5416 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5417 }
5418
5419 /**
5420 * @brief Check if PLLSAI2 output mapped on LTDC domain clock is enabled
5421 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_IsEnabledDomain_LTDC
5422 * @retval State of bit (1 or 0).
5423 */
LL_RCC_PLLSAI2_IsEnabledDomain_LTDC(void)5424 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_LTDC(void)
5425 {
5426 return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN) == (RCC_PLLSAI2CFGR_PLLSAI2REN)) ? 1UL : 0UL);
5427 }
5428 #else
5429 /**
5430 * @brief Enable PLLSAI2 output mapped on ADC domain clock
5431 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC
5432 * @retval None
5433 */
LL_RCC_PLLSAI2_EnableDomain_ADC(void)5434 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
5435 {
5436 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5437 }
5438
5439 /**
5440 * @brief Disable PLLSAI2 output mapped on ADC domain clock
5441 * @note In order to save power, when of the PLLSAI2 is
5442 * not used, Main PLLSAI2 should be 0
5443 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC
5444 * @retval None
5445 */
LL_RCC_PLLSAI2_DisableDomain_ADC(void)5446 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
5447 {
5448 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5449 }
5450
5451 /**
5452 * @brief Check if PLLSAI2 output mapped on ADC domain clock is enabled
5453 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_IsEnabledDomain_ADC
5454 * @retval State of bit (1 or 0).
5455 */
LL_RCC_PLLSAI2_IsEnabledDomain_ADC(void)5456 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_ADC(void)
5457 {
5458 return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN) == (RCC_PLLSAI2CFGR_PLLSAI2REN)) ? 1UL : 0UL);
5459 }
5460 #endif /* LTDC */
5461
5462 /**
5463 * @}
5464 */
5465 #endif /* RCC_PLLSAI2_SUPPORT */
5466
5467 #if defined(OCTOSPI1)
5468 /** @defgroup RCC_LL_EF_OCTOSPI OCTOSPI
5469 * @{
5470 */
5471
5472 /**
5473 * @brief Configure OCTOSPI1 DQS delay
5474 * @rmtoll DLYCFGR OCTOSPI1_DLY LL_RCC_OCTOSPI1_DelayConfig
5475 * @param Delay OCTOSPI1 DQS delay between 0 and 15
5476 * @retval None
5477 */
LL_RCC_OCTOSPI1_DelayConfig(uint32_t Delay)5478 __STATIC_INLINE void LL_RCC_OCTOSPI1_DelayConfig(uint32_t Delay)
5479 {
5480 MODIFY_REG(RCC->DLYCFGR, RCC_DLYCFGR_OCTOSPI1_DLY, Delay);
5481 }
5482
5483 #if defined(OCTOSPI2)
5484 /**
5485 * @brief Configure OCTOSPI2 DQS delay
5486 * @rmtoll DLYCFGR OCTOSPI2_DLY LL_RCC_OCTOSPI2_DelayConfig
5487 * @param Delay OCTOSPI2 DQS delay between 0 and 15
5488 * @retval None
5489 */
LL_RCC_OCTOSPI2_DelayConfig(uint32_t Delay)5490 __STATIC_INLINE void LL_RCC_OCTOSPI2_DelayConfig(uint32_t Delay)
5491 {
5492 MODIFY_REG(RCC->DLYCFGR, RCC_DLYCFGR_OCTOSPI2_DLY, (Delay << RCC_DLYCFGR_OCTOSPI2_DLY_Pos));
5493 }
5494 #endif /* OCTOSPI2 */
5495
5496 /**
5497 * @}
5498 */
5499 #endif /* OCTOSPI1 */
5500
5501 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
5502 * @{
5503 */
5504
5505 /**
5506 * @brief Clear LSI ready interrupt flag
5507 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
5508 * @retval None
5509 */
LL_RCC_ClearFlag_LSIRDY(void)5510 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
5511 {
5512 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
5513 }
5514
5515 /**
5516 * @brief Clear LSE ready interrupt flag
5517 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
5518 * @retval None
5519 */
LL_RCC_ClearFlag_LSERDY(void)5520 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
5521 {
5522 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
5523 }
5524
5525 /**
5526 * @brief Clear MSI ready interrupt flag
5527 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
5528 * @retval None
5529 */
LL_RCC_ClearFlag_MSIRDY(void)5530 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
5531 {
5532 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
5533 }
5534
5535 /**
5536 * @brief Clear HSI ready interrupt flag
5537 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
5538 * @retval None
5539 */
LL_RCC_ClearFlag_HSIRDY(void)5540 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
5541 {
5542 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
5543 }
5544
5545 /**
5546 * @brief Clear HSE ready interrupt flag
5547 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
5548 * @retval None
5549 */
LL_RCC_ClearFlag_HSERDY(void)5550 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
5551 {
5552 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
5553 }
5554
5555 /**
5556 * @brief Clear PLL ready interrupt flag
5557 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
5558 * @retval None
5559 */
LL_RCC_ClearFlag_PLLRDY(void)5560 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
5561 {
5562 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
5563 }
5564
5565 #if defined(RCC_HSI48_SUPPORT)
5566 /**
5567 * @brief Clear HSI48 ready interrupt flag
5568 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
5569 * @retval None
5570 */
LL_RCC_ClearFlag_HSI48RDY(void)5571 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
5572 {
5573 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
5574 }
5575 #endif /* RCC_HSI48_SUPPORT */
5576
5577 #if defined(RCC_PLLSAI1_SUPPORT)
5578 /**
5579 * @brief Clear PLLSAI1 ready interrupt flag
5580 * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
5581 * @retval None
5582 */
LL_RCC_ClearFlag_PLLSAI1RDY(void)5583 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
5584 {
5585 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
5586 }
5587 #endif /* RCC_PLLSAI1_SUPPORT */
5588
5589 #if defined(RCC_PLLSAI2_SUPPORT)
5590 /**
5591 * @brief Clear PLLSAI1 ready interrupt flag
5592 * @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY
5593 * @retval None
5594 */
LL_RCC_ClearFlag_PLLSAI2RDY(void)5595 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
5596 {
5597 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
5598 }
5599 #endif /* RCC_PLLSAI2_SUPPORT */
5600
5601 /**
5602 * @brief Clear Clock security system interrupt flag
5603 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
5604 * @retval None
5605 */
LL_RCC_ClearFlag_HSECSS(void)5606 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
5607 {
5608 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
5609 }
5610
5611 /**
5612 * @brief Clear LSE Clock security system interrupt flag
5613 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
5614 * @retval None
5615 */
LL_RCC_ClearFlag_LSECSS(void)5616 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
5617 {
5618 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
5619 }
5620
5621 /**
5622 * @brief Check if LSI ready interrupt occurred or not
5623 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
5624 * @retval State of bit (1 or 0).
5625 */
LL_RCC_IsActiveFlag_LSIRDY(void)5626 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
5627 {
5628 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
5629 }
5630
5631 /**
5632 * @brief Check if LSE ready interrupt occurred or not
5633 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
5634 * @retval State of bit (1 or 0).
5635 */
LL_RCC_IsActiveFlag_LSERDY(void)5636 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
5637 {
5638 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
5639 }
5640
5641 /**
5642 * @brief Check if MSI ready interrupt occurred or not
5643 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
5644 * @retval State of bit (1 or 0).
5645 */
LL_RCC_IsActiveFlag_MSIRDY(void)5646 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
5647 {
5648 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL);
5649 }
5650
5651 /**
5652 * @brief Check if HSI ready interrupt occurred or not
5653 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
5654 * @retval State of bit (1 or 0).
5655 */
LL_RCC_IsActiveFlag_HSIRDY(void)5656 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
5657 {
5658 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
5659 }
5660
5661 /**
5662 * @brief Check if HSE ready interrupt occurred or not
5663 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
5664 * @retval State of bit (1 or 0).
5665 */
LL_RCC_IsActiveFlag_HSERDY(void)5666 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
5667 {
5668 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
5669 }
5670
5671 /**
5672 * @brief Check if PLL ready interrupt occurred or not
5673 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
5674 * @retval State of bit (1 or 0).
5675 */
LL_RCC_IsActiveFlag_PLLRDY(void)5676 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
5677 {
5678 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == RCC_CIFR_PLLRDYF) ? 1UL : 0UL);
5679 }
5680
5681 #if defined(RCC_HSI48_SUPPORT)
5682 /**
5683 * @brief Check if HSI48 ready interrupt occurred or not
5684 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
5685 * @retval State of bit (1 or 0).
5686 */
LL_RCC_IsActiveFlag_HSI48RDY(void)5687 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
5688 {
5689 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL);
5690 }
5691 #endif /* RCC_HSI48_SUPPORT */
5692
5693 #if defined(RCC_PLLSAI1_SUPPORT)
5694 /**
5695 * @brief Check if PLLSAI1 ready interrupt occurred or not
5696 * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
5697 * @retval State of bit (1 or 0).
5698 */
LL_RCC_IsActiveFlag_PLLSAI1RDY(void)5699 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
5700 {
5701 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) ? 1UL : 0UL);
5702 }
5703 #endif /* RCC_PLLSAI1_SUPPORT */
5704
5705 #if defined(RCC_PLLSAI2_SUPPORT)
5706 /**
5707 * @brief Check if PLLSAI1 ready interrupt occurred or not
5708 * @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY
5709 * @retval State of bit (1 or 0).
5710 */
LL_RCC_IsActiveFlag_PLLSAI2RDY(void)5711 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
5712 {
5713 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) ? 1UL : 0UL);
5714 }
5715 #endif /* RCC_PLLSAI2_SUPPORT */
5716
5717 /**
5718 * @brief Check if Clock security system interrupt occurred or not
5719 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
5720 * @retval State of bit (1 or 0).
5721 */
LL_RCC_IsActiveFlag_HSECSS(void)5722 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
5723 {
5724 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL);
5725 }
5726
5727 /**
5728 * @brief Check if LSE Clock security system interrupt occurred or not
5729 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
5730 * @retval State of bit (1 or 0).
5731 */
LL_RCC_IsActiveFlag_LSECSS(void)5732 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
5733 {
5734 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL);
5735 }
5736
5737 /**
5738 * @brief Check if RCC flag FW reset is set or not.
5739 * @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
5740 * @retval State of bit (1 or 0).
5741 */
LL_RCC_IsActiveFlag_FWRST(void)5742 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
5743 {
5744 return ((READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == RCC_CSR_FWRSTF) ? 1UL : 0UL);
5745 }
5746
5747 /**
5748 * @brief Check if RCC flag Independent Watchdog reset is set or not.
5749 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
5750 * @retval State of bit (1 or 0).
5751 */
LL_RCC_IsActiveFlag_IWDGRST(void)5752 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
5753 {
5754 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
5755 }
5756
5757 /**
5758 * @brief Check if RCC flag Low Power reset is set or not.
5759 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
5760 * @retval State of bit (1 or 0).
5761 */
LL_RCC_IsActiveFlag_LPWRRST(void)5762 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
5763 {
5764 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
5765 }
5766
5767 /**
5768 * @brief Check if RCC flag is set or not.
5769 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
5770 * @retval State of bit (1 or 0).
5771 */
LL_RCC_IsActiveFlag_OBLRST(void)5772 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
5773 {
5774 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
5775 }
5776
5777 /**
5778 * @brief Check if RCC flag Pin reset is set or not.
5779 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
5780 * @retval State of bit (1 or 0).
5781 */
LL_RCC_IsActiveFlag_PINRST(void)5782 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
5783 {
5784 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
5785 }
5786
5787 /**
5788 * @brief Check if RCC flag Software reset is set or not.
5789 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
5790 * @retval State of bit (1 or 0).
5791 */
LL_RCC_IsActiveFlag_SFTRST(void)5792 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
5793 {
5794 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
5795 }
5796
5797 /**
5798 * @brief Check if RCC flag Window Watchdog reset is set or not.
5799 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
5800 * @retval State of bit (1 or 0).
5801 */
LL_RCC_IsActiveFlag_WWDGRST(void)5802 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
5803 {
5804 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
5805 }
5806
5807 /**
5808 * @brief Check if RCC flag BOR reset is set or not.
5809 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
5810 * @retval State of bit (1 or 0).
5811 */
LL_RCC_IsActiveFlag_BORRST(void)5812 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
5813 {
5814 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL);
5815 }
5816
5817 /**
5818 * @brief Set RMVF bit to clear the reset flags.
5819 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
5820 * @retval None
5821 */
LL_RCC_ClearResetFlags(void)5822 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
5823 {
5824 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
5825 }
5826
5827 /**
5828 * @}
5829 */
5830
5831 /** @defgroup RCC_LL_EF_IT_Management IT Management
5832 * @{
5833 */
5834
5835 /**
5836 * @brief Enable LSI ready interrupt
5837 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
5838 * @retval None
5839 */
LL_RCC_EnableIT_LSIRDY(void)5840 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
5841 {
5842 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5843 }
5844
5845 /**
5846 * @brief Enable LSE ready interrupt
5847 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
5848 * @retval None
5849 */
LL_RCC_EnableIT_LSERDY(void)5850 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
5851 {
5852 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5853 }
5854
5855 /**
5856 * @brief Enable MSI ready interrupt
5857 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
5858 * @retval None
5859 */
LL_RCC_EnableIT_MSIRDY(void)5860 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
5861 {
5862 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
5863 }
5864
5865 /**
5866 * @brief Enable HSI ready interrupt
5867 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
5868 * @retval None
5869 */
LL_RCC_EnableIT_HSIRDY(void)5870 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
5871 {
5872 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5873 }
5874
5875 /**
5876 * @brief Enable HSE ready interrupt
5877 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
5878 * @retval None
5879 */
LL_RCC_EnableIT_HSERDY(void)5880 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
5881 {
5882 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5883 }
5884
5885 /**
5886 * @brief Enable PLL ready interrupt
5887 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
5888 * @retval None
5889 */
LL_RCC_EnableIT_PLLRDY(void)5890 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
5891 {
5892 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
5893 }
5894
5895 #if defined(RCC_HSI48_SUPPORT)
5896 /**
5897 * @brief Enable HSI48 ready interrupt
5898 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
5899 * @retval None
5900 */
LL_RCC_EnableIT_HSI48RDY(void)5901 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
5902 {
5903 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
5904 }
5905 #endif /* RCC_HSI48_SUPPORT */
5906
5907 #if defined(RCC_PLLSAI1_SUPPORT)
5908 /**
5909 * @brief Enable PLLSAI1 ready interrupt
5910 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
5911 * @retval None
5912 */
LL_RCC_EnableIT_PLLSAI1RDY(void)5913 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
5914 {
5915 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
5916 }
5917 #endif /* RCC_PLLSAI1_SUPPORT */
5918
5919 #if defined(RCC_PLLSAI2_SUPPORT)
5920 /**
5921 * @brief Enable PLLSAI2 ready interrupt
5922 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY
5923 * @retval None
5924 */
LL_RCC_EnableIT_PLLSAI2RDY(void)5925 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
5926 {
5927 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
5928 }
5929 #endif /* RCC_PLLSAI2_SUPPORT */
5930
5931 /**
5932 * @brief Enable LSE clock security system interrupt
5933 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
5934 * @retval None
5935 */
LL_RCC_EnableIT_LSECSS(void)5936 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
5937 {
5938 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
5939 }
5940
5941 /**
5942 * @brief Disable LSI ready interrupt
5943 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
5944 * @retval None
5945 */
LL_RCC_DisableIT_LSIRDY(void)5946 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
5947 {
5948 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5949 }
5950
5951 /**
5952 * @brief Disable LSE ready interrupt
5953 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
5954 * @retval None
5955 */
LL_RCC_DisableIT_LSERDY(void)5956 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
5957 {
5958 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5959 }
5960
5961 /**
5962 * @brief Disable MSI ready interrupt
5963 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
5964 * @retval None
5965 */
LL_RCC_DisableIT_MSIRDY(void)5966 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
5967 {
5968 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
5969 }
5970
5971 /**
5972 * @brief Disable HSI ready interrupt
5973 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
5974 * @retval None
5975 */
LL_RCC_DisableIT_HSIRDY(void)5976 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
5977 {
5978 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5979 }
5980
5981 /**
5982 * @brief Disable HSE ready interrupt
5983 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
5984 * @retval None
5985 */
LL_RCC_DisableIT_HSERDY(void)5986 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
5987 {
5988 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5989 }
5990
5991 /**
5992 * @brief Disable PLL ready interrupt
5993 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
5994 * @retval None
5995 */
LL_RCC_DisableIT_PLLRDY(void)5996 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
5997 {
5998 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
5999 }
6000
6001 #if defined(RCC_HSI48_SUPPORT)
6002 /**
6003 * @brief Disable HSI48 ready interrupt
6004 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
6005 * @retval None
6006 */
LL_RCC_DisableIT_HSI48RDY(void)6007 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
6008 {
6009 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
6010 }
6011 #endif /* RCC_HSI48_SUPPORT */
6012
6013 #if defined(RCC_PLLSAI1_SUPPORT)
6014 /**
6015 * @brief Disable PLLSAI1 ready interrupt
6016 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
6017 * @retval None
6018 */
LL_RCC_DisableIT_PLLSAI1RDY(void)6019 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
6020 {
6021 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
6022 }
6023 #endif /* RCC_PLLSAI1_SUPPORT */
6024
6025 #if defined(RCC_PLLSAI2_SUPPORT)
6026 /**
6027 * @brief Disable PLLSAI2 ready interrupt
6028 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY
6029 * @retval None
6030 */
LL_RCC_DisableIT_PLLSAI2RDY(void)6031 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
6032 {
6033 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
6034 }
6035 #endif /* RCC_PLLSAI2_SUPPORT */
6036
6037 /**
6038 * @brief Disable LSE clock security system interrupt
6039 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
6040 * @retval None
6041 */
LL_RCC_DisableIT_LSECSS(void)6042 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
6043 {
6044 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
6045 }
6046
6047 /**
6048 * @brief Checks if LSI ready interrupt source is enabled or disabled.
6049 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
6050 * @retval State of bit (1 or 0).
6051 */
LL_RCC_IsEnabledIT_LSIRDY(void)6052 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
6053 {
6054 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
6055 }
6056
6057 /**
6058 * @brief Checks if LSE ready interrupt source is enabled or disabled.
6059 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
6060 * @retval State of bit (1 or 0).
6061 */
LL_RCC_IsEnabledIT_LSERDY(void)6062 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
6063 {
6064 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
6065 }
6066
6067 /**
6068 * @brief Checks if MSI ready interrupt source is enabled or disabled.
6069 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
6070 * @retval State of bit (1 or 0).
6071 */
LL_RCC_IsEnabledIT_MSIRDY(void)6072 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
6073 {
6074 return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL);
6075 }
6076
6077 /**
6078 * @brief Checks if HSI ready interrupt source is enabled or disabled.
6079 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
6080 * @retval State of bit (1 or 0).
6081 */
LL_RCC_IsEnabledIT_HSIRDY(void)6082 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
6083 {
6084 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
6085 }
6086
6087 /**
6088 * @brief Checks if HSE ready interrupt source is enabled or disabled.
6089 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
6090 * @retval State of bit (1 or 0).
6091 */
LL_RCC_IsEnabledIT_HSERDY(void)6092 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
6093 {
6094 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
6095 }
6096
6097 /**
6098 * @brief Checks if PLL ready interrupt source is enabled or disabled.
6099 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
6100 * @retval State of bit (1 or 0).
6101 */
LL_RCC_IsEnabledIT_PLLRDY(void)6102 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
6103 {
6104 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == RCC_CIER_PLLRDYIE) ? 1UL : 0UL);
6105 }
6106
6107 #if defined(RCC_HSI48_SUPPORT)
6108 /**
6109 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
6110 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
6111 * @retval State of bit (1 or 0).
6112 */
LL_RCC_IsEnabledIT_HSI48RDY(void)6113 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
6114 {
6115 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
6116 }
6117 #endif /* RCC_HSI48_SUPPORT */
6118
6119 #if defined(RCC_PLLSAI1_SUPPORT)
6120 /**
6121 * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
6122 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
6123 * @retval State of bit (1 or 0).
6124 */
LL_RCC_IsEnabledIT_PLLSAI1RDY(void)6125 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
6126 {
6127 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == RCC_CIER_PLLSAI1RDYIE) ? 1UL : 0UL);
6128 }
6129 #endif /* RCC_PLLSAI1_SUPPORT */
6130
6131 #if defined(RCC_PLLSAI2_SUPPORT)
6132 /**
6133 * @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled.
6134 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY
6135 * @retval State of bit (1 or 0).
6136 */
LL_RCC_IsEnabledIT_PLLSAI2RDY(void)6137 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
6138 {
6139 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == RCC_CIER_PLLSAI2RDYIE) ? 1UL : 0UL);
6140 }
6141 #endif /* RCC_PLLSAI2_SUPPORT */
6142
6143 /**
6144 * @brief Checks if LSECSS interrupt source is enabled or disabled.
6145 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
6146 * @retval State of bit (1 or 0).
6147 */
LL_RCC_IsEnabledIT_LSECSS(void)6148 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
6149 {
6150 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);
6151 }
6152
6153 /**
6154 * @}
6155 */
6156
6157 #if defined(USE_FULL_LL_DRIVER)
6158 /** @defgroup RCC_LL_EF_Init De-initialization function
6159 * @{
6160 */
6161 ErrorStatus LL_RCC_DeInit(void);
6162 /**
6163 * @}
6164 */
6165
6166 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
6167 * @{
6168 */
6169 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
6170 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
6171 #if defined(UART4) || defined(UART5)
6172 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
6173 #endif /* UART4 || UART5 */
6174 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
6175 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
6176 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
6177 #if defined(SAI1)
6178 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
6179 #endif /* SAI1 */
6180 #if defined(SDMMC1)
6181 #if defined(RCC_CCIPR2_SDMMCSEL)
6182 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);
6183 #endif
6184 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
6185 #endif /* SDMMC1 */
6186 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
6187 #if defined(USB_OTG_FS) || defined(USB)
6188 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
6189 #endif /* USB_OTG_FS || USB */
6190 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
6191 #if defined(SWPMI1)
6192 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);
6193 #endif /* SWPMI1 */
6194 #if defined(DFSDM1_Channel0)
6195 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
6196 #if defined(RCC_CCIPR2_DFSDM1SEL)
6197 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
6198 #endif /* RCC_CCIPR2_DFSDM1SEL */
6199 #endif /* DFSDM1_Channel0 */
6200 #if defined(LTDC)
6201 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
6202 #endif /* LTDC */
6203 #if defined(DSI)
6204 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
6205 #endif /* DSI */
6206 #if defined(OCTOSPI1)
6207 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
6208 #endif /* OCTOSPI1 */
6209 /**
6210 * @}
6211 */
6212 #endif /* USE_FULL_LL_DRIVER */
6213
6214 /**
6215 * @}
6216 */
6217
6218 /**
6219 * @}
6220 */
6221
6222 #endif /* defined(RCC) */
6223
6224 /**
6225 * @}
6226 */
6227
6228 #ifdef __cplusplus
6229 }
6230 #endif
6231
6232 #endif /* STM32L4xx_LL_RCC_H */
6233
6234
