1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef STM32G0xx_LL_RCC_H
20 #define STM32G0xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32g0xx.h"
28
29 /** @addtogroup STM32G0xx_LL_Driver
30 * @{
31 */
32
33 #if defined(RCC)
34
35 /** @defgroup RCC_LL RCC
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
42 * @{
43 */
44
45
46 /**
47 * @}
48 */
49
50 /* Private constants ---------------------------------------------------------*/
51 /* Private macros ------------------------------------------------------------*/
52 #if defined(USE_FULL_LL_DRIVER)
53 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
54 * @{
55 */
56 /**
57 * @}
58 */
59 #endif /*USE_FULL_LL_DRIVER*/
60
61 /* Exported types ------------------------------------------------------------*/
62 #if defined(USE_FULL_LL_DRIVER)
63 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
64 * @{
65 */
66
67 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
68 * @{
69 */
70
71 /**
72 * @brief RCC Clocks Frequency Structure
73 */
74 typedef struct
75 {
76 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
77 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
78 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
79 } LL_RCC_ClocksTypeDef;
80
81 /**
82 * @}
83 */
84
85 /**
86 * @}
87 */
88 #endif /* USE_FULL_LL_DRIVER */
89
90 /* Exported constants --------------------------------------------------------*/
91 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
92 * @{
93 */
94
95 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
96 * @brief Defines used to adapt values of different oscillators
97 * @note These values could be modified in the user environment according to
98 * HW set-up.
99 * @{
100 */
101 #if !defined (HSE_VALUE)
102 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
103 #endif /* HSE_VALUE */
104
105 #if !defined (HSI_VALUE)
106 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
107 #endif /* HSI_VALUE */
108
109 #if !defined (LSE_VALUE)
110 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
111 #endif /* LSE_VALUE */
112
113 #if !defined (LSI_VALUE)
114 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
115 #endif /* LSI_VALUE */
116 #if !defined (EXTERNAL_CLOCK_VALUE)
117 #define EXTERNAL_CLOCK_VALUE 48000000U /*!< Value of the I2S_CKIN external oscillator in Hz */
118 #endif /* EXTERNAL_CLOCK_VALUE */
119
120 #if defined(RCC_HSI48_SUPPORT)
121 #if !defined (HSI48_VALUE)
122 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
123 #endif /* HSI48_VALUE */
124 #endif /* RCC_HSI48_SUPPORT */
125 /**
126 * @}
127 */
128
129 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
130 * @brief Flags defines which can be used with LL_RCC_WriteReg function
131 * @{
132 */
133 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
134 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
135 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
136 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
137 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
138 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
139 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
140 #if defined(RCC_HSI48_SUPPORT)
141 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
142 #endif /* RCC_HSI48_SUPPORT */
143 /**
144 * @}
145 */
146
147 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
148 * @brief Flags defines which can be used with LL_RCC_ReadReg function
149 * @{
150 */
151 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
152 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
153 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
154 #if defined(RCC_HSI48_SUPPORT)
155 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
156 #endif /* RCC_HSI48_SUPPORT */
157 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
158 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
159 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
160 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
161 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
162 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
163 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
164 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
165 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
166 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
167 #define LL_RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */
168 /**
169 * @}
170 */
171
172 /** @defgroup RCC_LL_EC_IT IT Defines
173 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
174 * @{
175 */
176 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
177 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
178 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
179 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
180 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
181 #if defined(RCC_HSI48_SUPPORT)
182 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
183 #endif /* RCC_HSI48_SUPPORT */
184 /**
185 * @}
186 */
187
188 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
189 * @{
190 */
191 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
192 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
193 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
194 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
195 /**
196 * @}
197 */
198
199 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
200 * @{
201 */
202 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
203 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
204 /**
205 * @}
206 */
207
208 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
209 * @{
210 */
211 #define LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */
212 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */
213 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_1 /*!< PLL selection as system clock */
214 #define LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection used as system clock */
215 #define LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection used as system clock */
216 /**
217 * @}
218 */
219
220 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
221 * @{
222 */
223 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */
224 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */
225 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_1 /*!< PLL used as system clock */
226 #define LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */
227 #define LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */
228 /**
229 * @}
230 */
231
232 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
233 * @{
234 */
235 #define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
236 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
237 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
238 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
239 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
240 #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
241 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
242 #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
243 #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
244 /**
245 * @}
246 */
247
248 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
249 * @{
250 */
251 #define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */
252 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */
253 #define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */
254 #define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */
255 #define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */
256 /**
257 * @}
258 */
259
260 /** @defgroup RCC_LL_EC_HSI_DIV HSI division factor
261 * @{
262 */
263 #define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI not divided */
264 #define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI divided by 2 */
265 #define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI divided by 4 */
266 #define LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0) /*!< HSI divided by 8 */
267 #define LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2 /*!< HSI divided by 16 */
268 #define LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0) /*!< HSI divided by 32 */
269 #define LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1) /*!< HSI divided by 64 */
270 #define LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV /*!< HSI divided by 128 */
271 /**
272 * @}
273 */
274
275 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
276 * @{
277 */
278 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
279 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
280 #if defined(RCC_HSI48_SUPPORT)
281 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1 /*!< HSI48 selection as MCO1 source */
282 #endif /* RCC_HSI48_SUPPORT */
283 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
284 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
285 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
286 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
287 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
288 #if defined(RCC_CFGR_MCOSEL_3)
289 #define LL_RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3 /*!< PLLPCLK selection as MCO1 source */
290 #define LL_RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0) /*!< PLLQCLK selection as MCO1 source */
291 #define LL_RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1) /*!< RTCCLK selection as MCO1 source */
292 #define LL_RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0) /*!< RTC_Wakeup selection as MCO1 source */
293 #endif /* RCC_CFGR_MCOSEL_3 */
294 /**
295 * @}
296 */
297
298 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
299 * @{
300 */
301 #define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO1 not divided */
302 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO1 divided by 2 */
303 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO1 divided by 4 */
304 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 8 */
305 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO1 divided by 16 */
306 #define LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 32 */
307 #define LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO1 divided by 64 */
308 #define LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 128 */
309 #if defined(RCC_CFGR_MCOPRE_3)
310 #define LL_RCC_MCO1_DIV_256 RCC_CFGR_MCOPRE_3 /*!< MCO divided by 256 */
311 #define LL_RCC_MCO1_DIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 512 */
312 #define LL_RCC_MCO1_DIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 1024 */
313 #endif /* RCC_CFGR_MCOPRE_3 */
314 /**
315 * @}
316 */
317
318 #if defined(RCC_MCO2_SUPPORT)
319 /** @defgroup RCC_LL_EC_MCO2SOURCE MCO2 SOURCE selection
320 * @{
321 */
322 #define LL_RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
323 #define LL_RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */
324 #if defined(RCC_HSI48_SUPPORT)
325 #define LL_RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1 /*!< HSI48 selection as MCO2 source */
326 #endif /* RCC_HSI48_SUPPORT */
327 #define LL_RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< HSI16 selection as MCO2 source */
328 #define LL_RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */
329 #define LL_RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0) /*!< Main PLL "R" clock selection as MCO2 source */
330 #define LL_RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1) /*!< LSI selection as MCO2 source */
331 #define LL_RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< LSE selection as MCO2 source */
332 #define LL_RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3 /*!< PLL "P" clock selection as MCO2 source */
333 #define LL_RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_0) /*!< PLL "Q" clock selection as MCO2 source */
334 #define LL_RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1) /*!< RTC Clock selection as MCO2 source */
335 #define LL_RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< RTC Wakeup timer selection as MCO2 source */
336 /**
337 * @}
338 */
339
340 /** @defgroup RCC_LL_EC_MCO2_DIV MCO2 prescaler
341 * @{
342 */
343 #define LL_RCC_MCO2_DIV_1 0x00000000U /*!< MCO2 not divided */
344 #define LL_RCC_MCO2_DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO2 divided by 2 */
345 #define LL_RCC_MCO2_DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO2 divided by 4 */
346 #define LL_RCC_MCO2_DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 8 */
347 #define LL_RCC_MCO2_DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO2 divided by 16 */
348 #define LL_RCC_MCO2_DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 32 */
349 #define LL_RCC_MCO2_DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 64 */
350 #define LL_RCC_MCO2_DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */
351 #define LL_RCC_MCO2_DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO2 divided by 256 */
352 #define LL_RCC_MCO2_DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 512 */
353 #define LL_RCC_MCO2_DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 1024 */
354 /**
355 * @}
356 */
357 #endif /* RCC_MCO2_SUPPORT */
358
359 #if defined(USE_FULL_LL_DRIVER)
360 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
361 * @{
362 */
363 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
364 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
365 /**
366 * @}
367 */
368 #endif /* USE_FULL_LL_DRIVER */
369
370 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
371 * @{
372 */
373 #define LL_RCC_USART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART1 clock source */
374 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
375 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
376 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
377 #define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */
378 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
379 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
380 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
381 #if defined(RCC_CCIPR_USART3SEL)
382 #define LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART3SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */
383 #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
384 #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
385 #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
386 #endif /* RCC_CCIPR_USART3SEL */
387 /**
388 * @}
389 */
390
391 #if defined(LPUART1) || defined(LPUART2)
392 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection
393 * @{
394 */
395 #if defined(LPUART2)
396 #define LL_RCC_LPUART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as LPUART2 clock source */
397 #define LL_RCC_LPUART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_0) /*!< SYSCLK clock used as LPUART2 clock source */
398 #define LL_RCC_LPUART2_CLKSOURCE_HSI ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_1) /*!< HSI clock used as LPUART2 clock source */
399 #define LL_RCC_LPUART2_CLKSOURCE_LSE ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL) /*!< LSE clock used as LPUART2 clock source */
400 #endif /* LPUART2 */
401 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as LPUART1 clock source */
402 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_0) /*!< SYSCLK clock used as LPUART1 clock source */
403 #define LL_RCC_LPUART1_CLKSOURCE_HSI ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_1) /*!< HSI clock used as LPUART1 clock source */
404 #define LL_RCC_LPUART1_CLKSOURCE_LSE ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL) /*!< LSE clock used as LPUART1 clock source */
405 /**
406 * @}
407 */
408 #endif /* LPUART1 || LPUART2 */
409
410 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
411 * @{
412 */
413 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */
414 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_0) /*!< SYSCLK clock used as I2C1 clock source */
415 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_1) /*!< HSI clock used as I2C1 clock source */
416 #if defined(RCC_CCIPR_I2C2SEL)
417 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */
418 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_0) /*!< SYSCLK clock used as I2C2 clock source */
419 #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_1) /*!< HSI clock used as I2C2 clock source */
420 #endif /* RCC_CCIPR_I2C2SEL */
421 /**
422 * @}
423 */
424
425 /** @defgroup RCC_LL_EC_I2Sx_CLKSOURCE Peripheral I2S clock source selection
426 * @{
427 */
428 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
429 #define LL_RCC_I2S1_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S1SEL << 16U) | 0x00000000U) /*!< SYSCLK clock used as I2S1 clock source */
430 #define LL_RCC_I2S1_CLKSOURCE_PLL ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_0) /*!< PLL clock used as I2S1 clock source */
431 #define LL_RCC_I2S1_CLKSOURCE_HSI ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_1) /*!< HSI clock used as I2S1 clock source */
432 #define LL_RCC_I2S1_CLKSOURCE_PIN ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL) /*!< External clock used as I2S1 clock source */
433 #define LL_RCC_I2S2_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S2SEL << 16U) | 0x00000000U) /*!< SYSCLK clock used as I2S2 clock source */
434 #define LL_RCC_I2S2_CLKSOURCE_PLL ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_0) /*!< PLL clock used as I2S2 clock source */
435 #define LL_RCC_I2S2_CLKSOURCE_HSI ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_1) /*!< HSI clock used as I2S2 clock source */
436 #define LL_RCC_I2S2_CLKSOURCE_PIN ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL) /*!< External clock used as I2S2 clock source */
437 #else
438 #define LL_RCC_I2S1_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as I2S1 clock source */
439 #define LL_RCC_I2S1_CLKSOURCE_PLL RCC_CCIPR_I2S1SEL_0 /*!< PLL clock used as I2S1 clock source */
440 #define LL_RCC_I2S1_CLKSOURCE_HSI RCC_CCIPR_I2S1SEL_1 /*!< HSI clock used as I2S1 clock source */
441 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CCIPR_I2S1SEL /*!< External clock used as I2S1 clock source */
442 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
443
444 /**
445 * @}
446 */
447
448 #if defined(RCC_CCIPR_TIM1SEL)
449 /** @defgroup RCC_LL_EC_TIMx_CLKSOURCE Peripheral TIM clock source selection
450 * @{
451 */
452 #define LL_RCC_TIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM1SEL | (0x00000000U >> 16U)) /*!< PCLK1 clock used as TIM1 clock source */
453 #define LL_RCC_TIM1_CLKSOURCE_PLL (RCC_CCIPR_TIM1SEL | (RCC_CCIPR_TIM1SEL >> 16U)) /*!< PLL used as TIM1 clock source */
454 /**
455 * @}
456 */
457 #endif /* RCC_CCIPR_TIM1SEL */
458
459 #if defined(RCC_CCIPR_TIM15SEL)
460 /** @addtogroup RCC_LL_EC_TIMx_CLKSOURCE
461 * @{
462 */
463 #define LL_RCC_TIM15_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM15SEL | (0x00000000U >> 16U)) /*!< PCLK1 clock used as TIM15 clock source */
464 #define LL_RCC_TIM15_CLKSOURCE_PLL (RCC_CCIPR_TIM15SEL | (RCC_CCIPR_TIM15SEL >> 16U)) /*!< PLL used as TIM15 clock source */
465 /**
466 * @}
467 */
468 #endif /* RCC_CCIPR_TIM15SEL */
469
470 #if defined(LPTIM1) && defined(LPTIM2)
471 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection
472 * @{
473 */
474 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16U)) /*!< PCLK1 selected as LPTIM1 clock */
475 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI selected as LPTIM1 clock */
476 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI selected as LPTIM1 clock */
477 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) /*!< LSE selected as LPTIM1 clock */
478 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16U)) /*!< PCLK1 selected as LPTIM2 clock */
479 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI selected as LPTIM2 clock */
480 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI selected as LPTIM2 clock */
481 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) /*!< LSE selected as LPTIM2 clock */
482 /**
483 * @}
484 */
485 #endif /* LPTIM1 && LPTIM2*/
486
487 #if defined(CEC)
488 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE_HSI Peripheral CEC clock source selection
489 * @{
490 */
491 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */
492 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CCIPR_CECSEL /*!< LSE oscillator clock used as CEC clock */
493
494 /**
495 * @}
496 */
497 #endif /* CEC */
498
499 #if defined(FDCAN1) || defined(FDCAN2)
500 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE_HSI Peripheral FDCAN clock source selection
501 * @{
502 */
503 #define LL_RCC_FDCAN_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 oscillator clock used as FDCAN clock */
504 #define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0 /*!< PLL "Q" oscillator clock used as FDCAN clock */
505 #define LL_RCC_FDCAN_CLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1 /*!< HSE oscillator clock used as FDCAN clock */
506
507 /**
508 * @}
509 */
510 #endif /* FDCAN1 || FDCAN2 */
511
512 #if defined(RNG)
513 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
514 * @{
515 */
516 #define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock */
517 #define LL_RCC_RNG_CLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0 /*!< HSI oscillator clock divided by 8 used as RNG clock, available on cut2.0 */
518 #define LL_RCC_RNG_CLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1 /*!< SYSCLK divided by 1 used as RNG clock */
519 #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_RNGSEL /*!< PLL used as RNG clock */
520 /**
521 * @}
522 */
523 #endif /* RNG */
524
525 #if defined(RNG)
526 /** @defgroup RCC_LL_EC_RNG_CLK_DIV Peripheral RNG clock division factor
527 * @{
528 */
529 #define LL_RCC_RNG_CLK_DIV1 0x00000000U /*!< RNG clock not divided */
530 #define LL_RCC_RNG_CLK_DIV2 RCC_CCIPR_RNGDIV_0 /*!< RNG clock divided by 2 */
531 #define LL_RCC_RNG_CLK_DIV4 RCC_CCIPR_RNGDIV_1 /*!< RNG clock divided by 4 */
532 #define LL_RCC_RNG_CLK_DIV8 RCC_CCIPR_RNGDIV /*!< RNG clock divided by 8 */
533 /**
534 * @}
535 */
536 #endif /* RNG */
537
538 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
539 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
540 * @{
541 */
542 #if defined(RCC_HSI48_SUPPORT)
543 #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
544 #endif /* RCC_HSI48_SUPPORT */
545 #define LL_RCC_USB_CLKSOURCE_HSE RCC_CCIPR2_USBSEL_0 /*!< PLL clock used as USB clock source */
546 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR2_USBSEL_1 /*!< PLL clock used as USB clock source */
547 /**
548 * @}
549 */
550 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
551
552 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
553 * @{
554 */
555 #define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */
556 #define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_0 /*!< PLL used as ADC clock */
557 #define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_1 /*!< HSI used as ADC clock */
558 /**
559 * @}
560 */
561
562 /** @defgroup RCC_LL_EC_USARTx Peripheral USARTx get clock source
563 * @{
564 */
565 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
566 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
567 #if defined(RCC_CCIPR_USART3SEL)
568 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
569 #endif /* RCC_CCIPR_USART3SEL */
570 /**
571 * @}
572 */
573
574 #if defined(LPUART1)
575 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
576 * @{
577 */
578 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
579 #if defined(LPUART2)
580 #define LL_RCC_LPUART2_CLKSOURCE RCC_CCIPR_LPUART2SEL /*!< LPUART2 Clock source selection */
581 #endif /* LPUART2 */
582 /**
583 * @}
584 */
585 #endif /* LPUART1 */
586
587 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
588 * @{
589 */
590 #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */
591 #if defined(RCC_CCIPR_I2C2SEL)
592 #define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL /*!< I2C2 Clock source selection */
593 #endif /* RCC_CCIPR_I2C2SEL */
594 /**
595 * @}
596 */
597
598 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
599 * @{
600 */
601 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
602 #define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR2_I2S1SEL /*!< I2S1 Clock source selection */
603 #define LL_RCC_I2S2_CLKSOURCE RCC_CCIPR2_I2S2SEL /*!< I2S2 Clock source selection */
604 #else
605 #define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR_I2S1SEL /*!< I2S1 Clock source selection */
606 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
607 /**
608 * @}
609 */
610
611 #if defined(RCC_CCIPR_TIM1SEL)
612 /** @defgroup RCC_LL_EC_TIMx Peripheral TIMx get clock source
613 * @{
614 */
615 #define LL_RCC_TIM1_CLKSOURCE RCC_CCIPR_TIM1SEL /*!< TIM1 Clock source selection */
616 #if defined(RCC_CCIPR_TIM15SEL)
617 #define LL_RCC_TIM15_CLKSOURCE RCC_CCIPR_TIM15SEL /*!< TIM15 Clock source selection */
618 #endif /* RCC_CCIPR_TIM15SEL */
619 /**
620 * @}
621 */
622 #endif /* RCC_CCIPR_TIM1SEL */
623
624 #if defined(LPTIM1) && defined(LPTIM2)
625 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
626 * @{
627 */
628 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM2 Clock source selection */
629 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */
630 /**
631 * @}
632 */
633 #endif /* LPTIM1 && LPTIM2 */
634
635 #if defined(CEC)
636 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
637 * @{
638 */
639 #define LL_RCC_CEC_CLKSOURCE RCC_CCIPR_CECSEL /*!< CEC Clock source selection */
640 /**
641 * @}
642 */
643 #endif /* CEC */
644
645 #if defined(FDCAN1) || defined(FDCAN2)
646 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
647 * @{
648 */
649 #define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR2_FDCANSEL /*!< FDCAN Clock source selection */
650 /**
651 * @}
652 */
653 #endif /* FDCAN1 */
654
655 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
656 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
657 * @{
658 */
659 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR2_USBSEL /*!< USB Clock source selection */
660 /**
661 * @}
662 */
663 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
664
665 #if defined(RNG)
666 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
667 * @{
668 */
669 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL /*!< RNG Clock source selection */
670 /**
671 * @}
672 */
673
674 /** @defgroup RCC_LL_EC_RNG_DIV Peripheral RNG get clock division factor
675 * @{
676 */
677 #define LL_RCC_RNG_CLKDIV RCC_CCIPR_RNGDIV /*!< RNG Clock division factor */
678 /**
679 * @}
680 */
681 #endif /* RNG */
682
683 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
684 * @{
685 */
686 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */
687 /**
688 * @}
689 */
690
691 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
692 * @{
693 */
694 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
695 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
696 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
697 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
698 /**
699 * @}
700 */
701
702
703 /** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
704 * @{
705 */
706 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
707 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
708 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
709 /**
710 * @}
711 */
712
713 /** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor (PLLM)
714 * @{
715 */
716 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL division factor by 1 */
717 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 2 */
718 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 3 */
719 #define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 4 */
720 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL division factor by 5 */
721 #define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 6 */
722 #define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL division factor by 7 */
723 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL division factor by 8 */
724 /**
725 * @}
726 */
727
728 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
729 * @{
730 */
731 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
732 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
733 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
734 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
735 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
736 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
737 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
738 /**
739 * @}
740 */
741
742 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
743 * @{
744 */
745 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
746 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
747 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
748 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
749 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
750 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
751 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */
752 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
753 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
754 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
755 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */
756 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
757 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */
758 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */
759 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */
760 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
761 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
762 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
763 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */
764 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
765 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */
766 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */
767 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */
768 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
769 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */
770 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/
771 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */
772 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */
773 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */
774 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */
775 #define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */
776 /**
777 * @}
778 */
779
780 #if defined(RCC_PLLQ_SUPPORT)
781 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
782 * @{
783 */
784 #define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 2 */
785 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 3 */
786 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
787 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 5 */
788 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */
789 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */
790 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
791 /**
792 * @}
793 */
794 #endif /* RCC_PLLQ_SUPPORT */
795
796 /**
797 * @}
798 */
799
800 /* Exported macro ------------------------------------------------------------*/
801 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
802 * @{
803 */
804
805 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
806 * @{
807 */
808
809 /**
810 * @brief Write a value in RCC register
811 * @param __REG__ Register to be written
812 * @param __VALUE__ Value to be written in the register
813 * @retval None
814 */
815 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__))
816
817 /**
818 * @brief Read a value in RCC register
819 * @param __REG__ Register to be read
820 * @retval Register value
821 */
822 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
823 /**
824 * @}
825 */
826
827 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
828 * @{
829 */
830
831 /**
832 * @brief Helper macro to calculate the PLLCLK frequency on system domain
833 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
834 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
835 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
836 * @param __PLLM__ This parameter can be one of the following values:
837 * @arg @ref LL_RCC_PLLM_DIV_1
838 * @arg @ref LL_RCC_PLLM_DIV_2
839 * @arg @ref LL_RCC_PLLM_DIV_3
840 * @arg @ref LL_RCC_PLLM_DIV_4
841 * @arg @ref LL_RCC_PLLM_DIV_5
842 * @arg @ref LL_RCC_PLLM_DIV_6
843 * @arg @ref LL_RCC_PLLM_DIV_7
844 * @arg @ref LL_RCC_PLLM_DIV_8
845 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
846 * @param __PLLR__ This parameter can be one of the following values:
847 * @arg @ref LL_RCC_PLLR_DIV_2
848 * @arg @ref LL_RCC_PLLR_DIV_3
849 * @arg @ref LL_RCC_PLLR_DIV_4
850 * @arg @ref LL_RCC_PLLR_DIV_5
851 * @arg @ref LL_RCC_PLLR_DIV_6
852 * @arg @ref LL_RCC_PLLR_DIV_7
853 * @arg @ref LL_RCC_PLLR_DIV_8
854 * @retval PLL clock frequency (in Hz)
855 */
856 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \
857 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
858 (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U))
859
860 /**
861 * @brief Helper macro to calculate the PLLPCLK frequency used on I2S domain
862 * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
863 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
864 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
865 * @param __PLLM__ This parameter can be one of the following values:
866 * @arg @ref LL_RCC_PLLM_DIV_1
867 * @arg @ref LL_RCC_PLLM_DIV_2
868 * @arg @ref LL_RCC_PLLM_DIV_3
869 * @arg @ref LL_RCC_PLLM_DIV_4
870 * @arg @ref LL_RCC_PLLM_DIV_5
871 * @arg @ref LL_RCC_PLLM_DIV_6
872 * @arg @ref LL_RCC_PLLM_DIV_7
873 * @arg @ref LL_RCC_PLLM_DIV_8
874 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
875 * @param __PLLP__ This parameter can be one of the following values:
876 * @arg @ref LL_RCC_PLLP_DIV_2
877 * @arg @ref LL_RCC_PLLP_DIV_3
878 * @arg @ref LL_RCC_PLLP_DIV_4
879 * @arg @ref LL_RCC_PLLP_DIV_5
880 * @arg @ref LL_RCC_PLLP_DIV_6
881 * @arg @ref LL_RCC_PLLP_DIV_7
882 * @arg @ref LL_RCC_PLLP_DIV_8
883 * @arg @ref LL_RCC_PLLP_DIV_9
884 * @arg @ref LL_RCC_PLLP_DIV_10
885 * @arg @ref LL_RCC_PLLP_DIV_11
886 * @arg @ref LL_RCC_PLLP_DIV_12
887 * @arg @ref LL_RCC_PLLP_DIV_13
888 * @arg @ref LL_RCC_PLLP_DIV_14
889 * @arg @ref LL_RCC_PLLP_DIV_15
890 * @arg @ref LL_RCC_PLLP_DIV_16
891 * @arg @ref LL_RCC_PLLP_DIV_17
892 * @arg @ref LL_RCC_PLLP_DIV_18
893 * @arg @ref LL_RCC_PLLP_DIV_19
894 * @arg @ref LL_RCC_PLLP_DIV_20
895 * @arg @ref LL_RCC_PLLP_DIV_21
896 * @arg @ref LL_RCC_PLLP_DIV_22
897 * @arg @ref LL_RCC_PLLP_DIV_23
898 * @arg @ref LL_RCC_PLLP_DIV_24
899 * @arg @ref LL_RCC_PLLP_DIV_25
900 * @arg @ref LL_RCC_PLLP_DIV_26
901 * @arg @ref LL_RCC_PLLP_DIV_27
902 * @arg @ref LL_RCC_PLLP_DIV_28
903 * @arg @ref LL_RCC_PLLP_DIV_29
904 * @arg @ref LL_RCC_PLLP_DIV_30
905 * @arg @ref LL_RCC_PLLP_DIV_31
906 * @arg @ref LL_RCC_PLLP_DIV_32
907 * @retval PLL clock frequency (in Hz)
908 */
909 #define __LL_RCC_CALC_PLLCLK_I2S1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \
910 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
911 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
912
913 #if defined(RCC_CCIPR2_I2S2SEL)
914 /**
915 * @brief Helper macro to calculate the PLLPCLK frequency used on I2S2 domain
916 * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S2_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
917 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
918 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
919 * @param __PLLM__ This parameter can be one of the following values:
920 * @arg @ref LL_RCC_PLLM_DIV_1
921 * @arg @ref LL_RCC_PLLM_DIV_2
922 * @arg @ref LL_RCC_PLLM_DIV_3
923 * @arg @ref LL_RCC_PLLM_DIV_4
924 * @arg @ref LL_RCC_PLLM_DIV_5
925 * @arg @ref LL_RCC_PLLM_DIV_6
926 * @arg @ref LL_RCC_PLLM_DIV_7
927 * @arg @ref LL_RCC_PLLM_DIV_8
928 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
929 * @param __PLLP__ This parameter can be one of the following values:
930 * @arg @ref LL_RCC_PLLP_DIV_2
931 * @arg @ref LL_RCC_PLLP_DIV_3
932 * @arg @ref LL_RCC_PLLP_DIV_4
933 * @arg @ref LL_RCC_PLLP_DIV_5
934 * @arg @ref LL_RCC_PLLP_DIV_6
935 * @arg @ref LL_RCC_PLLP_DIV_7
936 * @arg @ref LL_RCC_PLLP_DIV_8
937 * @arg @ref LL_RCC_PLLP_DIV_9
938 * @arg @ref LL_RCC_PLLP_DIV_10
939 * @arg @ref LL_RCC_PLLP_DIV_11
940 * @arg @ref LL_RCC_PLLP_DIV_12
941 * @arg @ref LL_RCC_PLLP_DIV_13
942 * @arg @ref LL_RCC_PLLP_DIV_14
943 * @arg @ref LL_RCC_PLLP_DIV_15
944 * @arg @ref LL_RCC_PLLP_DIV_16
945 * @arg @ref LL_RCC_PLLP_DIV_17
946 * @arg @ref LL_RCC_PLLP_DIV_18
947 * @arg @ref LL_RCC_PLLP_DIV_19
948 * @arg @ref LL_RCC_PLLP_DIV_20
949 * @arg @ref LL_RCC_PLLP_DIV_21
950 * @arg @ref LL_RCC_PLLP_DIV_22
951 * @arg @ref LL_RCC_PLLP_DIV_23
952 * @arg @ref LL_RCC_PLLP_DIV_24
953 * @arg @ref LL_RCC_PLLP_DIV_25
954 * @arg @ref LL_RCC_PLLP_DIV_26
955 * @arg @ref LL_RCC_PLLP_DIV_27
956 * @arg @ref LL_RCC_PLLP_DIV_28
957 * @arg @ref LL_RCC_PLLP_DIV_29
958 * @arg @ref LL_RCC_PLLP_DIV_30
959 * @arg @ref LL_RCC_PLLP_DIV_31
960 * @arg @ref LL_RCC_PLLP_DIV_32
961 * @retval PLL clock frequency (in Hz)
962 */
963 #define __LL_RCC_CALC_PLLCLK_I2S2_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \
964 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
965 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
966 #endif /* RCC_CCIPR2_I2S2SEL */
967
968 /**
969 * @brief Helper macro to calculate the PLLPCLK frequency used on ADC domain
970 * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
971 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
972 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
973 * @param __PLLM__ This parameter can be one of the following values:
974 * @arg @ref LL_RCC_PLLM_DIV_1
975 * @arg @ref LL_RCC_PLLM_DIV_2
976 * @arg @ref LL_RCC_PLLM_DIV_3
977 * @arg @ref LL_RCC_PLLM_DIV_4
978 * @arg @ref LL_RCC_PLLM_DIV_5
979 * @arg @ref LL_RCC_PLLM_DIV_6
980 * @arg @ref LL_RCC_PLLM_DIV_7
981 * @arg @ref LL_RCC_PLLM_DIV_8
982 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
983 * @param __PLLP__ This parameter can be one of the following values:
984 * @arg @ref LL_RCC_PLLP_DIV_2
985 * @arg @ref LL_RCC_PLLP_DIV_3
986 * @arg @ref LL_RCC_PLLP_DIV_4
987 * @arg @ref LL_RCC_PLLP_DIV_5
988 * @arg @ref LL_RCC_PLLP_DIV_6
989 * @arg @ref LL_RCC_PLLP_DIV_7
990 * @arg @ref LL_RCC_PLLP_DIV_8
991 * @arg @ref LL_RCC_PLLP_DIV_9
992 * @arg @ref LL_RCC_PLLP_DIV_10
993 * @arg @ref LL_RCC_PLLP_DIV_11
994 * @arg @ref LL_RCC_PLLP_DIV_12
995 * @arg @ref LL_RCC_PLLP_DIV_13
996 * @arg @ref LL_RCC_PLLP_DIV_14
997 * @arg @ref LL_RCC_PLLP_DIV_15
998 * @arg @ref LL_RCC_PLLP_DIV_16
999 * @arg @ref LL_RCC_PLLP_DIV_17
1000 * @arg @ref LL_RCC_PLLP_DIV_18
1001 * @arg @ref LL_RCC_PLLP_DIV_19
1002 * @arg @ref LL_RCC_PLLP_DIV_20
1003 * @arg @ref LL_RCC_PLLP_DIV_21
1004 * @arg @ref LL_RCC_PLLP_DIV_22
1005 * @arg @ref LL_RCC_PLLP_DIV_23
1006 * @arg @ref LL_RCC_PLLP_DIV_24
1007 * @arg @ref LL_RCC_PLLP_DIV_25
1008 * @arg @ref LL_RCC_PLLP_DIV_26
1009 * @arg @ref LL_RCC_PLLP_DIV_27
1010 * @arg @ref LL_RCC_PLLP_DIV_28
1011 * @arg @ref LL_RCC_PLLP_DIV_29
1012 * @arg @ref LL_RCC_PLLP_DIV_30
1013 * @arg @ref LL_RCC_PLLP_DIV_31
1014 * @arg @ref LL_RCC_PLLP_DIV_32
1015 * @retval PLL clock frequency (in Hz)
1016 */
1017 #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \
1018 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1019 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
1020
1021 #if defined(RNG)
1022 /**
1023 * @brief Helper macro to calculate the PLLQCLK frequency used on RNG domain
1024 * @note ex: @ref __LL_RCC_CALC_PLLCLK_RNG_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1025 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1026 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1027 * @param __PLLM__ This parameter can be one of the following values:
1028 * @arg @ref LL_RCC_PLLM_DIV_1
1029 * @arg @ref LL_RCC_PLLM_DIV_2
1030 * @arg @ref LL_RCC_PLLM_DIV_3
1031 * @arg @ref LL_RCC_PLLM_DIV_4
1032 * @arg @ref LL_RCC_PLLM_DIV_5
1033 * @arg @ref LL_RCC_PLLM_DIV_6
1034 * @arg @ref LL_RCC_PLLM_DIV_7
1035 * @arg @ref LL_RCC_PLLM_DIV_8
1036 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
1037 * @param __PLLQ__ This parameter can be one of the following values:
1038 * @arg @ref LL_RCC_PLLQ_DIV_2
1039 * @arg @ref LL_RCC_PLLQ_DIV_3
1040 * @arg @ref LL_RCC_PLLQ_DIV_4
1041 * @arg @ref LL_RCC_PLLQ_DIV_5
1042 * @arg @ref LL_RCC_PLLQ_DIV_6
1043 * @arg @ref LL_RCC_PLLQ_DIV_7
1044 * @arg @ref LL_RCC_PLLQ_DIV_8
1045 * @retval PLL clock frequency (in Hz)
1046 */
1047 #define __LL_RCC_CALC_PLLCLK_RNG_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
1048 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1049 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
1050 #endif /* RNG */
1051
1052 #if defined(RCC_PLLQ_SUPPORT)
1053 /**
1054 * @brief Helper macro to calculate the PLLQCLK frequency used on TIM1 domain
1055 * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1056 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1057 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1058 * @param __PLLM__ This parameter can be one of the following values:
1059 * @arg @ref LL_RCC_PLLM_DIV_1
1060 * @arg @ref LL_RCC_PLLM_DIV_2
1061 * @arg @ref LL_RCC_PLLM_DIV_3
1062 * @arg @ref LL_RCC_PLLM_DIV_4
1063 * @arg @ref LL_RCC_PLLM_DIV_5
1064 * @arg @ref LL_RCC_PLLM_DIV_6
1065 * @arg @ref LL_RCC_PLLM_DIV_7
1066 * @arg @ref LL_RCC_PLLM_DIV_8
1067 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
1068 * @param __PLLQ__ This parameter can be one of the following values:
1069 * @arg @ref LL_RCC_PLLQ_DIV_2
1070 * @arg @ref LL_RCC_PLLQ_DIV_3
1071 * @arg @ref LL_RCC_PLLQ_DIV_4
1072 * @arg @ref LL_RCC_PLLQ_DIV_5
1073 * @arg @ref LL_RCC_PLLQ_DIV_6
1074 * @arg @ref LL_RCC_PLLQ_DIV_7
1075 * @arg @ref LL_RCC_PLLQ_DIV_8
1076 * @retval PLL clock frequency (in Hz)
1077 */
1078 #define __LL_RCC_CALC_PLLCLK_TIM1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
1079 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1080 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
1081 #if defined(TIM15)
1082 /**
1083 * @brief Helper macro to calculate the PLLQCLK frequency used on TIM15 domain
1084 * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM15_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1085 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1086 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1087 * @param __PLLM__ This parameter can be one of the following values:
1088 * @arg @ref LL_RCC_PLLM_DIV_1
1089 * @arg @ref LL_RCC_PLLM_DIV_2
1090 * @arg @ref LL_RCC_PLLM_DIV_3
1091 * @arg @ref LL_RCC_PLLM_DIV_4
1092 * @arg @ref LL_RCC_PLLM_DIV_5
1093 * @arg @ref LL_RCC_PLLM_DIV_6
1094 * @arg @ref LL_RCC_PLLM_DIV_7
1095 * @arg @ref LL_RCC_PLLM_DIV_8
1096 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
1097 * @param __PLLQ__ This parameter can be one of the following values:
1098 * @arg @ref LL_RCC_PLLQ_DIV_2
1099 * @arg @ref LL_RCC_PLLQ_DIV_3
1100 * @arg @ref LL_RCC_PLLQ_DIV_4
1101 * @arg @ref LL_RCC_PLLQ_DIV_5
1102 * @arg @ref LL_RCC_PLLQ_DIV_6
1103 * @arg @ref LL_RCC_PLLQ_DIV_7
1104 * @arg @ref LL_RCC_PLLQ_DIV_8
1105 * @retval PLL clock frequency (in Hz)
1106 */
1107 #define __LL_RCC_CALC_PLLCLK_TIM15_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
1108 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1109 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
1110 #endif /* TIM15 */
1111 #endif /* RCC_PLLQ_SUPPORT */
1112
1113 #if defined(FDCAN1) || defined(FDCAN2)
1114 /**
1115 * @brief Helper macro to calculate the PLLQCLK frequency used on FDCAN domain
1116 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FDCAN_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1117 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1118 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1119 * @param __PLLM__ This parameter can be one of the following values:
1120 * @arg @ref LL_RCC_PLLM_DIV_1
1121 * @arg @ref LL_RCC_PLLM_DIV_2
1122 * @arg @ref LL_RCC_PLLM_DIV_3
1123 * @arg @ref LL_RCC_PLLM_DIV_4
1124 * @arg @ref LL_RCC_PLLM_DIV_5
1125 * @arg @ref LL_RCC_PLLM_DIV_6
1126 * @arg @ref LL_RCC_PLLM_DIV_7
1127 * @arg @ref LL_RCC_PLLM_DIV_8
1128 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
1129 * @param __PLLQ__ This parameter can be one of the following values:
1130 * @arg @ref LL_RCC_PLLQ_DIV_2
1131 * @arg @ref LL_RCC_PLLQ_DIV_3
1132 * @arg @ref LL_RCC_PLLQ_DIV_4
1133 * @arg @ref LL_RCC_PLLQ_DIV_5
1134 * @arg @ref LL_RCC_PLLQ_DIV_6
1135 * @arg @ref LL_RCC_PLLQ_DIV_7
1136 * @arg @ref LL_RCC_PLLQ_DIV_8
1137 * @retval PLL clock frequency (in Hz)
1138 */
1139 #define __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
1140 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1141 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
1142 #endif /* FDCAN1 || FDCAN2 */
1143
1144 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
1145 /**
1146 * @brief Helper macro to calculate the PLLQCLK frequency used on USB domain
1147 * @note ex: @ref __LL_RCC_CALC_PLLCLK_USB_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1148 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1149 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1150 * @param __PLLM__ This parameter can be one of the following values:
1151 * @arg @ref LL_RCC_PLLM_DIV_1
1152 * @arg @ref LL_RCC_PLLM_DIV_2
1153 * @arg @ref LL_RCC_PLLM_DIV_3
1154 * @arg @ref LL_RCC_PLLM_DIV_4
1155 * @arg @ref LL_RCC_PLLM_DIV_5
1156 * @arg @ref LL_RCC_PLLM_DIV_6
1157 * @arg @ref LL_RCC_PLLM_DIV_7
1158 * @arg @ref LL_RCC_PLLM_DIV_8
1159 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
1160 * @param __PLLQ__ This parameter can be one of the following values:
1161 * @arg @ref LL_RCC_PLLQ_DIV_2
1162 * @arg @ref LL_RCC_PLLQ_DIV_3
1163 * @arg @ref LL_RCC_PLLQ_DIV_4
1164 * @arg @ref LL_RCC_PLLQ_DIV_5
1165 * @arg @ref LL_RCC_PLLQ_DIV_6
1166 * @arg @ref LL_RCC_PLLQ_DIV_7
1167 * @arg @ref LL_RCC_PLLQ_DIV_8
1168 * @retval PLL clock frequency (in Hz)
1169 */
1170 #define __LL_RCC_CALC_PLLCLK_USB_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
1171 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1172 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
1173 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
1174
1175 /**
1176 * @brief Helper macro to calculate the HCLK frequency
1177 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
1178 * @param __AHBPRESCALER__ This parameter can be one of the following values:
1179 * @arg @ref LL_RCC_SYSCLK_DIV_1
1180 * @arg @ref LL_RCC_SYSCLK_DIV_2
1181 * @arg @ref LL_RCC_SYSCLK_DIV_4
1182 * @arg @ref LL_RCC_SYSCLK_DIV_8
1183 * @arg @ref LL_RCC_SYSCLK_DIV_16
1184 * @arg @ref LL_RCC_SYSCLK_DIV_64
1185 * @arg @ref LL_RCC_SYSCLK_DIV_128
1186 * @arg @ref LL_RCC_SYSCLK_DIV_256
1187 * @arg @ref LL_RCC_SYSCLK_DIV_512
1188 * @retval HCLK clock frequency (in Hz)
1189 */
1190 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) \
1191 ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))
1192
1193 /**
1194 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1195 * @param __HCLKFREQ__ HCLK frequency
1196 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1197 * @arg @ref LL_RCC_APB1_DIV_1
1198 * @arg @ref LL_RCC_APB1_DIV_2
1199 * @arg @ref LL_RCC_APB1_DIV_4
1200 * @arg @ref LL_RCC_APB1_DIV_8
1201 * @arg @ref LL_RCC_APB1_DIV_16
1202 * @retval PCLK1 clock frequency (in Hz)
1203 */
1204 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \
1205 ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos] & 0x1FU))
1206
1207 /**
1208 * @brief Helper macro to calculate the HSISYS frequency
1209 * @param __HSIDIV__ This parameter can be one of the following values:
1210 * @arg @ref LL_RCC_HSI_DIV_1
1211 * @arg @ref LL_RCC_HSI_DIV_2
1212 * @arg @ref LL_RCC_HSI_DIV_4
1213 * @arg @ref LL_RCC_HSI_DIV_8
1214 * @arg @ref LL_RCC_HSI_DIV_16
1215 * @arg @ref LL_RCC_HSI_DIV_32
1216 * @arg @ref LL_RCC_HSI_DIV_64
1217 * @arg @ref LL_RCC_HSI_DIV_128
1218 * @retval HSISYS clock frequency (in Hz)
1219 */
1220 #define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos)))
1221
1222 /**
1223 * @}
1224 */
1225
1226 /**
1227 * @}
1228 */
1229
1230 /* Exported functions --------------------------------------------------------*/
1231 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1232 * @{
1233 */
1234
1235 /** @defgroup RCC_LL_EF_HSE HSE
1236 * @{
1237 */
1238
1239 /**
1240 * @brief Enable the Clock Security System.
1241 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1242 * @retval None
1243 */
LL_RCC_HSE_EnableCSS(void)1244 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1245 {
1246 SET_BIT(RCC->CR, RCC_CR_CSSON);
1247 }
1248
1249 /**
1250 * @brief Enable HSE external oscillator (HSE Bypass)
1251 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1252 * @retval None
1253 */
LL_RCC_HSE_EnableBypass(void)1254 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1255 {
1256 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1257 }
1258
1259 /**
1260 * @brief Disable HSE external oscillator (HSE Bypass)
1261 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1262 * @retval None
1263 */
LL_RCC_HSE_DisableBypass(void)1264 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1265 {
1266 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1267 }
1268
1269 /**
1270 * @brief Enable HSE crystal oscillator (HSE ON)
1271 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1272 * @retval None
1273 */
LL_RCC_HSE_Enable(void)1274 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1275 {
1276 SET_BIT(RCC->CR, RCC_CR_HSEON);
1277 }
1278
1279 /**
1280 * @brief Disable HSE crystal oscillator (HSE ON)
1281 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1282 * @retval None
1283 */
LL_RCC_HSE_Disable(void)1284 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1285 {
1286 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1287 }
1288
1289 /**
1290 * @brief Check if HSE oscillator Ready
1291 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1292 * @retval State of bit (1 or 0).
1293 */
LL_RCC_HSE_IsReady(void)1294 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1295 {
1296 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
1297 }
1298
1299 /**
1300 * @}
1301 */
1302
1303 /** @defgroup RCC_LL_EF_HSI HSI
1304 * @{
1305 */
1306
1307 /**
1308 * @brief Enable HSI even in stop mode
1309 * @note HSI oscillator is forced ON even in Stop mode
1310 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
1311 * @retval None
1312 */
LL_RCC_HSI_EnableInStopMode(void)1313 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
1314 {
1315 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1316 }
1317
1318 /**
1319 * @brief Disable HSI in stop mode
1320 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
1321 * @retval None
1322 */
LL_RCC_HSI_DisableInStopMode(void)1323 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1324 {
1325 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1326 }
1327
1328 /**
1329 * @brief Check if HSI in stop mode is enabled
1330 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
1331 * @retval State of bit (1 or 0).
1332 */
LL_RCC_HSI_IsEnabledInStopMode(void)1333 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
1334 {
1335 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL);
1336 }
1337
1338 /**
1339 * @brief Enable HSI oscillator
1340 * @rmtoll CR HSION LL_RCC_HSI_Enable
1341 * @retval None
1342 */
LL_RCC_HSI_Enable(void)1343 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1344 {
1345 SET_BIT(RCC->CR, RCC_CR_HSION);
1346 }
1347
1348 /**
1349 * @brief Disable HSI oscillator
1350 * @rmtoll CR HSION LL_RCC_HSI_Disable
1351 * @retval None
1352 */
LL_RCC_HSI_Disable(void)1353 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1354 {
1355 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1356 }
1357
1358 /**
1359 * @brief Check if HSI clock is ready
1360 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1361 * @retval State of bit (1 or 0).
1362 */
LL_RCC_HSI_IsReady(void)1363 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1364 {
1365 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
1366 }
1367
1368 /**
1369 * @brief Get HSI Calibration value
1370 * @note When HSITRIM is written, HSICAL is updated with the sum of
1371 * HSITRIM and the factory trim value
1372 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
1373 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1374 */
LL_RCC_HSI_GetCalibration(void)1375 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1376 {
1377 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
1378 }
1379
1380 /**
1381 * @brief Set HSI Calibration trimming
1382 * @note user-programmable trimming value that is added to the HSICAL
1383 * @note Default value is 64, which, when added to the HSICAL value,
1384 * should trim the HSI to 16 MHz +/- 1 %
1385 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
1386 * @param Value Between Min_Data = 0 and Max_Data = 127
1387 * @retval None
1388 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1389 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1390 {
1391 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
1392 }
1393
1394 /**
1395 * @brief Get HSI Calibration trimming
1396 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
1397 * @retval Between Min_Data = 0 and Max_Data = 127
1398 */
LL_RCC_HSI_GetCalibTrimming(void)1399 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1400 {
1401 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
1402 }
1403
1404 /**
1405 * @}
1406 */
1407
1408 #if defined(RCC_HSI48_SUPPORT)
1409 /** @defgroup RCC_LL_EF_HSI48 HSI48
1410 * @{
1411 */
1412
1413 /**
1414 * @brief Enable HSI48
1415 * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable
1416 * @retval None
1417 */
LL_RCC_HSI48_Enable(void)1418 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1419 {
1420 SET_BIT(RCC->CR, RCC_CR_HSI48ON);
1421 }
1422
1423 /**
1424 * @brief Disable HSI48
1425 * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable
1426 * @retval None
1427 */
LL_RCC_HSI48_Disable(void)1428 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1429 {
1430 CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
1431 }
1432
1433 /**
1434 * @brief Check if HSI48 oscillator Ready
1435 * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady
1436 * @retval State of bit (1 or 0).
1437 */
LL_RCC_HSI48_IsReady(void)1438 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1439 {
1440 return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL);
1441 }
1442
1443 /**
1444 * @brief Get HSI48 Calibration value
1445 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1446 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
1447 */
LL_RCC_HSI48_GetCalibration(void)1448 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1449 {
1450 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1451 }
1452
1453 /**
1454 * @}
1455 */
1456 #endif /* RCC_HSI48_SUPPORT */
1457
1458 /** @defgroup RCC_LL_EF_LSE LSE
1459 * @{
1460 */
1461
1462 /**
1463 * @brief Enable Low Speed External (LSE) crystal.
1464 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1465 * @retval None
1466 */
LL_RCC_LSE_Enable(void)1467 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1468 {
1469 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1470 }
1471
1472 /**
1473 * @brief Disable Low Speed External (LSE) crystal.
1474 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1475 * @retval None
1476 */
LL_RCC_LSE_Disable(void)1477 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1478 {
1479 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1480 }
1481
1482 /**
1483 * @brief Enable external clock source (LSE bypass).
1484 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1485 * @retval None
1486 */
LL_RCC_LSE_EnableBypass(void)1487 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1488 {
1489 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1490 }
1491
1492 /**
1493 * @brief Disable external clock source (LSE bypass).
1494 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1495 * @retval None
1496 */
LL_RCC_LSE_DisableBypass(void)1497 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1498 {
1499 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1500 }
1501
1502 /**
1503 * @brief Set LSE oscillator drive capability
1504 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1505 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1506 * @param LSEDrive This parameter can be one of the following values:
1507 * @arg @ref LL_RCC_LSEDRIVE_LOW
1508 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1509 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1510 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1511 * @retval None
1512 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1513 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1514 {
1515 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1516 }
1517
1518 /**
1519 * @brief Get LSE oscillator drive capability
1520 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1521 * @retval Returned value can be one of the following values:
1522 * @arg @ref LL_RCC_LSEDRIVE_LOW
1523 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1524 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1525 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1526 */
LL_RCC_LSE_GetDriveCapability(void)1527 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1528 {
1529 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1530 }
1531
1532 /**
1533 * @brief Enable Clock security system on LSE.
1534 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
1535 * @retval None
1536 */
LL_RCC_LSE_EnableCSS(void)1537 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1538 {
1539 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1540 }
1541
1542 /**
1543 * @brief Disable Clock security system on LSE.
1544 * @note Clock security system can be disabled only after a LSE
1545 * failure detection. In that case it MUST be disabled by software.
1546 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
1547 * @retval None
1548 */
LL_RCC_LSE_DisableCSS(void)1549 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1550 {
1551 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1552 }
1553
1554 /**
1555 * @brief Check if LSE oscillator Ready
1556 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1557 * @retval State of bit (1 or 0).
1558 */
LL_RCC_LSE_IsReady(void)1559 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1560 {
1561 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
1562 }
1563
1564 /**
1565 * @brief Check if CSS on LSE failure Detection
1566 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
1567 * @retval State of bit (1 or 0).
1568 */
LL_RCC_LSE_IsCSSDetected(void)1569 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1570 {
1571 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
1572 }
1573
1574 /**
1575 * @}
1576 */
1577
1578 /** @defgroup RCC_LL_EF_LSI LSI
1579 * @{
1580 */
1581
1582 /**
1583 * @brief Enable LSI Oscillator
1584 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1585 * @retval None
1586 */
LL_RCC_LSI_Enable(void)1587 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1588 {
1589 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1590 }
1591
1592 /**
1593 * @brief Disable LSI Oscillator
1594 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1595 * @retval None
1596 */
LL_RCC_LSI_Disable(void)1597 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1598 {
1599 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1600 }
1601
1602 /**
1603 * @brief Check if LSI is Ready
1604 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1605 * @retval State of bit (1 or 0).
1606 */
LL_RCC_LSI_IsReady(void)1607 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1608 {
1609 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
1610 }
1611
1612 /**
1613 * @}
1614 */
1615
1616 /** @defgroup RCC_LL_EF_LSCO LSCO
1617 * @{
1618 */
1619
1620 /**
1621 * @brief Enable Low speed clock
1622 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
1623 * @retval None
1624 */
LL_RCC_LSCO_Enable(void)1625 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1626 {
1627 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1628 }
1629
1630 /**
1631 * @brief Disable Low speed clock
1632 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
1633 * @retval None
1634 */
LL_RCC_LSCO_Disable(void)1635 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1636 {
1637 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1638 }
1639
1640 /**
1641 * @brief Configure Low speed clock selection
1642 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
1643 * @param Source This parameter can be one of the following values:
1644 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1645 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1646 * @retval None
1647 */
LL_RCC_LSCO_SetSource(uint32_t Source)1648 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
1649 {
1650 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
1651 }
1652
1653 /**
1654 * @brief Get Low speed clock selection
1655 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
1656 * @retval Returned value can be one of the following values:
1657 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1658 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1659 */
LL_RCC_LSCO_GetSource(void)1660 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
1661 {
1662 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
1663 }
1664
1665 /**
1666 * @}
1667 */
1668
1669 /** @defgroup RCC_LL_EF_System System
1670 * @{
1671 */
1672
1673 /**
1674 * @brief Configure the system clock source
1675 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1676 * @param Source This parameter can be one of the following values:
1677 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1678 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1679 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1680 * @arg @ref LL_RCC_SYS_CLKSOURCE_LSI
1681 * @arg @ref LL_RCC_SYS_CLKSOURCE_LSE
1682 * @retval None
1683 */
LL_RCC_SetSysClkSource(uint32_t Source)1684 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1685 {
1686 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1687 }
1688
1689 /**
1690 * @brief Get the system clock source
1691 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1692 * @retval Returned value can be one of the following values:
1693 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1694 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1695 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1696 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI
1697 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE
1698 */
LL_RCC_GetSysClkSource(void)1699 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1700 {
1701 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1702 }
1703
1704 /**
1705 * @brief Set AHB prescaler
1706 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1707 * @param Prescaler This parameter can be one of the following values:
1708 * @arg @ref LL_RCC_SYSCLK_DIV_1
1709 * @arg @ref LL_RCC_SYSCLK_DIV_2
1710 * @arg @ref LL_RCC_SYSCLK_DIV_4
1711 * @arg @ref LL_RCC_SYSCLK_DIV_8
1712 * @arg @ref LL_RCC_SYSCLK_DIV_16
1713 * @arg @ref LL_RCC_SYSCLK_DIV_64
1714 * @arg @ref LL_RCC_SYSCLK_DIV_128
1715 * @arg @ref LL_RCC_SYSCLK_DIV_256
1716 * @arg @ref LL_RCC_SYSCLK_DIV_512
1717 * @retval None
1718 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1719 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1720 {
1721 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1722 }
1723
1724 /**
1725 * @brief Set APB1 prescaler
1726 * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler
1727 * @param Prescaler This parameter can be one of the following values:
1728 * @arg @ref LL_RCC_APB1_DIV_1
1729 * @arg @ref LL_RCC_APB1_DIV_2
1730 * @arg @ref LL_RCC_APB1_DIV_4
1731 * @arg @ref LL_RCC_APB1_DIV_8
1732 * @arg @ref LL_RCC_APB1_DIV_16
1733 * @retval None
1734 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1735 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1736 {
1737 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
1738 }
1739
1740 /**
1741 * @brief Set HSI16 division factor
1742 * @rmtoll CR HSIDIV LL_RCC_SetHSIDiv
1743 * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as
1744 * system clock source.
1745 * @param HSIDiv This parameter can be one of the following values:
1746 * @arg @ref LL_RCC_HSI_DIV_1
1747 * @arg @ref LL_RCC_HSI_DIV_2
1748 * @arg @ref LL_RCC_HSI_DIV_4
1749 * @arg @ref LL_RCC_HSI_DIV_8
1750 * @arg @ref LL_RCC_HSI_DIV_16
1751 * @arg @ref LL_RCC_HSI_DIV_32
1752 * @arg @ref LL_RCC_HSI_DIV_64
1753 * @arg @ref LL_RCC_HSI_DIV_128
1754 * @retval None
1755 */
LL_RCC_SetHSIDiv(uint32_t HSIDiv)1756 __STATIC_INLINE void LL_RCC_SetHSIDiv(uint32_t HSIDiv)
1757 {
1758 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, HSIDiv);
1759 }
1760 /**
1761 * @brief Get AHB prescaler
1762 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1763 * @retval Returned value can be one of the following values:
1764 * @arg @ref LL_RCC_SYSCLK_DIV_1
1765 * @arg @ref LL_RCC_SYSCLK_DIV_2
1766 * @arg @ref LL_RCC_SYSCLK_DIV_4
1767 * @arg @ref LL_RCC_SYSCLK_DIV_8
1768 * @arg @ref LL_RCC_SYSCLK_DIV_16
1769 * @arg @ref LL_RCC_SYSCLK_DIV_64
1770 * @arg @ref LL_RCC_SYSCLK_DIV_128
1771 * @arg @ref LL_RCC_SYSCLK_DIV_256
1772 * @arg @ref LL_RCC_SYSCLK_DIV_512
1773 */
LL_RCC_GetAHBPrescaler(void)1774 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1775 {
1776 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1777 }
1778
1779 /**
1780 * @brief Get APB1 prescaler
1781 * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler
1782 * @retval Returned value can be one of the following values:
1783 * @arg @ref LL_RCC_APB1_DIV_1
1784 * @arg @ref LL_RCC_APB1_DIV_2
1785 * @arg @ref LL_RCC_APB1_DIV_4
1786 * @arg @ref LL_RCC_APB1_DIV_8
1787 * @arg @ref LL_RCC_APB1_DIV_16
1788 */
LL_RCC_GetAPB1Prescaler(void)1789 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1790 {
1791 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
1792 }
1793
1794 /**
1795 * @brief Get HSI16 Division factor
1796 * @rmtoll CR HSIDIV LL_RCC_GetHSIDiv
1797 * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as
1798 * system clock source.
1799 * @retval Returned value can be one of the following values:
1800 * @arg @ref LL_RCC_HSI_DIV_1
1801 * @arg @ref LL_RCC_HSI_DIV_2
1802 * @arg @ref LL_RCC_HSI_DIV_4
1803 * @arg @ref LL_RCC_HSI_DIV_8
1804 * @arg @ref LL_RCC_HSI_DIV_16
1805 * @arg @ref LL_RCC_HSI_DIV_32
1806 * @arg @ref LL_RCC_HSI_DIV_64
1807 * @arg @ref LL_RCC_HSI_DIV_128
1808 */
LL_RCC_GetHSIDiv(void)1809 __STATIC_INLINE uint32_t LL_RCC_GetHSIDiv(void)
1810 {
1811 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV));
1812 }
1813 /**
1814 * @}
1815 */
1816
1817 /** @defgroup RCC_LL_EF_MCO1 MCO1
1818 * @{
1819 */
1820
1821 /**
1822 * @brief Configure MCOx
1823 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
1824 * CFGR MCOPRE LL_RCC_ConfigMCO
1825 * @param MCOxSource This parameter can be one of the following values:
1826 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1827 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1828 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1829 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
1830 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1831 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
1832 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1833 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1834 * @arg @ref LL_RCC_MCO1SOURCE_PLLPCLK (*)
1835 * @arg @ref LL_RCC_MCO1SOURCE_PLLQCLK (*)
1836 * @arg @ref LL_RCC_MCO1SOURCE_RTCCLK (*)
1837 * @arg @ref LL_RCC_MCO1SOURCE_RTC_WKUP (*)
1838 *
1839 * (*) value not defined in all devices.
1840 * @param MCOxPrescaler This parameter can be one of the following values:
1841 * @arg @ref LL_RCC_MCO1_DIV_1
1842 * @arg @ref LL_RCC_MCO1_DIV_2
1843 * @arg @ref LL_RCC_MCO1_DIV_4
1844 * @arg @ref LL_RCC_MCO1_DIV_8
1845 * @arg @ref LL_RCC_MCO1_DIV_32
1846 * @arg @ref LL_RCC_MCO1_DIV_64
1847 * @arg @ref LL_RCC_MCO1_DIV_128
1848 * @retval None
1849 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1850 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1851 {
1852 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1853 }
1854
1855 /**
1856 * @}
1857 */
1858
1859 #if defined(RCC_MCO2_SUPPORT)
1860 /** @defgroup RCC_LL_EF_MCO2 MCO2
1861 * @{
1862 */
1863
1864 /**
1865 * @brief Configure MCO2
1866 * @rmtoll CFGR MCO2SEL LL_RCC_ConfigMCO2\n
1867 * CFGR MCO2PRE LL_RCC_ConfigMCO2
1868 * @note feature not available in all devices.
1869 * @param MCOxSource This parameter can be one of the following values:
1870 * @arg @ref LL_RCC_MCO2SOURCE_NOCLOCK
1871 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
1872 * @arg @ref LL_RCC_MCO2SOURCE_HSI
1873 * @arg @ref LL_RCC_MCO2SOURCE_HSI48
1874 * @arg @ref LL_RCC_MCO2SOURCE_HSE
1875 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
1876 * @arg @ref LL_RCC_MCO2SOURCE_LSI
1877 * @arg @ref LL_RCC_MCO2SOURCE_LSE
1878 * @arg @ref LL_RCC_MCO2SOURCE_PLLPCLK
1879 * @arg @ref LL_RCC_MCO2SOURCE_PLLQCLK
1880 * @arg @ref LL_RCC_MCO2SOURCE_RTCCLK
1881 * @arg @ref LL_RCC_MCO2SOURCE_RTC_WKUP
1882 *
1883 * @param MCOxPrescaler This parameter can be one of the following values:
1884 * @arg @ref LL_RCC_MCO2_DIV_1
1885 * @arg @ref LL_RCC_MCO2_DIV_2
1886 * @arg @ref LL_RCC_MCO2_DIV_4
1887 * @arg @ref LL_RCC_MCO2_DIV_8
1888 * @arg @ref LL_RCC_MCO2_DIV_16
1889 * @arg @ref LL_RCC_MCO2_DIV_32
1890 * @arg @ref LL_RCC_MCO2_DIV_64
1891 * @arg @ref LL_RCC_MCO2_DIV_128
1892 * @arg @ref LL_RCC_MCO2_DIV_256
1893 * @arg @ref LL_RCC_MCO2_DIV_512
1894 * @arg @ref LL_RCC_MCO2_DIV_1024
1895 * @retval None
1896 */
LL_RCC_ConfigMCO2(uint32_t MCOxSource,uint32_t MCOxPrescaler)1897 __STATIC_INLINE void LL_RCC_ConfigMCO2(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1898 {
1899 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE, MCOxSource | MCOxPrescaler);
1900 }
1901
1902 /**
1903 * @}
1904 */
1905 #endif /* RCC_MCO2_SUPPORT */
1906
1907 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1908 * @{
1909 */
1910
1911 /**
1912 * @brief Configure USARTx clock source
1913 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
1914 * @param USARTxSource This parameter can be one of the following values:
1915 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
1916 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1917 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1918 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1919 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1920 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1921 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1922 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1923 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
1924 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
1925 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
1926 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
1927 *
1928 * (*) value not defined in all devices.
1929 * @retval None
1930 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1931 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1932 {
1933 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
1934 }
1935
1936 #if defined(LPUART1)
1937 /**
1938 * @brief Configure LPUARTx clock source
1939 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
1940 * @rmtoll CCIPR LPUART2SEL LL_RCC_SetLPUARTClockSource
1941 * @param LPUARTxSource This parameter can be one of the following values:
1942 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
1943 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1944 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1945 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1946 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*)
1947 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*)
1948 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI (*)
1949 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE (*)
1950 * (*) feature not available on all devices
1951 * @retval None
1952 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)1953 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
1954 {
1955 MODIFY_REG(RCC->CCIPR, (LPUARTxSource >> 16U), (LPUARTxSource & 0x0000FFFFU));
1956 }
1957 #endif /* LPUART1 */
1958
1959 /**
1960 * @brief Configure I2Cx clock source
1961 * @rmtoll CCIPR I2C1SEL LL_RCC_SetI2CClockSource
1962 * @param I2CxSource This parameter can be one of the following values:
1963 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1964 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1965 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1966 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
1967 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
1968 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
1969 * (*) value not defined in all devices.
1970 * @retval None
1971 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1972 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1973 {
1974 MODIFY_REG(RCC->CCIPR, (I2CxSource >> 16U), (I2CxSource & 0x0000FFFFU));
1975 }
1976
1977 #if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)
1978 /**
1979 * @brief Configure TIMx clock source
1980 * @rmtoll CCIPR TIMxSEL LL_RCC_SetTIMClockSource
1981 * @param TIMxSource This parameter can be one of the following values:
1982 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
1983 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1
1984 * @if defined(STM32G081xx)
1985 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL
1986 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1
1987 * @endif
1988 * @retval None
1989 */
LL_RCC_SetTIMClockSource(uint32_t TIMxSource)1990 __STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
1991 {
1992 MODIFY_REG(RCC->CCIPR, (TIMxSource & 0xFFFF0000U), (TIMxSource << 16));
1993 }
1994 #endif /* RCC_CCIPR_TIM1SEL && RCC_CCIPR_TIM15SEL */
1995
1996 #if defined(LPTIM1) && defined(LPTIM2)
1997 /**
1998 * @brief Configure LPTIMx clock source
1999 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
2000 * @param LPTIMxSource This parameter can be one of the following values:
2001 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2002 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2003 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2004 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2005 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2006 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2007 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2008 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2009 * @retval None
2010 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)2011 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
2012 {
2013 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
2014 }
2015 #endif /* LPTIM1 && LPTIM2 */
2016
2017 #if defined(CEC)
2018 /**
2019 * @brief Configure CEC clock source
2020 * @rmtoll CCIPR CECSEL LL_RCC_SetCECClockSource
2021 * @param CECxSource This parameter can be one of the following values:
2022 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
2023 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2024 * @retval None
2025 */
LL_RCC_SetCECClockSource(uint32_t CECxSource)2026 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
2027 {
2028 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, CECxSource);
2029 }
2030 #endif /* CEC */
2031
2032 #if defined(RCC_CCIPR_RNGDIV)
2033 /**
2034 * @brief Configure RNG division factor
2035 * @rmtoll CCIPR RNGDIV LL_RCC_SetRNGClockDiv
2036 * @param RNGxDiv This parameter can be one of the following values:
2037 * @arg @ref LL_RCC_RNG_CLK_DIV1
2038 * @arg @ref LL_RCC_RNG_CLK_DIV2
2039 * @arg @ref LL_RCC_RNG_CLK_DIV4
2040 * @arg @ref LL_RCC_RNG_CLK_DIV8
2041 * @retval None
2042 */
LL_RCC_SetRNGClockDiv(uint32_t RNGxDiv)2043 __STATIC_INLINE void LL_RCC_SetRNGClockDiv(uint32_t RNGxDiv)
2044 {
2045 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, RNGxDiv);
2046 }
2047 #endif /* RNG */
2048
2049 #if defined (RCC_CCIPR_RNGSEL)
2050 /**
2051 * @brief Configure RNG clock source
2052 * @rmtoll CCIPR RNGSEL LL_RCC_SetRNGClockSource
2053 * @param RNGxSource This parameter can be one of the following values:
2054 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
2055 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI_DIV8
2056 * @arg @ref LL_RCC_RNG_CLKSOURCE_SYSCLK
2057 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2058 * @retval None
2059 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)2060 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
2061 {
2062 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource);
2063 }
2064 #endif /* RNG */
2065
2066 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
2067 /**
2068 * @brief Configure USB clock source
2069 * @rmtoll CCIPR2 CK48MSEL LL_RCC_SetUSBClockSource
2070 * @param USBxSource This parameter can be one of the following values:
2071 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2072 * @arg @ref LL_RCC_USB_CLKSOURCE_HSE
2073 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2074 *
2075 * (*) value not defined in all devices.
2076 * @retval None
2077 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)2078 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
2079 {
2080 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, USBxSource);
2081 }
2082 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
2083
2084 #if defined (FDCAN1) || defined (FDCAN2)
2085 /**
2086 * @brief Configure FDCAN clock source
2087 * @rmtoll CCIPR2 FDCANSEL LL_RCC_SetFDCANClockSource
2088 * @param FDCANxSource This parameter can be one of the following values:
2089 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
2090 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
2091 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
2092 * @retval None
2093 */
LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)2094 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
2095 {
2096 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, FDCANxSource);
2097 }
2098 #endif /* FDCAN1 || FDCAN2 */
2099
2100 /**
2101 * @brief Configure ADC clock source
2102 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
2103 * @param ADCxSource This parameter can be one of the following values:
2104 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
2105 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2106 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
2107 * @retval None
2108 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)2109 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
2110 {
2111 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
2112 }
2113
2114 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
2115 /**
2116 * @brief Configure I2Sx clock source
2117 * @rmtoll CCIPR2 I2SxSEL LL_RCC_SetI2SClockSource
2118 * @param I2SxSource This parameter can be one of the following values:
2119 * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
2120 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2121 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
2122 * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
2123 * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
2124 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN
2125 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL
2126 * @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI
2127 * @retval None
2128 */
LL_RCC_SetI2SClockSource(uint32_t I2SxSource)2129 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
2130 {
2131 MODIFY_REG(RCC->CCIPR2, (I2SxSource >> 16U), (I2SxSource & 0x0000FFFFU));
2132 }
2133
2134 #else
2135 /**
2136 * @brief Configure I2Sx clock source
2137 * @rmtoll CCIPR I2S1SEL LL_RCC_SetI2SClockSource
2138 * @param I2SxSource This parameter can be one of the following values:
2139 * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
2140 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2141 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
2142 * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
2143 * @retval None
2144 */
LL_RCC_SetI2SClockSource(uint32_t I2SxSource)2145 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
2146 {
2147 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, I2SxSource);
2148 }
2149 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
2150
2151 /**
2152 * @brief Get USARTx clock source
2153 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
2154 * @param USARTx This parameter can be one of the following values:
2155 * @arg @ref LL_RCC_USART1_CLKSOURCE
2156 * @arg @ref LL_RCC_USART2_CLKSOURCE
2157 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
2158 * @retval Returned value can be one of the following values:
2159 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
2160 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2161 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2162 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2163 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2164 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2165 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2166 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2167 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
2168 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
2169 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
2170 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
2171 * (*) feature not available on all devices
2172 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)2173 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
2174 {
2175 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
2176 }
2177
2178 #if defined (LPUART2) || defined (LPUART1)
2179 /**
2180 * @brief Get LPUARTx clock source
2181 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource\n
2182 * CCIPR LPUART2SEL LL_RCC_GetLPUARTClockSource
2183 * @param LPUARTx This parameter can be one of the following values:
2184 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
2185 * @arg @ref LL_RCC_LPUART2_CLKSOURCE (*)
2186 * @retval Returned value can be one of the following values:
2187 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2188 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2189 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2190 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2191 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*)
2192 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*)
2193 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI (*)
2194 * @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE (*)
2195 * (*) feature not available on all devices
2196 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)2197 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
2198 {
2199 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx) | (LPUARTx << 16U));
2200 }
2201 #endif /* LPUART2 || LPUART1 */
2202
2203 /**
2204 * @brief Get I2Cx clock source
2205 * @rmtoll CCIPR I2C1SEL LL_RCC_GetI2CClockSource\n
2206 * CCIPR I2C2SEL LL_RCC_GetI2CClockSource
2207 * @param I2Cx This parameter can be one of the following values:
2208 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2209 * @arg @ref LL_RCC_I2C2_CLKSOURCE
2210 * @retval Returned value can be one of the following values:
2211 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2212 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2213 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2214 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2215 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
2216 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2217 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)2218 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2219 {
2220 return (uint32_t)(READ_BIT(RCC->CCIPR, I2Cx) | (I2Cx << 16U));
2221 }
2222
2223 #if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)
2224 /**
2225 * @brief Get TIMx clock source
2226 * @rmtoll CCIPR TIMxSEL LL_RCC_GetTIMClockSource
2227 * @param TIMx This parameter can be one of the following values:
2228 * @arg @ref LL_RCC_TIM1_CLKSOURCE
2229 * @arg @ref LL_RCC_TIM15_CLKSOURCE
2230 * @retval Returned value can be one of the following values:
2231 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
2232 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1
2233 * @if defined(STM32G081xx)
2234 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL
2235 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1
2236 * @endif
2237 */
LL_RCC_GetTIMClockSource(uint32_t TIMx)2238 __STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
2239 {
2240 return (uint32_t)((READ_BIT(RCC->CCIPR, TIMx) >> 16U) | TIMx);
2241 }
2242 #endif /* RCC_CCIPR_TIM1SEL || RCC_CCIPR_TIM15SEL */
2243
2244 #if defined(LPTIM1) && defined(LPTIM2)
2245 /**
2246 * @brief Get LPTIMx clock source
2247 * @rmtoll CCIPR LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
2248 CCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource
2249 * @param LPTIMx This parameter can be one of the following values:
2250 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2251 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2252 * @retval Returned value can be one of the following values:
2253 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2254 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2255 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2256 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2257 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2258 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2259 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2260 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2261 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)2262 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2263 {
2264 return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx);
2265 }
2266 #endif /* LPTIM1 && LPTIM2 */
2267
2268 #if defined (RCC_CCIPR_CECSEL)
2269 /**
2270 * @brief Get CEC clock source
2271 * @rmtoll CCIPR CECSEL LL_RCC_GetCECClockSource
2272 * @param CECx This parameter can be one of the following values:
2273 * @arg @ref LL_RCC_CEC_CLKSOURCE
2274 * @retval Returned value can be one of the following values:
2275 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
2276 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2277 */
LL_RCC_GetCECClockSource(uint32_t CECx)2278 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
2279 {
2280 return (uint32_t)(READ_BIT(RCC->CCIPR, CECx));
2281 }
2282 #endif /* CEC */
2283
2284 #if defined(RCC_CCIPR2_FDCANSEL)
2285 /**
2286 * @brief Get FDCAN clock source
2287 * @rmtoll CCIPR2 FDCANSEL LL_RCC_GetFDCANClockSource
2288 * @param FDCANx This parameter can be one of the following values:
2289 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
2290 * @retval Returned value can be one of the following values:
2291 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
2292 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
2293 */
LL_RCC_GetFDCANClockSource(uint32_t FDCANx)2294 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
2295 {
2296 return (uint32_t)(READ_BIT(RCC->CCIPR2, FDCANx));
2297 }
2298 #endif /* RCC_CCIPR2_FDCANSEL */
2299
2300 #if defined(RNG)
2301 /**
2302 * @brief Get RNGx clock source
2303 * @rmtoll CCIPR RNGSEL LL_RCC_GetRNGClockSource
2304 * @param RNGx This parameter can be one of the following values:
2305 * @arg @ref LL_RCC_RNG_CLKSOURCE
2306 * @retval Returned value can be one of the following values:
2307 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
2308 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI_DIV8
2309 * @arg @ref LL_RCC_RNG_CLKSOURCE_SYSCLK
2310 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2311 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)2312 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2313 {
2314 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
2315 }
2316 #endif /* RNG */
2317
2318 #if defined(RNG)
2319 /**
2320 * @brief Get RNGx clock division factor
2321 * @rmtoll CCIPR RNGDIV LL_RCC_GetRNGClockDiv
2322 * @retval Returned value can be one of the following values:
2323 * @arg @ref LL_RCC_RNG_CLK_DIV1
2324 * @arg @ref LL_RCC_RNG_CLK_DIV2
2325 * @arg @ref LL_RCC_RNG_CLK_DIV4
2326 * @arg @ref LL_RCC_RNG_CLK_DIV8
2327 */
LL_RCC_GetRNGClockDiv(void)2328 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockDiv(void)
2329 {
2330 return (uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV));
2331 }
2332 #endif /* RNG */
2333
2334 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
2335 /**
2336 * @brief Get USBx clock source
2337 * @rmtoll CCIPR2 CK48MSEL LL_RCC_GetUSBClockSource
2338 * @param USBx This parameter can be one of the following values:
2339 * @arg @ref LL_RCC_USB_CLKSOURCE
2340 * @retval Returned value can be one of the following values:
2341 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2342 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2343 */
LL_RCC_GetUSBClockSource(uint32_t USBx)2344 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
2345 {
2346 return (uint32_t)(READ_BIT(RCC->CCIPR2, USBx));
2347 }
2348 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
2349
2350 /**
2351 * @brief Get ADCx clock source
2352 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
2353 * @param ADCx This parameter can be one of the following values:
2354 * @arg @ref LL_RCC_ADC_CLKSOURCE
2355 * @retval Returned value can be one of the following values:
2356 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
2357 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
2358 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2359 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2360 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2361 {
2362 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
2363 }
2364
2365 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
2366 /**
2367 * @brief Get I2Sx clock source
2368 * @rmtoll CCIPR2 I2S1SEL LL_RCC_GetI2SClockSource\n
2369 * CCIPR2 I2S2SEL LL_RCC_GetI2SClockSource
2370 * @param I2Sx This parameter can be one of the following values:
2371 * @arg @ref LL_RCC_I2S1_CLKSOURCE
2372 * @arg @ref LL_RCC_I2S2_CLKSOURCE
2373 * @retval Returned value can be one of the following values:
2374 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2375 * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
2376 * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
2377 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
2378 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN
2379 * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
2380 * @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI
2381 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL
2382 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)2383 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
2384 {
2385 return (uint32_t)(READ_BIT(RCC->CCIPR2, I2Sx) | (I2Sx << 16U));
2386 }
2387 #else
2388 /**
2389 * @brief Get I2Sx clock source
2390 * @rmtoll CCIPR I2S1SEL LL_RCC_GetI2SClockSource
2391 * @param I2Sx This parameter can be one of the following values:
2392 * @arg @ref LL_RCC_I2S1_CLKSOURCE
2393 * @retval Returned value can be one of the following values:
2394 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2395 * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
2396 * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
2397 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
2398 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)2399 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
2400 {
2401 return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
2402 }
2403 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
2404 /**
2405 * @}
2406 */
2407
2408 /** @defgroup RCC_LL_EF_RTC RTC
2409 * @{
2410 */
2411
2412 /**
2413 * @brief Set RTC Clock Source
2414 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2415 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2416 * set). The BDRST bit can be used to reset them.
2417 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2418 * @param Source This parameter can be one of the following values:
2419 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2420 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2421 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2422 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2423 * @retval None
2424 */
LL_RCC_SetRTCClockSource(uint32_t Source)2425 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2426 {
2427 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2428 }
2429
2430 /**
2431 * @brief Get RTC Clock Source
2432 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2433 * @retval Returned value can be one of the following values:
2434 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2435 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2436 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2437 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2438 */
LL_RCC_GetRTCClockSource(void)2439 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2440 {
2441 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2442 }
2443
2444 /**
2445 * @brief Enable RTC
2446 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2447 * @retval None
2448 */
LL_RCC_EnableRTC(void)2449 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2450 {
2451 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2452 }
2453
2454 /**
2455 * @brief Disable RTC
2456 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2457 * @retval None
2458 */
LL_RCC_DisableRTC(void)2459 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2460 {
2461 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2462 }
2463
2464 /**
2465 * @brief Check if RTC has been enabled or not
2466 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2467 * @retval State of bit (1 or 0).
2468 */
LL_RCC_IsEnabledRTC(void)2469 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2470 {
2471 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
2472 }
2473
2474 /**
2475 * @brief Force the Backup domain reset
2476 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2477 * @retval None
2478 */
LL_RCC_ForceBackupDomainReset(void)2479 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2480 {
2481 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2482 }
2483
2484 /**
2485 * @brief Release the Backup domain reset
2486 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2487 * @retval None
2488 */
LL_RCC_ReleaseBackupDomainReset(void)2489 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2490 {
2491 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2492 }
2493
2494 /**
2495 * @}
2496 */
2497
2498
2499 /** @defgroup RCC_LL_EF_PLL PLL
2500 * @{
2501 */
2502
2503 /**
2504 * @brief Enable PLL
2505 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2506 * @retval None
2507 */
LL_RCC_PLL_Enable(void)2508 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2509 {
2510 SET_BIT(RCC->CR, RCC_CR_PLLON);
2511 }
2512
2513 /**
2514 * @brief Disable PLL
2515 * @note Cannot be disabled if the PLL clock is used as the system clock
2516 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2517 * @retval None
2518 */
LL_RCC_PLL_Disable(void)2519 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2520 {
2521 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2522 }
2523
2524 /**
2525 * @brief Check if PLL Ready
2526 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2527 * @retval State of bit (1 or 0).
2528 */
LL_RCC_PLL_IsReady(void)2529 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2530 {
2531 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
2532 }
2533
2534 /**
2535 * @brief Configure PLL used for SYSCLK Domain
2536 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2537 * @note PLLN/PLLR can be written only when PLL is disabled
2538 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2539 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
2540 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
2541 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
2542 * @param Source This parameter can be one of the following values:
2543 * @arg @ref LL_RCC_PLLSOURCE_NONE
2544 * @arg @ref LL_RCC_PLLSOURCE_HSI
2545 * @arg @ref LL_RCC_PLLSOURCE_HSE
2546 * @param PLLM This parameter can be one of the following values:
2547 * @arg @ref LL_RCC_PLLM_DIV_1
2548 * @arg @ref LL_RCC_PLLM_DIV_2
2549 * @arg @ref LL_RCC_PLLM_DIV_3
2550 * @arg @ref LL_RCC_PLLM_DIV_4
2551 * @arg @ref LL_RCC_PLLM_DIV_5
2552 * @arg @ref LL_RCC_PLLM_DIV_6
2553 * @arg @ref LL_RCC_PLLM_DIV_7
2554 * @arg @ref LL_RCC_PLLM_DIV_8
2555 * @param PLLN Between 8 and 86
2556 * @param PLLR This parameter can be one of the following values:
2557 * @arg @ref LL_RCC_PLLR_DIV_2
2558 * @arg @ref LL_RCC_PLLR_DIV_3
2559 * @arg @ref LL_RCC_PLLR_DIV_4
2560 * @arg @ref LL_RCC_PLLR_DIV_5
2561 * @arg @ref LL_RCC_PLLR_DIV_6
2562 * @arg @ref LL_RCC_PLLR_DIV_7
2563 * @arg @ref LL_RCC_PLLR_DIV_8
2564 * @retval None
2565 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)2566 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
2567 {
2568 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
2569 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
2570 }
2571
2572 /**
2573 * @brief Configure PLL used for ADC domain clock
2574 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2575 * @note PLLN/PLLP can be written only when PLL is disabled
2576 * @note User shall verify whether the PLL configuration is not done through
2577 * other functions (ex: I2S1)
2578 * @note This can be selected for ADC
2579 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n
2580 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n
2581 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n
2582 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_ADC
2583 * @param Source This parameter can be one of the following values:
2584 * @arg @ref LL_RCC_PLLSOURCE_NONE
2585 * @arg @ref LL_RCC_PLLSOURCE_HSI
2586 * @arg @ref LL_RCC_PLLSOURCE_HSE
2587 * @param PLLM This parameter can be one of the following values:
2588 * @arg @ref LL_RCC_PLLM_DIV_1
2589 * @arg @ref LL_RCC_PLLM_DIV_2
2590 * @arg @ref LL_RCC_PLLM_DIV_3
2591 * @arg @ref LL_RCC_PLLM_DIV_4
2592 * @arg @ref LL_RCC_PLLM_DIV_5
2593 * @arg @ref LL_RCC_PLLM_DIV_6
2594 * @arg @ref LL_RCC_PLLM_DIV_7
2595 * @arg @ref LL_RCC_PLLM_DIV_8
2596 * @param PLLN Between 8 and 86
2597 * @param PLLP This parameter can be one of the following values:
2598 * @arg @ref LL_RCC_PLLP_DIV_2
2599 * @arg @ref LL_RCC_PLLP_DIV_3
2600 * @arg @ref LL_RCC_PLLP_DIV_4
2601 * @arg @ref LL_RCC_PLLP_DIV_5
2602 * @arg @ref LL_RCC_PLLP_DIV_6
2603 * @arg @ref LL_RCC_PLLP_DIV_7
2604 * @arg @ref LL_RCC_PLLP_DIV_8
2605 * @arg @ref LL_RCC_PLLP_DIV_9
2606 * @arg @ref LL_RCC_PLLP_DIV_10
2607 * @arg @ref LL_RCC_PLLP_DIV_11
2608 * @arg @ref LL_RCC_PLLP_DIV_12
2609 * @arg @ref LL_RCC_PLLP_DIV_13
2610 * @arg @ref LL_RCC_PLLP_DIV_14
2611 * @arg @ref LL_RCC_PLLP_DIV_15
2612 * @arg @ref LL_RCC_PLLP_DIV_16
2613 * @arg @ref LL_RCC_PLLP_DIV_17
2614 * @arg @ref LL_RCC_PLLP_DIV_18
2615 * @arg @ref LL_RCC_PLLP_DIV_19
2616 * @arg @ref LL_RCC_PLLP_DIV_20
2617 * @arg @ref LL_RCC_PLLP_DIV_21
2618 * @arg @ref LL_RCC_PLLP_DIV_22
2619 * @arg @ref LL_RCC_PLLP_DIV_23
2620 * @arg @ref LL_RCC_PLLP_DIV_24
2621 * @arg @ref LL_RCC_PLLP_DIV_25
2622 * @arg @ref LL_RCC_PLLP_DIV_26
2623 * @arg @ref LL_RCC_PLLP_DIV_27
2624 * @arg @ref LL_RCC_PLLP_DIV_28
2625 * @arg @ref LL_RCC_PLLP_DIV_29
2626 * @arg @ref LL_RCC_PLLP_DIV_30
2627 * @arg @ref LL_RCC_PLLP_DIV_31
2628 * @arg @ref LL_RCC_PLLP_DIV_32
2629 * @retval None
2630 */
LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2631 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2632 {
2633 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
2634 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
2635 }
2636
2637 /**
2638 * @brief Configure PLL used for I2S1 domain clock
2639 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2640 * @note PLLN/PLLP can be written only when PLL is disabled
2641 * @note User shall verify whether the PLL configuration is not done through
2642 * other functions (ex: ADC)
2643 * @note This can be selected for I2S1
2644 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S1\n
2645 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S1\n
2646 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S1\n
2647 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_I2S1
2648 * @param Source This parameter can be one of the following values:
2649 * @arg @ref LL_RCC_PLLSOURCE_NONE
2650 * @arg @ref LL_RCC_PLLSOURCE_HSI
2651 * @arg @ref LL_RCC_PLLSOURCE_HSE
2652 * @param PLLM This parameter can be one of the following values:
2653 * @arg @ref LL_RCC_PLLM_DIV_1
2654 * @arg @ref LL_RCC_PLLM_DIV_2
2655 * @arg @ref LL_RCC_PLLM_DIV_3
2656 * @arg @ref LL_RCC_PLLM_DIV_4
2657 * @arg @ref LL_RCC_PLLM_DIV_5
2658 * @arg @ref LL_RCC_PLLM_DIV_6
2659 * @arg @ref LL_RCC_PLLM_DIV_7
2660 * @arg @ref LL_RCC_PLLM_DIV_8
2661 * @param PLLN Between 8 and 86
2662 * @param PLLP This parameter can be one of the following values:
2663 * @arg @ref LL_RCC_PLLP_DIV_2
2664 * @arg @ref LL_RCC_PLLP_DIV_3
2665 * @arg @ref LL_RCC_PLLP_DIV_4
2666 * @arg @ref LL_RCC_PLLP_DIV_5
2667 * @arg @ref LL_RCC_PLLP_DIV_6
2668 * @arg @ref LL_RCC_PLLP_DIV_7
2669 * @arg @ref LL_RCC_PLLP_DIV_8
2670 * @arg @ref LL_RCC_PLLP_DIV_9
2671 * @arg @ref LL_RCC_PLLP_DIV_10
2672 * @arg @ref LL_RCC_PLLP_DIV_11
2673 * @arg @ref LL_RCC_PLLP_DIV_12
2674 * @arg @ref LL_RCC_PLLP_DIV_13
2675 * @arg @ref LL_RCC_PLLP_DIV_14
2676 * @arg @ref LL_RCC_PLLP_DIV_15
2677 * @arg @ref LL_RCC_PLLP_DIV_16
2678 * @arg @ref LL_RCC_PLLP_DIV_17
2679 * @arg @ref LL_RCC_PLLP_DIV_18
2680 * @arg @ref LL_RCC_PLLP_DIV_19
2681 * @arg @ref LL_RCC_PLLP_DIV_20
2682 * @arg @ref LL_RCC_PLLP_DIV_21
2683 * @arg @ref LL_RCC_PLLP_DIV_22
2684 * @arg @ref LL_RCC_PLLP_DIV_23
2685 * @arg @ref LL_RCC_PLLP_DIV_24
2686 * @arg @ref LL_RCC_PLLP_DIV_25
2687 * @arg @ref LL_RCC_PLLP_DIV_26
2688 * @arg @ref LL_RCC_PLLP_DIV_27
2689 * @arg @ref LL_RCC_PLLP_DIV_28
2690 * @arg @ref LL_RCC_PLLP_DIV_29
2691 * @arg @ref LL_RCC_PLLP_DIV_30
2692 * @arg @ref LL_RCC_PLLP_DIV_31
2693 * @arg @ref LL_RCC_PLLP_DIV_32
2694 * @retval None
2695 */
LL_RCC_PLL_ConfigDomain_I2S1(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2696 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S1(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2697 {
2698 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
2699 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
2700 }
2701
2702 #if defined(RCC_CCIPR2_I2S2SEL)
2703 /**
2704 * @brief Configure PLL used for I2S2 domain clock
2705 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2706 * @note PLLN/PLLP can be written only when PLL is disabled
2707 * @note User shall verify whether the PLL configuration is not done through
2708 * other functions (ex: ADC)
2709 * @note This can be selected for I2S2
2710 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S2\n
2711 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S2\n
2712 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S2\n
2713 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_I2S2
2714 * @param Source This parameter can be one of the following values:
2715 * @arg @ref LL_RCC_PLLSOURCE_NONE
2716 * @arg @ref LL_RCC_PLLSOURCE_HSI
2717 * @arg @ref LL_RCC_PLLSOURCE_HSE
2718 * @param PLLM This parameter can be one of the following values:
2719 * @arg @ref LL_RCC_PLLM_DIV_1
2720 * @arg @ref LL_RCC_PLLM_DIV_2
2721 * @arg @ref LL_RCC_PLLM_DIV_3
2722 * @arg @ref LL_RCC_PLLM_DIV_4
2723 * @arg @ref LL_RCC_PLLM_DIV_5
2724 * @arg @ref LL_RCC_PLLM_DIV_6
2725 * @arg @ref LL_RCC_PLLM_DIV_7
2726 * @arg @ref LL_RCC_PLLM_DIV_8
2727 * @param PLLN Between 8 and 86
2728 * @param PLLP This parameter can be one of the following values:
2729 * @arg @ref LL_RCC_PLLP_DIV_2
2730 * @arg @ref LL_RCC_PLLP_DIV_3
2731 * @arg @ref LL_RCC_PLLP_DIV_4
2732 * @arg @ref LL_RCC_PLLP_DIV_5
2733 * @arg @ref LL_RCC_PLLP_DIV_6
2734 * @arg @ref LL_RCC_PLLP_DIV_7
2735 * @arg @ref LL_RCC_PLLP_DIV_8
2736 * @arg @ref LL_RCC_PLLP_DIV_9
2737 * @arg @ref LL_RCC_PLLP_DIV_10
2738 * @arg @ref LL_RCC_PLLP_DIV_11
2739 * @arg @ref LL_RCC_PLLP_DIV_12
2740 * @arg @ref LL_RCC_PLLP_DIV_13
2741 * @arg @ref LL_RCC_PLLP_DIV_14
2742 * @arg @ref LL_RCC_PLLP_DIV_15
2743 * @arg @ref LL_RCC_PLLP_DIV_16
2744 * @arg @ref LL_RCC_PLLP_DIV_17
2745 * @arg @ref LL_RCC_PLLP_DIV_18
2746 * @arg @ref LL_RCC_PLLP_DIV_19
2747 * @arg @ref LL_RCC_PLLP_DIV_20
2748 * @arg @ref LL_RCC_PLLP_DIV_21
2749 * @arg @ref LL_RCC_PLLP_DIV_22
2750 * @arg @ref LL_RCC_PLLP_DIV_23
2751 * @arg @ref LL_RCC_PLLP_DIV_24
2752 * @arg @ref LL_RCC_PLLP_DIV_25
2753 * @arg @ref LL_RCC_PLLP_DIV_26
2754 * @arg @ref LL_RCC_PLLP_DIV_27
2755 * @arg @ref LL_RCC_PLLP_DIV_28
2756 * @arg @ref LL_RCC_PLLP_DIV_29
2757 * @arg @ref LL_RCC_PLLP_DIV_30
2758 * @arg @ref LL_RCC_PLLP_DIV_31
2759 * @arg @ref LL_RCC_PLLP_DIV_32
2760 * @retval None
2761 */
LL_RCC_PLL_ConfigDomain_I2S2(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2762 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S2(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2763 {
2764 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
2765 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
2766 }
2767 #endif /* RCC_CCIPR2_I2S2SEL */
2768
2769 #if defined(RNG)
2770 /**
2771 * @brief Configure PLL used for RNG domain clock
2772 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2773 * @note PLLN/PLLQ can be written only when PLL is disabled
2774 * @note User shall verify whether the PLL configuration is not done through
2775 * other functions (ex: TIM1, TIM15)
2776 * @note This can be selected for RNG
2777 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_RNG\n
2778 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_RNG\n
2779 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_RNG\n
2780 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_RNG
2781 * @param Source This parameter can be one of the following values:
2782 * @arg @ref LL_RCC_PLLSOURCE_NONE
2783 * @arg @ref LL_RCC_PLLSOURCE_HSI
2784 * @arg @ref LL_RCC_PLLSOURCE_HSE
2785 * @param PLLM This parameter can be one of the following values:
2786 * @arg @ref LL_RCC_PLLM_DIV_1
2787 * @arg @ref LL_RCC_PLLM_DIV_2
2788 * @arg @ref LL_RCC_PLLM_DIV_3
2789 * @arg @ref LL_RCC_PLLM_DIV_4
2790 * @arg @ref LL_RCC_PLLM_DIV_5
2791 * @arg @ref LL_RCC_PLLM_DIV_6
2792 * @arg @ref LL_RCC_PLLM_DIV_7
2793 * @arg @ref LL_RCC_PLLM_DIV_8
2794 * @param PLLN Between 8 and 86
2795 * @param PLLQ This parameter can be one of the following values:
2796 * @arg @ref LL_RCC_PLLQ_DIV_2
2797 * @arg @ref LL_RCC_PLLQ_DIV_3
2798 * @arg @ref LL_RCC_PLLQ_DIV_4
2799 * @arg @ref LL_RCC_PLLQ_DIV_5
2800 * @arg @ref LL_RCC_PLLQ_DIV_6
2801 * @arg @ref LL_RCC_PLLQ_DIV_7
2802 * @arg @ref LL_RCC_PLLQ_DIV_8
2803 * @retval None
2804 */
LL_RCC_PLL_ConfigDomain_RNG(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2805 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_RNG(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2806 {
2807 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2808 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2809 }
2810 #endif /* RNG */
2811
2812 #if defined(FDCAN1) || defined(FDCAN2)
2813 /**
2814 * @brief Configure PLL used for FDCAN domain clock
2815 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2816 * @note PLLN/PLLQ can be written only when PLL is disabled
2817 * @note User shall verify whether the PLL configuration is not done through
2818 * other functions (ex: TIM1, TIM15)
2819 * @note This can be selected for FDCAN
2820 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_FDCAN\n
2821 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_FDCAN\n
2822 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_FDCAN\n
2823 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_FDCAN
2824 * @param Source This parameter can be one of the following values:
2825 * @arg @ref LL_RCC_PLLSOURCE_NONE
2826 * @arg @ref LL_RCC_PLLSOURCE_HSI
2827 * @arg @ref LL_RCC_PLLSOURCE_HSE
2828 * @param PLLM This parameter can be one of the following values:
2829 * @arg @ref LL_RCC_PLLM_DIV_1
2830 * @arg @ref LL_RCC_PLLM_DIV_2
2831 * @arg @ref LL_RCC_PLLM_DIV_3
2832 * @arg @ref LL_RCC_PLLM_DIV_4
2833 * @arg @ref LL_RCC_PLLM_DIV_5
2834 * @arg @ref LL_RCC_PLLM_DIV_6
2835 * @arg @ref LL_RCC_PLLM_DIV_7
2836 * @arg @ref LL_RCC_PLLM_DIV_8
2837 * @param PLLN Between 8 and 86
2838 * @param PLLQ This parameter can be one of the following values:
2839 * @arg @ref LL_RCC_PLLQ_DIV_2
2840 * @arg @ref LL_RCC_PLLQ_DIV_3
2841 * @arg @ref LL_RCC_PLLQ_DIV_4
2842 * @arg @ref LL_RCC_PLLQ_DIV_5
2843 * @arg @ref LL_RCC_PLLQ_DIV_6
2844 * @arg @ref LL_RCC_PLLQ_DIV_7
2845 * @arg @ref LL_RCC_PLLQ_DIV_8
2846 * @retval None
2847 */
LL_RCC_PLL_ConfigDomain_FDCAN(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2848 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_FDCAN(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2849 {
2850 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2851 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2852 }
2853 #endif /* FDCAN1 || FDCAN2 */
2854
2855 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
2856 /**
2857 * @brief Configure PLL used for USB domain clock
2858 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2859 * @note PLLN/PLLQ can be written only when PLL is disabled
2860 * @note User shall verify whether the PLL configuration is not done through
2861 * other functions (ex: TIM1, TIM15)
2862 * @note This can be selected for USB
2863 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_USB\n
2864 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_USB\n
2865 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_USB\n
2866 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_USB
2867 * @param Source This parameter can be one of the following values:
2868 * @arg @ref LL_RCC_PLLSOURCE_NONE
2869 * @arg @ref LL_RCC_PLLSOURCE_HSI
2870 * @arg @ref LL_RCC_PLLSOURCE_HSE
2871 * @param PLLM This parameter can be one of the following values:
2872 * @arg @ref LL_RCC_PLLM_DIV_1
2873 * @arg @ref LL_RCC_PLLM_DIV_2
2874 * @arg @ref LL_RCC_PLLM_DIV_3
2875 * @arg @ref LL_RCC_PLLM_DIV_4
2876 * @arg @ref LL_RCC_PLLM_DIV_5
2877 * @arg @ref LL_RCC_PLLM_DIV_6
2878 * @arg @ref LL_RCC_PLLM_DIV_7
2879 * @arg @ref LL_RCC_PLLM_DIV_8
2880 * @param PLLN Between 8 and 86
2881 * @param PLLQ This parameter can be one of the following values:
2882 * @arg @ref LL_RCC_PLLQ_DIV_2
2883 * @arg @ref LL_RCC_PLLQ_DIV_3
2884 * @arg @ref LL_RCC_PLLQ_DIV_4
2885 * @arg @ref LL_RCC_PLLQ_DIV_5
2886 * @arg @ref LL_RCC_PLLQ_DIV_6
2887 * @arg @ref LL_RCC_PLLQ_DIV_7
2888 * @arg @ref LL_RCC_PLLQ_DIV_8
2889 * @retval None
2890 */
LL_RCC_PLL_ConfigDomain_USB(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2891 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_USB(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2892 {
2893 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2894 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2895 }
2896 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
2897
2898 #if defined(RCC_PLLQ_SUPPORT)
2899 /**
2900 * @brief Configure PLL used for TIM1 domain clock
2901 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2902 * @note PLLN/PLLQ can be written only when PLL is disabled
2903 * @note User shall verify whether the PLL configuration is not done through
2904 * other functions (ex: RNG, TIM15)
2905 * @note This can be selected for TIM1
2906 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_TIM1\n
2907 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_TIM1\n
2908 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_TIM1\n
2909 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_TIM1
2910 * @param Source This parameter can be one of the following values:
2911 * @arg @ref LL_RCC_PLLSOURCE_NONE
2912 * @arg @ref LL_RCC_PLLSOURCE_HSI
2913 * @arg @ref LL_RCC_PLLSOURCE_HSE
2914 * @param PLLM This parameter can be one of the following values:
2915 * @arg @ref LL_RCC_PLLM_DIV_1
2916 * @arg @ref LL_RCC_PLLM_DIV_2
2917 * @arg @ref LL_RCC_PLLM_DIV_3
2918 * @arg @ref LL_RCC_PLLM_DIV_4
2919 * @arg @ref LL_RCC_PLLM_DIV_5
2920 * @arg @ref LL_RCC_PLLM_DIV_6
2921 * @arg @ref LL_RCC_PLLM_DIV_7
2922 * @arg @ref LL_RCC_PLLM_DIV_8
2923 * @param PLLN Between 8 and 86
2924 * @param PLLQ This parameter can be one of the following values:
2925 * @arg @ref LL_RCC_PLLQ_DIV_2
2926 * @arg @ref LL_RCC_PLLQ_DIV_3
2927 * @arg @ref LL_RCC_PLLQ_DIV_4
2928 * @arg @ref LL_RCC_PLLQ_DIV_5
2929 * @arg @ref LL_RCC_PLLQ_DIV_6
2930 * @arg @ref LL_RCC_PLLQ_DIV_7
2931 * @arg @ref LL_RCC_PLLQ_DIV_8
2932 * @retval None
2933 */
LL_RCC_PLL_ConfigDomain_TIM1(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2934 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM1(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2935 {
2936 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2937 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2938 }
2939 #endif /* RCC_PLLQ_SUPPORT */
2940
2941 #if defined(RCC_PLLQ_SUPPORT) && defined(TIM15)
2942 /**
2943 * @brief Configure PLL used for TIM15 domain clock
2944 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2945 * @note PLLN/PLLQ can be written only when PLL is disabled
2946 * @note User shall verify whether the PLL configuration is not done through
2947 * other functions (ex: RNG, TIM1)
2948 * @note This can be selected for TIM15
2949 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_TIM15\n
2950 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_TIM15\n
2951 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_TIM15\n
2952 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_TIM15
2953 * @param Source This parameter can be one of the following values:
2954 * @arg @ref LL_RCC_PLLSOURCE_NONE
2955 * @arg @ref LL_RCC_PLLSOURCE_HSI
2956 * @arg @ref LL_RCC_PLLSOURCE_HSE
2957 * @param PLLM This parameter can be one of the following values:
2958 * @arg @ref LL_RCC_PLLM_DIV_1
2959 * @arg @ref LL_RCC_PLLM_DIV_2
2960 * @arg @ref LL_RCC_PLLM_DIV_3
2961 * @arg @ref LL_RCC_PLLM_DIV_4
2962 * @arg @ref LL_RCC_PLLM_DIV_5
2963 * @arg @ref LL_RCC_PLLM_DIV_6
2964 * @arg @ref LL_RCC_PLLM_DIV_7
2965 * @arg @ref LL_RCC_PLLM_DIV_8
2966 * @param PLLN Between 8 and 86
2967 * @param PLLQ This parameter can be one of the following values:
2968 * @arg @ref LL_RCC_PLLQ_DIV_2
2969 * @arg @ref LL_RCC_PLLQ_DIV_3
2970 * @arg @ref LL_RCC_PLLQ_DIV_4
2971 * @arg @ref LL_RCC_PLLQ_DIV_5
2972 * @arg @ref LL_RCC_PLLQ_DIV_6
2973 * @arg @ref LL_RCC_PLLQ_DIV_7
2974 * @arg @ref LL_RCC_PLLQ_DIV_8
2975 * @retval None
2976 */
LL_RCC_PLL_ConfigDomain_TIM15(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2977 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM15(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2978 {
2979 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2980 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2981 }
2982 #endif /* RCC_PLLQ_SUPPORT && TIM15 */
2983
2984 /**
2985 * @brief Get Main PLL multiplication factor for VCO
2986 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
2987 * @retval Between 8 and 86
2988 */
LL_RCC_PLL_GetN(void)2989 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
2990 {
2991 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
2992 }
2993
2994 /**
2995 * @brief Get Main PLL division factor for PLLP
2996 * @note used for PLLPCLK (ADC & I2S clock)
2997 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
2998 * @retval Returned value can be one of the following values:
2999 * @arg @ref LL_RCC_PLLP_DIV_2
3000 * @arg @ref LL_RCC_PLLP_DIV_3
3001 * @arg @ref LL_RCC_PLLP_DIV_4
3002 * @arg @ref LL_RCC_PLLP_DIV_5
3003 * @arg @ref LL_RCC_PLLP_DIV_6
3004 * @arg @ref LL_RCC_PLLP_DIV_7
3005 * @arg @ref LL_RCC_PLLP_DIV_8
3006 * @arg @ref LL_RCC_PLLP_DIV_9
3007 * @arg @ref LL_RCC_PLLP_DIV_10
3008 * @arg @ref LL_RCC_PLLP_DIV_11
3009 * @arg @ref LL_RCC_PLLP_DIV_12
3010 * @arg @ref LL_RCC_PLLP_DIV_13
3011 * @arg @ref LL_RCC_PLLP_DIV_14
3012 * @arg @ref LL_RCC_PLLP_DIV_15
3013 * @arg @ref LL_RCC_PLLP_DIV_16
3014 * @arg @ref LL_RCC_PLLP_DIV_17
3015 * @arg @ref LL_RCC_PLLP_DIV_18
3016 * @arg @ref LL_RCC_PLLP_DIV_19
3017 * @arg @ref LL_RCC_PLLP_DIV_20
3018 * @arg @ref LL_RCC_PLLP_DIV_21
3019 * @arg @ref LL_RCC_PLLP_DIV_22
3020 * @arg @ref LL_RCC_PLLP_DIV_23
3021 * @arg @ref LL_RCC_PLLP_DIV_24
3022 * @arg @ref LL_RCC_PLLP_DIV_25
3023 * @arg @ref LL_RCC_PLLP_DIV_26
3024 * @arg @ref LL_RCC_PLLP_DIV_27
3025 * @arg @ref LL_RCC_PLLP_DIV_28
3026 * @arg @ref LL_RCC_PLLP_DIV_29
3027 * @arg @ref LL_RCC_PLLP_DIV_30
3028 * @arg @ref LL_RCC_PLLP_DIV_31
3029 * @arg @ref LL_RCC_PLLP_DIV_32
3030 */
LL_RCC_PLL_GetP(void)3031 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
3032 {
3033 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
3034 }
3035
3036 #if defined(RCC_PLLQ_SUPPORT)
3037 /**
3038 * @brief Get Main PLL division factor for PLLQ
3039 * @note used for PLLQCLK selected for RNG, TIM1, TIM15 clock
3040 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
3041 * @retval Returned value can be one of the following values:
3042 * @arg @ref LL_RCC_PLLQ_DIV_2
3043 * @arg @ref LL_RCC_PLLQ_DIV_3
3044 * @arg @ref LL_RCC_PLLQ_DIV_4
3045 * @arg @ref LL_RCC_PLLQ_DIV_5
3046 * @arg @ref LL_RCC_PLLQ_DIV_6
3047 * @arg @ref LL_RCC_PLLQ_DIV_7
3048 * @arg @ref LL_RCC_PLLQ_DIV_8
3049 */
LL_RCC_PLL_GetQ(void)3050 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
3051 {
3052 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
3053 }
3054 #endif /* RCC_PLLQ_SUPPORT */
3055
3056 /**
3057 * @brief Get Main PLL division factor for PLLR
3058 * @note used for PLLCLK (system clock)
3059 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
3060 * @retval Returned value can be one of the following values:
3061 * @arg @ref LL_RCC_PLLR_DIV_2
3062 * @arg @ref LL_RCC_PLLR_DIV_3
3063 * @arg @ref LL_RCC_PLLR_DIV_4
3064 * @arg @ref LL_RCC_PLLR_DIV_5
3065 * @arg @ref LL_RCC_PLLR_DIV_6
3066 * @arg @ref LL_RCC_PLLR_DIV_7
3067 * @arg @ref LL_RCC_PLLR_DIV_8
3068 */
LL_RCC_PLL_GetR(void)3069 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
3070 {
3071 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
3072 }
3073
3074 /**
3075 * @brief Configure PLL clock source
3076 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
3077 * @param PLLSource This parameter can be one of the following values:
3078 * @arg @ref LL_RCC_PLLSOURCE_HSI
3079 * @arg @ref LL_RCC_PLLSOURCE_HSE
3080 * @retval None
3081 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)3082 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
3083 {
3084 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
3085 }
3086
3087 /**
3088 * @brief Get the oscillator used as PLL clock source.
3089 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
3090 * @retval Returned value can be one of the following values:
3091 * @arg @ref LL_RCC_PLLSOURCE_NONE
3092 * @arg @ref LL_RCC_PLLSOURCE_HSI
3093 * @arg @ref LL_RCC_PLLSOURCE_HSE
3094 */
LL_RCC_PLL_GetMainSource(void)3095 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
3096 {
3097 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
3098 }
3099
3100 /**
3101 * @brief Get Division factor for the main PLL and other PLL
3102 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
3103 * @retval Returned value can be one of the following values:
3104 * @arg @ref LL_RCC_PLLM_DIV_1
3105 * @arg @ref LL_RCC_PLLM_DIV_2
3106 * @arg @ref LL_RCC_PLLM_DIV_3
3107 * @arg @ref LL_RCC_PLLM_DIV_4
3108 * @arg @ref LL_RCC_PLLM_DIV_5
3109 * @arg @ref LL_RCC_PLLM_DIV_6
3110 * @arg @ref LL_RCC_PLLM_DIV_7
3111 * @arg @ref LL_RCC_PLLM_DIV_8
3112 */
LL_RCC_PLL_GetDivider(void)3113 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
3114 {
3115 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
3116 }
3117
3118 /**
3119 * @brief Enable PLL output mapped on ADC domain clock
3120 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
3121 * @note User shall check that PLL enable is not done through
3122 * other functions (ex: I2S1)
3123 * @retval None
3124 */
LL_RCC_PLL_EnableDomain_ADC(void)3125 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
3126 {
3127 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3128 }
3129
3130 /**
3131 * @brief Disable PLL output mapped on ADC domain clock
3132 * @note Cannot be disabled if the PLL clock is used as the system clock
3133 * @note User shall check that PLL is not used by any other peripheral
3134 * (ex: I2S1)
3135 * @note In order to save power, when the PLLCLK of the PLL is
3136 * not used, should be 0
3137 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
3138 * @retval None
3139 */
LL_RCC_PLL_DisableDomain_ADC(void)3140 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
3141 {
3142 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3143 }
3144
3145 /**
3146 * @brief Check if PLL output mapped on ADC domain clock is enabled
3147 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC
3148 * @retval State of bit (1 or 0).
3149 */
LL_RCC_PLL_IsEnabledDomain_ADC(void)3150 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void)
3151 {
3152 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
3153 }
3154
3155 /**
3156 * @brief Enable PLL output mapped on I2S domain clock
3157 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_I2S1
3158 * @note User shall check that PLL enable is not done through
3159 * other functions (ex: ADC)
3160 * @retval None
3161 */
LL_RCC_PLL_EnableDomain_I2S1(void)3162 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S1(void)
3163 {
3164 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3165 }
3166
3167 #if defined(RCC_CCIPR2_I2S2SEL)
3168 /**
3169 * @brief Enable PLL output mapped on I2S2 domain clock
3170 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_I2S2
3171 * @note User shall check that PLL enable is not done through
3172 * other functions (ex: ADC)
3173 * @retval None
3174 */
LL_RCC_PLL_EnableDomain_I2S2(void)3175 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S2(void)
3176 {
3177 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3178 }
3179 #endif /* RCC_CCIPR2_I2S2SEL */
3180
3181 /**
3182 * @brief Disable PLL output mapped on I2S1 domain clock
3183 * @note Cannot be disabled if the PLL clock is used as the system clock
3184 * @note User shall check that PLL is not used by any other peripheral
3185 * (ex: RNG)
3186 * @note In order to save power, when the PLLCLK of the PLL is
3187 * not used, should be 0
3188 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_I2S1
3189 * @retval None
3190 */
LL_RCC_PLL_DisableDomain_I2S1(void)3191 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S1(void)
3192 {
3193 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3194 }
3195
3196 /**
3197 * @brief Check if PLL output mapped on I2S1 domain clock is enabled
3198 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_I2S1
3199 * @retval State of bit (1 or 0).
3200 */
LL_RCC_PLL_IsEnabledDomain_I2S1(void)3201 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_I2S1(void)
3202 {
3203 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
3204 }
3205
3206 #if defined(RCC_CCIPR2_I2S2SEL)
3207 /**
3208 * @brief Disable PLL output mapped on I2S2 domain clock
3209 * @note Cannot be disabled if the PLL clock is used as the system clock
3210 * @note User shall check that PLL is not used by any other peripheral
3211 * (ex: RNG)
3212 * @note In order to save power, when the PLLCLK of the PLL is
3213 * not used, should be 0
3214 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_I2S2
3215 * @retval None
3216 */
LL_RCC_PLL_DisableDomain_I2S2(void)3217 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S2(void)
3218 {
3219 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3220 }
3221
3222 /**
3223 * @brief Check if PLL output mapped on I2S2 domain clock is enabled
3224 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_I2S2
3225 * @retval State of bit (1 or 0).
3226 */
LL_RCC_PLL_IsEnabledDomain_I2S2(void)3227 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_I2S2(void)
3228 {
3229 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
3230 }
3231 #endif /* RCC_CCIPR2_I2S2SEL */
3232
3233 #if defined(RNG)
3234 /**
3235 * @brief Enable PLL output mapped on RNG domain clock
3236 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_RNG
3237 * @note User shall check that PLL enable is not done through
3238 * other functions (ex: TIM1, TIM15)
3239 * @retval None
3240 */
LL_RCC_PLL_EnableDomain_RNG(void)3241 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_RNG(void)
3242 {
3243 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3244 }
3245
3246 /**
3247 * @brief Disable PLL output mapped on RNG domain clock
3248 * @note Cannot be disabled if the PLL clock is used as the system clock
3249 * @note User shall check that PLL is not used by any other peripheral
3250 * (ex: TIM, TIM15)
3251 * @note In order to save power, when the PLLCLK of the PLL is
3252 * not used, should be 0
3253 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_RNG
3254 * @retval None
3255 */
LL_RCC_PLL_DisableDomain_RNG(void)3256 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_RNG(void)
3257 {
3258 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3259 }
3260
3261 /**
3262 * @brief Check if PLL output mapped on RNG domain clock is enabled
3263 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_RNG
3264 * @retval State of bit (1 or 0).
3265 */
LL_RCC_PLL_IsEnabledDomain_RNG(void)3266 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_RNG(void)
3267 {
3268 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
3269 }
3270 #endif /* RNG */
3271
3272 #if defined(FDCAN1) || defined(FDCAN2)
3273 /**
3274 * @brief Enable PLL output mapped on FDCAN domain clock
3275 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_FDCAN
3276 * @note User shall check that PLL enable is not done through
3277 * other functions (ex: TIM1, TIM15)
3278 * @retval None
3279 */
LL_RCC_PLL_EnableDomain_FDCAN(void)3280 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_FDCAN(void)
3281 {
3282 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3283 }
3284
3285 /**
3286 * @brief Disable PLL output mapped on FDCAN domain clock
3287 * @note Cannot be disabled if the PLL clock is used as the system clock
3288 * @note User shall check that PLL is not used by any other peripheral
3289 * (ex: TIM, TIM15)
3290 * @note In order to save power, when the PLLCLK of the PLL is
3291 * not used, should be 0
3292 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_FDCAN
3293 * @retval None
3294 */
LL_RCC_PLL_DisableDomain_FDCAN(void)3295 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_FDCAN(void)
3296 {
3297 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3298 }
3299
3300 /**
3301 * @brief Check if PLL output mapped on FDCAN domain clock is enabled
3302 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_FDCAN
3303 * @retval State of bit (1 or 0).
3304 */
LL_RCC_PLL_IsEnabledDomain_FDCAN(void)3305 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_FDCAN(void)
3306 {
3307 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
3308 }
3309 #endif /* FDCAN1 || FDCAN2 */
3310
3311 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
3312 /**
3313 * @brief Enable PLL output mapped on USB domain clock
3314 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_USB
3315 * @note User shall check that PLL enable is not done through
3316 * other functions (ex: TIM1, TIM15)
3317 * @retval None
3318 */
LL_RCC_PLL_EnableDomain_USB(void)3319 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_USB(void)
3320 {
3321 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3322 }
3323
3324 /**
3325 * @brief Disable PLL output mapped on USB domain clock
3326 * @note Cannot be disabled if the PLL clock is used as the system clock
3327 * @note User shall check that PLL is not used by any other peripheral
3328 * (ex: TIM, TIM15)
3329 * @note In order to save power, when the PLLCLK of the PLL is
3330 * not used, should be 0
3331 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_USB
3332 * @retval None
3333 */
LL_RCC_PLL_DisableDomain_USB(void)3334 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_USB(void)
3335 {
3336 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3337 }
3338
3339 /**
3340 * @brief Check if PLL output mapped on USB domain clock is enabled
3341 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_USB
3342 * @retval State of bit (1 or 0).
3343 */
LL_RCC_PLL_IsEnabledDomain_USB(void)3344 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_USB(void)
3345 {
3346 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
3347 }
3348 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
3349
3350 #if defined(RCC_PLLQ_SUPPORT)
3351 /**
3352 * @brief Enable PLL output mapped on TIM1 domain clock
3353 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_TIM1
3354 * @note User shall check that PLL enable is not done through
3355 * other functions (ex: RNG, TIM15)
3356 * @retval None
3357 */
LL_RCC_PLL_EnableDomain_TIM1(void)3358 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM1(void)
3359 {
3360 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3361 }
3362
3363 /**
3364 * @brief Disable PLL output mapped on TIM1 domain clock
3365 * @note Cannot be disabled if the PLL clock is used as the system clock
3366 * @note User shall check that PLL is not used by any other peripheral
3367 * (ex: RNG, TIM15)
3368 * @note In order to save power, when the PLLCLK of the PLL is
3369 * not used, should be 0
3370 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_TIM1
3371 * @retval None
3372 */
LL_RCC_PLL_DisableDomain_TIM1(void)3373 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM1(void)
3374 {
3375 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3376 }
3377
3378 /**
3379 * @brief Check if PLL output mapped on TIM1 domain clock is enabled
3380 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_TIM1
3381 * @retval State of bit (1 or 0).
3382 */
LL_RCC_PLL_IsEnabledDomain_TIM1(void)3383 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_TIM1(void)
3384 {
3385 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
3386 }
3387 #endif /* RCC_PLLQ_SUPPORT */
3388
3389 #if defined(RCC_PLLQ_SUPPORT) && defined(TIM15)
3390 /**
3391 * @brief Enable PLL output mapped on TIM15 domain clock
3392 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_TIM15
3393 * @note User shall check that PLL enable is not done through
3394 * other functions (ex: RNG, TIM1)
3395 * @retval None
3396 */
LL_RCC_PLL_EnableDomain_TIM15(void)3397 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM15(void)
3398 {
3399 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3400 }
3401
3402 /**
3403 * @brief Disable PLL output mapped on TIM15 domain clock
3404 * @note Cannot be disabled if the PLL clock is used as the system clock
3405 * @note User shall check that PLL is not used by any other peripheral
3406 * (ex: RNG, TIM1)
3407 * @note In order to save power, when the PLLCLK of the PLL is
3408 * not used, should be 0
3409 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_TIM15
3410 * @retval None
3411 */
LL_RCC_PLL_DisableDomain_TIM15(void)3412 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM15(void)
3413 {
3414 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3415 }
3416
3417 /**
3418 * @brief Check if PLL output mapped on TIM15 domain clock is enabled
3419 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_TIM15
3420 * @retval State of bit (1 or 0).
3421 */
LL_RCC_PLL_IsEnabledDomain_TIM15(void)3422 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_TIM15(void)
3423 {
3424 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
3425 }
3426 #endif /* RCC_PLLQ_SUPPORT && TIM15 */
3427
3428 /**
3429 * @brief Enable PLL output mapped on SYSCLK domain
3430 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
3431 * @retval None
3432 */
LL_RCC_PLL_EnableDomain_SYS(void)3433 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
3434 {
3435 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
3436 }
3437
3438 /**
3439 * @brief Disable PLL output mapped on SYSCLK domain
3440 * @note Cannot be disabled if the PLL clock is used as the system clock
3441 * @note In order to save power, when the PLLCLK of the PLL is
3442 * not used, Main PLL should be 0
3443 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
3444 * @retval None
3445 */
LL_RCC_PLL_DisableDomain_SYS(void)3446 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
3447 {
3448 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
3449 }
3450
3451 /**
3452 * @brief Check if PLL output mapped on SYSCLK domain clock is enabled
3453 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
3454 * @retval State of bit (1 or 0).
3455 */
LL_RCC_PLL_IsEnabledDomain_SYS(void)3456 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
3457 {
3458 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
3459 }
3460
3461 /**
3462 * @}
3463 */
3464
3465
3466
3467 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
3468 * @{
3469 */
3470
3471 /**
3472 * @brief Clear LSI ready interrupt flag
3473 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
3474 * @retval None
3475 */
LL_RCC_ClearFlag_LSIRDY(void)3476 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
3477 {
3478 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
3479 }
3480
3481 /**
3482 * @brief Clear LSE ready interrupt flag
3483 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
3484 * @retval None
3485 */
LL_RCC_ClearFlag_LSERDY(void)3486 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
3487 {
3488 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
3489 }
3490
3491 /**
3492 * @brief Clear HSI ready interrupt flag
3493 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
3494 * @retval None
3495 */
LL_RCC_ClearFlag_HSIRDY(void)3496 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
3497 {
3498 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
3499 }
3500
3501 /**
3502 * @brief Clear HSE ready interrupt flag
3503 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
3504 * @retval None
3505 */
LL_RCC_ClearFlag_HSERDY(void)3506 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
3507 {
3508 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
3509 }
3510
3511 /**
3512 * @brief Clear PLL ready interrupt flag
3513 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
3514 * @retval None
3515 */
LL_RCC_ClearFlag_PLLRDY(void)3516 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
3517 {
3518 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
3519 }
3520
3521 #if defined(RCC_HSI48_SUPPORT)
3522 /**
3523 * @brief Clear HSI48 ready interrupt flag
3524 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
3525 * @retval None
3526 */
LL_RCC_ClearFlag_HSI48RDY(void)3527 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
3528 {
3529 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
3530 }
3531 #endif /* RCC_HSI48_SUPPORT */
3532 /**
3533 * @brief Clear Clock security system interrupt flag
3534 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
3535 * @retval None
3536 */
LL_RCC_ClearFlag_HSECSS(void)3537 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
3538 {
3539 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
3540 }
3541
3542 /**
3543 * @brief Clear LSE Clock security system interrupt flag
3544 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
3545 * @retval None
3546 */
LL_RCC_ClearFlag_LSECSS(void)3547 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
3548 {
3549 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
3550 }
3551
3552 /**
3553 * @brief Check if LSI ready interrupt occurred or not
3554 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
3555 * @retval State of bit (1 or 0).
3556 */
LL_RCC_IsActiveFlag_LSIRDY(void)3557 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
3558 {
3559 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
3560 }
3561
3562 /**
3563 * @brief Check if LSE ready interrupt occurred or not
3564 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
3565 * @retval State of bit (1 or 0).
3566 */
LL_RCC_IsActiveFlag_LSERDY(void)3567 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
3568 {
3569 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
3570 }
3571
3572 /**
3573 * @brief Check if HSI ready interrupt occurred or not
3574 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
3575 * @retval State of bit (1 or 0).
3576 */
LL_RCC_IsActiveFlag_HSIRDY(void)3577 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
3578 {
3579 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
3580 }
3581
3582 /**
3583 * @brief Check if HSE ready interrupt occurred or not
3584 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
3585 * @retval State of bit (1 or 0).
3586 */
LL_RCC_IsActiveFlag_HSERDY(void)3587 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
3588 {
3589 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
3590 }
3591
3592 /**
3593 * @brief Check if PLL ready interrupt occurred or not
3594 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
3595 * @retval State of bit (1 or 0).
3596 */
LL_RCC_IsActiveFlag_PLLRDY(void)3597 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
3598 {
3599 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
3600 }
3601
3602 #if defined(RCC_HSI48_SUPPORT)
3603 /**
3604 * @brief Check if HSI48 ready interrupt occurred or not
3605 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
3606 * @retval State of bit (1 or 0).
3607 */
LL_RCC_IsActiveFlag_HSI48RDY(void)3608 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
3609 {
3610 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
3611 }
3612 #endif /* RCC_HSI48_SUPPORT */
3613
3614 /**
3615 * @brief Check if Clock security system interrupt occurred or not
3616 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
3617 * @retval State of bit (1 or 0).
3618 */
LL_RCC_IsActiveFlag_HSECSS(void)3619 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
3620 {
3621 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
3622 }
3623
3624 /**
3625 * @brief Check if LSE Clock security system interrupt occurred or not
3626 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
3627 * @retval State of bit (1 or 0).
3628 */
LL_RCC_IsActiveFlag_LSECSS(void)3629 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
3630 {
3631 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
3632 }
3633
3634 /**
3635 * @brief Check if RCC flag Independent Watchdog reset is set or not.
3636 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
3637 * @retval State of bit (1 or 0).
3638 */
LL_RCC_IsActiveFlag_IWDGRST(void)3639 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
3640 {
3641 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
3642 }
3643
3644 /**
3645 * @brief Check if RCC flag Low Power reset is set or not.
3646 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
3647 * @retval State of bit (1 or 0).
3648 */
LL_RCC_IsActiveFlag_LPWRRST(void)3649 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
3650 {
3651 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
3652 }
3653
3654 /**
3655 * @brief Check if RCC flag Option byte reset is set or not.
3656 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
3657 * @retval State of bit (1 or 0).
3658 */
LL_RCC_IsActiveFlag_OBLRST(void)3659 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
3660 {
3661 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
3662 }
3663
3664 /**
3665 * @brief Check if RCC flag Pin reset is set or not.
3666 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
3667 * @retval State of bit (1 or 0).
3668 */
LL_RCC_IsActiveFlag_PINRST(void)3669 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
3670 {
3671 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
3672 }
3673
3674 /**
3675 * @brief Check if RCC flag Software reset is set or not.
3676 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
3677 * @retval State of bit (1 or 0).
3678 */
LL_RCC_IsActiveFlag_SFTRST(void)3679 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
3680 {
3681 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
3682 }
3683
3684 /**
3685 * @brief Check if RCC flag Window Watchdog reset is set or not.
3686 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
3687 * @retval State of bit (1 or 0).
3688 */
LL_RCC_IsActiveFlag_WWDGRST(void)3689 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
3690 {
3691 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
3692 }
3693
3694 /**
3695 * @brief Check if RCC flag BOR or POR/PDR reset is set or not.
3696 * @rmtoll CSR PWRRSTF LL_RCC_IsActiveFlag_PWRRST
3697 * @retval State of bit (1 or 0).
3698 */
LL_RCC_IsActiveFlag_PWRRST(void)3699 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST(void)
3700 {
3701 return ((READ_BIT(RCC->CSR, RCC_CSR_PWRRSTF) == (RCC_CSR_PWRRSTF)) ? 1UL : 0UL);
3702 }
3703
3704 /**
3705 * @brief Set RMVF bit to clear the reset flags.
3706 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
3707 * @retval None
3708 */
LL_RCC_ClearResetFlags(void)3709 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
3710 {
3711 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
3712 }
3713
3714 /**
3715 * @}
3716 */
3717
3718 /** @defgroup RCC_LL_EF_IT_Management IT Management
3719 * @{
3720 */
3721
3722 /**
3723 * @brief Enable LSI ready interrupt
3724 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
3725 * @retval None
3726 */
LL_RCC_EnableIT_LSIRDY(void)3727 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
3728 {
3729 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
3730 }
3731
3732 /**
3733 * @brief Enable LSE ready interrupt
3734 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
3735 * @retval None
3736 */
LL_RCC_EnableIT_LSERDY(void)3737 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
3738 {
3739 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3740 }
3741
3742 /**
3743 * @brief Enable HSI ready interrupt
3744 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
3745 * @retval None
3746 */
LL_RCC_EnableIT_HSIRDY(void)3747 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
3748 {
3749 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3750 }
3751
3752 /**
3753 * @brief Enable HSE ready interrupt
3754 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
3755 * @retval None
3756 */
LL_RCC_EnableIT_HSERDY(void)3757 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
3758 {
3759 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3760 }
3761
3762 /**
3763 * @brief Enable PLL ready interrupt
3764 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
3765 * @retval None
3766 */
LL_RCC_EnableIT_PLLRDY(void)3767 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
3768 {
3769 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
3770 }
3771
3772 #if defined(RCC_HSI48_SUPPORT)
3773 /**
3774 * @brief Enable HSI48 ready interrupt
3775 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
3776 * @retval None
3777 */
LL_RCC_EnableIT_HSI48RDY(void)3778 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
3779 {
3780 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
3781 }
3782 #endif /* RCC_HSI48_SUPPORT */
3783
3784 /**
3785 * @brief Disable LSI ready interrupt
3786 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
3787 * @retval None
3788 */
LL_RCC_DisableIT_LSIRDY(void)3789 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
3790 {
3791 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
3792 }
3793
3794 /**
3795 * @brief Disable LSE ready interrupt
3796 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
3797 * @retval None
3798 */
LL_RCC_DisableIT_LSERDY(void)3799 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
3800 {
3801 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3802 }
3803
3804 /**
3805 * @brief Disable HSI ready interrupt
3806 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
3807 * @retval None
3808 */
LL_RCC_DisableIT_HSIRDY(void)3809 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
3810 {
3811 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3812 }
3813
3814 /**
3815 * @brief Disable HSE ready interrupt
3816 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
3817 * @retval None
3818 */
LL_RCC_DisableIT_HSERDY(void)3819 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
3820 {
3821 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3822 }
3823
3824 /**
3825 * @brief Disable PLL ready interrupt
3826 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
3827 * @retval None
3828 */
LL_RCC_DisableIT_PLLRDY(void)3829 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
3830 {
3831 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
3832 }
3833
3834 #if defined(RCC_HSI48_SUPPORT)
3835 /**
3836 * @brief Disable HSI48 ready interrupt
3837 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
3838 * @retval None
3839 */
LL_RCC_DisableIT_HSI48RDY(void)3840 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
3841 {
3842 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
3843 }
3844 #endif /* RCC_HSI48_SUPPORT */
3845
3846 /**
3847 * @brief Checks if LSI ready interrupt source is enabled or disabled.
3848 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
3849 * @retval State of bit (1 or 0).
3850 */
LL_RCC_IsEnabledIT_LSIRDY(void)3851 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
3852 {
3853 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
3854 }
3855
3856 /**
3857 * @brief Checks if LSE ready interrupt source is enabled or disabled.
3858 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
3859 * @retval State of bit (1 or 0).
3860 */
LL_RCC_IsEnabledIT_LSERDY(void)3861 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
3862 {
3863 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
3864 }
3865
3866 /**
3867 * @brief Checks if HSI ready interrupt source is enabled or disabled.
3868 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
3869 * @retval State of bit (1 or 0).
3870 */
LL_RCC_IsEnabledIT_HSIRDY(void)3871 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
3872 {
3873 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
3874 }
3875
3876 #if defined(RCC_HSI48_SUPPORT)
3877 /**
3878 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
3879 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
3880 * @retval State of bit (1 or 0).
3881 */
LL_RCC_IsEnabledIT_HSI48RDY(void)3882 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
3883 {
3884 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
3885 }
3886 #endif /* RCC_HSI48_SUPPORT */
3887
3888 /**
3889 * @brief Checks if HSE ready interrupt source is enabled or disabled.
3890 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
3891 * @retval State of bit (1 or 0).
3892 */
LL_RCC_IsEnabledIT_HSERDY(void)3893 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
3894 {
3895 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
3896 }
3897
3898 /**
3899 * @brief Checks if PLL ready interrupt source is enabled or disabled.
3900 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
3901 * @retval State of bit (1 or 0).
3902 */
LL_RCC_IsEnabledIT_PLLRDY(void)3903 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
3904 {
3905 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
3906 }
3907
3908 /**
3909 * @}
3910 */
3911
3912 #if defined(USE_FULL_LL_DRIVER)
3913 /** @defgroup RCC_LL_EF_Init De-initialization function
3914 * @{
3915 */
3916 ErrorStatus LL_RCC_DeInit(void);
3917 /**
3918 * @}
3919 */
3920
3921 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
3922 * @{
3923 */
3924 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
3925 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
3926 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
3927 #if defined(LPUART1) || defined(LPUART2)
3928 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
3929 #endif /* LPUART1 */
3930 #if defined(LPTIM1) && defined(LPTIM2)
3931 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
3932 #endif /* LPTIM1 && LPTIM2 */
3933 #if defined(RNG)
3934 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
3935 #endif /* RNG */
3936 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
3937 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
3938 #if defined(CEC)
3939 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
3940 #endif /* CEC */
3941 #if defined(FDCAN1) || defined(FDCAN2)
3942 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
3943 #endif /* FDCAN1 */
3944 uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
3945 uint32_t LL_RCC_GetRTCClockFreq(void);
3946 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
3947 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
3948 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
3949 /**
3950 * @}
3951 */
3952 #endif /* USE_FULL_LL_DRIVER */
3953
3954 /**
3955 * @}
3956 */
3957
3958 /**
3959 * @}
3960 */
3961
3962 #endif /* RCC */
3963
3964 /**
3965 * @}
3966 */
3967
3968 #ifdef __cplusplus
3969 }
3970 #endif
3971
3972 #endif /* STM32G0xx_LL_RCC_H */
3973
3974
