1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WLxx_LL_LPTIM_H
21 #define STM32WLxx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wlxx.h"
29
30 /** @addtogroup STM32WLxx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46 #if defined(USE_FULL_LL_DRIVER)
47 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
48 * @{
49 */
50 /**
51 * @}
52 */
53 #endif /*USE_FULL_LL_DRIVER*/
54
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
58 * @{
59 */
60
61 /**
62 * @brief LPTIM Init structure definition
63 */
64 typedef struct
65 {
66 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
67 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
68
69 This feature can be modified afterwards using unitary
70 function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary
76 function @ref LL_LPTIM_SetPrescaler().*/
77
78 uint32_t Waveform; /*!< Specifies the waveform shape.
79 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
80
81 This feature can be modified afterwards using unitary
82 function @ref LL_LPTIM_ConfigOutput().*/
83
84 uint32_t Polarity; /*!< Specifies waveform polarity.
85 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
86
87 This feature can be modified afterwards using unitary
88 function @ref LL_LPTIM_ConfigOutput().*/
89 } LL_LPTIM_InitTypeDef;
90
91 /**
92 * @}
93 */
94 #endif /* USE_FULL_LL_DRIVER */
95
96 /* Exported constants --------------------------------------------------------*/
97 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
98 * @{
99 */
100
101 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
102 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
103 * @{
104 */
105 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
106 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
107 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
108 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
109 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
110 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
111 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
112 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
113 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
114 /**
115 * @}
116 */
117
118 /** @defgroup LPTIM_LL_EC_IT IT Defines
119 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
120 * @{
121 */
122 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
123 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
124 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
125 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
126 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
127 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
128 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
129 #define LL_LPTIM_IER_UEIE LPTIM_IER_UEIE /*!< Update event */
130 #define LL_LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE /*!< Repetition register update OK */
131 /**
132 * @}
133 */
134
135 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
136 * @{
137 */
138 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
139 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
140 /**
141 * @}
142 */
143
144 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
145 * @{
146 */
147 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
148 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
149 /**
150 * @}
151 */
152
153 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
154 * @{
155 */
156 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
157 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
158 /**
159 * @}
160 */
161
162 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
163 * @{
164 */
165 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
166 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
167 /**
168 * @}
169 */
170
171 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
172 * @{
173 */
174 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
175 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
176 /**
177 * @}
178 */
179
180 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
181 * @{
182 */
183 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
184 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
185 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
186 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
187 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
188 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
189 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
190 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
191 /**
192 * @}
193 */
194
195 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
196 * @{
197 */
198 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
199 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
200 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
201 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
202 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
203 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
204 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
205 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
206 #define LL_LPTIM_TRIG_SOURCE_LPTIM1 LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to LPTIM1 output*/
207 #define LL_LPTIM_TRIG_SOURCE_LPTIM2 LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to LPTIM1 output*/
208 /**
209 * @}
210 */
211
212 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
213 * @{
214 */
215 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
216 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
217 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
218 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
219 /**
220 * @}
221 */
222
223 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
224 * @{
225 */
226 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
227 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
228 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
229 /**
230 * @}
231 */
232
233 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
234 * @{
235 */
236 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
237 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
238 /**
239 * @}
240 */
241
242 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
243 * @{
244 */
245 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
246 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
247 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
248 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
249 /**
250 * @}
251 */
252
253 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
254 * @{
255 */
256 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
257 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
258 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
259 /**
260 * @}
261 */
262
263 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
264 * @{
265 */
266 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
267 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
268 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
269 /**
270 * @}
271 */
272
273 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
274 * @{
275 */
276 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
277 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_OR_0 /*!< For LPTIM1 and LPTIM2 */
278 #define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM2 */
279 #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 LPTIM_OR_OR /*!< For LPTIM2 */
280 /**
281 * @}
282 */
283
284 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
285 * @{
286 */
287 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U /*!< For LPTIM1 */
288 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM1 */
289 /**
290 * @}
291 */
292
293 /**
294 * @}
295 */
296
297 /* Exported macro ------------------------------------------------------------*/
298 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
299 * @{
300 */
301
302 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
303 * @{
304 */
305
306 /**
307 * @brief Write a value in LPTIM register
308 * @param __INSTANCE__ LPTIM Instance
309 * @param __REG__ Register to be written
310 * @param __VALUE__ Value to be written in the register
311 * @retval None
312 */
313 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
314
315 /**
316 * @brief Read a value in LPTIM register
317 * @param __INSTANCE__ LPTIM Instance
318 * @param __REG__ Register to be read
319 * @retval Register value
320 */
321 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
322 /**
323 * @}
324 */
325
326 /**
327 * @}
328 */
329
330 /* Exported functions --------------------------------------------------------*/
331 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
332 * @{
333 */
334
335 /** Legacy definitions for compatibility purpose
336 @cond 0
337 */
338 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
339 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
340 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
341 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
342 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
343 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
344 /**
345 @endcond
346 */
347
348 #if defined(USE_FULL_LL_DRIVER)
349 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
350 * @{
351 */
352
353 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
354 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
355 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
356 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
357 /**
358 * @}
359 */
360 #endif /* USE_FULL_LL_DRIVER */
361
362 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
363 * @{
364 */
365
366 /**
367 * @brief Enable the LPTIM instance
368 * @note After setting the ENABLE bit, a delay of two counter clock is needed
369 * before the LPTIM instance is actually enabled.
370 * @rmtoll CR ENABLE LL_LPTIM_Enable
371 * @param LPTIMx Low-Power Timer instance
372 * @retval None
373 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)374 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
375 {
376 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
377 }
378
379 /**
380 * @brief Indicates whether the LPTIM instance is enabled.
381 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
382 * @param LPTIMx Low-Power Timer instance
383 * @retval State of bit (1 or 0).
384 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)385 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
386 {
387 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
388 }
389
390 /**
391 * @brief Starts the LPTIM counter in the desired mode.
392 * @note LPTIM instance must be enabled before starting the counter.
393 * @note It is possible to change on the fly from One Shot mode to
394 * Continuous mode.
395 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
396 * CR SNGSTRT LL_LPTIM_StartCounter
397 * @param LPTIMx Low-Power Timer instance
398 * @param OperatingMode This parameter can be one of the following values:
399 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
400 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
401 * @retval None
402 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)403 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
404 {
405 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
406 }
407
408 /**
409 * @brief Enable reset after read.
410 * @note After calling this function any read access to LPTIM_CNT
411 * register will asynchronously reset the LPTIM_CNT register content.
412 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
413 * @param LPTIMx Low-Power Timer instance
414 * @retval None
415 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)416 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
417 {
418 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
419 }
420
421 /**
422 * @brief Disable reset after read.
423 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
424 * @param LPTIMx Low-Power Timer instance
425 * @retval None
426 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)427 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
428 {
429 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
430 }
431
432 /**
433 * @brief Indicate whether the reset after read feature is enabled.
434 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
435 * @param LPTIMx Low-Power Timer instance
436 * @retval State of bit (1 or 0).
437 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)438 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
439 {
440 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
441 }
442
443 /**
444 * @brief Reset of the LPTIM_CNT counter register (synchronous).
445 * @note Due to the synchronous nature of this reset, it only takes
446 * place after a synchronization delay of 3 LPTIM core clock cycles
447 * (LPTIM core clock may be different from APB clock).
448 * @note COUNTRST is automatically cleared by hardware
449 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
450 * @param LPTIMx Low-Power Timer instance
451 * @retval None
452 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)453 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
454 {
455 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
456 }
457
458 /**
459 * @brief Set the LPTIM registers update mode (enable/disable register preload)
460 * @note This function must be called when the LPTIM instance is disabled.
461 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
462 * @param LPTIMx Low-Power Timer instance
463 * @param UpdateMode This parameter can be one of the following values:
464 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
465 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
466 * @retval None
467 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)468 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
469 {
470 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
471 }
472
473 /**
474 * @brief Get the LPTIM registers update mode
475 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
476 * @param LPTIMx Low-Power Timer instance
477 * @retval Returned value can be one of the following values:
478 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
479 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
480 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)481 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
482 {
483 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
484 }
485
486 /**
487 * @brief Set the auto reload value
488 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
489 * @note After a write to the LPTIMx_ARR register a new write operation to the
490 * same register can only be performed when the previous write operation
491 * is completed. Any successive write before the ARROK flag is set, will
492 * lead to unpredictable results.
493 * @note autoreload value be strictly greater than the compare value.
494 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
495 * @param LPTIMx Low-Power Timer instance
496 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
497 * @retval None
498 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)499 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
500 {
501 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
502 }
503
504 /**
505 * @brief Get actual auto reload value
506 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
507 * @param LPTIMx Low-Power Timer instance
508 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
509 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)510 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
511 {
512 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
513 }
514
515 /**
516 * @brief Set the repetition value
517 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
518 * @rmtoll RCR REP LL_LPTIM_SetRepetition
519 * @param LPTIMx Low-Power Timer instance
520 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
521 * @retval None
522 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)523 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
524 {
525 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
526 }
527
528 /**
529 * @brief Get the repetition value
530 * @rmtoll RCR REP LL_LPTIM_GetRepetition
531 * @param LPTIMx Low-Power Timer instance
532 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
533 */
LL_LPTIM_GetRepetition(const LPTIM_TypeDef * LPTIMx)534 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
535 {
536 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
537 }
538
539 /**
540 * @brief Set the compare value
541 * @note After a write to the LPTIMx_CMP register a new write operation to the
542 * same register can only be performed when the previous write operation
543 * is completed. Any successive write before the CMPOK flag is set, will
544 * lead to unpredictable results.
545 * @rmtoll CMP CMP LL_LPTIM_SetCompare
546 * @param LPTIMx Low-Power Timer instance
547 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
548 * @retval None
549 */
LL_LPTIM_SetCompare(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)550 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
551 {
552 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
553 }
554
555 /**
556 * @brief Get actual compare value
557 * @rmtoll CMP CMP LL_LPTIM_GetCompare
558 * @param LPTIMx Low-Power Timer instance
559 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
560 */
LL_LPTIM_GetCompare(const LPTIM_TypeDef * LPTIMx)561 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx)
562 {
563 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
564 }
565
566 /**
567 * @brief Get actual counter value
568 * @note When the LPTIM instance is running with an asynchronous clock, reading
569 * the LPTIMx_CNT register may return unreliable values. So in this case
570 * it is necessary to perform two consecutive read accesses and verify
571 * that the two returned values are identical.
572 * @rmtoll CNT CNT LL_LPTIM_GetCounter
573 * @param LPTIMx Low-Power Timer instance
574 * @retval Counter value
575 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)576 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
577 {
578 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
579 }
580
581 /**
582 * @brief Set the counter mode (selection of the LPTIM counter clock source).
583 * @note The counter mode can be set only when the LPTIM instance is disabled.
584 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
585 * @param LPTIMx Low-Power Timer instance
586 * @param CounterMode This parameter can be one of the following values:
587 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
588 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
589 * @retval None
590 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)591 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
592 {
593 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
594 }
595
596 /**
597 * @brief Get the counter mode
598 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
599 * @param LPTIMx Low-Power Timer instance
600 * @retval Returned value can be one of the following values:
601 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
602 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
603 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)604 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
605 {
606 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
607 }
608
609 /**
610 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
611 * @note This function must be called when the LPTIM instance is disabled.
612 * @note Regarding the LPTIM output polarity the change takes effect
613 * immediately, so the output default value will change immediately after
614 * the polarity is re-configured, even before the timer is enabled.
615 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
616 * CFGR WAVPOL LL_LPTIM_ConfigOutput
617 * @param LPTIMx Low-Power Timer instance
618 * @param Waveform This parameter can be one of the following values:
619 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
620 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
621 * @param Polarity This parameter can be one of the following values:
622 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
623 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
624 * @retval None
625 */
LL_LPTIM_ConfigOutput(LPTIM_TypeDef * LPTIMx,uint32_t Waveform,uint32_t Polarity)626 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
627 {
628 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
629 }
630
631 /**
632 * @brief Set waveform shape
633 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
634 * @param LPTIMx Low-Power Timer instance
635 * @param Waveform This parameter can be one of the following values:
636 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
637 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
638 * @retval None
639 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)640 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
641 {
642 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
643 }
644
645 /**
646 * @brief Get actual waveform shape
647 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
648 * @param LPTIMx Low-Power Timer instance
649 * @retval Returned value can be one of the following values:
650 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
651 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
652 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)653 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
654 {
655 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
656 }
657
658 /**
659 * @brief Set output polarity
660 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
661 * @param LPTIMx Low-Power Timer instance
662 * @param Polarity This parameter can be one of the following values:
663 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
664 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
665 * @retval None
666 */
LL_LPTIM_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Polarity)667 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
668 {
669 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
670 }
671
672 /**
673 * @brief Get actual output polarity
674 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
675 * @param LPTIMx Low-Power Timer instance
676 * @retval Returned value can be one of the following values:
677 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
678 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
679 */
LL_LPTIM_GetPolarity(const LPTIM_TypeDef * LPTIMx)680 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx)
681 {
682 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
683 }
684
685 /**
686 * @brief Set actual prescaler division ratio.
687 * @note This function must be called when the LPTIM instance is disabled.
688 * @note When the LPTIM is configured to be clocked by an internal clock source
689 * and the LPTIM counter is configured to be updated by active edges
690 * detected on the LPTIM external Input1, the internal clock provided to
691 * the LPTIM must be not be prescaled.
692 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
693 * @param LPTIMx Low-Power Timer instance
694 * @param Prescaler This parameter can be one of the following values:
695 * @arg @ref LL_LPTIM_PRESCALER_DIV1
696 * @arg @ref LL_LPTIM_PRESCALER_DIV2
697 * @arg @ref LL_LPTIM_PRESCALER_DIV4
698 * @arg @ref LL_LPTIM_PRESCALER_DIV8
699 * @arg @ref LL_LPTIM_PRESCALER_DIV16
700 * @arg @ref LL_LPTIM_PRESCALER_DIV32
701 * @arg @ref LL_LPTIM_PRESCALER_DIV64
702 * @arg @ref LL_LPTIM_PRESCALER_DIV128
703 * @retval None
704 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)705 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
706 {
707 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
708 }
709
710 /**
711 * @brief Get actual prescaler division ratio.
712 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
713 * @param LPTIMx Low-Power Timer instance
714 * @retval Returned value can be one of the following values:
715 * @arg @ref LL_LPTIM_PRESCALER_DIV1
716 * @arg @ref LL_LPTIM_PRESCALER_DIV2
717 * @arg @ref LL_LPTIM_PRESCALER_DIV4
718 * @arg @ref LL_LPTIM_PRESCALER_DIV8
719 * @arg @ref LL_LPTIM_PRESCALER_DIV16
720 * @arg @ref LL_LPTIM_PRESCALER_DIV32
721 * @arg @ref LL_LPTIM_PRESCALER_DIV64
722 * @arg @ref LL_LPTIM_PRESCALER_DIV128
723 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)724 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
725 {
726 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
727 }
728
729 /**
730 * @brief Set LPTIM input 1 source (default GPIO).
731 * @rmtoll OR OR LL_LPTIM_SetInput1Src
732 * @param LPTIMx Low-Power Timer instance
733 * @param Src This parameter can be one of the following values:
734 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
735 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
736 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
737 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
738 * @retval None
739 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)740 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
741 {
742 MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
743 }
744
745 /**
746 * @brief Set LPTIM input 2 source (default GPIO).
747 * @rmtoll OR OR LL_LPTIM_SetInput2Src
748 * @param LPTIMx Low-Power Timer instance
749 * @param Src This parameter can be one of the following values:
750 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
751 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
752 * @retval None
753 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)754 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
755 {
756 MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
757 }
758
759 /**
760 * @}
761 */
762
763 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
764 * @{
765 */
766
767 /**
768 * @brief Enable the timeout function
769 * @note This function must be called when the LPTIM instance is disabled.
770 * @note The first trigger event will start the timer, any successive trigger
771 * event will reset the counter and the timer will restart.
772 * @note The timeout value corresponds to the compare value; if no trigger
773 * occurs within the expected time frame, the MCU is waked-up by the
774 * compare match event.
775 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
776 * @param LPTIMx Low-Power Timer instance
777 * @retval None
778 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)779 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
780 {
781 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
782 }
783
784 /**
785 * @brief Disable the timeout function
786 * @note This function must be called when the LPTIM instance is disabled.
787 * @note A trigger event arriving when the timer is already started will be
788 * ignored.
789 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
790 * @param LPTIMx Low-Power Timer instance
791 * @retval None
792 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)793 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
794 {
795 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
796 }
797
798 /**
799 * @brief Indicate whether the timeout function is enabled.
800 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
801 * @param LPTIMx Low-Power Timer instance
802 * @retval State of bit (1 or 0).
803 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)804 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
805 {
806 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
807 }
808
809 /**
810 * @brief Start the LPTIM counter
811 * @note This function must be called when the LPTIM instance is disabled.
812 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
813 * @param LPTIMx Low-Power Timer instance
814 * @retval None
815 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)816 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
817 {
818 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
819 }
820
821 /**
822 * @brief Configure the external trigger used as a trigger event for the LPTIM.
823 * @note This function must be called when the LPTIM instance is disabled.
824 * @note An internal clock source must be present when a digital filter is
825 * required for the trigger.
826 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
827 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
828 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
829 * @param LPTIMx Low-Power Timer instance
830 * @param Source This parameter can be one of the following values:
831 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
832 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
833 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
834 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
835 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
836 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
837 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
838 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
839 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM1 (*)
840 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2 (*)
841 *
842 * (*) Value not defined in all devices. \n
843 *
844 * @param Filter This parameter can be one of the following values:
845 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
846 * @arg @ref LL_LPTIM_TRIG_FILTER_2
847 * @arg @ref LL_LPTIM_TRIG_FILTER_4
848 * @arg @ref LL_LPTIM_TRIG_FILTER_8
849 * @param Polarity This parameter can be one of the following values:
850 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
851 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
852 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
853 * @retval None
854 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)855 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
856 {
857 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
858 }
859
860 /**
861 * @brief Get actual external trigger source.
862 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
863 * @param LPTIMx Low-Power Timer instance
864 * @retval Returned value can be one of the following values:
865 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
866 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
867 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
868 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
869 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
870 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
871 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
872 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
873 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM1 (*)
874 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2 (*)
875 *
876 * (*) Value not defined in all devices. \n
877 *
878 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)879 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
880 {
881 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
882 }
883
884 /**
885 * @brief Get actual external trigger filter.
886 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
887 * @param LPTIMx Low-Power Timer instance
888 * @retval Returned value can be one of the following values:
889 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
890 * @arg @ref LL_LPTIM_TRIG_FILTER_2
891 * @arg @ref LL_LPTIM_TRIG_FILTER_4
892 * @arg @ref LL_LPTIM_TRIG_FILTER_8
893 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)894 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
895 {
896 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
897 }
898
899 /**
900 * @brief Get actual external trigger polarity.
901 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
902 * @param LPTIMx Low-Power Timer instance
903 * @retval Returned value can be one of the following values:
904 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
905 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
906 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
907 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)908 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
909 {
910 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
911 }
912
913 /**
914 * @}
915 */
916
917 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
918 * @{
919 */
920
921 /**
922 * @brief Set the source of the clock used by the LPTIM instance.
923 * @note This function must be called when the LPTIM instance is disabled.
924 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
925 * @param LPTIMx Low-Power Timer instance
926 * @param ClockSource This parameter can be one of the following values:
927 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
928 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
929 * @retval None
930 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)931 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
932 {
933 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
934 }
935
936 /**
937 * @brief Get actual LPTIM instance clock source.
938 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
939 * @param LPTIMx Low-Power Timer instance
940 * @retval Returned value can be one of the following values:
941 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
942 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
943 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)944 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
945 {
946 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
947 }
948
949 /**
950 * @brief Configure the active edge or edges used by the counter when
951 the LPTIM is clocked by an external clock source.
952 * @note This function must be called when the LPTIM instance is disabled.
953 * @note When both external clock signal edges are considered active ones,
954 * the LPTIM must also be clocked by an internal clock source with a
955 * frequency equal to at least four times the external clock frequency.
956 * @note An internal clock source must be present when a digital filter is
957 * required for external clock.
958 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
959 * CFGR CKPOL LL_LPTIM_ConfigClock
960 * @param LPTIMx Low-Power Timer instance
961 * @param ClockFilter This parameter can be one of the following values:
962 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
963 * @arg @ref LL_LPTIM_CLK_FILTER_2
964 * @arg @ref LL_LPTIM_CLK_FILTER_4
965 * @arg @ref LL_LPTIM_CLK_FILTER_8
966 * @param ClockPolarity This parameter can be one of the following values:
967 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
968 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
969 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
970 * @retval None
971 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)972 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
973 {
974 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
975 }
976
977 /**
978 * @brief Get actual clock polarity
979 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
980 * @param LPTIMx Low-Power Timer instance
981 * @retval Returned value can be one of the following values:
982 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
983 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
984 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
985 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)986 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
987 {
988 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
989 }
990
991 /**
992 * @brief Get actual clock digital filter
993 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
994 * @param LPTIMx Low-Power Timer instance
995 * @retval Returned value can be one of the following values:
996 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
997 * @arg @ref LL_LPTIM_CLK_FILTER_2
998 * @arg @ref LL_LPTIM_CLK_FILTER_4
999 * @arg @ref LL_LPTIM_CLK_FILTER_8
1000 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)1001 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1002 {
1003 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1004 }
1005
1006 /**
1007 * @}
1008 */
1009
1010 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1011 * @{
1012 */
1013
1014 /**
1015 * @brief Configure the encoder mode.
1016 * @note This function must be called when the LPTIM instance is disabled.
1017 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1018 * @param LPTIMx Low-Power Timer instance
1019 * @param EncoderMode This parameter can be one of the following values:
1020 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1021 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1022 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1023 * @retval None
1024 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1025 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1026 {
1027 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1028 }
1029
1030 /**
1031 * @brief Get actual encoder mode.
1032 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1033 * @param LPTIMx Low-Power Timer instance
1034 * @retval Returned value can be one of the following values:
1035 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1036 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1037 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1038 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1039 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1040 {
1041 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1042 }
1043
1044 /**
1045 * @brief Enable the encoder mode
1046 * @note This function must be called when the LPTIM instance is disabled.
1047 * @note In this mode the LPTIM instance must be clocked by an internal clock
1048 * source. Also, the prescaler division ratio must be equal to 1.
1049 * @note LPTIM instance must be configured in continuous mode prior enabling
1050 * the encoder mode.
1051 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1052 * @param LPTIMx Low-Power Timer instance
1053 * @retval None
1054 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1055 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1056 {
1057 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1058 }
1059
1060 /**
1061 * @brief Disable the encoder mode
1062 * @note This function must be called when the LPTIM instance is disabled.
1063 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1064 * @param LPTIMx Low-Power Timer instance
1065 * @retval None
1066 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1067 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1068 {
1069 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1070 }
1071
1072 /**
1073 * @brief Indicates whether the LPTIM operates in encoder mode.
1074 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1075 * @param LPTIMx Low-Power Timer instance
1076 * @retval State of bit (1 or 0).
1077 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1078 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1079 {
1080 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1081 }
1082
1083 /**
1084 * @}
1085 */
1086
1087 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1088 * @{
1089 */
1090
1091
1092 /**
1093 * @brief Clear the compare match flag (CMPMCF)
1094 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM
1095 * @param LPTIMx Low-Power Timer instance
1096 * @retval None
1097 */
LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef * LPTIMx)1098 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx)
1099 {
1100 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
1101 }
1102
1103 /**
1104 * @brief Inform application whether a compare match interrupt has occurred.
1105 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
1106 * @param LPTIMx Low-Power Timer instance
1107 * @retval State of bit (1 or 0).
1108 */
LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef * LPTIMx)1109 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx)
1110 {
1111 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
1112 }
1113
1114 /**
1115 * @brief Clear the autoreload match flag (ARRMCF)
1116 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1117 * @param LPTIMx Low-Power Timer instance
1118 * @retval None
1119 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1120 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1121 {
1122 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1123 }
1124
1125 /**
1126 * @brief Inform application whether a autoreload match interrupt has occurred.
1127 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1128 * @param LPTIMx Low-Power Timer instance
1129 * @retval State of bit (1 or 0).
1130 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1131 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1132 {
1133 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1134 }
1135
1136 /**
1137 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1138 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1139 * @param LPTIMx Low-Power Timer instance
1140 * @retval None
1141 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1142 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1143 {
1144 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1145 }
1146
1147 /**
1148 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1149 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1150 * @param LPTIMx Low-Power Timer instance
1151 * @retval State of bit (1 or 0).
1152 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1153 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1154 {
1155 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1156 }
1157
1158 /**
1159 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1160 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1161 * @param LPTIMx Low-Power Timer instance
1162 * @retval None
1163 */
LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1164 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1165 {
1166 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1167 }
1168
1169 /**
1170 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
1171 completed. If so, a new one can be initiated.
1172 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1173 * @param LPTIMx Low-Power Timer instance
1174 * @retval State of bit (1 or 0).
1175 */
LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef * LPTIMx)1176 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx)
1177 {
1178 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
1179 }
1180
1181 /**
1182 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1183 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1184 * @param LPTIMx Low-Power Timer instance
1185 * @retval None
1186 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1187 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1188 {
1189 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1190 }
1191
1192 /**
1193 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1194 completed. If so, a new one can be initiated.
1195 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1196 * @param LPTIMx Low-Power Timer instance
1197 * @retval State of bit (1 or 0).
1198 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1199 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1200 {
1201 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1202 }
1203
1204 /**
1205 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1206 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1207 * @param LPTIMx Low-Power Timer instance
1208 * @retval None
1209 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1210 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1211 {
1212 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1213 }
1214
1215 /**
1216 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1217 operates in encoder mode).
1218 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1219 * @param LPTIMx Low-Power Timer instance
1220 * @retval State of bit (1 or 0).
1221 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1222 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1223 {
1224 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1225 }
1226
1227 /**
1228 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1229 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1230 * @param LPTIMx Low-Power Timer instance
1231 * @retval None
1232 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1233 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1234 {
1235 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1236 }
1237
1238 /**
1239 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1240 operates in encoder mode).
1241 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1242 * @param LPTIMx Low-Power Timer instance
1243 * @retval State of bit (1 or 0).
1244 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1245 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1246 {
1247 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1248 }
1249
1250 /**
1251 * @brief Clear the repetition register update interrupt flag (REPOKCF).
1252 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
1253 * @param LPTIMx Low-Power Timer instance
1254 * @retval None
1255 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)1256 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1257 {
1258 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
1259 }
1260
1261 /**
1262 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
1263 completed; If so, a new one can be initiated.
1264 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
1265 * @param LPTIMx Low-Power Timer instance
1266 * @retval State of bit (1 or 0).
1267 */
LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef * LPTIMx)1268 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
1269 {
1270 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
1271 }
1272
1273 /**
1274 * @brief Clear the update event flag (UECF).
1275 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
1276 * @param LPTIMx Low-Power Timer instance
1277 * @retval None
1278 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)1279 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
1280 {
1281 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
1282 }
1283
1284 /**
1285 * @brief Informs application whether the LPTIMx update event has occurred.
1286 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
1287 * @param LPTIMx Low-Power Timer instance
1288 * @retval State of bit (1 or 0).
1289 */
LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef * LPTIMx)1290 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
1291 {
1292 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
1293 }
1294
1295 /**
1296 * @}
1297 */
1298
1299 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1300 * @{
1301 */
1302
1303 /**
1304 * @brief Enable compare match interrupt (CMPMIE).
1305 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1306 * @param LPTIMx Low-Power Timer instance
1307 * @retval None
1308 */
LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef * LPTIMx)1309 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1310 {
1311 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1312 }
1313
1314 /**
1315 * @brief Disable compare match interrupt (CMPMIE).
1316 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1317 * @param LPTIMx Low-Power Timer instance
1318 * @retval None
1319 */
LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef * LPTIMx)1320 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1321 {
1322 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1323 }
1324
1325 /**
1326 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1327 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1328 * @param LPTIMx Low-Power Timer instance
1329 * @retval State of bit (1 or 0).
1330 */
LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef * LPTIMx)1331 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx)
1332 {
1333 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
1334 }
1335
1336 /**
1337 * @brief Enable autoreload match interrupt (ARRMIE).
1338 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1339 * @param LPTIMx Low-Power Timer instance
1340 * @retval None
1341 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)1342 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1343 {
1344 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1345 }
1346
1347 /**
1348 * @brief Disable autoreload match interrupt (ARRMIE).
1349 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1350 * @param LPTIMx Low-Power Timer instance
1351 * @retval None
1352 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)1353 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1354 {
1355 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1356 }
1357
1358 /**
1359 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1360 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1361 * @param LPTIMx Low-Power Timer instance
1362 * @retval State of bit (1 or 0).
1363 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)1364 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
1365 {
1366 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
1367 }
1368
1369 /**
1370 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1371 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1372 * @param LPTIMx Low-Power Timer instance
1373 * @retval None
1374 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1375 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1376 {
1377 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1378 }
1379
1380 /**
1381 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1382 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1383 * @param LPTIMx Low-Power Timer instance
1384 * @retval None
1385 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1386 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1387 {
1388 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1389 }
1390
1391 /**
1392 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1393 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1394 * @param LPTIMx Low-Power Timer instance
1395 * @retval State of bit (1 or 0).
1396 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1397 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1398 {
1399 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
1400 }
1401
1402 /**
1403 * @brief Enable compare register write completed interrupt (CMPOKIE).
1404 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1405 * @param LPTIMx Low-Power Timer instance
1406 * @retval None
1407 */
LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1408 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1409 {
1410 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1411 }
1412
1413 /**
1414 * @brief Disable compare register write completed interrupt (CMPOKIE).
1415 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1416 * @param LPTIMx Low-Power Timer instance
1417 * @retval None
1418 */
LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1419 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1420 {
1421 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1422 }
1423
1424 /**
1425 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1426 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1427 * @param LPTIMx Low-Power Timer instance
1428 * @retval State of bit (1 or 0).
1429 */
LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef * LPTIMx)1430 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx)
1431 {
1432 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
1433 }
1434
1435 /**
1436 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1437 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1438 * @param LPTIMx Low-Power Timer instance
1439 * @retval None
1440 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)1441 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1442 {
1443 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1444 }
1445
1446 /**
1447 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1448 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1449 * @param LPTIMx Low-Power Timer instance
1450 * @retval None
1451 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)1452 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1453 {
1454 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1455 }
1456
1457 /**
1458 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1459 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1460 * @param LPTIMx Low-Power Timer instance
1461 * @retval State of bit(1 or 0).
1462 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)1463 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
1464 {
1465 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
1466 }
1467
1468 /**
1469 * @brief Enable direction change to up interrupt (UPIE).
1470 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1471 * @param LPTIMx Low-Power Timer instance
1472 * @retval None
1473 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)1474 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1475 {
1476 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1477 }
1478
1479 /**
1480 * @brief Disable direction change to up interrupt (UPIE).
1481 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1482 * @param LPTIMx Low-Power Timer instance
1483 * @retval None
1484 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)1485 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1486 {
1487 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1488 }
1489
1490 /**
1491 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1492 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1493 * @param LPTIMx Low-Power Timer instance
1494 * @retval State of bit(1 or 0).
1495 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)1496 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
1497 {
1498 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
1499 }
1500
1501 /**
1502 * @brief Enable direction change to down interrupt (DOWNIE).
1503 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1504 * @param LPTIMx Low-Power Timer instance
1505 * @retval None
1506 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)1507 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1508 {
1509 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1510 }
1511
1512 /**
1513 * @brief Disable direction change to down interrupt (DOWNIE).
1514 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1515 * @param LPTIMx Low-Power Timer instance
1516 * @retval None
1517 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)1518 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1519 {
1520 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1521 }
1522
1523 /**
1524 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1525 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1526 * @param LPTIMx Low-Power Timer instance
1527 * @retval State of bit(1 or 0).
1528 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)1529 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
1530 {
1531 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
1532 }
1533
1534 /**
1535 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
1536 * @rmtoll IER REPOKIE LL_LPTIM_EnableIT_REPOK
1537 * @param LPTIMx Low-Power Timer instance
1538 * @retval None
1539 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)1540 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
1541 {
1542 SET_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE);
1543 }
1544
1545 /**
1546 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
1547 * @rmtoll IER REPOKIE LL_LPTIM_DisableIT_REPOK
1548 * @param LPTIMx Low-Power Timer instance
1549 * @retval None
1550 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)1551 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
1552 {
1553 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE);
1554 }
1555
1556 /**
1557 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
1558 * @rmtoll IER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
1559 * @param LPTIMx Low-Power Timer instance
1560 * @retval State of bit(1 or 0).
1561 */
LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef * LPTIMx)1562 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
1563 {
1564 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE) == (LPTIM_IER_REPOKIE)) ? 1UL : 0UL);
1565 }
1566
1567 /**
1568 * @brief Enable update event interrupt (UEIE).
1569 * @rmtoll IER UEIE LL_LPTIM_EnableIT_UE
1570 * @param LPTIMx Low-Power Timer instance
1571 * @retval None
1572 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)1573 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
1574 {
1575 SET_BIT(LPTIMx->IER, LPTIM_IER_UEIE);
1576 }
1577
1578 /**
1579 * @brief Disable update event interrupt (UEIE).
1580 * @rmtoll IER UEIE LL_LPTIM_DisableIT_UE
1581 * @param LPTIMx Low-Power Timer instance
1582 * @retval None
1583 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)1584 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
1585 {
1586 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UEIE);
1587 }
1588
1589 /**
1590 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
1591 * @rmtoll IER UEIE LL_LPTIM_IsEnabledIT_UE
1592 * @param LPTIMx Low-Power Timer instance
1593 *@ retval State of bit(1 or 0).
1594 */
LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef * LPTIMx)1595 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
1596 {
1597 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_UEIE) == (LPTIM_IER_UEIE)) ? 1UL : 0UL);
1598 }
1599 /**
1600 * @}
1601 */
1602
1603 /**
1604 * @}
1605 */
1606
1607 /**
1608 * @}
1609 */
1610
1611 #endif /* LPTIM1 || LPTIM2 || LPTIM3 */
1612
1613 /**
1614 * @}
1615 */
1616
1617 #ifdef __cplusplus
1618 }
1619 #endif
1620
1621 #endif /* STM32WLxx_LL_LPTIM_H */
1622
