1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_ADC_H
21 #define STM32L4xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #define ADC_SQR1_REGOFFSET (0x00000000UL)
56 #define ADC_SQR2_REGOFFSET (0x00000100UL)
57 #define ADC_SQR3_REGOFFSET (0x00000200UL)
58 #define ADC_SQR4_REGOFFSET (0x00000300UL)
59
60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
61 | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
63 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
64
65 /* Definition of ADC group regular sequencer bits information to be inserted */
66 /* into ADC group regular sequencer ranks literals definition. */
67 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
68 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
69 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
70 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
71 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
72 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
73 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
74 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
75 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
76 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
77 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
78 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
79 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
80 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
81 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
82 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
83
84
85
86 /* Internal mask for ADC group injected sequencer: */
87 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
88 /* - data register offset */
89 /* - sequencer rank bits position into the selected register */
90
91 /* Internal register offset for ADC group injected data register */
92 /* (offset placed into a spare area of literal definition) */
93 #define ADC_JDR1_REGOFFSET (0x00000000UL)
94 #define ADC_JDR2_REGOFFSET (0x00000100UL)
95 #define ADC_JDR3_REGOFFSET (0x00000200UL)
96 #define ADC_JDR4_REGOFFSET (0x00000300UL)
97
98 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
99 | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
100 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
101 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
102
103 /* Definition of ADC group injected sequencer bits information to be inserted */
104 /* into ADC group injected sequencer ranks literals definition. */
105 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ1" position in register */
106 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ2" position in register */
107 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ3" position in register */
108 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ4" position in register */
109
110
111
112 /* Internal mask for ADC group regular trigger: */
113 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
114 /* - regular trigger source */
115 /* - regular trigger edge */
116 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
117
118 /* Mask containing trigger source masks for each of possible */
119 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
120 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
121 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
122 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
123 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
124 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
125
126 /* Mask containing trigger edge masks for each of possible */
127 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
128 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
129 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
130 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
131 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
132 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
133
134 /* Definition of ADC group regular trigger bits information. */
135 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
136 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
137
138
139
140 /* Internal mask for ADC group injected trigger: */
141 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
142 /* - injected trigger source */
143 /* - injected trigger edge */
144 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
145
146 /* Mask containing trigger source masks for each of possible */
147 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
148 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
149 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
150 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
151 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
152 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
153
154 /* Mask containing trigger edge masks for each of possible */
155 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
156 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
157 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
158 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
159 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
160 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
161
162 /* Definition of ADC group injected trigger bits information. */
163 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
164 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
165
166
167
168
169
170
171 /* Internal mask for ADC channel: */
172 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
173 /* - channel identifier defined by number */
174 /* - channel identifier defined by bitfield */
175 /* - channel differentiation between external channels (connected to */
176 /* GPIO pins) and internal channels (connected to internal paths) */
177 /* - channel sampling time defined by SMPRx register offset */
178 /* and SMPx bits positions into SMPRx register */
179 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
180 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
181 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
182 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
183 | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
184 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
185 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
186
187 /* Channel differentiation between external and internal channels */
188 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
189 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
190 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
191
192 /* Internal register offset for ADC channel sampling time configuration */
193 /* (offset placed into a spare area of literal definition) */
194 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
195 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
196 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
197 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
198
199 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
200 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
201
202 /* Definition of channels ID number information to be inserted into */
203 /* channels literals definition. */
204 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
205 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
206 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
207 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
208 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
209 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
210 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
211 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
212 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
213 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
214 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
215 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
216 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
217 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
218 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
219 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
220 ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
221 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
222 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
223 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
224
225 /* Definition of channels ID bitfield information to be inserted into */
226 /* channels literals definition. */
227 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
228 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
229 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
230 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
231 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
232 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
233 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
234 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
235 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
236 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
237 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
238 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
239 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
240 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
241 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
242 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
243 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
244 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
245 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
246
247 /* Definition of channels sampling time information to be inserted into */
248 /* channels literals definition. */
249 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
250 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
251 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
252 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
253 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
254 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
255 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
256 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
257 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
258 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
259 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
260 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
261 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
262 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
263 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
264 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
265 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
266 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
267 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
268
269
270 /* Internal mask for ADC mode single or differential ended: */
271 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
272 /* the relevant bits for: */
273 /* (concatenation of multiple bits used in different registers) */
274 /* - ADC calibration: calibration start, calibration factor get or set */
275 /* - ADC channels: set each ADC channel ending mode */
276 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
277 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
278 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
279 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
280 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
281 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
282 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
283
284 /* Internal mask for ADC analog watchdog: */
285 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
286 /* (concatenation of multiple bits used in different analog watchdogs, */
287 /* (feature of several watchdogs not available on all STM32 families)). */
288 /* - analog watchdog 1: monitored channel defined by number, */
289 /* selection of ADC group (ADC groups regular and-or injected). */
290 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
291 /* selection on groups. */
292
293 /* Internal register offset for ADC analog watchdog channel configuration */
294 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
295 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
296 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
297
298 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
299 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
300 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
301 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
302
303 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
304
305 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
306 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
307 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
308
309 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
310
311 /* Internal register offset for ADC analog watchdog threshold configuration */
312 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
313 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
314 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
315 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
316 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
317 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
318 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
319 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
320
321 /* Internal mask for ADC offset: */
322 /* Internal register offset for ADC offset number configuration */
323 #define ADC_OFR1_REGOFFSET (0x00000000UL)
324 #define ADC_OFR2_REGOFFSET (0x00000001UL)
325 #define ADC_OFR3_REGOFFSET (0x00000002UL)
326 #define ADC_OFR4_REGOFFSET (0x00000003UL)
327 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
328 | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
329
330
331 /* ADC registers bits positions */
332 #define ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */
333 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */
334 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */
335 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */
336 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
337
338
339 /* ADC registers bits groups */
340 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
341
342
343 /* ADC internal channels related definitions */
344 /* Internal voltage reference VrefInt */
345 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
346 #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
347 /* Temperature sensor */
348 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
349 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
350 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
351 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
352 #define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
353 #else
354 #define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
355 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
356 #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
357
358 /**
359 * @}
360 */
361
362
363 /* Private macros ------------------------------------------------------------*/
364 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
365 * @{
366 */
367
368 /**
369 * @brief Driver macro reserved for internal use: set a pointer to
370 * a register from a register basis from which an offset
371 * is applied.
372 * @param __REG__ Register basis from which the offset is applied.
373 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
374 * @retval Pointer to register address
375 */
376 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
377 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
378
379 /**
380 * @}
381 */
382
383
384 /* Exported types ------------------------------------------------------------*/
385 #if defined(USE_FULL_LL_DRIVER)
386 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
387 * @{
388 */
389
390 /**
391 * @brief Structure definition of some features of ADC common parameters
392 * and multimode
393 * (all ADC instances belonging to the same ADC common instance).
394 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
395 * is conditioned to ADC instances state (all ADC instances
396 * sharing the same ADC common instance):
397 * All ADC instances sharing the same ADC common instance must be
398 * disabled.
399 */
400 typedef struct
401 {
402 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
403 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
404 @note On this STM32 series, if ADC group injected is used, some
405 clock ratio constraints between ADC clock and AHB clock
406 must be respected. Refer to reference manual.
407
408 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
409
410 #if defined(ADC_MULTIMODE_SUPPORT)
411 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
412 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
413
414 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
415
416 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
417 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
418
419 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
420
421 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
422 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
423
424 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
425 #endif /* ADC_MULTIMODE_SUPPORT */
426
427 } LL_ADC_CommonInitTypeDef;
428
429 /**
430 * @brief Structure definition of some features of ADC instance.
431 * @note These parameters have an impact on ADC scope: ADC instance.
432 * Affects both group regular and group injected (availability
433 * of ADC group injected depends on STM32 families).
434 * Refer to corresponding unitary functions into
435 * @ref ADC_LL_EF_Configuration_ADC_Instance .
436 * @note The setting of these parameters by function @ref LL_ADC_Init()
437 * is conditioned to ADC state:
438 * ADC instance must be disabled.
439 * This condition is applied to all ADC features, for efficiency
440 * and compatibility over all STM32 families. However, the different
441 * features can be set under different ADC state conditions
442 * (setting possible with ADC enabled without conversion on going,
443 * ADC enabled with conversion on going, ...)
444 * Each feature can be updated afterwards with a unitary function
445 * and potentially with ADC in a different state than disabled,
446 * refer to description of each function for setting
447 * conditioned to ADC state.
448 */
449 typedef struct
450 {
451 uint32_t Resolution; /*!< Set ADC resolution.
452 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
453
454 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
455
456 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
457 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
458
459 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
460
461 uint32_t LowPowerMode; /*!< Set ADC low power mode.
462 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
463
464 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
465
466 } LL_ADC_InitTypeDef;
467
468 /**
469 * @brief Structure definition of some features of ADC group regular.
470 * @note These parameters have an impact on ADC scope: ADC group regular.
471 * Refer to corresponding unitary functions into
472 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
473 * (functions with prefix "REG").
474 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
475 * is conditioned to ADC state:
476 * ADC instance must be disabled.
477 * This condition is applied to all ADC features, for efficiency
478 * and compatibility over all STM32 families. However, the different
479 * features can be set under different ADC state conditions
480 * (setting possible with ADC enabled without conversion on going,
481 * ADC enabled with conversion on going, ...)
482 * Each feature can be updated afterwards with a unitary function
483 * and potentially with ADC in a different state than disabled,
484 * refer to description of each function for setting
485 * conditioned to ADC state.
486 */
487 typedef struct
488 {
489 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
490 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
491 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
492 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
493 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
494
495 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
496
497 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
498 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
499
500 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
501
502 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
503 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
504 @note This parameter has an effect only if group regular sequencer is enabled
505 (scan length of 2 ranks or more).
506
507 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
508
509 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
510 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
511 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
512
513 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
514
515 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
516 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
517
518 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
519
520 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
521 data preserved or overwritten.
522 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
523
524 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
525
526 } LL_ADC_REG_InitTypeDef;
527
528 /**
529 * @brief Structure definition of some features of ADC group injected.
530 * @note These parameters have an impact on ADC scope: ADC group injected.
531 * Refer to corresponding unitary functions into
532 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
533 * (functions with prefix "INJ").
534 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
535 * is conditioned to ADC state:
536 * ADC instance must be disabled.
537 * This condition is applied to all ADC features, for efficiency
538 * and compatibility over all STM32 families. However, the different
539 * features can be set under different ADC state conditions
540 * (setting possible with ADC enabled without conversion on going,
541 * ADC enabled with conversion on going, ...)
542 * Each feature can be updated afterwards with a unitary function
543 * and potentially with ADC in a different state than disabled,
544 * refer to description of each function for setting
545 * conditioned to ADC state.
546 */
547 typedef struct
548 {
549 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
550 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
551 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
552 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
553 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
554
555 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
556
557 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
558 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
559
560 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
561
562 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
563 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
564 @note This parameter has an effect only if group injected sequencer is enabled
565 (scan length of 2 ranks or more).
566
567 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
568
569 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
570 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
571 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
572
573 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
574
575 } LL_ADC_INJ_InitTypeDef;
576
577 /**
578 * @}
579 */
580 #endif /* USE_FULL_LL_DRIVER */
581
582 /* Exported constants --------------------------------------------------------*/
583 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
584 * @{
585 */
586
587 /** @defgroup ADC_LL_EC_FLAG ADC flags
588 * @brief Flags defines which can be used with LL_ADC_ReadReg function
589 * @{
590 */
591 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
592 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
593 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
594 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
595 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
596 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
597 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
598 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
599 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
600 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
601 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
602 #if defined(ADC_MULTIMODE_SUPPORT)
603 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
604 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
605 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
606 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
607 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
608 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
609 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
610 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
611 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
612 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
613 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
614 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
615 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
616 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
617 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
618 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
619 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
620 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
621 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
622 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
623 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
624 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
625 #endif /* ADC_MULTIMODE_SUPPORT */
626 /**
627 * @}
628 */
629
630 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
631 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
632 * @{
633 */
634 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
635 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
636 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
637 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
638 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
639 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
640 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
641 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
642 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
643 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
644 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
645 /**
646 * @}
647 */
648
649 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
650 * @{
651 */
652 /* List of ADC registers intended to be used (most commonly) with */
653 /* DMA transfer. */
654 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
655 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
656 #if defined(ADC_MULTIMODE_SUPPORT)
657 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
658 #endif /* ADC_MULTIMODE_SUPPORT */
659 /**
660 * @}
661 */
662
663 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
664 * @{
665 */
666 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
667 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
668 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
669 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
670 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */
671 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */
672 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */
673 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */
674 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */
675 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */
676 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */
677 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */
678 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */
679 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */
680 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
681 /**
682 * @}
683 */
684
685 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
686 * @{
687 */
688 /* Note: Other measurement paths to internal channels may be available */
689 /* (connections to other peripherals). */
690 /* If they are not listed below, they do not require any specific */
691 /* path enable. In this case, Access to measurement path is done */
692 /* only by selecting the corresponding ADC internal channel. */
693 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
694 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
695 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
696 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
697 /**
698 * @}
699 */
700
701 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
702 * @{
703 */
704 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
705 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
706 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
707 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
708 /**
709 * @}
710 */
711
712 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
713 * @{
714 */
715 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
716 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
717 /**
718 * @}
719 */
720
721 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
722 * @{
723 */
724 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
725 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
726 /**
727 * @}
728 */
729
730 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
731 * @{
732 */
733 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
734 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
735 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
736 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
737 /**
738 * @}
739 */
740
741 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
742 * @{
743 */
744 #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
745 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
746 /**
747 * @}
748 */
749
750 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
751 * @{
752 */
753 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
754 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
755 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
756 /**
757 * @}
758 */
759
760 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
761 * @{
762 */
763 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
764 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
765 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
766 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
767 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
768 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
769 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
770 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
771 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
772 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
773 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
774 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
775 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
776 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
777 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
778 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
779 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
780 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
781 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
782 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32L4, ADC channel available only on ADC instance: ADC1. */
783 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
784 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
785 #if defined(ADC1) && !defined(ADC2)
786 #define LL_ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
787 #define LL_ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
788 #elif defined(ADC2)
789 #define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
790 #define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
791 #if defined(ADC3)
792 #define LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
793 #define LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
794 #endif /* ADC3 */
795 #endif /* ADC1 && !ADC2 */
796 /**
797 * @}
798 */
799
800 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
801 * @{
802 */
803 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
804 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
805 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
806 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
807 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
808 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
809 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
810 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
811 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
812 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
813 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
814 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
815 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
816 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
817 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
818 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
819 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
820 /**
821 * @}
822 */
823
824 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
825 * @{
826 */
827 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
828 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
829 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
830 /**
831 * @}
832 */
833
834 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
835 * @{
836 */
837 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
838 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
839 /**
840 * @}
841 */
842
843 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
844 * @{
845 */
846 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
847 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
848 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
849 /**
850 * @}
851 */
852
853 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
854 /** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
855 * @{
856 */
857 #define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */
858 #define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
859 /**
860 * @}
861 */
862 #endif /* ADC_CFGR_DFSDMCFG */
863
864 #if defined(ADC_SMPR1_SMPPLUS)
865 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
866 * @{
867 */
868 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */
869 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */
870 /**
871 * @}
872 */
873 #endif
874
875 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
876 * @{
877 */
878 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
879 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
880 /**
881 * @}
882 */
883
884 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
885 * @{
886 */
887 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
888 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
889 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
890 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
891 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
892 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
893 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
894 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
895 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
896 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
897 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
898 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
899 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
900 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
901 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
902 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
903 /**
904 * @}
905 */
906
907 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
908 * @{
909 */
910 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
911 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
912 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
913 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
914 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
915 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
916 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
917 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
918 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
919 /**
920 * @}
921 */
922
923 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
924 * @{
925 */
926 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
927 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
928 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
929 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
930 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
931 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
932 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
933 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
934 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
935 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
936 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
937 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
938 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
939 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
940 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
941 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
942 /**
943 * @}
944 */
945
946 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
947 * @{
948 */
949 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
950 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
951 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
952 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
953 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
954 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
955 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
956 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
957 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
958 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
959 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
960 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
961 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
962 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
963 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
964 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
965 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
966 /**
967 * @}
968 */
969
970 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
971 * @{
972 */
973 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
974 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
975 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
976 /**
977 * @}
978 */
979
980 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
981 * @{
982 */
983 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
984 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
985 /**
986 * @}
987 */
988
989 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
990 * @{
991 */
992 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
993 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
994 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
995 /**
996 * @}
997 */
998
999 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1000 * @{
1001 */
1002 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1003 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1004 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1005 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1006 /**
1007 * @}
1008 */
1009
1010 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1011 * @{
1012 */
1013 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
1014 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1015 /**
1016 * @}
1017 */
1018
1019 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1020 * @{
1021 */
1022 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1023 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1024 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1025 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1026 /**
1027 * @}
1028 */
1029
1030 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1031 * @{
1032 */
1033 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
1034 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
1035 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */
1036 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
1037 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles */
1038 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
1039 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */
1040 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
1041 /**
1042 * @}
1043 */
1044
1045 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1046 * @{
1047 */
1048 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1049 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1050 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1051 /**
1052 * @}
1053 */
1054
1055 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1056 * @{
1057 */
1058 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1059 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1060 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1061 /**
1062 * @}
1063 */
1064
1065 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1066 * @{
1067 */
1068 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
1069 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1070 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1071 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1072 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1073 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1074 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1075 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1076 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1077 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1078 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1079 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1080 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1081 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1082 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1083 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1084 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1085 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1086 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1087 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1088 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1089 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1090 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1091 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1092 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1093 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1094 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1095 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1096 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1097 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1098 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1099 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1100 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1101 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1102 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1103 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1104 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1105 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1106 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1107 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1108 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1109 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1110 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1111 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1112 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1113 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1114 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1115 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1116 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1117 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1118 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1119 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1120 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1121 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1122 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1123 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1124 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1125 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1126 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1127 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1128 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1129 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1130 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1131 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1132 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
1133 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
1134 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
1135 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
1136 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
1137 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
1138 #if defined(ADC1) && !defined(ADC2)
1139 #define LL_ADC_AWD_CH_DAC1CH1_REG ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */
1140 #define LL_ADC_AWD_CH_DAC1CH1_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */
1141 #define LL_ADC_AWD_CH_DAC1CH1_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */
1142 #define LL_ADC_AWD_CH_DAC1CH2_REG ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC1, converted by group regular only */
1143 #define LL_ADC_AWD_CH_DAC1CH2_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC1, converted by group injected only */
1144 #define LL_ADC_AWD_CH_DAC1CH2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC1, converted by either group regular or injected */
1145 #elif defined(ADC2)
1146 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1147 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1148 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1149 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC2, converted by group regular only */
1150 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC2, converted by group injected only */
1151 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC2, converted by either group regular or injected */
1152 #if defined(ADC3)
1153 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
1154 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
1155 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
1156 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC3, converted by group regular only */
1157 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC3, converted by group injected only */
1158 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC3, converted by either group regular or injected */
1159 #endif /* ADC3 */
1160 #endif /* ADC1 && !ADC2 */
1161 /**
1162 * @}
1163 */
1164
1165 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1166 * @{
1167 */
1168 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */
1169 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
1170 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
1171 /**
1172 * @}
1173 */
1174
1175 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1176 * @{
1177 */
1178 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1179 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
1180 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1181 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
1182 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1183 /**
1184 * @}
1185 */
1186
1187 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1188 * @{
1189 */
1190 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
1191 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
1192 /**
1193 * @}
1194 */
1195
1196 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1197 * @{
1198 */
1199 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1200 #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1201 #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1202 #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1203 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1204 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1205 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1206 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1207 /**
1208 * @}
1209 */
1210
1211 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
1212 * @{
1213 */
1214 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
1215 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
1216 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
1217 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
1218 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
1219 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
1220 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
1221 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
1222 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
1223 /**
1224 * @}
1225 */
1226
1227 #if defined(ADC_MULTIMODE_SUPPORT)
1228 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1229 * @{
1230 */
1231 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
1232 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
1233 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
1234 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
1235 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
1236 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
1237 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
1238 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
1239 /**
1240 * @}
1241 */
1242
1243 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1244 * @{
1245 */
1246 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1247 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
1248 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
1249 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
1250 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
1251 /**
1252 * @}
1253 */
1254
1255 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1256 * @{
1257 */
1258 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
1259 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
1260 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
1261 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
1262 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
1263 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
1264 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
1265 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
1266 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
1267 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
1268 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
1269 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
1270 /**
1271 * @}
1272 */
1273
1274 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1275 * @{
1276 */
1277 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1278 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1279 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1280 /**
1281 * @}
1282 */
1283
1284 #endif /* ADC_MULTIMODE_SUPPORT */
1285
1286 /** @defgroup ADC_LL_EC_LEGACY ADC literals legacy naming
1287 * @{
1288 */
1289 #define LL_ADC_REG_TRIG_SW_START (LL_ADC_REG_TRIG_SOFTWARE)
1290 #define LL_ADC_REG_TRIG_EXT_TIM1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
1291 #define LL_ADC_REG_TRIG_EXT_TIM1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
1292 #define LL_ADC_REG_TRIG_EXT_TIM1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
1293 #define LL_ADC_REG_TRIG_EXT_TIM2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
1294 #define LL_ADC_REG_TRIG_EXT_TIM3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
1295 #define LL_ADC_REG_TRIG_EXT_TIM4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
1296
1297 #define LL_ADC_INJ_TRIG_SW_START (LL_ADC_INJ_TRIG_SOFTWARE)
1298 #define LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
1299 #define LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
1300 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
1301 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
1302 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
1303 #define LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
1304
1305 #define LL_ADC_OVS_DATA_SHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
1306 #define LL_ADC_OVS_DATA_SHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
1307 #define LL_ADC_OVS_DATA_SHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
1308 #define LL_ADC_OVS_DATA_SHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
1309 #define LL_ADC_OVS_DATA_SHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
1310 #define LL_ADC_OVS_DATA_SHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
1311 #define LL_ADC_OVS_DATA_SHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
1312 #define LL_ADC_OVS_DATA_SHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
1313 #define LL_ADC_OVS_DATA_SHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
1314
1315 /**
1316 * @}
1317 */
1318
1319
1320 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1321 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1322 * not timeout values.
1323 * For details on delays values, refer to descriptions in source code
1324 * above each literal definition.
1325 * @{
1326 */
1327
1328 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1329 /* not timeout values. */
1330 /* Timeout values for ADC operations are dependent to device clock */
1331 /* configuration (system clock versus ADC clock), */
1332 /* and therefore must be defined in user application. */
1333 /* Indications for estimation of ADC timeout delays, for this */
1334 /* STM32 series: */
1335 /* - ADC calibration time: maximum delay is 112/fADC. */
1336 /* (refer to device datasheet, parameter "tCAL") */
1337 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1338 /* (refer to device datasheet, parameter "tSTAB") */
1339 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1340 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1341 /* cycles */
1342 /* - ADC conversion time: duration depending on ADC clock and ADC */
1343 /* configuration. */
1344 /* (refer to device reference manual, section "Timing") */
1345
1346 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1347 /* Delay set to maximum value (refer to device datasheet, */
1348 /* parameter "tADCVREG_STUP"). */
1349 /* Unit: us */
1350 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1351
1352 /* Delay for internal voltage reference stabilization time. */
1353 /* Delay set to maximum value (refer to device datasheet, */
1354 /* parameter "tstart_vrefint"). */
1355 /* Unit: us */
1356 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
1357
1358 /* Delay for temperature sensor stabilization time. */
1359 /* Literal set to maximum value (refer to device datasheet, */
1360 /* parameter "tSTART"). */
1361 /* Unit: us */
1362 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
1363 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */
1364
1365 /* Delay required between ADC end of calibration and ADC enable. */
1366 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1367 /* are required between ADC end of calibration and ADC enable. */
1368 /* Wait time can be computed in user application by waiting for the */
1369 /* equivalent number of CPU cycles, by taking into account */
1370 /* ratio of CPU clock versus ADC clock prescalers. */
1371 /* Unit: ADC clock cycles. */
1372 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
1373
1374 /**
1375 * @}
1376 */
1377
1378 /**
1379 * @}
1380 */
1381
1382
1383 /* Exported macro ------------------------------------------------------------*/
1384 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1385 * @{
1386 */
1387
1388 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1389 * @{
1390 */
1391
1392 /**
1393 * @brief Write a value in ADC register
1394 * @param __INSTANCE__ ADC Instance
1395 * @param __REG__ Register to be written
1396 * @param __VALUE__ Value to be written in the register
1397 * @retval None
1398 */
1399 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1400
1401 /**
1402 * @brief Read a value in ADC register
1403 * @param __INSTANCE__ ADC Instance
1404 * @param __REG__ Register to be read
1405 * @retval Register value
1406 */
1407 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1408 /**
1409 * @}
1410 */
1411
1412 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1413 * @{
1414 */
1415
1416 /**
1417 * @brief Helper macro to get ADC channel number in decimal format
1418 * from literals LL_ADC_CHANNEL_x.
1419 * @note Example:
1420 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1421 * will return decimal number "4".
1422 * @note The input can be a value from functions where a channel
1423 * number is returned, either defined with number
1424 * or with bitfield (only one bit must be set).
1425 * @param __CHANNEL__ This parameter can be one of the following values:
1426 * @arg @ref LL_ADC_CHANNEL_0
1427 * @arg @ref LL_ADC_CHANNEL_1 (7)
1428 * @arg @ref LL_ADC_CHANNEL_2 (7)
1429 * @arg @ref LL_ADC_CHANNEL_3 (7)
1430 * @arg @ref LL_ADC_CHANNEL_4 (7)
1431 * @arg @ref LL_ADC_CHANNEL_5 (7)
1432 * @arg @ref LL_ADC_CHANNEL_6
1433 * @arg @ref LL_ADC_CHANNEL_7
1434 * @arg @ref LL_ADC_CHANNEL_8
1435 * @arg @ref LL_ADC_CHANNEL_9
1436 * @arg @ref LL_ADC_CHANNEL_10
1437 * @arg @ref LL_ADC_CHANNEL_11
1438 * @arg @ref LL_ADC_CHANNEL_12
1439 * @arg @ref LL_ADC_CHANNEL_13
1440 * @arg @ref LL_ADC_CHANNEL_14
1441 * @arg @ref LL_ADC_CHANNEL_15
1442 * @arg @ref LL_ADC_CHANNEL_16
1443 * @arg @ref LL_ADC_CHANNEL_17
1444 * @arg @ref LL_ADC_CHANNEL_18
1445 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1446 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1447 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1448 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1449 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1450 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1451 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1452 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1453 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1454 *
1455 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1456 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1457 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1458 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1459 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1460 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1461 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1462 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
1463 * @retval Value between Min_Data=0 and Max_Data=18
1464 */
1465 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1466 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
1467 ( \
1468 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1469 ) \
1470 : \
1471 ( \
1472 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1473 ) \
1474 )
1475
1476 /**
1477 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1478 * from number in decimal format.
1479 * @note Example:
1480 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1481 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1482 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1483 * @retval Returned value can be one of the following values:
1484 * @arg @ref LL_ADC_CHANNEL_0
1485 * @arg @ref LL_ADC_CHANNEL_1 (7)
1486 * @arg @ref LL_ADC_CHANNEL_2 (7)
1487 * @arg @ref LL_ADC_CHANNEL_3 (7)
1488 * @arg @ref LL_ADC_CHANNEL_4 (7)
1489 * @arg @ref LL_ADC_CHANNEL_5 (7)
1490 * @arg @ref LL_ADC_CHANNEL_6
1491 * @arg @ref LL_ADC_CHANNEL_7
1492 * @arg @ref LL_ADC_CHANNEL_8
1493 * @arg @ref LL_ADC_CHANNEL_9
1494 * @arg @ref LL_ADC_CHANNEL_10
1495 * @arg @ref LL_ADC_CHANNEL_11
1496 * @arg @ref LL_ADC_CHANNEL_12
1497 * @arg @ref LL_ADC_CHANNEL_13
1498 * @arg @ref LL_ADC_CHANNEL_14
1499 * @arg @ref LL_ADC_CHANNEL_15
1500 * @arg @ref LL_ADC_CHANNEL_16
1501 * @arg @ref LL_ADC_CHANNEL_17
1502 * @arg @ref LL_ADC_CHANNEL_18
1503 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1504 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1505 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1506 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1507 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1508 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1509 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1510 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1511 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1512 *
1513 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1514 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1515 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1516 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1517 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1518 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1519 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1520 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
1521 * (1, 2, 3, 4) For ADC channel read back from ADC register,
1522 * comparison with internal channel parameter to be done
1523 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1524 */
1525 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1526 (((__DECIMAL_NB__) <= 9UL) ? \
1527 ( \
1528 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1529 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1530 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1531 ) \
1532 : \
1533 ( \
1534 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1535 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1536 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1537 ) \
1538 )
1539
1540 /**
1541 * @brief Helper macro to determine whether the selected channel
1542 * corresponds to literal definitions of driver.
1543 * @note The different literal definitions of ADC channels are:
1544 * - ADC internal channel:
1545 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1546 * - ADC external channel (channel connected to a GPIO pin):
1547 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1548 * @note The channel parameter must be a value defined from literal
1549 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1550 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1551 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1552 * must not be a value from functions where a channel number is
1553 * returned from ADC registers,
1554 * because internal and external channels share the same channel
1555 * number in ADC registers. The differentiation is made only with
1556 * parameters definitions of driver.
1557 * @param __CHANNEL__ This parameter can be one of the following values:
1558 * @arg @ref LL_ADC_CHANNEL_0
1559 * @arg @ref LL_ADC_CHANNEL_1 (7)
1560 * @arg @ref LL_ADC_CHANNEL_2 (7)
1561 * @arg @ref LL_ADC_CHANNEL_3 (7)
1562 * @arg @ref LL_ADC_CHANNEL_4 (7)
1563 * @arg @ref LL_ADC_CHANNEL_5 (7)
1564 * @arg @ref LL_ADC_CHANNEL_6
1565 * @arg @ref LL_ADC_CHANNEL_7
1566 * @arg @ref LL_ADC_CHANNEL_8
1567 * @arg @ref LL_ADC_CHANNEL_9
1568 * @arg @ref LL_ADC_CHANNEL_10
1569 * @arg @ref LL_ADC_CHANNEL_11
1570 * @arg @ref LL_ADC_CHANNEL_12
1571 * @arg @ref LL_ADC_CHANNEL_13
1572 * @arg @ref LL_ADC_CHANNEL_14
1573 * @arg @ref LL_ADC_CHANNEL_15
1574 * @arg @ref LL_ADC_CHANNEL_16
1575 * @arg @ref LL_ADC_CHANNEL_17
1576 * @arg @ref LL_ADC_CHANNEL_18
1577 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1578 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1579 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1580 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1581 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1582 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1583 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1584 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1585 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1586 *
1587 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1588 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1589 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1590 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1591 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1592 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1593 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1594 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
1595 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1596 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1597 */
1598 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1599 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1600
1601 /**
1602 * @brief Helper macro to convert a channel defined from parameter
1603 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1604 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1605 * to its equivalent parameter definition of a ADC external channel
1606 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1607 * @note The channel parameter can be, additionally to a value
1608 * defined from parameter definition of a ADC internal channel
1609 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1610 * a value defined from parameter definition of
1611 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1612 * or a value from functions where a channel number is returned
1613 * from ADC registers.
1614 * @param __CHANNEL__ This parameter can be one of the following values:
1615 * @arg @ref LL_ADC_CHANNEL_0
1616 * @arg @ref LL_ADC_CHANNEL_1 (7)
1617 * @arg @ref LL_ADC_CHANNEL_2 (7)
1618 * @arg @ref LL_ADC_CHANNEL_3 (7)
1619 * @arg @ref LL_ADC_CHANNEL_4 (7)
1620 * @arg @ref LL_ADC_CHANNEL_5 (7)
1621 * @arg @ref LL_ADC_CHANNEL_6
1622 * @arg @ref LL_ADC_CHANNEL_7
1623 * @arg @ref LL_ADC_CHANNEL_8
1624 * @arg @ref LL_ADC_CHANNEL_9
1625 * @arg @ref LL_ADC_CHANNEL_10
1626 * @arg @ref LL_ADC_CHANNEL_11
1627 * @arg @ref LL_ADC_CHANNEL_12
1628 * @arg @ref LL_ADC_CHANNEL_13
1629 * @arg @ref LL_ADC_CHANNEL_14
1630 * @arg @ref LL_ADC_CHANNEL_15
1631 * @arg @ref LL_ADC_CHANNEL_16
1632 * @arg @ref LL_ADC_CHANNEL_17
1633 * @arg @ref LL_ADC_CHANNEL_18
1634 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1635 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1636 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1637 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1638 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1639 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1640 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1641 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1642 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1643 *
1644 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1645 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1646 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1647 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1648 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1649 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1650 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1651 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
1652 * @retval Returned value can be one of the following values:
1653 * @arg @ref LL_ADC_CHANNEL_0
1654 * @arg @ref LL_ADC_CHANNEL_1
1655 * @arg @ref LL_ADC_CHANNEL_2
1656 * @arg @ref LL_ADC_CHANNEL_3
1657 * @arg @ref LL_ADC_CHANNEL_4
1658 * @arg @ref LL_ADC_CHANNEL_5
1659 * @arg @ref LL_ADC_CHANNEL_6
1660 * @arg @ref LL_ADC_CHANNEL_7
1661 * @arg @ref LL_ADC_CHANNEL_8
1662 * @arg @ref LL_ADC_CHANNEL_9
1663 * @arg @ref LL_ADC_CHANNEL_10
1664 * @arg @ref LL_ADC_CHANNEL_11
1665 * @arg @ref LL_ADC_CHANNEL_12
1666 * @arg @ref LL_ADC_CHANNEL_13
1667 * @arg @ref LL_ADC_CHANNEL_14
1668 * @arg @ref LL_ADC_CHANNEL_15
1669 * @arg @ref LL_ADC_CHANNEL_16
1670 * @arg @ref LL_ADC_CHANNEL_17
1671 * @arg @ref LL_ADC_CHANNEL_18
1672 */
1673 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1674 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1675
1676 /**
1677 * @brief Helper macro to determine whether the internal channel
1678 * selected is available on the ADC instance selected.
1679 * @note The channel parameter must be a value defined from parameter
1680 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1681 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1682 * must not be a value defined from parameter definition of
1683 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1684 * or a value from functions where a channel number is
1685 * returned from ADC registers,
1686 * because internal and external channels share the same channel
1687 * number in ADC registers. The differentiation is made only with
1688 * parameters definitions of driver.
1689 * @param __ADC_INSTANCE__ ADC instance
1690 * @param __CHANNEL__ This parameter can be one of the following values:
1691 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1692 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1693 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1694 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1695 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1696 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1697 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1698 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1699 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1700 *
1701 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1702 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1703 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1704 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1705 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1706 * (6) On STM32L4, parameter available on devices with several ADC instances.
1707 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1708 * Value "1" if the internal channel selected is available on the ADC instance selected.
1709 */
1710 #if defined (ADC1) && defined (ADC2) && defined (ADC3)
1711 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1712 (((__ADC_INSTANCE__) == ADC1) ? \
1713 ( \
1714 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1715 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1716 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1717 ) \
1718 : \
1719 ((__ADC_INSTANCE__) == ADC2) ? \
1720 ( \
1721 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1722 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1723 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1724 ) \
1725 : \
1726 ((__ADC_INSTANCE__) == ADC3) ? \
1727 ( \
1728 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1729 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1730 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1731 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) || \
1732 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3) \
1733 ) \
1734 : \
1735 (0UL) \
1736 )
1737 #elif defined (ADC1) && defined (ADC2)
1738 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1739 (((__ADC_INSTANCE__) == ADC1) ? \
1740 ( \
1741 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1742 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1743 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1744 ) \
1745 : \
1746 ((__ADC_INSTANCE__) == ADC2) ? \
1747 ( \
1748 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1749 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1750 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1751 ) \
1752 : \
1753 (0UL) \
1754 )
1755 #elif defined (ADC1)
1756 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1757 ( \
1758 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1759 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1760 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1761 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1) || \
1762 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2) \
1763 )
1764 #endif /* defined (ADC1) && defined (ADC2) && defined (ADC3) */
1765
1766 /**
1767 * @brief Helper macro to define ADC analog watchdog parameter:
1768 * define a single channel to monitor with analog watchdog
1769 * from sequencer channel and groups definition.
1770 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1771 * Example:
1772 * LL_ADC_SetAnalogWDMonitChannels(
1773 * ADC1, LL_ADC_AWD1,
1774 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1775 * @param __CHANNEL__ This parameter can be one of the following values:
1776 * @arg @ref LL_ADC_CHANNEL_0
1777 * @arg @ref LL_ADC_CHANNEL_1 (7)
1778 * @arg @ref LL_ADC_CHANNEL_2 (7)
1779 * @arg @ref LL_ADC_CHANNEL_3 (7)
1780 * @arg @ref LL_ADC_CHANNEL_4 (7)
1781 * @arg @ref LL_ADC_CHANNEL_5 (7)
1782 * @arg @ref LL_ADC_CHANNEL_6
1783 * @arg @ref LL_ADC_CHANNEL_7
1784 * @arg @ref LL_ADC_CHANNEL_8
1785 * @arg @ref LL_ADC_CHANNEL_9
1786 * @arg @ref LL_ADC_CHANNEL_10
1787 * @arg @ref LL_ADC_CHANNEL_11
1788 * @arg @ref LL_ADC_CHANNEL_12
1789 * @arg @ref LL_ADC_CHANNEL_13
1790 * @arg @ref LL_ADC_CHANNEL_14
1791 * @arg @ref LL_ADC_CHANNEL_15
1792 * @arg @ref LL_ADC_CHANNEL_16
1793 * @arg @ref LL_ADC_CHANNEL_17
1794 * @arg @ref LL_ADC_CHANNEL_18
1795 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1796 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1797 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1798 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1799 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1800 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1801 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1802 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1803 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1804 *
1805 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1806 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1807 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1808 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1809 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1810 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1811 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1812 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
1813 * (1, 2, 3, 4) For ADC channel read back from ADC register,
1814 * comparison with internal channel parameter to be done
1815 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1816 * @param __GROUP__ This parameter can be one of the following values:
1817 * @arg @ref LL_ADC_GROUP_REGULAR
1818 * @arg @ref LL_ADC_GROUP_INJECTED
1819 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1820 * @retval Returned value can be one of the following values:
1821 * @arg @ref LL_ADC_AWD_DISABLE
1822 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
1823 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
1824 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1825 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
1826 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
1827 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1828 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
1829 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
1830 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1831 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
1832 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
1833 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1834 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
1835 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
1836 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1837 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
1838 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
1839 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1840 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
1841 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
1842 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1843 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
1844 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
1845 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1846 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
1847 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
1848 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1849 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
1850 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
1851 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1852 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
1853 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
1854 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1855 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
1856 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
1857 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1858 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
1859 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
1860 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1861 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
1862 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
1863 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1864 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
1865 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
1866 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1867 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
1868 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
1869 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1870 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
1871 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
1872 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1873 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
1874 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
1875 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1876 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
1877 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
1878 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1879 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
1880 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
1881 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
1882 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
1883 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
1884 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1885 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
1886 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4)
1887 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
1888 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
1889 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
1890 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
1891 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5)
1892 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5)
1893 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5)
1894 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5)
1895 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5)
1896 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5)
1897 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6)
1898 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6)
1899 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6)
1900 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6)
1901 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6)
1902 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6)
1903 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6)
1904 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6)
1905 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6)
1906 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6)
1907 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6)
1908 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6)
1909 *
1910 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
1911 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1912 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1913 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1914 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
1915 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1916 * (6) On STM32L4, parameter available on devices with several ADC instances.
1917 */
1918 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1919 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1920 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
1921 : \
1922 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1923 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
1924 : \
1925 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
1926 )
1927
1928 /**
1929 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1930 * or low in function of ADC resolution, when ADC resolution is
1931 * different of 12 bits.
1932 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1933 * or @ref LL_ADC_SetAnalogWDThresholds().
1934 * Example, with a ADC resolution of 8 bits, to set the value of
1935 * analog watchdog threshold high (on 8 bits):
1936 * LL_ADC_SetAnalogWDThresholds
1937 * (< ADCx param >,
1938 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1939 * );
1940 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1941 * @arg @ref LL_ADC_RESOLUTION_12B
1942 * @arg @ref LL_ADC_RESOLUTION_10B
1943 * @arg @ref LL_ADC_RESOLUTION_8B
1944 * @arg @ref LL_ADC_RESOLUTION_6B
1945 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1946 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1947 */
1948 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1949 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
1950
1951 /**
1952 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1953 * or low in function of ADC resolution, when ADC resolution is
1954 * different of 12 bits.
1955 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1956 * Example, with a ADC resolution of 8 bits, to get the value of
1957 * analog watchdog threshold high (on 8 bits):
1958 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1959 * (LL_ADC_RESOLUTION_8B,
1960 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1961 * );
1962 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1963 * @arg @ref LL_ADC_RESOLUTION_12B
1964 * @arg @ref LL_ADC_RESOLUTION_10B
1965 * @arg @ref LL_ADC_RESOLUTION_8B
1966 * @arg @ref LL_ADC_RESOLUTION_6B
1967 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1968 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1969 */
1970 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1971 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
1972
1973 /**
1974 * @brief Helper macro to get the ADC analog watchdog threshold high
1975 * or low from raw value containing both thresholds concatenated.
1976 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1977 * Example, to get analog watchdog threshold high from the register raw value:
1978 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
1979 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
1980 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
1981 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
1982 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1983 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1984 */
1985 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1986 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
1987
1988 /**
1989 * @brief Helper macro to set the ADC calibration value with both single ended
1990 * and differential modes calibration factors concatenated.
1991 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
1992 * Example, to set calibration factors single ended to 0x55
1993 * and differential ended to 0x2A:
1994 * LL_ADC_SetCalibrationFactor(
1995 * ADC1,
1996 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
1997 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
1998 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
1999 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2000 */
2001 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2002 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2003
2004 #if defined(ADC_MULTIMODE_SUPPORT)
2005 /**
2006 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2007 * or ADC slave from raw value with both ADC conversion data concatenated.
2008 * @note This macro is intended to be used when multimode transfer by DMA
2009 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2010 * In this case the transferred data need to processed with this macro
2011 * to separate the conversion data of ADC master and ADC slave.
2012 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2013 * @arg @ref LL_ADC_MULTI_MASTER
2014 * @arg @ref LL_ADC_MULTI_SLAVE
2015 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2016 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2017 */
2018 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2019 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2020 #endif /* ADC_MULTIMODE_SUPPORT */
2021
2022 #if defined(ADC_MULTIMODE_SUPPORT)
2023 /**
2024 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2025 * it has a dependence in multimode (ADC master of the corresponding
2026 * ADC common instance).
2027 * @note In case of device with multimode available and a mix of
2028 * ADC instances compliant and not compliant with multimode feature,
2029 * ADC instances not compliant with multimode feature are
2030 * considered as master instances (do not depend to
2031 * any other ADC instance).
2032 * @param __ADCx__ ADC instance
2033 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2034 */
2035 #if defined(ADC2)
2036 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2037 ((((__ADCx__) == ADC2))? \
2038 (ADC1) \
2039 : \
2040 (__ADCx__) \
2041 )
2042 #else
2043 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2044 (__ADCx__)
2045 #endif /* ADC2 */
2046 #endif /* ADC_MULTIMODE_SUPPORT */
2047
2048 /**
2049 * @brief Helper macro to select the ADC common instance
2050 * to which is belonging the selected ADC instance.
2051 * @note ADC common register instance can be used for:
2052 * - Set parameters common to several ADC instances
2053 * - Multimode (for devices with several ADC instances)
2054 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2055 * @param __ADCx__ ADC instance
2056 * @retval ADC common register instance
2057 */
2058 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2059 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2060 (ADC123_COMMON)
2061 #elif defined(ADC1) && defined(ADC2)
2062 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2063 (ADC12_COMMON)
2064 #else
2065 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2066 (ADC1_COMMON)
2067 #endif /* defined(ADC1) && defined(ADC2) && defined(ADC3) */
2068
2069 /**
2070 * @brief Helper macro to check if all ADC instances sharing the same
2071 * ADC common instance are disabled.
2072 * @note This check is required by functions with setting conditioned to
2073 * ADC state:
2074 * All ADC instances of the ADC common group must be disabled.
2075 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2076 * @note On devices with only 1 ADC common instance, parameter of this macro
2077 * is useless and can be ignored (parameter kept for compatibility
2078 * with devices featuring several ADC common instances).
2079 * @param __ADCXY_COMMON__ ADC common instance
2080 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2081 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2082 * are disabled.
2083 * Value "1" if at least one ADC instance sharing the same ADC common instance
2084 * is enabled.
2085 */
2086 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2087 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2088 (LL_ADC_IsEnabled(ADC1) | \
2089 LL_ADC_IsEnabled(ADC2) | \
2090 LL_ADC_IsEnabled(ADC3) )
2091 #elif defined(ADC1) && defined(ADC2)
2092 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2093 (LL_ADC_IsEnabled(ADC1) | \
2094 LL_ADC_IsEnabled(ADC2) )
2095 #else
2096 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2097 (LL_ADC_IsEnabled(ADC1))
2098 #endif /* defined(ADC1) && defined(ADC2) && defined(ADC3) */
2099
2100 /**
2101 * @brief Helper macro to define the ADC conversion data full-scale digital
2102 * value corresponding to the selected ADC resolution.
2103 * @note ADC conversion data full-scale corresponds to voltage range
2104 * determined by analog voltage references Vref+ and Vref-
2105 * (refer to reference manual).
2106 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2107 * @arg @ref LL_ADC_RESOLUTION_12B
2108 * @arg @ref LL_ADC_RESOLUTION_10B
2109 * @arg @ref LL_ADC_RESOLUTION_8B
2110 * @arg @ref LL_ADC_RESOLUTION_6B
2111 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2112 */
2113 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2114 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2115
2116 /**
2117 * @brief Helper macro to convert the ADC conversion data from
2118 * a resolution to another resolution.
2119 * @param __DATA__ ADC conversion data to be converted
2120 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2121 * This parameter can be one of the following values:
2122 * @arg @ref LL_ADC_RESOLUTION_12B
2123 * @arg @ref LL_ADC_RESOLUTION_10B
2124 * @arg @ref LL_ADC_RESOLUTION_8B
2125 * @arg @ref LL_ADC_RESOLUTION_6B
2126 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2127 * This parameter can be one of the following values:
2128 * @arg @ref LL_ADC_RESOLUTION_12B
2129 * @arg @ref LL_ADC_RESOLUTION_10B
2130 * @arg @ref LL_ADC_RESOLUTION_8B
2131 * @arg @ref LL_ADC_RESOLUTION_6B
2132 * @retval ADC conversion data to the requested resolution
2133 */
2134 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2135 __ADC_RESOLUTION_CURRENT__,\
2136 __ADC_RESOLUTION_TARGET__) \
2137 (((__DATA__) \
2138 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2139 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2140 )
2141
2142 /**
2143 * @brief Helper macro to calculate the voltage (unit: mVolt)
2144 * corresponding to a ADC conversion data (unit: digital value).
2145 * @note Analog reference voltage (Vref+) must be either known from
2146 * user board environment or can be calculated using ADC measurement
2147 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2148 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2149 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2150 * (unit: digital value).
2151 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2152 * @arg @ref LL_ADC_RESOLUTION_12B
2153 * @arg @ref LL_ADC_RESOLUTION_10B
2154 * @arg @ref LL_ADC_RESOLUTION_8B
2155 * @arg @ref LL_ADC_RESOLUTION_6B
2156 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2157 */
2158 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2159 __ADC_DATA__,\
2160 __ADC_RESOLUTION__) \
2161 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2162 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2163 )
2164
2165 /* Legacy define */
2166 #define __LL_ADC_CALC_DATA_VOLTAGE() __LL_ADC_CALC_DATA_TO_VOLTAGE()
2167
2168 /**
2169 * @brief Helper macro to calculate analog reference voltage (Vref+)
2170 * (unit: mVolt) from ADC conversion data of internal voltage
2171 * reference VrefInt.
2172 * @note Computation is using VrefInt calibration value
2173 * stored in system memory for each device during production.
2174 * @note This voltage depends on user board environment: voltage level
2175 * connected to pin Vref+.
2176 * On devices with small package, the pin Vref+ is not present
2177 * and internally bonded to pin Vdda.
2178 * @note On this STM32 series, calibration data of internal voltage reference
2179 * VrefInt corresponds to a resolution of 12 bits,
2180 * this is the recommended ADC resolution to convert voltage of
2181 * internal voltage reference VrefInt.
2182 * Otherwise, this macro performs the processing to scale
2183 * ADC conversion data to 12 bits.
2184 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
2185 * of internal voltage reference VrefInt (unit: digital value).
2186 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2187 * @arg @ref LL_ADC_RESOLUTION_12B
2188 * @arg @ref LL_ADC_RESOLUTION_10B
2189 * @arg @ref LL_ADC_RESOLUTION_8B
2190 * @arg @ref LL_ADC_RESOLUTION_6B
2191 * @retval Analog reference voltage (unit: mV)
2192 */
2193 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2194 __ADC_RESOLUTION__) \
2195 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2196 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2197 (__ADC_RESOLUTION__), \
2198 LL_ADC_RESOLUTION_12B) \
2199 )
2200
2201 /**
2202 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2203 * from ADC conversion data of internal temperature sensor.
2204 * @note Computation is using temperature sensor calibration values
2205 * stored in system memory for each device during production.
2206 * @note Calculation formula:
2207 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2208 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2209 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2210 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2211 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2212 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2213 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2214 * TEMP_DEGC_CAL1 (calibrated in factory)
2215 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2216 * TEMP_DEGC_CAL2 (calibrated in factory)
2217 * Caution: Calculation relevancy under reserve that calibration
2218 * parameters are correct (address and data).
2219 * To calculate temperature using temperature sensor
2220 * datasheet typical values (generic values less, therefore
2221 * less accurate than calibrated values),
2222 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2223 * @note As calculation input, the analog reference voltage (Vref+) must be
2224 * defined as it impacts the ADC LSB equivalent voltage.
2225 * @note Analog reference voltage (Vref+) must be either known from
2226 * user board environment or can be calculated using ADC measurement
2227 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2228 * @note On this STM32 series, calibration data of temperature sensor
2229 * corresponds to a resolution of 12 bits,
2230 * this is the recommended ADC resolution to convert voltage of
2231 * temperature sensor.
2232 * Otherwise, this macro performs the processing to scale
2233 * ADC conversion data to 12 bits.
2234 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2235 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2236 * temperature sensor (unit: digital value).
2237 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2238 * sensor voltage has been measured.
2239 * This parameter can be one of the following values:
2240 * @arg @ref LL_ADC_RESOLUTION_12B
2241 * @arg @ref LL_ADC_RESOLUTION_10B
2242 * @arg @ref LL_ADC_RESOLUTION_8B
2243 * @arg @ref LL_ADC_RESOLUTION_6B
2244 * @retval Temperature (unit: degree Celsius)
2245 */
2246 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2247 __TEMPSENSOR_ADC_DATA__,\
2248 __ADC_RESOLUTION__) \
2249 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2250 (__ADC_RESOLUTION__), \
2251 LL_ADC_RESOLUTION_12B) \
2252 * (__VREFANALOG_VOLTAGE__)) \
2253 / TEMPSENSOR_CAL_VREFANALOG) \
2254 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2255 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2256 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2257 ) + TEMPSENSOR_CAL1_TEMP \
2258 )
2259
2260 /**
2261 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2262 * from ADC conversion data of internal temperature sensor.
2263 * @note Computation is using temperature sensor typical values
2264 * (refer to device datasheet).
2265 * @note Calculation formula:
2266 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2267 * / Avg_Slope + CALx_TEMP
2268 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2269 * (unit: digital value)
2270 * Avg_Slope = temperature sensor slope
2271 * (unit: uV/Degree Celsius)
2272 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2273 * temperature CALx_TEMP (unit: mV)
2274 * Caution: Calculation relevancy under reserve the temperature sensor
2275 * of the current device has characteristics in line with
2276 * datasheet typical values.
2277 * If temperature sensor calibration values are available on
2278 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2279 * temperature calculation will be more accurate using
2280 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2281 * @note As calculation input, the analog reference voltage (Vref+) must be
2282 * defined as it impacts the ADC LSB equivalent voltage.
2283 * @note Analog reference voltage (Vref+) must be either known from
2284 * user board environment or can be calculated using ADC measurement
2285 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2286 * @note ADC measurement data must correspond to a resolution of 12 bits
2287 * (full scale digital value 4095). If not the case, the data must be
2288 * preliminarily rescaled to an equivalent resolution of 12 bits.
2289 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
2290 * On STM32L4, refer to device datasheet parameter "Avg_Slope".
2291 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
2292 * On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
2293 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
2294 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2295 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2296 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2297 * This parameter can be one of the following values:
2298 * @arg @ref LL_ADC_RESOLUTION_12B
2299 * @arg @ref LL_ADC_RESOLUTION_10B
2300 * @arg @ref LL_ADC_RESOLUTION_8B
2301 * @arg @ref LL_ADC_RESOLUTION_6B
2302 * @retval Temperature (unit: degree Celsius)
2303 */
2304 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2305 __TEMPSENSOR_TYP_CALX_V__,\
2306 __TEMPSENSOR_CALX_TEMP__,\
2307 __VREFANALOG_VOLTAGE__,\
2308 __TEMPSENSOR_ADC_DATA__,\
2309 __ADC_RESOLUTION__) \
2310 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2311 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2312 * 1000UL) \
2313 - \
2314 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2315 * 1000UL) \
2316 ) \
2317 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2318 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2319 )
2320
2321 /**
2322 * @}
2323 */
2324
2325 /**
2326 * @}
2327 */
2328
2329
2330 /* Exported functions --------------------------------------------------------*/
2331 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2332 * @{
2333 */
2334
2335 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2336 * @{
2337 */
2338 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2339 /* configuration of ADC instance, groups and multimode (if available): */
2340 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2341
2342 /**
2343 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2344 * ADC register address from ADC instance and a list of ADC registers
2345 * intended to be used (most commonly) with DMA transfer.
2346 * @note These ADC registers are data registers:
2347 * when ADC conversion data is available in ADC data registers,
2348 * ADC generates a DMA transfer request.
2349 * @note This macro is intended to be used with LL DMA driver, refer to
2350 * function "LL_DMA_ConfigAddresses()".
2351 * Example:
2352 * LL_DMA_ConfigAddresses(DMA1,
2353 * LL_DMA_CHANNEL_1,
2354 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2355 * (uint32_t)&< array or variable >,
2356 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2357 * @note For devices with several ADC: in multimode, some devices
2358 * use a different data register outside of ADC instance scope
2359 * (common data register). This macro manages this register difference,
2360 * only ADC instance has to be set as parameter.
2361 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2362 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2363 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2364 * @param ADCx ADC instance
2365 * @param Register This parameter can be one of the following values:
2366 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2367 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2368 *
2369 * (1) Available on devices with several ADC instances.
2370 * @retval ADC register address
2371 */
2372 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)2373 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2374 {
2375 uint32_t data_reg_addr;
2376
2377 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2378 {
2379 /* Retrieve address of register DR */
2380 data_reg_addr = (uint32_t) &(ADCx->DR);
2381 }
2382 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2383 {
2384 /* Retrieve address of register CDR */
2385 data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2386 }
2387
2388 return data_reg_addr;
2389 }
2390 #else
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)2391 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2392 {
2393 /* Prevent unused argument(s) compilation warning */
2394 (void)(Register);
2395
2396 /* Retrieve address of register DR */
2397 return (uint32_t) &(ADCx->DR);
2398 }
2399 #endif /* ADC_MULTIMODE_SUPPORT */
2400
2401 /**
2402 * @}
2403 */
2404
2405 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
2406 * @{
2407 */
2408
2409 /**
2410 * @brief Set parameter common to several ADC: Clock source and prescaler.
2411 * @note On this STM32 series, if ADC group injected is used, some
2412 * clock ratio constraints between ADC clock and AHB clock
2413 * must be respected.
2414 * Refer to reference manual.
2415 * @note On this STM32 series, setting of this feature is conditioned to
2416 * ADC state:
2417 * All ADC instances of the ADC common group must be disabled.
2418 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2419 * ADC instance or by using helper macro helper macro
2420 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2421 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
2422 * CCR PRESC LL_ADC_SetCommonClock
2423 * @param ADCxy_COMMON ADC common instance
2424 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2425 * @param CommonClock This parameter can be one of the following values:
2426 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2427 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2428 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2429 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2430 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2431 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2432 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2433 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2434 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2435 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2436 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2437 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2438 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2439 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2440 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2441 * @retval None
2442 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)2443 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2444 {
2445 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2446 }
2447
2448 /**
2449 * @brief Get parameter common to several ADC: Clock source and prescaler.
2450 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
2451 * CCR PRESC LL_ADC_GetCommonClock
2452 * @param ADCxy_COMMON ADC common instance
2453 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2454 * @retval Returned value can be one of the following values:
2455 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2456 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2457 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2458 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2459 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2460 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2461 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2462 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2463 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2464 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2465 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2466 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2467 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2468 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2469 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2470 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)2471 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2472 {
2473 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2474 }
2475
2476 /**
2477 * @brief Set parameter common to several ADC: measurement path to
2478 * internal channels (VrefInt, temperature sensor, ...).
2479 * Configure all paths (overwrite current configuration).
2480 * @note One or several values can be selected.
2481 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2482 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2483 * The values not selected are removed from configuration.
2484 * @note Stabilization time of measurement path to internal channel:
2485 * After enabling internal paths, before starting ADC conversion,
2486 * a delay is required for internal voltage reference and
2487 * temperature sensor stabilization time.
2488 * Refer to device datasheet.
2489 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2490 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
2491 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
2492 * @note ADC internal channel sampling time constraint:
2493 * For ADC conversion of internal channels,
2494 * a sampling time minimum value is required.
2495 * Refer to device datasheet.
2496 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2497 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
2498 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2499 * @param ADCxy_COMMON ADC common instance
2500 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2501 * @param PathInternal This parameter can be a combination of the following values:
2502 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2503 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2504 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2505 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2506 * @retval None
2507 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2508 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2509 {
2510 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
2511 }
2512
2513 /**
2514 * @brief Set parameter common to several ADC: measurement path to
2515 * internal channels (VrefInt, temperature sensor, ...).
2516 * Add paths to the current configuration.
2517 * @note One or several values can be selected.
2518 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2519 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2520 * @note Stabilization time of measurement path to internal channel:
2521 * After enabling internal paths, before starting ADC conversion,
2522 * a delay is required for internal voltage reference and
2523 * temperature sensor stabilization time.
2524 * Refer to device datasheet.
2525 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2526 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
2527 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
2528 * @note ADC internal channel sampling time constraint:
2529 * For ADC conversion of internal channels,
2530 * a sampling time minimum value is required.
2531 * Refer to device datasheet.
2532 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
2533 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
2534 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
2535 * @param ADCxy_COMMON ADC common instance
2536 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2537 * @param PathInternal This parameter can be a combination of the following values:
2538 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2539 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2540 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2541 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2542 * @retval None
2543 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2544 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2545 {
2546 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
2547 }
2548
2549 /**
2550 * @brief Set parameter common to several ADC: measurement path to
2551 * internal channels (VrefInt, temperature sensor, ...).
2552 * Remove paths to the current configuration.
2553 * @note One or several values can be selected.
2554 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2555 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2556 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
2557 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
2558 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
2559 * @param ADCxy_COMMON ADC common instance
2560 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2561 * @param PathInternal This parameter can be a combination of the following values:
2562 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2563 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2564 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2565 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2566 * @retval None
2567 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2568 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2569 {
2570 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2571 }
2572
2573 /**
2574 * @brief Get parameter common to several ADC: measurement path to internal
2575 * channels (VrefInt, temperature sensor, ...).
2576 * @note One or several values can be selected.
2577 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2578 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2579 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2580 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
2581 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2582 * @param ADCxy_COMMON ADC common instance
2583 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2584 * @retval Returned value can be a combination of the following values:
2585 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2586 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2587 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2588 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2589 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)2590 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2591 {
2592 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2593 }
2594
2595 /**
2596 * @}
2597 */
2598
2599 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2600 * @{
2601 */
2602
2603 /**
2604 * @brief Set ADC calibration factor in the mode single-ended
2605 * or differential (for devices with differential mode available).
2606 * @note This function is intended to set calibration parameters
2607 * without having to perform a new calibration using
2608 * @ref LL_ADC_StartCalibration().
2609 * @note For devices with differential mode available:
2610 * Calibration of offset is specific to each of
2611 * single-ended and differential modes
2612 * (calibration factor must be specified for each of these
2613 * differential modes, if used afterwards and if the application
2614 * requires their calibration).
2615 * @note In case of setting calibration factors of both modes single ended
2616 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
2617 * both calibration factors must be concatenated.
2618 * To perform this processing, use helper macro
2619 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
2620 * @note On this STM32 series, setting of this feature is conditioned to
2621 * ADC state:
2622 * ADC must be enabled, without calibration on going, without conversion
2623 * on going on group regular.
2624 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
2625 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
2626 * @param ADCx ADC instance
2627 * @param SingleDiff This parameter can be one of the following values:
2628 * @arg @ref LL_ADC_SINGLE_ENDED
2629 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2630 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
2631 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2632 * @retval None
2633 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)2634 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2635 {
2636 MODIFY_REG(ADCx->CALFACT,
2637 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2638 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2639 }
2640
2641 /**
2642 * @brief Get ADC calibration factor in the mode single-ended
2643 * or differential (for devices with differential mode available).
2644 * @note Calibration factors are set by hardware after performing
2645 * a calibration run using function @ref LL_ADC_StartCalibration().
2646 * @note For devices with differential mode available:
2647 * Calibration of offset is specific to each of
2648 * single-ended and differential modes
2649 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
2650 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
2651 * @param ADCx ADC instance
2652 * @param SingleDiff This parameter can be one of the following values:
2653 * @arg @ref LL_ADC_SINGLE_ENDED
2654 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2655 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2656 */
LL_ADC_GetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff)2657 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
2658 {
2659 /* Retrieve bits with position in register depending on parameter */
2660 /* "SingleDiff". */
2661 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2662 /* containing other bits reserved for other purpose. */
2663 return (uint32_t)(READ_BIT(ADCx->CALFACT,
2664 (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
2665 ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2666 }
2667
2668 /**
2669 * @brief Set ADC resolution.
2670 * Refer to reference manual for alignments formats
2671 * dependencies to ADC resolutions.
2672 * @note On this STM32 series, setting of this feature is conditioned to
2673 * ADC state:
2674 * ADC must be disabled or enabled without conversion on going
2675 * on either groups regular or injected.
2676 * @rmtoll CFGR RES LL_ADC_SetResolution
2677 * @param ADCx ADC instance
2678 * @param Resolution This parameter can be one of the following values:
2679 * @arg @ref LL_ADC_RESOLUTION_12B
2680 * @arg @ref LL_ADC_RESOLUTION_10B
2681 * @arg @ref LL_ADC_RESOLUTION_8B
2682 * @arg @ref LL_ADC_RESOLUTION_6B
2683 * @retval None
2684 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2685 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2686 {
2687 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2688 }
2689
2690 /**
2691 * @brief Get ADC resolution.
2692 * Refer to reference manual for alignments formats
2693 * dependencies to ADC resolutions.
2694 * @rmtoll CFGR RES LL_ADC_GetResolution
2695 * @param ADCx ADC instance
2696 * @retval Returned value can be one of the following values:
2697 * @arg @ref LL_ADC_RESOLUTION_12B
2698 * @arg @ref LL_ADC_RESOLUTION_10B
2699 * @arg @ref LL_ADC_RESOLUTION_8B
2700 * @arg @ref LL_ADC_RESOLUTION_6B
2701 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)2702 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2703 {
2704 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
2705 }
2706
2707 /**
2708 * @brief Set ADC conversion data alignment.
2709 * @note Refer to reference manual for alignments formats
2710 * dependencies to ADC resolutions.
2711 * @note On this STM32 series, setting of this feature is conditioned to
2712 * ADC state:
2713 * ADC must be disabled or enabled without conversion on going
2714 * on either groups regular or injected.
2715 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
2716 * @param ADCx ADC instance
2717 * @param DataAlignment This parameter can be one of the following values:
2718 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2719 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2720 * @retval None
2721 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2722 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2723 {
2724 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
2725 }
2726
2727 /**
2728 * @brief Get ADC conversion data alignment.
2729 * @note Refer to reference manual for alignments formats
2730 * dependencies to ADC resolutions.
2731 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
2732 * @param ADCx ADC instance
2733 * @retval Returned value can be one of the following values:
2734 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2735 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2736 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)2737 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2738 {
2739 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
2740 }
2741
2742 /**
2743 * @brief Set ADC low power mode.
2744 * @note Description of ADC low power modes:
2745 * - ADC low power mode "auto wait": Dynamic low power mode,
2746 * ADC conversions occurrences are limited to the minimum necessary
2747 * in order to reduce power consumption.
2748 * New ADC conversion starts only when the previous
2749 * unitary conversion data (for ADC group regular)
2750 * or previous sequence conversions data (for ADC group injected)
2751 * has been retrieved by user software.
2752 * In the meantime, ADC remains idle: does not performs any
2753 * other conversion.
2754 * This mode allows to automatically adapt the ADC conversions
2755 * triggers to the speed of the software that reads the data.
2756 * Moreover, this avoids risk of overrun for low frequency
2757 * applications.
2758 * How to use this low power mode:
2759 * - It is not recommended to use with interruption or DMA
2760 * since these modes have to clear immediately the EOC flag
2761 * (by CPU to free the IRQ pending event or by DMA).
2762 * Auto wait will work but fort a very short time, discarding
2763 * its intended benefit (except specific case of high load of CPU
2764 * or DMA transfers which can justify usage of auto wait).
2765 * - Do use with polling: 1. Start conversion,
2766 * 2. Later on, when conversion data is needed: poll for end of
2767 * conversion to ensure that conversion is completed and
2768 * retrieve ADC conversion data. This will trig another
2769 * ADC conversion start.
2770 * - ADC low power mode "auto power-off" (feature available on
2771 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2772 * the ADC automatically powers-off after a conversion and
2773 * automatically wakes up when a new conversion is triggered
2774 * (with startup time between trigger and start of sampling).
2775 * This feature can be combined with low power mode "auto wait".
2776 * @note With ADC low power mode "auto wait", the ADC conversion data read
2777 * is corresponding to previous ADC conversion start, independently
2778 * of delay during which ADC was idle.
2779 * Therefore, the ADC conversion data may be outdated: does not
2780 * correspond to the current voltage level on the selected
2781 * ADC channel.
2782 * @note On this STM32 series, setting of this feature is conditioned to
2783 * ADC state:
2784 * ADC must be disabled or enabled without conversion on going
2785 * on either groups regular or injected.
2786 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
2787 * @param ADCx ADC instance
2788 * @param LowPowerMode This parameter can be one of the following values:
2789 * @arg @ref LL_ADC_LP_MODE_NONE
2790 * @arg @ref LL_ADC_LP_AUTOWAIT
2791 * @retval None
2792 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2793 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2794 {
2795 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
2796 }
2797
2798 /**
2799 * @brief Get ADC low power mode:
2800 * @note Description of ADC low power modes:
2801 * - ADC low power mode "auto wait": Dynamic low power mode,
2802 * ADC conversions occurrences are limited to the minimum necessary
2803 * in order to reduce power consumption.
2804 * New ADC conversion starts only when the previous
2805 * unitary conversion data (for ADC group regular)
2806 * or previous sequence conversions data (for ADC group injected)
2807 * has been retrieved by user software.
2808 * In the meantime, ADC remains idle: does not performs any
2809 * other conversion.
2810 * This mode allows to automatically adapt the ADC conversions
2811 * triggers to the speed of the software that reads the data.
2812 * Moreover, this avoids risk of overrun for low frequency
2813 * applications.
2814 * How to use this low power mode:
2815 * - It is not recommended to use with interruption or DMA
2816 * since these modes have to clear immediately the EOC flag
2817 * (by CPU to free the IRQ pending event or by DMA).
2818 * Auto wait will work but fort a very short time, discarding
2819 * its intended benefit (except specific case of high load of CPU
2820 * or DMA transfers which can justify usage of auto wait).
2821 * - Do use with polling: 1. Start conversion,
2822 * 2. Later on, when conversion data is needed: poll for end of
2823 * conversion to ensure that conversion is completed and
2824 * retrieve ADC conversion data. This will trig another
2825 * ADC conversion start.
2826 * - ADC low power mode "auto power-off" (feature available on
2827 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2828 * the ADC automatically powers-off after a conversion and
2829 * automatically wakes up when a new conversion is triggered
2830 * (with startup time between trigger and start of sampling).
2831 * This feature can be combined with low power mode "auto wait".
2832 * @note With ADC low power mode "auto wait", the ADC conversion data read
2833 * is corresponding to previous ADC conversion start, independently
2834 * of delay during which ADC was idle.
2835 * Therefore, the ADC conversion data may be outdated: does not
2836 * correspond to the current voltage level on the selected
2837 * ADC channel.
2838 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
2839 * @param ADCx ADC instance
2840 * @retval Returned value can be one of the following values:
2841 * @arg @ref LL_ADC_LP_MODE_NONE
2842 * @arg @ref LL_ADC_LP_AUTOWAIT
2843 */
LL_ADC_GetLowPowerMode(ADC_TypeDef * ADCx)2844 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
2845 {
2846 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
2847 }
2848
2849 /**
2850 * @brief Set ADC selected offset number 1, 2, 3 or 4.
2851 * @note This function set the 2 items of offset configuration:
2852 * - ADC channel to which the offset programmed will be applied
2853 * (independently of channel mapped on ADC group regular
2854 * or group injected)
2855 * - Offset level (offset to be subtracted from the raw
2856 * converted data).
2857 * @note Caution: Offset format is dependent to ADC resolution:
2858 * offset has to be left-aligned on bit 11, the LSB (right bits)
2859 * are set to 0.
2860 * @note This function enables the offset, by default. It can be forced
2861 * to disable state using function LL_ADC_SetOffsetState().
2862 * @note If a channel is mapped on several offsets numbers, only the offset
2863 * with the lowest value is considered for the subtraction.
2864 * @note On this STM32 series, setting of this feature is conditioned to
2865 * ADC state:
2866 * ADC must be disabled or enabled without conversion on going
2867 * on either groups regular or injected.
2868 * @note On STM32L4, some fast channels are available: fast analog inputs
2869 * coming from GPIO pads (ADC_IN1..5).
2870 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
2871 * OFR1 OFFSET1 LL_ADC_SetOffset\n
2872 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
2873 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
2874 * OFR2 OFFSET2 LL_ADC_SetOffset\n
2875 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
2876 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
2877 * OFR3 OFFSET3 LL_ADC_SetOffset\n
2878 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
2879 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
2880 * OFR4 OFFSET4 LL_ADC_SetOffset\n
2881 * OFR4 OFFSET4_EN LL_ADC_SetOffset
2882 * @param ADCx ADC instance
2883 * @param Offsety This parameter can be one of the following values:
2884 * @arg @ref LL_ADC_OFFSET_1
2885 * @arg @ref LL_ADC_OFFSET_2
2886 * @arg @ref LL_ADC_OFFSET_3
2887 * @arg @ref LL_ADC_OFFSET_4
2888 * @param Channel This parameter can be one of the following values:
2889 * @arg @ref LL_ADC_CHANNEL_0
2890 * @arg @ref LL_ADC_CHANNEL_1 (7)
2891 * @arg @ref LL_ADC_CHANNEL_2 (7)
2892 * @arg @ref LL_ADC_CHANNEL_3 (7)
2893 * @arg @ref LL_ADC_CHANNEL_4 (7)
2894 * @arg @ref LL_ADC_CHANNEL_5 (7)
2895 * @arg @ref LL_ADC_CHANNEL_6
2896 * @arg @ref LL_ADC_CHANNEL_7
2897 * @arg @ref LL_ADC_CHANNEL_8
2898 * @arg @ref LL_ADC_CHANNEL_9
2899 * @arg @ref LL_ADC_CHANNEL_10
2900 * @arg @ref LL_ADC_CHANNEL_11
2901 * @arg @ref LL_ADC_CHANNEL_12
2902 * @arg @ref LL_ADC_CHANNEL_13
2903 * @arg @ref LL_ADC_CHANNEL_14
2904 * @arg @ref LL_ADC_CHANNEL_15
2905 * @arg @ref LL_ADC_CHANNEL_16
2906 * @arg @ref LL_ADC_CHANNEL_17
2907 * @arg @ref LL_ADC_CHANNEL_18
2908 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2909 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2910 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2911 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
2912 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
2913 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2914 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2915 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
2916 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
2917 *
2918 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2919 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2920 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2921 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
2922 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
2923 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
2924 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2925 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
2926 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
2927 * @retval None
2928 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)2929 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
2930 {
2931 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2932
2933 MODIFY_REG(*preg,
2934 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
2935 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
2936 }
2937
2938 /**
2939 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
2940 * Channel to which the offset programmed will be applied
2941 * (independently of channel mapped on ADC group regular
2942 * or group injected)
2943 * @note Usage of the returned channel number:
2944 * - To reinject this channel into another function LL_ADC_xxx:
2945 * the returned channel number is only partly formatted on definition
2946 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2947 * with parts of literals LL_ADC_CHANNEL_x or using
2948 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2949 * Then the selected literal LL_ADC_CHANNEL_x can be used
2950 * as parameter for another function.
2951 * - To get the channel number in decimal format:
2952 * process the returned value with the helper macro
2953 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2954 * @note On STM32L4, some fast channels are available: fast analog inputs
2955 * coming from GPIO pads (ADC_IN1..5).
2956 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
2957 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
2958 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
2959 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
2960 * @param ADCx ADC instance
2961 * @param Offsety This parameter can be one of the following values:
2962 * @arg @ref LL_ADC_OFFSET_1
2963 * @arg @ref LL_ADC_OFFSET_2
2964 * @arg @ref LL_ADC_OFFSET_3
2965 * @arg @ref LL_ADC_OFFSET_4
2966 * @retval Returned value can be one of the following values:
2967 * @arg @ref LL_ADC_CHANNEL_0
2968 * @arg @ref LL_ADC_CHANNEL_1 (7)
2969 * @arg @ref LL_ADC_CHANNEL_2 (7)
2970 * @arg @ref LL_ADC_CHANNEL_3 (7)
2971 * @arg @ref LL_ADC_CHANNEL_4 (7)
2972 * @arg @ref LL_ADC_CHANNEL_5 (7)
2973 * @arg @ref LL_ADC_CHANNEL_6
2974 * @arg @ref LL_ADC_CHANNEL_7
2975 * @arg @ref LL_ADC_CHANNEL_8
2976 * @arg @ref LL_ADC_CHANNEL_9
2977 * @arg @ref LL_ADC_CHANNEL_10
2978 * @arg @ref LL_ADC_CHANNEL_11
2979 * @arg @ref LL_ADC_CHANNEL_12
2980 * @arg @ref LL_ADC_CHANNEL_13
2981 * @arg @ref LL_ADC_CHANNEL_14
2982 * @arg @ref LL_ADC_CHANNEL_15
2983 * @arg @ref LL_ADC_CHANNEL_16
2984 * @arg @ref LL_ADC_CHANNEL_17
2985 * @arg @ref LL_ADC_CHANNEL_18
2986 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2987 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2988 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2989 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
2990 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
2991 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2992 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2993 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
2994 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
2995 *
2996 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2997 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2998 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2999 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
3000 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
3001 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
3002 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3003 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
3004 * (1, 2, 3, 4) For ADC channel read back from ADC register,
3005 * comparison with internal channel parameter to be done
3006 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3007 */
LL_ADC_GetOffsetChannel(ADC_TypeDef * ADCx,uint32_t Offsety)3008 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
3009 {
3010 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3011
3012 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3013 }
3014
3015 /**
3016 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3017 * Offset level (offset to be subtracted from the raw
3018 * converted data).
3019 * @note Caution: Offset format is dependent to ADC resolution:
3020 * offset has to be left-aligned on bit 11, the LSB (right bits)
3021 * are set to 0.
3022 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3023 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3024 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3025 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3026 * @param ADCx ADC instance
3027 * @param Offsety This parameter can be one of the following values:
3028 * @arg @ref LL_ADC_OFFSET_1
3029 * @arg @ref LL_ADC_OFFSET_2
3030 * @arg @ref LL_ADC_OFFSET_3
3031 * @arg @ref LL_ADC_OFFSET_4
3032 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3033 */
LL_ADC_GetOffsetLevel(ADC_TypeDef * ADCx,uint32_t Offsety)3034 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
3035 {
3036 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3037
3038 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3039 }
3040
3041 /**
3042 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3043 * force offset state disable or enable
3044 * without modifying offset channel or offset value.
3045 * @note This function should be needed only in case of offset to be
3046 * enabled-disabled dynamically, and should not be needed in other cases:
3047 * function LL_ADC_SetOffset() automatically enables the offset.
3048 * @note On this STM32 series, setting of this feature is conditioned to
3049 * ADC state:
3050 * ADC must be disabled or enabled without conversion on going
3051 * on either groups regular or injected.
3052 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3053 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3054 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3055 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3056 * @param ADCx ADC instance
3057 * @param Offsety This parameter can be one of the following values:
3058 * @arg @ref LL_ADC_OFFSET_1
3059 * @arg @ref LL_ADC_OFFSET_2
3060 * @arg @ref LL_ADC_OFFSET_3
3061 * @arg @ref LL_ADC_OFFSET_4
3062 * @param OffsetState This parameter can be one of the following values:
3063 * @arg @ref LL_ADC_OFFSET_DISABLE
3064 * @arg @ref LL_ADC_OFFSET_ENABLE
3065 * @retval None
3066 */
LL_ADC_SetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetState)3067 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3068 {
3069 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3070
3071 MODIFY_REG(*preg,
3072 ADC_OFR1_OFFSET1_EN,
3073 OffsetState);
3074 }
3075
3076 /**
3077 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3078 * offset state disabled or enabled.
3079 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3080 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3081 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3082 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3083 * @param ADCx ADC instance
3084 * @param Offsety This parameter can be one of the following values:
3085 * @arg @ref LL_ADC_OFFSET_1
3086 * @arg @ref LL_ADC_OFFSET_2
3087 * @arg @ref LL_ADC_OFFSET_3
3088 * @arg @ref LL_ADC_OFFSET_4
3089 * @retval Returned value can be one of the following values:
3090 * @arg @ref LL_ADC_OFFSET_DISABLE
3091 * @arg @ref LL_ADC_OFFSET_ENABLE
3092 */
LL_ADC_GetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety)3093 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
3094 {
3095 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3096
3097 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
3098 }
3099
3100 #if defined(ADC_SMPR1_SMPPLUS)
3101 /**
3102 * @brief Set ADC sampling time common configuration impacting
3103 * settings of sampling time channel wise.
3104 * @note On this STM32 series, setting of this feature is conditioned to
3105 * ADC state:
3106 * ADC must be disabled or enabled without conversion on going
3107 * on either groups regular or injected.
3108 * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
3109 * @param ADCx ADC instance
3110 * @param SamplingTimeCommonConfig This parameter can be one of the following values:
3111 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3112 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3113 * @retval None
3114 */
LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef * ADCx,uint32_t SamplingTimeCommonConfig)3115 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
3116 {
3117 MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
3118 }
3119
3120 /**
3121 * @brief Get ADC sampling time common configuration impacting
3122 * settings of sampling time channel wise.
3123 * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
3124 * @param ADCx ADC instance
3125 * @retval Returned value can be one of the following values:
3126 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3127 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3128 */
LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef * ADCx)3129 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
3130 {
3131 return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
3132 }
3133 #endif /* ADC_SMPR1_SMPPLUS */
3134
3135 /**
3136 * @}
3137 */
3138
3139 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3140 * @{
3141 */
3142
3143 /**
3144 * @brief Set ADC group regular conversion trigger source:
3145 * internal (SW start) or from external peripheral (timer event,
3146 * external interrupt line).
3147 * @note On this STM32 series, setting trigger source to external trigger
3148 * also set trigger polarity to rising edge
3149 * (default setting for compatibility with some ADC on other
3150 * STM32 families having this setting set by HW default value).
3151 * In case of need to modify trigger edge, use
3152 * function @ref LL_ADC_REG_SetTriggerEdge().
3153 * @note Availability of parameters of trigger sources from timer
3154 * depends on timers availability on the selected device.
3155 * @note On this STM32 series, setting of this feature is conditioned to
3156 * ADC state:
3157 * ADC must be disabled or enabled without conversion on going
3158 * on group regular.
3159 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3160 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3161 * @param ADCx ADC instance
3162 * @param TriggerSource This parameter can be one of the following values:
3163 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3164 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3165 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3166 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3167 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3168 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3169 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3170 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3171 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3172 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3173 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3174 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3175 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3176 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3177 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3178 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3179 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3180 * @retval None
3181 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3182 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3183 {
3184 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3185 }
3186
3187 /**
3188 * @brief Get ADC group regular conversion trigger source:
3189 * internal (SW start) or from external peripheral (timer event,
3190 * external interrupt line).
3191 * @note To determine whether group regular trigger source is
3192 * internal (SW start) or external, without detail
3193 * of which peripheral is selected as external trigger,
3194 * (equivalent to
3195 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3196 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3197 * @note Availability of parameters of trigger sources from timer
3198 * depends on timers availability on the selected device.
3199 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3200 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3201 * @param ADCx ADC instance
3202 * @retval Returned value can be one of the following values:
3203 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3204 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3205 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3206 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3207 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3208 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3209 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3210 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3211 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3212 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3213 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3214 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3215 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3216 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3217 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3218 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3219 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3220 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)3221 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
3222 {
3223 __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3224
3225 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3226 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3227 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3228
3229 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3230 /* to match with triggers literals definition. */
3231 return ((TriggerSource
3232 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
3233 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
3234 );
3235 }
3236
3237 /**
3238 * @brief Get ADC group regular conversion trigger source internal (SW start)
3239 * or external.
3240 * @note In case of group regular trigger source set to external trigger,
3241 * to determine which peripheral is selected as external trigger,
3242 * use function @ref LL_ADC_REG_GetTriggerSource().
3243 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3244 * @param ADCx ADC instance
3245 * @retval Value "0" if trigger source external trigger
3246 * Value "1" if trigger source SW start.
3247 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)3248 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3249 {
3250 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3251 }
3252
3253 /**
3254 * @brief Set ADC group regular conversion trigger polarity.
3255 * @note Applicable only for trigger source set to external trigger.
3256 * @note On this STM32 series, setting of this feature is conditioned to
3257 * ADC state:
3258 * ADC must be disabled or enabled without conversion on going
3259 * on group regular.
3260 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3261 * @param ADCx ADC instance
3262 * @param ExternalTriggerEdge This parameter can be one of the following values:
3263 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3264 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3265 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3266 * @retval None
3267 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3268 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3269 {
3270 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
3271 }
3272
3273 /**
3274 * @brief Get ADC group regular conversion trigger polarity.
3275 * @note Applicable only for trigger source set to external trigger.
3276 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
3277 * @param ADCx ADC instance
3278 * @retval Returned value can be one of the following values:
3279 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3280 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3281 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3282 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)3283 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
3284 {
3285 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
3286 }
3287
3288 /**
3289 * @brief Set ADC group regular sequencer length and scan direction.
3290 * @note Description of ADC group regular sequencer features:
3291 * - For devices with sequencer fully configurable
3292 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3293 * sequencer length and each rank affectation to a channel
3294 * are configurable.
3295 * This function performs configuration of:
3296 * - Sequence length: Number of ranks in the scan sequence.
3297 * - Sequence direction: Unless specified in parameters, sequencer
3298 * scan direction is forward (from rank 1 to rank n).
3299 * Sequencer ranks are selected using
3300 * function "LL_ADC_REG_SetSequencerRanks()".
3301 * - For devices with sequencer not fully configurable
3302 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3303 * sequencer length and each rank affectation to a channel
3304 * are defined by channel number.
3305 * This function performs configuration of:
3306 * - Sequence length: Number of ranks in the scan sequence is
3307 * defined by number of channels set in the sequence,
3308 * rank of each channel is fixed by channel HW number.
3309 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3310 * - Sequence direction: Unless specified in parameters, sequencer
3311 * scan direction is forward (from lowest channel number to
3312 * highest channel number).
3313 * Sequencer ranks are selected using
3314 * function "LL_ADC_REG_SetSequencerChannels()".
3315 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3316 * ADC conversion on only 1 channel.
3317 * @note On this STM32 series, setting of this feature is conditioned to
3318 * ADC state:
3319 * ADC must be disabled or enabled without conversion on going
3320 * on group regular.
3321 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
3322 * @param ADCx ADC instance
3323 * @param SequencerNbRanks This parameter can be one of the following values:
3324 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3325 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3326 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3327 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3328 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3329 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3330 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3331 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3332 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3333 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3334 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3335 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3336 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3337 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3338 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3339 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3340 * @retval None
3341 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)3342 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3343 {
3344 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
3345 }
3346
3347 /**
3348 * @brief Get ADC group regular sequencer length and scan direction.
3349 * @note Description of ADC group regular sequencer features:
3350 * - For devices with sequencer fully configurable
3351 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3352 * sequencer length and each rank affectation to a channel
3353 * are configurable.
3354 * This function retrieves:
3355 * - Sequence length: Number of ranks in the scan sequence.
3356 * - Sequence direction: Unless specified in parameters, sequencer
3357 * scan direction is forward (from rank 1 to rank n).
3358 * Sequencer ranks are selected using
3359 * function "LL_ADC_REG_SetSequencerRanks()".
3360 * - For devices with sequencer not fully configurable
3361 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3362 * sequencer length and each rank affectation to a channel
3363 * are defined by channel number.
3364 * This function retrieves:
3365 * - Sequence length: Number of ranks in the scan sequence is
3366 * defined by number of channels set in the sequence,
3367 * rank of each channel is fixed by channel HW number.
3368 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3369 * - Sequence direction: Unless specified in parameters, sequencer
3370 * scan direction is forward (from lowest channel number to
3371 * highest channel number).
3372 * Sequencer ranks are selected using
3373 * function "LL_ADC_REG_SetSequencerChannels()".
3374 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3375 * ADC conversion on only 1 channel.
3376 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
3377 * @param ADCx ADC instance
3378 * @retval Returned value can be one of the following values:
3379 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3380 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3381 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3382 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3383 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3384 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3385 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3386 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3387 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3388 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3389 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3390 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3391 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3392 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3393 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3394 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3395 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)3396 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
3397 {
3398 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
3399 }
3400
3401 /**
3402 * @brief Set ADC group regular sequencer discontinuous mode:
3403 * sequence subdivided and scan conversions interrupted every selected
3404 * number of ranks.
3405 * @note It is not possible to enable both ADC group regular
3406 * continuous mode and sequencer discontinuous mode.
3407 * @note It is not possible to enable both ADC auto-injected mode
3408 * and ADC group regular sequencer discontinuous mode.
3409 * @note On this STM32 series, setting of this feature is conditioned to
3410 * ADC state:
3411 * ADC must be disabled or enabled without conversion on going
3412 * on group regular.
3413 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
3414 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
3415 * @param ADCx ADC instance
3416 * @param SeqDiscont This parameter can be one of the following values:
3417 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3418 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3419 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3420 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3421 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3422 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3423 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3424 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3425 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3426 * @retval None
3427 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)3428 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3429 {
3430 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
3431 }
3432
3433 /**
3434 * @brief Get ADC group regular sequencer discontinuous mode:
3435 * sequence subdivided and scan conversions interrupted every selected
3436 * number of ranks.
3437 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
3438 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
3439 * @param ADCx ADC instance
3440 * @retval Returned value can be one of the following values:
3441 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3442 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3443 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3444 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3445 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3446 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3447 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3448 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3449 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3450 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)3451 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
3452 {
3453 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
3454 }
3455
3456 /**
3457 * @brief Set ADC group regular sequence: channel on the selected
3458 * scan sequence rank.
3459 * @note This function performs configuration of:
3460 * - Channels ordering into each rank of scan sequence:
3461 * whatever channel can be placed into whatever rank.
3462 * @note On this STM32 series, ADC group regular sequencer is
3463 * fully configurable: sequencer length and each rank
3464 * affectation to a channel are configurable.
3465 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3466 * @note Depending on devices and packages, some channels may not be available.
3467 * Refer to device datasheet for channels availability.
3468 * @note On this STM32 series, to measure internal channels (VrefInt,
3469 * TempSensor, ...), measurement paths to internal channels must be
3470 * enabled separately.
3471 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3472 * @note On this STM32 series, setting of this feature is conditioned to
3473 * ADC state:
3474 * ADC must be disabled or enabled without conversion on going
3475 * on group regular.
3476 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
3477 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
3478 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
3479 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
3480 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
3481 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
3482 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
3483 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
3484 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
3485 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
3486 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
3487 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
3488 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
3489 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
3490 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
3491 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
3492 * @param ADCx ADC instance
3493 * @param Rank This parameter can be one of the following values:
3494 * @arg @ref LL_ADC_REG_RANK_1
3495 * @arg @ref LL_ADC_REG_RANK_2
3496 * @arg @ref LL_ADC_REG_RANK_3
3497 * @arg @ref LL_ADC_REG_RANK_4
3498 * @arg @ref LL_ADC_REG_RANK_5
3499 * @arg @ref LL_ADC_REG_RANK_6
3500 * @arg @ref LL_ADC_REG_RANK_7
3501 * @arg @ref LL_ADC_REG_RANK_8
3502 * @arg @ref LL_ADC_REG_RANK_9
3503 * @arg @ref LL_ADC_REG_RANK_10
3504 * @arg @ref LL_ADC_REG_RANK_11
3505 * @arg @ref LL_ADC_REG_RANK_12
3506 * @arg @ref LL_ADC_REG_RANK_13
3507 * @arg @ref LL_ADC_REG_RANK_14
3508 * @arg @ref LL_ADC_REG_RANK_15
3509 * @arg @ref LL_ADC_REG_RANK_16
3510 * @param Channel This parameter can be one of the following values:
3511 * @arg @ref LL_ADC_CHANNEL_0
3512 * @arg @ref LL_ADC_CHANNEL_1 (7)
3513 * @arg @ref LL_ADC_CHANNEL_2 (7)
3514 * @arg @ref LL_ADC_CHANNEL_3 (7)
3515 * @arg @ref LL_ADC_CHANNEL_4 (7)
3516 * @arg @ref LL_ADC_CHANNEL_5 (7)
3517 * @arg @ref LL_ADC_CHANNEL_6
3518 * @arg @ref LL_ADC_CHANNEL_7
3519 * @arg @ref LL_ADC_CHANNEL_8
3520 * @arg @ref LL_ADC_CHANNEL_9
3521 * @arg @ref LL_ADC_CHANNEL_10
3522 * @arg @ref LL_ADC_CHANNEL_11
3523 * @arg @ref LL_ADC_CHANNEL_12
3524 * @arg @ref LL_ADC_CHANNEL_13
3525 * @arg @ref LL_ADC_CHANNEL_14
3526 * @arg @ref LL_ADC_CHANNEL_15
3527 * @arg @ref LL_ADC_CHANNEL_16
3528 * @arg @ref LL_ADC_CHANNEL_17
3529 * @arg @ref LL_ADC_CHANNEL_18
3530 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3531 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
3532 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
3533 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
3534 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
3535 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
3536 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
3537 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
3538 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
3539 *
3540 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
3541 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
3542 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
3543 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
3544 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
3545 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
3546 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3547 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
3548 * @retval None
3549 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)3550 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3551 {
3552 /* Set bits with content of parameter "Channel" with bits position */
3553 /* in register and register position depending on parameter "Rank". */
3554 /* Parameters "Rank" and "Channel" are used with masks because containing */
3555 /* other bits reserved for other purpose. */
3556 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
3557
3558 MODIFY_REG(*preg,
3559 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
3560 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
3561 }
3562
3563 /**
3564 * @brief Get ADC group regular sequence: channel on the selected
3565 * scan sequence rank.
3566 * @note On this STM32 series, ADC group regular sequencer is
3567 * fully configurable: sequencer length and each rank
3568 * affectation to a channel are configurable.
3569 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3570 * @note Depending on devices and packages, some channels may not be available.
3571 * Refer to device datasheet for channels availability.
3572 * @note Usage of the returned channel number:
3573 * - To reinject this channel into another function LL_ADC_xxx:
3574 * the returned channel number is only partly formatted on definition
3575 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3576 * with parts of literals LL_ADC_CHANNEL_x or using
3577 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3578 * Then the selected literal LL_ADC_CHANNEL_x can be used
3579 * as parameter for another function.
3580 * - To get the channel number in decimal format:
3581 * process the returned value with the helper macro
3582 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3583 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
3584 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
3585 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
3586 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
3587 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
3588 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
3589 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
3590 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
3591 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
3592 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
3593 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
3594 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
3595 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
3596 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
3597 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
3598 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
3599 * @param ADCx ADC instance
3600 * @param Rank This parameter can be one of the following values:
3601 * @arg @ref LL_ADC_REG_RANK_1
3602 * @arg @ref LL_ADC_REG_RANK_2
3603 * @arg @ref LL_ADC_REG_RANK_3
3604 * @arg @ref LL_ADC_REG_RANK_4
3605 * @arg @ref LL_ADC_REG_RANK_5
3606 * @arg @ref LL_ADC_REG_RANK_6
3607 * @arg @ref LL_ADC_REG_RANK_7
3608 * @arg @ref LL_ADC_REG_RANK_8
3609 * @arg @ref LL_ADC_REG_RANK_9
3610 * @arg @ref LL_ADC_REG_RANK_10
3611 * @arg @ref LL_ADC_REG_RANK_11
3612 * @arg @ref LL_ADC_REG_RANK_12
3613 * @arg @ref LL_ADC_REG_RANK_13
3614 * @arg @ref LL_ADC_REG_RANK_14
3615 * @arg @ref LL_ADC_REG_RANK_15
3616 * @arg @ref LL_ADC_REG_RANK_16
3617 * @retval Returned value can be one of the following values:
3618 * @arg @ref LL_ADC_CHANNEL_0
3619 * @arg @ref LL_ADC_CHANNEL_1 (7)
3620 * @arg @ref LL_ADC_CHANNEL_2 (7)
3621 * @arg @ref LL_ADC_CHANNEL_3 (7)
3622 * @arg @ref LL_ADC_CHANNEL_4 (7)
3623 * @arg @ref LL_ADC_CHANNEL_5 (7)
3624 * @arg @ref LL_ADC_CHANNEL_6
3625 * @arg @ref LL_ADC_CHANNEL_7
3626 * @arg @ref LL_ADC_CHANNEL_8
3627 * @arg @ref LL_ADC_CHANNEL_9
3628 * @arg @ref LL_ADC_CHANNEL_10
3629 * @arg @ref LL_ADC_CHANNEL_11
3630 * @arg @ref LL_ADC_CHANNEL_12
3631 * @arg @ref LL_ADC_CHANNEL_13
3632 * @arg @ref LL_ADC_CHANNEL_14
3633 * @arg @ref LL_ADC_CHANNEL_15
3634 * @arg @ref LL_ADC_CHANNEL_16
3635 * @arg @ref LL_ADC_CHANNEL_17
3636 * @arg @ref LL_ADC_CHANNEL_18
3637 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3638 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
3639 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
3640 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
3641 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
3642 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
3643 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
3644 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
3645 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
3646 *
3647 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
3648 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
3649 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
3650 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
3651 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
3652 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
3653 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3654 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
3655 * (1, 2, 3, 4) For ADC channel read back from ADC register,
3656 * comparison with internal channel parameter to be done
3657 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3658 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)3659 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3660 {
3661 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
3662
3663 return (uint32_t)((READ_BIT(*preg,
3664 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
3665 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
3666 );
3667 }
3668
3669 /**
3670 * @brief Set ADC continuous conversion mode on ADC group regular.
3671 * @note Description of ADC continuous conversion mode:
3672 * - single mode: one conversion per trigger
3673 * - continuous mode: after the first trigger, following
3674 * conversions launched successively automatically.
3675 * @note It is not possible to enable both ADC group regular
3676 * continuous mode and sequencer discontinuous mode.
3677 * @note On this STM32 series, setting of this feature is conditioned to
3678 * ADC state:
3679 * ADC must be disabled or enabled without conversion on going
3680 * on group regular.
3681 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
3682 * @param ADCx ADC instance
3683 * @param Continuous This parameter can be one of the following values:
3684 * @arg @ref LL_ADC_REG_CONV_SINGLE
3685 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3686 * @retval None
3687 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)3688 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3689 {
3690 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
3691 }
3692
3693 /**
3694 * @brief Get ADC continuous conversion mode on ADC group regular.
3695 * @note Description of ADC continuous conversion mode:
3696 * - single mode: one conversion per trigger
3697 * - continuous mode: after the first trigger, following
3698 * conversions launched successively automatically.
3699 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
3700 * @param ADCx ADC instance
3701 * @retval Returned value can be one of the following values:
3702 * @arg @ref LL_ADC_REG_CONV_SINGLE
3703 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3704 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)3705 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
3706 {
3707 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
3708 }
3709
3710 /**
3711 * @brief Set ADC group regular conversion data transfer: no transfer or
3712 * transfer by DMA, and DMA requests mode.
3713 * @note If transfer by DMA selected, specifies the DMA requests
3714 * mode:
3715 * - Limited mode (One shot mode): DMA transfer requests are stopped
3716 * when number of DMA data transfers (number of
3717 * ADC conversions) is reached.
3718 * This ADC mode is intended to be used with DMA mode non-circular.
3719 * - Unlimited mode: DMA transfer requests are unlimited,
3720 * whatever number of DMA data transfers (number of
3721 * ADC conversions).
3722 * This ADC mode is intended to be used with DMA mode circular.
3723 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3724 * mode non-circular:
3725 * when DMA transfers size will be reached, DMA will stop transfers of
3726 * ADC conversions data ADC will raise an overrun error
3727 * (overrun flag and interruption if enabled).
3728 * @note For devices with several ADC instances: ADC multimode DMA
3729 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
3730 * @note To configure DMA source address (peripheral address),
3731 * use function @ref LL_ADC_DMA_GetRegAddr().
3732 * @note On this STM32 series, setting of this feature is conditioned to
3733 * ADC state:
3734 * ADC must be disabled or enabled without conversion on going
3735 * on either groups regular or injected.
3736 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
3737 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
3738 * @param ADCx ADC instance
3739 * @param DMATransfer This parameter can be one of the following values:
3740 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3741 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3742 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3743 * @retval None
3744 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)3745 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3746 {
3747 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
3748 }
3749
3750 /**
3751 * @brief Get ADC group regular conversion data transfer: no transfer or
3752 * transfer by DMA, and DMA requests mode.
3753 * @note If transfer by DMA selected, specifies the DMA requests
3754 * mode:
3755 * - Limited mode (One shot mode): DMA transfer requests are stopped
3756 * when number of DMA data transfers (number of
3757 * ADC conversions) is reached.
3758 * This ADC mode is intended to be used with DMA mode non-circular.
3759 * - Unlimited mode: DMA transfer requests are unlimited,
3760 * whatever number of DMA data transfers (number of
3761 * ADC conversions).
3762 * This ADC mode is intended to be used with DMA mode circular.
3763 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3764 * mode non-circular:
3765 * when DMA transfers size will be reached, DMA will stop transfers of
3766 * ADC conversions data ADC will raise an overrun error
3767 * (overrun flag and interruption if enabled).
3768 * @note For devices with several ADC instances: ADC multimode DMA
3769 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
3770 * @note To configure DMA source address (peripheral address),
3771 * use function @ref LL_ADC_DMA_GetRegAddr().
3772 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
3773 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
3774 * @param ADCx ADC instance
3775 * @retval Returned value can be one of the following values:
3776 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3777 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3778 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3779 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)3780 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
3781 {
3782 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
3783 }
3784
3785 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
3786 /**
3787 * @brief Set ADC group regular conversion data transfer to DFSDM.
3788 * @note DFSDM transfer cannot be used if DMA transfer is enabled.
3789 * @note To configure DFSDM source address (peripheral address),
3790 * use the same function as for DMA transfer:
3791 * function @ref LL_ADC_DMA_GetRegAddr().
3792 * @note On this STM32 series, setting of this feature is conditioned to
3793 * ADC state:
3794 * ADC must be disabled or enabled without conversion on going
3795 * on either groups regular or injected.
3796 * @rmtoll CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer
3797 * @param ADCx ADC instance
3798 * @param DFSDMTransfer This parameter can be one of the following values:
3799 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE
3800 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE
3801 * @retval None
3802 */
LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef * ADCx,uint32_t DFSDMTransfer)3803 __STATIC_INLINE void LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef *ADCx, uint32_t DFSDMTransfer)
3804 {
3805 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DFSDMCFG, DFSDMTransfer);
3806 }
3807
3808 /**
3809 * @brief Get ADC group regular conversion data transfer to DFSDM.
3810 * @rmtoll CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer
3811 * @param ADCx ADC instance
3812 * @retval Returned value can be one of the following values:
3813 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE
3814 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE
3815 */
LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef * ADCx)3816 __STATIC_INLINE uint32_t LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef *ADCx)
3817 {
3818 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DFSDMCFG));
3819 }
3820 #endif /* ADC_CFGR_DFSDMCFG */
3821
3822 /**
3823 * @brief Set ADC group regular behavior in case of overrun:
3824 * data preserved or overwritten.
3825 * @note Compatibility with devices without feature overrun:
3826 * other devices without this feature have a behavior
3827 * equivalent to data overwritten.
3828 * The default setting of overrun is data preserved.
3829 * Therefore, for compatibility with all devices, parameter
3830 * overrun should be set to data overwritten.
3831 * @note On this STM32 series, setting of this feature is conditioned to
3832 * ADC state:
3833 * ADC must be disabled or enabled without conversion on going
3834 * on group regular.
3835 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
3836 * @param ADCx ADC instance
3837 * @param Overrun This parameter can be one of the following values:
3838 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3839 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3840 * @retval None
3841 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)3842 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3843 {
3844 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
3845 }
3846
3847 /**
3848 * @brief Get ADC group regular behavior in case of overrun:
3849 * data preserved or overwritten.
3850 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
3851 * @param ADCx ADC instance
3852 * @retval Returned value can be one of the following values:
3853 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3854 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3855 */
LL_ADC_REG_GetOverrun(ADC_TypeDef * ADCx)3856 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
3857 {
3858 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
3859 }
3860
3861 /**
3862 * @}
3863 */
3864
3865 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
3866 * @{
3867 */
3868
3869 /**
3870 * @brief Set ADC group injected conversion trigger source:
3871 * internal (SW start) or from external peripheral (timer event,
3872 * external interrupt line).
3873 * @note On this STM32 series, setting trigger source to external trigger
3874 * also set trigger polarity to rising edge
3875 * (default setting for compatibility with some ADC on other
3876 * STM32 families having this setting set by HW default value).
3877 * In case of need to modify trigger edge, use
3878 * function @ref LL_ADC_INJ_SetTriggerEdge().
3879 * @note Availability of parameters of trigger sources from timer
3880 * depends on timers availability on the selected device.
3881 * @note On this STM32 series, setting of this feature is conditioned to
3882 * ADC state:
3883 * ADC must not be disabled. Can be enabled with or without conversion
3884 * on going on either groups regular or injected.
3885 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
3886 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
3887 * @param ADCx ADC instance
3888 * @param TriggerSource This parameter can be one of the following values:
3889 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3890 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
3891 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
3892 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
3893 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
3894 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
3895 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
3896 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
3897 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
3898 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
3899 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
3900 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
3901 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
3902 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
3903 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
3904 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
3905 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
3906 * @retval None
3907 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3908 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3909 {
3910 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
3911 }
3912
3913 /**
3914 * @brief Get ADC group injected conversion trigger source:
3915 * internal (SW start) or from external peripheral (timer event,
3916 * external interrupt line).
3917 * @note To determine whether group injected trigger source is
3918 * internal (SW start) or external, without detail
3919 * of which peripheral is selected as external trigger,
3920 * (equivalent to
3921 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
3922 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
3923 * @note Availability of parameters of trigger sources from timer
3924 * depends on timers availability on the selected device.
3925 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
3926 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
3927 * @param ADCx ADC instance
3928 * @retval Returned value can be one of the following values:
3929 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3930 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
3931 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
3932 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
3933 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
3934 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
3935 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
3936 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
3937 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
3938 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
3939 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
3940 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
3941 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
3942 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
3943 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
3944 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
3945 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
3946 */
LL_ADC_INJ_GetTriggerSource(ADC_TypeDef * ADCx)3947 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
3948 {
3949 __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
3950
3951 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3952 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
3953 uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3954
3955 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
3956 /* to match with triggers literals definition. */
3957 return ((TriggerSource
3958 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
3959 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
3960 );
3961 }
3962
3963 /**
3964 * @brief Get ADC group injected conversion trigger source internal (SW start)
3965 or external
3966 * @note In case of group injected trigger source set to external trigger,
3967 * to determine which peripheral is selected as external trigger,
3968 * use function @ref LL_ADC_INJ_GetTriggerSource.
3969 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
3970 * @param ADCx ADC instance
3971 * @retval Value "0" if trigger source external trigger
3972 * Value "1" if trigger source SW start.
3973 */
LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)3974 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3975 {
3976 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
3977 }
3978
3979 /**
3980 * @brief Set ADC group injected conversion trigger polarity.
3981 * Applicable only for trigger source set to external trigger.
3982 * @note On this STM32 series, setting of this feature is conditioned to
3983 * ADC state:
3984 * ADC must not be disabled. Can be enabled with or without conversion
3985 * on going on either groups regular or injected.
3986 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
3987 * @param ADCx ADC instance
3988 * @param ExternalTriggerEdge This parameter can be one of the following values:
3989 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
3990 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
3991 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
3992 * @retval None
3993 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3994 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3995 {
3996 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
3997 }
3998
3999 /**
4000 * @brief Get ADC group injected conversion trigger polarity.
4001 * Applicable only for trigger source set to external trigger.
4002 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4003 * @param ADCx ADC instance
4004 * @retval Returned value can be one of the following values:
4005 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4006 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4007 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4008 */
LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef * ADCx)4009 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
4010 {
4011 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4012 }
4013
4014 /**
4015 * @brief Set ADC group injected sequencer length and scan direction.
4016 * @note This function performs configuration of:
4017 * - Sequence length: Number of ranks in the scan sequence.
4018 * - Sequence direction: Unless specified in parameters, sequencer
4019 * scan direction is forward (from rank 1 to rank n).
4020 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4021 * ADC conversion on only 1 channel.
4022 * @note On this STM32 series, setting of this feature is conditioned to
4023 * ADC state:
4024 * ADC must not be disabled. Can be enabled with or without conversion
4025 * on going on either groups regular or injected.
4026 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4027 * @param ADCx ADC instance
4028 * @param SequencerNbRanks This parameter can be one of the following values:
4029 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4030 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4031 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4032 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4033 * @retval None
4034 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4035 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4036 {
4037 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4038 }
4039
4040 /**
4041 * @brief Get ADC group injected sequencer length and scan direction.
4042 * @note This function retrieves:
4043 * - Sequence length: Number of ranks in the scan sequence.
4044 * - Sequence direction: Unless specified in parameters, sequencer
4045 * scan direction is forward (from rank 1 to rank n).
4046 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4047 * ADC conversion on only 1 channel.
4048 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4049 * @param ADCx ADC instance
4050 * @retval Returned value can be one of the following values:
4051 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4052 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4053 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4054 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4055 */
LL_ADC_INJ_GetSequencerLength(ADC_TypeDef * ADCx)4056 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
4057 {
4058 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4059 }
4060
4061 /**
4062 * @brief Set ADC group injected sequencer discontinuous mode:
4063 * sequence subdivided and scan conversions interrupted every selected
4064 * number of ranks.
4065 * @note It is not possible to enable both ADC group injected
4066 * auto-injected mode and sequencer discontinuous mode.
4067 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4068 * @param ADCx ADC instance
4069 * @param SeqDiscont This parameter can be one of the following values:
4070 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4071 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4072 * @retval None
4073 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4074 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4075 {
4076 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4077 }
4078
4079 /**
4080 * @brief Get ADC group injected sequencer discontinuous mode:
4081 * sequence subdivided and scan conversions interrupted every selected
4082 * number of ranks.
4083 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4084 * @param ADCx ADC instance
4085 * @retval Returned value can be one of the following values:
4086 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4087 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4088 */
LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef * ADCx)4089 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
4090 {
4091 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4092 }
4093
4094 /**
4095 * @brief Set ADC group injected sequence: channel on the selected
4096 * sequence rank.
4097 * @note Depending on devices and packages, some channels may not be available.
4098 * Refer to device datasheet for channels availability.
4099 * @note On this STM32 series, to measure internal channels (VrefInt,
4100 * TempSensor, ...), measurement paths to internal channels must be
4101 * enabled separately.
4102 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4103 * @note On STM32L4, some fast channels are available: fast analog inputs
4104 * coming from GPIO pads (ADC_IN1..5).
4105 * @note On this STM32 series, setting of this feature is conditioned to
4106 * ADC state:
4107 * ADC must not be disabled. Can be enabled with or without conversion
4108 * on going on either groups regular or injected.
4109 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4110 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4111 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4112 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4113 * @param ADCx ADC instance
4114 * @param Rank This parameter can be one of the following values:
4115 * @arg @ref LL_ADC_INJ_RANK_1
4116 * @arg @ref LL_ADC_INJ_RANK_2
4117 * @arg @ref LL_ADC_INJ_RANK_3
4118 * @arg @ref LL_ADC_INJ_RANK_4
4119 * @param Channel This parameter can be one of the following values:
4120 * @arg @ref LL_ADC_CHANNEL_0
4121 * @arg @ref LL_ADC_CHANNEL_1 (7)
4122 * @arg @ref LL_ADC_CHANNEL_2 (7)
4123 * @arg @ref LL_ADC_CHANNEL_3 (7)
4124 * @arg @ref LL_ADC_CHANNEL_4 (7)
4125 * @arg @ref LL_ADC_CHANNEL_5 (7)
4126 * @arg @ref LL_ADC_CHANNEL_6
4127 * @arg @ref LL_ADC_CHANNEL_7
4128 * @arg @ref LL_ADC_CHANNEL_8
4129 * @arg @ref LL_ADC_CHANNEL_9
4130 * @arg @ref LL_ADC_CHANNEL_10
4131 * @arg @ref LL_ADC_CHANNEL_11
4132 * @arg @ref LL_ADC_CHANNEL_12
4133 * @arg @ref LL_ADC_CHANNEL_13
4134 * @arg @ref LL_ADC_CHANNEL_14
4135 * @arg @ref LL_ADC_CHANNEL_15
4136 * @arg @ref LL_ADC_CHANNEL_16
4137 * @arg @ref LL_ADC_CHANNEL_17
4138 * @arg @ref LL_ADC_CHANNEL_18
4139 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4140 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4141 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4142 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4143 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4144 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4145 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4146 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4147 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4148 *
4149 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4150 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4151 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4152 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4153 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4154 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4155 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4156 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4157 * @retval None
4158 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4159 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4160 {
4161 /* Set bits with content of parameter "Channel" with bits position */
4162 /* in register depending on parameter "Rank". */
4163 /* Parameters "Rank" and "Channel" are used with masks because containing */
4164 /* other bits reserved for other purpose. */
4165 MODIFY_REG(ADCx->JSQR,
4166 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4167 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4168 }
4169
4170 /**
4171 * @brief Get ADC group injected sequence: channel on the selected
4172 * sequence rank.
4173 * @note Depending on devices and packages, some channels may not be available.
4174 * Refer to device datasheet for channels availability.
4175 * @note Usage of the returned channel number:
4176 * - To reinject this channel into another function LL_ADC_xxx:
4177 * the returned channel number is only partly formatted on definition
4178 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4179 * with parts of literals LL_ADC_CHANNEL_x or using
4180 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4181 * Then the selected literal LL_ADC_CHANNEL_x can be used
4182 * as parameter for another function.
4183 * - To get the channel number in decimal format:
4184 * process the returned value with the helper macro
4185 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4186 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4187 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4188 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4189 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4190 * @param ADCx ADC instance
4191 * @param Rank This parameter can be one of the following values:
4192 * @arg @ref LL_ADC_INJ_RANK_1
4193 * @arg @ref LL_ADC_INJ_RANK_2
4194 * @arg @ref LL_ADC_INJ_RANK_3
4195 * @arg @ref LL_ADC_INJ_RANK_4
4196 * @retval Returned value can be one of the following values:
4197 * @arg @ref LL_ADC_CHANNEL_0
4198 * @arg @ref LL_ADC_CHANNEL_1 (7)
4199 * @arg @ref LL_ADC_CHANNEL_2 (7)
4200 * @arg @ref LL_ADC_CHANNEL_3 (7)
4201 * @arg @ref LL_ADC_CHANNEL_4 (7)
4202 * @arg @ref LL_ADC_CHANNEL_5 (7)
4203 * @arg @ref LL_ADC_CHANNEL_6
4204 * @arg @ref LL_ADC_CHANNEL_7
4205 * @arg @ref LL_ADC_CHANNEL_8
4206 * @arg @ref LL_ADC_CHANNEL_9
4207 * @arg @ref LL_ADC_CHANNEL_10
4208 * @arg @ref LL_ADC_CHANNEL_11
4209 * @arg @ref LL_ADC_CHANNEL_12
4210 * @arg @ref LL_ADC_CHANNEL_13
4211 * @arg @ref LL_ADC_CHANNEL_14
4212 * @arg @ref LL_ADC_CHANNEL_15
4213 * @arg @ref LL_ADC_CHANNEL_16
4214 * @arg @ref LL_ADC_CHANNEL_17
4215 * @arg @ref LL_ADC_CHANNEL_18
4216 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4217 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4218 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4219 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4220 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4221 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4222 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4223 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4224 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4225 *
4226 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4227 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4228 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4229 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4230 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4231 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4232 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4233 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
4234 * (1, 2, 3, 4) For ADC channel read back from ADC register,
4235 * comparison with internal channel parameter to be done
4236 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4237 */
LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)4238 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4239 {
4240 return (uint32_t)((READ_BIT(ADCx->JSQR,
4241 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4242 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4243 );
4244 }
4245
4246 /**
4247 * @brief Set ADC group injected conversion trigger:
4248 * independent or from ADC group regular.
4249 * @note This mode can be used to extend number of data registers
4250 * updated after one ADC conversion trigger and with data
4251 * permanently kept (not erased by successive conversions of scan of
4252 * ADC sequencer ranks), up to 5 data registers:
4253 * 1 data register on ADC group regular, 4 data registers
4254 * on ADC group injected.
4255 * @note If ADC group injected injected trigger source is set to an
4256 * external trigger, this feature must be must be set to
4257 * independent trigger.
4258 * ADC group injected automatic trigger is compliant only with
4259 * group injected trigger source set to SW start, without any
4260 * further action on ADC group injected conversion start or stop:
4261 * in this case, ADC group injected is controlled only
4262 * from ADC group regular.
4263 * @note It is not possible to enable both ADC group injected
4264 * auto-injected mode and sequencer discontinuous mode.
4265 * @note On this STM32 series, setting of this feature is conditioned to
4266 * ADC state:
4267 * ADC must be disabled or enabled without conversion on going
4268 * on either groups regular or injected.
4269 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
4270 * @param ADCx ADC instance
4271 * @param TrigAuto This parameter can be one of the following values:
4272 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4273 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4274 * @retval None
4275 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)4276 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
4277 {
4278 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
4279 }
4280
4281 /**
4282 * @brief Get ADC group injected conversion trigger:
4283 * independent or from ADC group regular.
4284 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
4285 * @param ADCx ADC instance
4286 * @retval Returned value can be one of the following values:
4287 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4288 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4289 */
LL_ADC_INJ_GetTrigAuto(ADC_TypeDef * ADCx)4290 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
4291 {
4292 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
4293 }
4294
4295 /**
4296 * @brief Set ADC group injected contexts queue mode.
4297 * @note A context is a setting of group injected sequencer:
4298 * - group injected trigger
4299 * - sequencer length
4300 * - sequencer ranks
4301 * If contexts queue is disabled:
4302 * - only 1 sequence can be configured
4303 * and is active perpetually.
4304 * If contexts queue is enabled:
4305 * - up to 2 contexts can be queued
4306 * and are checked in and out as a FIFO stack (first-in, first-out).
4307 * - If a new context is set when queues is full, error is triggered
4308 * by interruption "Injected Queue Overflow".
4309 * - Two behaviors are possible when all contexts have been processed:
4310 * the contexts queue can maintain the last context active perpetually
4311 * or can be empty and injected group triggers are disabled.
4312 * - Triggers can be only external (not internal SW start)
4313 * - Caution: The sequence must be fully configured in one time
4314 * (one write of register JSQR makes a check-in of a new context
4315 * into the queue).
4316 * Therefore functions to set separately injected trigger and
4317 * sequencer channels cannot be used, register JSQR must be set
4318 * using function @ref LL_ADC_INJ_ConfigQueueContext().
4319 * @note This parameter can be modified only when no conversion is on going
4320 * on either groups regular or injected.
4321 * @note A modification of the context mode (bit JQDIS) causes the contexts
4322 * queue to be flushed and the register JSQR is cleared.
4323 * @note On this STM32 series, setting of this feature is conditioned to
4324 * ADC state:
4325 * ADC must be disabled or enabled without conversion on going
4326 * on either groups regular or injected.
4327 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
4328 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
4329 * @param ADCx ADC instance
4330 * @param QueueMode This parameter can be one of the following values:
4331 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4332 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4333 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4334 * @retval None
4335 */
LL_ADC_INJ_SetQueueMode(ADC_TypeDef * ADCx,uint32_t QueueMode)4336 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
4337 {
4338 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
4339 }
4340
4341 /**
4342 * @brief Get ADC group injected context queue mode.
4343 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
4344 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
4345 * @param ADCx ADC instance
4346 * @retval Returned value can be one of the following values:
4347 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4348 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4349 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4350 */
LL_ADC_INJ_GetQueueMode(ADC_TypeDef * ADCx)4351 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
4352 {
4353 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
4354 }
4355
4356 /**
4357 * @brief Set one context on ADC group injected that will be checked in
4358 * contexts queue.
4359 * @note A context is a setting of group injected sequencer:
4360 * - group injected trigger
4361 * - sequencer length
4362 * - sequencer ranks
4363 * This function is intended to be used when contexts queue is enabled,
4364 * because the sequence must be fully configured in one time
4365 * (functions to set separately injected trigger and sequencer channels
4366 * cannot be used):
4367 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
4368 * @note In the contexts queue, only the active context can be read.
4369 * The parameters of this function can be read using functions:
4370 * @arg @ref LL_ADC_INJ_GetTriggerSource()
4371 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
4372 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
4373 * @note On this STM32 series, to measure internal channels (VrefInt,
4374 * TempSensor, ...), measurement paths to internal channels must be
4375 * enabled separately.
4376 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4377 * @note On STM32L4, some fast channels are available: fast analog inputs
4378 * coming from GPIO pads (ADC_IN1..5).
4379 * @note On this STM32 series, setting of this feature is conditioned to
4380 * ADC state:
4381 * ADC must not be disabled. Can be enabled with or without conversion
4382 * on going on either groups regular or injected.
4383 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
4384 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
4385 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
4386 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
4387 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
4388 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
4389 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
4390 * @param ADCx ADC instance
4391 * @param TriggerSource This parameter can be one of the following values:
4392 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4393 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4394 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4395 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4396 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4397 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4398 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4399 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4400 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4401 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4402 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4403 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4404 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4405 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4406 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4407 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4408 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4409 * @param ExternalTriggerEdge This parameter can be one of the following values:
4410 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4411 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4412 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4413 *
4414 * Note: This parameter is discarded in case of SW start:
4415 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
4416 * @param SequencerNbRanks This parameter can be one of the following values:
4417 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4418 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4419 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4420 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4421 * @param Rank1_Channel This parameter can be one of the following values:
4422 * @arg @ref LL_ADC_CHANNEL_0
4423 * @arg @ref LL_ADC_CHANNEL_1 (7)
4424 * @arg @ref LL_ADC_CHANNEL_2 (7)
4425 * @arg @ref LL_ADC_CHANNEL_3 (7)
4426 * @arg @ref LL_ADC_CHANNEL_4 (7)
4427 * @arg @ref LL_ADC_CHANNEL_5 (7)
4428 * @arg @ref LL_ADC_CHANNEL_6
4429 * @arg @ref LL_ADC_CHANNEL_7
4430 * @arg @ref LL_ADC_CHANNEL_8
4431 * @arg @ref LL_ADC_CHANNEL_9
4432 * @arg @ref LL_ADC_CHANNEL_10
4433 * @arg @ref LL_ADC_CHANNEL_11
4434 * @arg @ref LL_ADC_CHANNEL_12
4435 * @arg @ref LL_ADC_CHANNEL_13
4436 * @arg @ref LL_ADC_CHANNEL_14
4437 * @arg @ref LL_ADC_CHANNEL_15
4438 * @arg @ref LL_ADC_CHANNEL_16
4439 * @arg @ref LL_ADC_CHANNEL_17
4440 * @arg @ref LL_ADC_CHANNEL_18
4441 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4442 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4443 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4444 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4445 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4446 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4447 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4448 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4449 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4450 *
4451 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4452 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4453 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4454 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4455 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4456 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4457 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4458 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4459 * @param Rank2_Channel This parameter can be one of the following values:
4460 * @arg @ref LL_ADC_CHANNEL_0
4461 * @arg @ref LL_ADC_CHANNEL_1 (7)
4462 * @arg @ref LL_ADC_CHANNEL_2 (7)
4463 * @arg @ref LL_ADC_CHANNEL_3 (7)
4464 * @arg @ref LL_ADC_CHANNEL_4 (7)
4465 * @arg @ref LL_ADC_CHANNEL_5 (7)
4466 * @arg @ref LL_ADC_CHANNEL_6
4467 * @arg @ref LL_ADC_CHANNEL_7
4468 * @arg @ref LL_ADC_CHANNEL_8
4469 * @arg @ref LL_ADC_CHANNEL_9
4470 * @arg @ref LL_ADC_CHANNEL_10
4471 * @arg @ref LL_ADC_CHANNEL_11
4472 * @arg @ref LL_ADC_CHANNEL_12
4473 * @arg @ref LL_ADC_CHANNEL_13
4474 * @arg @ref LL_ADC_CHANNEL_14
4475 * @arg @ref LL_ADC_CHANNEL_15
4476 * @arg @ref LL_ADC_CHANNEL_16
4477 * @arg @ref LL_ADC_CHANNEL_17
4478 * @arg @ref LL_ADC_CHANNEL_18
4479 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4480 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4481 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4482 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4483 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4484 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4485 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4486 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4487 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4488 *
4489 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4490 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4491 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4492 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4493 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4494 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4495 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4496 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4497 * @param Rank3_Channel This parameter can be one of the following values:
4498 * @arg @ref LL_ADC_CHANNEL_0
4499 * @arg @ref LL_ADC_CHANNEL_1 (7)
4500 * @arg @ref LL_ADC_CHANNEL_2 (7)
4501 * @arg @ref LL_ADC_CHANNEL_3 (7)
4502 * @arg @ref LL_ADC_CHANNEL_4 (7)
4503 * @arg @ref LL_ADC_CHANNEL_5 (7)
4504 * @arg @ref LL_ADC_CHANNEL_6
4505 * @arg @ref LL_ADC_CHANNEL_7
4506 * @arg @ref LL_ADC_CHANNEL_8
4507 * @arg @ref LL_ADC_CHANNEL_9
4508 * @arg @ref LL_ADC_CHANNEL_10
4509 * @arg @ref LL_ADC_CHANNEL_11
4510 * @arg @ref LL_ADC_CHANNEL_12
4511 * @arg @ref LL_ADC_CHANNEL_13
4512 * @arg @ref LL_ADC_CHANNEL_14
4513 * @arg @ref LL_ADC_CHANNEL_15
4514 * @arg @ref LL_ADC_CHANNEL_16
4515 * @arg @ref LL_ADC_CHANNEL_17
4516 * @arg @ref LL_ADC_CHANNEL_18
4517 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4518 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4519 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4520 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4521 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4522 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4523 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4524 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4525 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4526 *
4527 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4528 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4529 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4530 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4531 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4532 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4533 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4534 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4535 * @param Rank4_Channel This parameter can be one of the following values:
4536 * @arg @ref LL_ADC_CHANNEL_0
4537 * @arg @ref LL_ADC_CHANNEL_1 (7)
4538 * @arg @ref LL_ADC_CHANNEL_2 (7)
4539 * @arg @ref LL_ADC_CHANNEL_3 (7)
4540 * @arg @ref LL_ADC_CHANNEL_4 (7)
4541 * @arg @ref LL_ADC_CHANNEL_5 (7)
4542 * @arg @ref LL_ADC_CHANNEL_6
4543 * @arg @ref LL_ADC_CHANNEL_7
4544 * @arg @ref LL_ADC_CHANNEL_8
4545 * @arg @ref LL_ADC_CHANNEL_9
4546 * @arg @ref LL_ADC_CHANNEL_10
4547 * @arg @ref LL_ADC_CHANNEL_11
4548 * @arg @ref LL_ADC_CHANNEL_12
4549 * @arg @ref LL_ADC_CHANNEL_13
4550 * @arg @ref LL_ADC_CHANNEL_14
4551 * @arg @ref LL_ADC_CHANNEL_15
4552 * @arg @ref LL_ADC_CHANNEL_16
4553 * @arg @ref LL_ADC_CHANNEL_17
4554 * @arg @ref LL_ADC_CHANNEL_18
4555 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4556 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4557 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4558 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4559 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4560 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4561 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4562 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4563 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4564 *
4565 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4566 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4567 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4568 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4569 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4570 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4571 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4572 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4573 * @retval None
4574 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)4575 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
4576 uint32_t TriggerSource,
4577 uint32_t ExternalTriggerEdge,
4578 uint32_t SequencerNbRanks,
4579 uint32_t Rank1_Channel,
4580 uint32_t Rank2_Channel,
4581 uint32_t Rank3_Channel,
4582 uint32_t Rank4_Channel)
4583 {
4584 /* Set bits with content of parameter "Rankx_Channel" with bits position */
4585 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
4586 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
4587 /* because containing other bits reserved for other purpose. */
4588 /* If parameter "TriggerSource" is set to SW start, then parameter */
4589 /* "ExternalTriggerEdge" is discarded. */
4590 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
4591 MODIFY_REG(ADCx->JSQR,
4592 ADC_JSQR_JEXTSEL |
4593 ADC_JSQR_JEXTEN |
4594 ADC_JSQR_JSQ4 |
4595 ADC_JSQR_JSQ3 |
4596 ADC_JSQR_JSQ2 |
4597 ADC_JSQR_JSQ1 |
4598 ADC_JSQR_JL,
4599 (TriggerSource & ADC_JSQR_JEXTSEL) |
4600 (ExternalTriggerEdge * (is_trigger_not_sw)) |
4601 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4602 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4603 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4604 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4605 SequencerNbRanks
4606 );
4607 }
4608
4609 /**
4610 * @}
4611 */
4612
4613 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
4614 * @{
4615 */
4616
4617 /**
4618 * @brief Set sampling time of the selected ADC channel
4619 * Unit: ADC clock cycles.
4620 * @note On this device, sampling time is on channel scope: independently
4621 * of channel mapped on ADC group regular or injected.
4622 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
4623 * converted:
4624 * sampling time constraints must be respected (sampling time can be
4625 * adjusted in function of ADC clock frequency and sampling time
4626 * setting).
4627 * Refer to device datasheet for timings values (parameters TS_vrefint,
4628 * TS_temp, ...).
4629 * @note Conversion time is the addition of sampling time and processing time.
4630 * On this STM32 series, ADC processing time is:
4631 * - 12.5 ADC clock cycles at ADC resolution 12 bits
4632 * - 10.5 ADC clock cycles at ADC resolution 10 bits
4633 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4634 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4635 * @note In case of ADC conversion of internal channel (VrefInt,
4636 * temperature sensor, ...), a sampling time minimum value
4637 * is required.
4638 * Refer to device datasheet.
4639 * @note On this STM32 series, setting of this feature is conditioned to
4640 * ADC state:
4641 * ADC must be disabled or enabled without conversion on going
4642 * on either groups regular or injected.
4643 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
4644 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
4645 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
4646 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
4647 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
4648 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
4649 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
4650 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
4651 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
4652 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
4653 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
4654 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
4655 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
4656 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
4657 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
4658 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
4659 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
4660 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
4661 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
4662 * @param ADCx ADC instance
4663 * @param Channel This parameter can be one of the following values:
4664 * @arg @ref LL_ADC_CHANNEL_0
4665 * @arg @ref LL_ADC_CHANNEL_1 (7)
4666 * @arg @ref LL_ADC_CHANNEL_2 (7)
4667 * @arg @ref LL_ADC_CHANNEL_3 (7)
4668 * @arg @ref LL_ADC_CHANNEL_4 (7)
4669 * @arg @ref LL_ADC_CHANNEL_5 (7)
4670 * @arg @ref LL_ADC_CHANNEL_6
4671 * @arg @ref LL_ADC_CHANNEL_7
4672 * @arg @ref LL_ADC_CHANNEL_8
4673 * @arg @ref LL_ADC_CHANNEL_9
4674 * @arg @ref LL_ADC_CHANNEL_10
4675 * @arg @ref LL_ADC_CHANNEL_11
4676 * @arg @ref LL_ADC_CHANNEL_12
4677 * @arg @ref LL_ADC_CHANNEL_13
4678 * @arg @ref LL_ADC_CHANNEL_14
4679 * @arg @ref LL_ADC_CHANNEL_15
4680 * @arg @ref LL_ADC_CHANNEL_16
4681 * @arg @ref LL_ADC_CHANNEL_17
4682 * @arg @ref LL_ADC_CHANNEL_18
4683 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4684 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4685 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4686 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4687 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4688 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4689 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4690 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4691 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4692 *
4693 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4694 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4695 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4696 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4697 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4698 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4699 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4700 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4701 * @param SamplingTime This parameter can be one of the following values:
4702 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
4703 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
4704 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
4705 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
4706 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
4707 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
4708 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
4709 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
4710 *
4711 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
4712 * can be replaced by 3.5 ADC clock cycles.
4713 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
4714 * @retval None
4715 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)4716 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
4717 {
4718 /* Set bits with content of parameter "SamplingTime" with bits position */
4719 /* in register and register position depending on parameter "Channel". */
4720 /* Parameter "Channel" is used with masks because containing */
4721 /* other bits reserved for other purpose. */
4722 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
4723
4724 MODIFY_REG(*preg,
4725 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
4726 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
4727 }
4728
4729 /**
4730 * @brief Get sampling time of the selected ADC channel
4731 * Unit: ADC clock cycles.
4732 * @note On this device, sampling time is on channel scope: independently
4733 * of channel mapped on ADC group regular or injected.
4734 * @note Conversion time is the addition of sampling time and processing time.
4735 * On this STM32 series, ADC processing time is:
4736 * - 12.5 ADC clock cycles at ADC resolution 12 bits
4737 * - 10.5 ADC clock cycles at ADC resolution 10 bits
4738 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4739 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4740 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
4741 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
4742 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
4743 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
4744 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
4745 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
4746 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
4747 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
4748 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
4749 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
4750 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
4751 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
4752 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
4753 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
4754 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
4755 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
4756 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
4757 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
4758 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
4759 * @param ADCx ADC instance
4760 * @param Channel This parameter can be one of the following values:
4761 * @arg @ref LL_ADC_CHANNEL_0
4762 * @arg @ref LL_ADC_CHANNEL_1 (7)
4763 * @arg @ref LL_ADC_CHANNEL_2 (7)
4764 * @arg @ref LL_ADC_CHANNEL_3 (7)
4765 * @arg @ref LL_ADC_CHANNEL_4 (7)
4766 * @arg @ref LL_ADC_CHANNEL_5 (7)
4767 * @arg @ref LL_ADC_CHANNEL_6
4768 * @arg @ref LL_ADC_CHANNEL_7
4769 * @arg @ref LL_ADC_CHANNEL_8
4770 * @arg @ref LL_ADC_CHANNEL_9
4771 * @arg @ref LL_ADC_CHANNEL_10
4772 * @arg @ref LL_ADC_CHANNEL_11
4773 * @arg @ref LL_ADC_CHANNEL_12
4774 * @arg @ref LL_ADC_CHANNEL_13
4775 * @arg @ref LL_ADC_CHANNEL_14
4776 * @arg @ref LL_ADC_CHANNEL_15
4777 * @arg @ref LL_ADC_CHANNEL_16
4778 * @arg @ref LL_ADC_CHANNEL_17
4779 * @arg @ref LL_ADC_CHANNEL_18
4780 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4781 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4782 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4783 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4784 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4785 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4786 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4787 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4788 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4789 *
4790 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4791 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4792 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4793 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4794 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4795 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4796 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4797 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4798 * @retval Returned value can be one of the following values:
4799 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
4800 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
4801 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
4802 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
4803 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
4804 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
4805 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
4806 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
4807 *
4808 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
4809 * can be replaced by 3.5 ADC clock cycles.
4810 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
4811 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)4812 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
4813 {
4814 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
4815
4816 return (uint32_t)(READ_BIT(*preg,
4817 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
4818 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
4819 );
4820 }
4821
4822 /**
4823 * @brief Set mode single-ended or differential input of the selected
4824 * ADC channel.
4825 * @note Channel ending is on channel scope: independently of channel mapped
4826 * on ADC group regular or injected.
4827 * In differential mode: Differential measurement is carried out
4828 * between the selected channel 'i' (positive input) and
4829 * channel 'i+1' (negative input). Only channel 'i' has to be
4830 * configured, channel 'i+1' is configured automatically.
4831 * @note Refer to Reference Manual to ensure the selected channel is
4832 * available in differential mode.
4833 * For example, internal channels (VrefInt, TempSensor, ...) are
4834 * not available in differential mode.
4835 * @note When configuring a channel 'i' in differential mode,
4836 * the channel 'i+1' is not usable separately.
4837 * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
4838 * are internally fixed to single-ended inputs configuration.
4839 * @note For ADC channels configured in differential mode, both inputs
4840 * should be biased at (Vref+)/2 +/-200mV.
4841 * (Vref+ is the analog voltage reference)
4842 * @note On this STM32 series, setting of this feature is conditioned to
4843 * ADC state:
4844 * ADC must be ADC disabled.
4845 * @note One or several values can be selected.
4846 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4847 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
4848 * @param ADCx ADC instance
4849 * @param Channel This parameter can be one of the following values:
4850 * @arg @ref LL_ADC_CHANNEL_1
4851 * @arg @ref LL_ADC_CHANNEL_2
4852 * @arg @ref LL_ADC_CHANNEL_3
4853 * @arg @ref LL_ADC_CHANNEL_4
4854 * @arg @ref LL_ADC_CHANNEL_5
4855 * @arg @ref LL_ADC_CHANNEL_6
4856 * @arg @ref LL_ADC_CHANNEL_7
4857 * @arg @ref LL_ADC_CHANNEL_8
4858 * @arg @ref LL_ADC_CHANNEL_9
4859 * @arg @ref LL_ADC_CHANNEL_10
4860 * @arg @ref LL_ADC_CHANNEL_11
4861 * @arg @ref LL_ADC_CHANNEL_12
4862 * @arg @ref LL_ADC_CHANNEL_13
4863 * @arg @ref LL_ADC_CHANNEL_14
4864 * @arg @ref LL_ADC_CHANNEL_15
4865 * @param SingleDiff This parameter can be a combination of the following values:
4866 * @arg @ref LL_ADC_SINGLE_ENDED
4867 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
4868 * @retval None
4869 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)4870 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
4871 {
4872 /* Bits of channels in single or differential mode are set only for */
4873 /* differential mode (for single mode, mask of bits allowed to be set is */
4874 /* shifted out of range of bits of channels in single or differential mode. */
4875 MODIFY_REG(ADCx->DIFSEL,
4876 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
4877 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
4878 }
4879
4880 /**
4881 * @brief Get mode single-ended or differential input of the selected
4882 * ADC channel.
4883 * @note When configuring a channel 'i' in differential mode,
4884 * the channel 'i+1' is not usable separately.
4885 * Therefore, to ensure a channel is configured in single-ended mode,
4886 * the configuration of channel itself and the channel 'i-1' must be
4887 * read back (to ensure that the selected channel channel has not been
4888 * configured in differential mode by the previous channel).
4889 * @note Refer to Reference Manual to ensure the selected channel is
4890 * available in differential mode.
4891 * For example, internal channels (VrefInt, TempSensor, ...) are
4892 * not available in differential mode.
4893 * @note When configuring a channel 'i' in differential mode,
4894 * the channel 'i+1' is not usable separately.
4895 * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
4896 * are internally fixed to single-ended inputs configuration.
4897 * @note One or several values can be selected. In this case, the value
4898 * returned is null if all channels are in single ended-mode.
4899 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4900 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
4901 * @param ADCx ADC instance
4902 * @param Channel This parameter can be a combination of the following values:
4903 * @arg @ref LL_ADC_CHANNEL_1
4904 * @arg @ref LL_ADC_CHANNEL_2
4905 * @arg @ref LL_ADC_CHANNEL_3
4906 * @arg @ref LL_ADC_CHANNEL_4
4907 * @arg @ref LL_ADC_CHANNEL_5
4908 * @arg @ref LL_ADC_CHANNEL_6
4909 * @arg @ref LL_ADC_CHANNEL_7
4910 * @arg @ref LL_ADC_CHANNEL_8
4911 * @arg @ref LL_ADC_CHANNEL_9
4912 * @arg @ref LL_ADC_CHANNEL_10
4913 * @arg @ref LL_ADC_CHANNEL_11
4914 * @arg @ref LL_ADC_CHANNEL_12
4915 * @arg @ref LL_ADC_CHANNEL_13
4916 * @arg @ref LL_ADC_CHANNEL_14
4917 * @arg @ref LL_ADC_CHANNEL_15
4918 * @retval 0: channel in single-ended mode, else: channel in differential mode
4919 */
LL_ADC_GetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel)4920 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
4921 {
4922 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
4923 }
4924
4925 /**
4926 * @}
4927 */
4928
4929 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
4930 * @{
4931 */
4932
4933 /**
4934 * @brief Set ADC analog watchdog monitored channels:
4935 * a single channel, multiple channels or all channels,
4936 * on ADC groups regular and-or injected.
4937 * @note Once monitored channels are selected, analog watchdog
4938 * is enabled.
4939 * @note In case of need to define a single channel to monitor
4940 * with analog watchdog from sequencer channel definition,
4941 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
4942 * @note On this STM32 series, there are 2 kinds of analog watchdog
4943 * instance:
4944 * - AWD standard (instance AWD1):
4945 * - channels monitored: can monitor 1 channel or all channels.
4946 * - groups monitored: ADC groups regular and-or injected.
4947 * - resolution: resolution is not limited (corresponds to
4948 * ADC resolution configured).
4949 * - AWD flexible (instances AWD2, AWD3):
4950 * - channels monitored: flexible on channels monitored, selection is
4951 * channel wise, from from 1 to all channels.
4952 * Specificity of this analog watchdog: Multiple channels can
4953 * be selected. For example:
4954 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4955 * - groups monitored: not selection possible (monitoring on both
4956 * groups regular and injected).
4957 * Channels selected are monitored on groups regular and injected:
4958 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4959 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4960 * - resolution: resolution is limited to 8 bits: if ADC resolution is
4961 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
4962 * the 2 LSB are ignored.
4963 * @note On this STM32 series, setting of this feature is conditioned to
4964 * ADC state:
4965 * ADC must be disabled or enabled without conversion on going
4966 * on either groups regular or injected.
4967 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
4968 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
4969 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
4970 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
4971 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
4972 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
4973 * @param ADCx ADC instance
4974 * @param AWDy This parameter can be one of the following values:
4975 * @arg @ref LL_ADC_AWD1
4976 * @arg @ref LL_ADC_AWD2
4977 * @arg @ref LL_ADC_AWD3
4978 * @param AWDChannelGroup This parameter can be one of the following values:
4979 * @arg @ref LL_ADC_AWD_DISABLE
4980 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
4981 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
4982 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
4983 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
4984 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
4985 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
4986 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
4987 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
4988 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
4989 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
4990 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
4991 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
4992 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
4993 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
4994 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
4995 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
4996 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
4997 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
4998 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
4999 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5000 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5001 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5002 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5003 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5004 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5005 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5006 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5007 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5008 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5009 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5010 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5011 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5012 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5013 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5014 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5015 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5016 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5017 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5018 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5019 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5020 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5021 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5022 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5023 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5024 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5025 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5026 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5027 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5028 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5029 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5030 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5031 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5032 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5033 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5034 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5035 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5036 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5037 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5038 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5039 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5040 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
5041 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
5042 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
5043 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
5044 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4)
5045 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
5046 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
5047 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
5048 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
5049 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5)
5050 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5)
5051 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5)
5052 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5)
5053 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5)
5054 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5)
5055 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6)
5056 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6)
5057 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6)
5058 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6)
5059 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6)
5060 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6)
5061 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6)
5062 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6)
5063 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6)
5064 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6)
5065 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6)
5066 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6)
5067 *
5068 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
5069 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
5070 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
5071 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
5072 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
5073 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
5074 * (6) On STM32L4, parameter available on devices with several ADC instances.
5075 * @retval None
5076 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)5077 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5078 {
5079 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5080 /* in register and register position depending on parameter "AWDy". */
5081 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5082 /* containing other bits reserved for other purpose. */
5083 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5084 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5085
5086 MODIFY_REG(*preg,
5087 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5088 AWDChannelGroup & AWDy);
5089 }
5090
5091 /**
5092 * @brief Get ADC analog watchdog monitored channel.
5093 * @note Usage of the returned channel number:
5094 * - To reinject this channel into another function LL_ADC_xxx:
5095 * the returned channel number is only partly formatted on definition
5096 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5097 * with parts of literals LL_ADC_CHANNEL_x or using
5098 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5099 * Then the selected literal LL_ADC_CHANNEL_x can be used
5100 * as parameter for another function.
5101 * - To get the channel number in decimal format:
5102 * process the returned value with the helper macro
5103 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5104 * Applicable only when the analog watchdog is set to monitor
5105 * one channel.
5106 * @note On this STM32 series, there are 2 kinds of analog watchdog
5107 * instance:
5108 * - AWD standard (instance AWD1):
5109 * - channels monitored: can monitor 1 channel or all channels.
5110 * - groups monitored: ADC groups regular and-or injected.
5111 * - resolution: resolution is not limited (corresponds to
5112 * ADC resolution configured).
5113 * - AWD flexible (instances AWD2, AWD3):
5114 * - channels monitored: flexible on channels monitored, selection is
5115 * channel wise, from from 1 to all channels.
5116 * Specificity of this analog watchdog: Multiple channels can
5117 * be selected. For example:
5118 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5119 * - groups monitored: not selection possible (monitoring on both
5120 * groups regular and injected).
5121 * Channels selected are monitored on groups regular and injected:
5122 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5123 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5124 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5125 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5126 * the 2 LSB are ignored.
5127 * @note On this STM32 series, setting of this feature is conditioned to
5128 * ADC state:
5129 * ADC must be disabled or enabled without conversion on going
5130 * on either groups regular or injected.
5131 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5132 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5133 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5134 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5135 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5136 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5137 * @param ADCx ADC instance
5138 * @param AWDy This parameter can be one of the following values:
5139 * @arg @ref LL_ADC_AWD1
5140 * @arg @ref LL_ADC_AWD2 (1)
5141 * @arg @ref LL_ADC_AWD3 (1)
5142 *
5143 * (1) On this AWD number, monitored channel can be retrieved
5144 * if only 1 channel is programmed (or none or all channels).
5145 * This function cannot retrieve monitored channel if
5146 * multiple channels are programmed simultaneously
5147 * by bitfield.
5148 * @retval Returned value can be one of the following values:
5149 * @arg @ref LL_ADC_AWD_DISABLE
5150 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5151 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5152 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5153 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5154 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5155 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5156 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5157 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5158 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5159 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5160 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5161 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5162 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5163 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5164 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5165 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5166 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5167 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5168 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5169 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5170 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5171 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5172 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5173 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5174 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5175 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5176 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5177 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5178 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5179 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5180 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5181 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5182 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5183 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5184 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5185 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5186 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5187 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5188 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5189 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5190 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5191 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5192 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5193 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5194 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5195 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5196 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5197 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5198 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5199 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5200 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5201 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5202 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5203 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5204 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5205 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5206 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5207 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5208 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5209 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5210 *
5211 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
5212 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy)5213 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
5214 {
5215 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5216 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5217
5218 uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK);
5219
5220 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
5221 /* (parameter value LL_ADC_AWD_DISABLE). */
5222 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5223 /* or a single channel. */
5224 if (AnalogWDMonitChannels != 0UL)
5225 {
5226 if (AWDy == LL_ADC_AWD1)
5227 {
5228 if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
5229 {
5230 /* AWD monitoring a group of channels */
5231 AnalogWDMonitChannels = ((AnalogWDMonitChannels
5232 | (ADC_AWD_CR23_CHANNEL_MASK)
5233 )
5234 & (~(ADC_CFGR_AWD1CH))
5235 );
5236 }
5237 else
5238 {
5239 /* AWD monitoring a single channel */
5240 AnalogWDMonitChannels = (AnalogWDMonitChannels
5241 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
5242 );
5243 }
5244 }
5245 else
5246 {
5247 if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
5248 {
5249 /* AWD monitoring a group of channels */
5250 AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
5251 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
5252 );
5253 }
5254 else
5255 {
5256 /* AWD monitoring a single channel */
5257 /* AWD monitoring a group of channels */
5258 AnalogWDMonitChannels = (AnalogWDMonitChannels
5259 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
5260 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
5261 );
5262 }
5263 }
5264 }
5265
5266 return AnalogWDMonitChannels;
5267 }
5268
5269 /**
5270 * @brief Set ADC analog watchdog thresholds value of both thresholds
5271 * high and low.
5272 * @note If value of only one threshold high or low must be set,
5273 * use function @ref LL_ADC_SetAnalogWDThresholds().
5274 * @note In case of ADC resolution different of 12 bits,
5275 * analog watchdog thresholds data require a specific shift.
5276 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5277 * @note On this STM32 series, there are 2 kinds of analog watchdog
5278 * instance:
5279 * - AWD standard (instance AWD1):
5280 * - channels monitored: can monitor 1 channel or all channels.
5281 * - groups monitored: ADC groups regular and-or injected.
5282 * - resolution: resolution is not limited (corresponds to
5283 * ADC resolution configured).
5284 * - AWD flexible (instances AWD2, AWD3):
5285 * - channels monitored: flexible on channels monitored, selection is
5286 * channel wise, from from 1 to all channels.
5287 * Specificity of this analog watchdog: Multiple channels can
5288 * be selected. For example:
5289 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5290 * - groups monitored: not selection possible (monitoring on both
5291 * groups regular and injected).
5292 * Channels selected are monitored on groups regular and injected:
5293 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5294 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5295 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5296 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5297 * the 2 LSB are ignored.
5298 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5299 * impacted: the comparison of analog watchdog thresholds is done on
5300 * oversampling final computation (after ratio and shift application):
5301 * ADC data register bitfield [15:4] (12 most significant bits).
5302 * @note On this STM32 series, setting of this feature is conditioned to
5303 * ADC state:
5304 * ADC must be disabled or enabled without conversion on going
5305 * on either groups regular or injected.
5306 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
5307 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
5308 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
5309 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
5310 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
5311 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
5312 * @param ADCx ADC instance
5313 * @param AWDy This parameter can be one of the following values:
5314 * @arg @ref LL_ADC_AWD1
5315 * @arg @ref LL_ADC_AWD2
5316 * @arg @ref LL_ADC_AWD3
5317 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
5318 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
5319 * @retval None
5320 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)5321 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
5322 uint32_t AWDThresholdLowValue)
5323 {
5324 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
5325 /* position in register and register position depending on parameter */
5326 /* "AWDy". */
5327 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
5328 /* containing other bits reserved for other purpose. */
5329 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5330
5331 MODIFY_REG(*preg,
5332 ADC_TR1_HT1 | ADC_TR1_LT1,
5333 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
5334 }
5335
5336 /**
5337 * @brief Set ADC analog watchdog threshold value of threshold
5338 * high or low.
5339 * @note If values of both thresholds high or low must be set,
5340 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
5341 * @note In case of ADC resolution different of 12 bits,
5342 * analog watchdog thresholds data require a specific shift.
5343 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5344 * @note On this STM32 series, there are 2 kinds of analog watchdog
5345 * instance:
5346 * - AWD standard (instance AWD1):
5347 * - channels monitored: can monitor 1 channel or all channels.
5348 * - groups monitored: ADC groups regular and-or injected.
5349 * - resolution: resolution is not limited (corresponds to
5350 * ADC resolution configured).
5351 * - AWD flexible (instances AWD2, AWD3):
5352 * - channels monitored: flexible on channels monitored, selection is
5353 * channel wise, from from 1 to all channels.
5354 * Specificity of this analog watchdog: Multiple channels can
5355 * be selected. For example:
5356 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5357 * - groups monitored: not selection possible (monitoring on both
5358 * groups regular and injected).
5359 * Channels selected are monitored on groups regular and injected:
5360 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5361 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5362 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5363 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5364 * the 2 LSB are ignored.
5365 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5366 * impacted: the comparison of analog watchdog thresholds is done on
5367 * oversampling final computation (after ratio and shift application):
5368 * ADC data register bitfield [15:4] (12 most significant bits).
5369 * @note On this STM32 series, setting of this feature is conditioned to
5370 * ADC state:
5371 * ADC must be disabled or enabled without conversion on going
5372 * on either ADC groups regular or injected.
5373 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
5374 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
5375 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
5376 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
5377 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
5378 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
5379 * @param ADCx ADC instance
5380 * @param AWDy This parameter can be one of the following values:
5381 * @arg @ref LL_ADC_AWD1
5382 * @arg @ref LL_ADC_AWD2
5383 * @arg @ref LL_ADC_AWD3
5384 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5385 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5386 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5387 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
5388 * @retval None
5389 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)5390 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
5391 uint32_t AWDThresholdValue)
5392 {
5393 /* Set bits with content of parameter "AWDThresholdValue" with bits */
5394 /* position in register and register position depending on parameters */
5395 /* "AWDThresholdsHighLow" and "AWDy". */
5396 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5397 /* containing other bits reserved for other purpose. */
5398 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
5399 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5400
5401 MODIFY_REG(*preg,
5402 AWDThresholdsHighLow,
5403 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
5404 }
5405
5406 /**
5407 * @brief Get ADC analog watchdog threshold value of threshold high,
5408 * threshold low or raw data with ADC thresholds high and low
5409 * concatenated.
5410 * @note If raw data with ADC thresholds high and low is retrieved,
5411 * the data of each threshold high or low can be isolated
5412 * using helper macro:
5413 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
5414 * @note In case of ADC resolution different of 12 bits,
5415 * analog watchdog thresholds data require a specific shift.
5416 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
5417 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
5418 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
5419 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
5420 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
5421 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
5422 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
5423 * @param ADCx ADC instance
5424 * @param AWDy This parameter can be one of the following values:
5425 * @arg @ref LL_ADC_AWD1
5426 * @arg @ref LL_ADC_AWD2
5427 * @arg @ref LL_ADC_AWD3
5428 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5429 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5430 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5431 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
5432 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
5433 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)5434 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
5435 {
5436 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
5437 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5438
5439 return (uint32_t)(READ_BIT(*preg,
5440 (AWDThresholdsHighLow | ADC_TR1_LT1))
5441 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
5442 & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
5443 }
5444
5445 /**
5446 * @}
5447 */
5448
5449 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
5450 * @{
5451 */
5452
5453 /**
5454 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
5455 * (availability of ADC group injected depends on STM32 families).
5456 * @note If both groups regular and injected are selected,
5457 * specify behavior of ADC group injected interrupting
5458 * group regular: when ADC group injected is triggered,
5459 * the oversampling on ADC group regular is either
5460 * temporary stopped and continued, or resumed from start
5461 * (oversampler buffer reset).
5462 * @note On this STM32 series, setting of this feature is conditioned to
5463 * ADC state:
5464 * ADC must be disabled or enabled without conversion on going
5465 * on either groups regular or injected.
5466 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
5467 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
5468 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
5469 * @param ADCx ADC instance
5470 * @param OvsScope This parameter can be one of the following values:
5471 * @arg @ref LL_ADC_OVS_DISABLE
5472 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
5473 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
5474 * @arg @ref LL_ADC_OVS_GRP_INJECTED
5475 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
5476 * @retval None
5477 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)5478 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
5479 {
5480 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
5481 }
5482
5483 /**
5484 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
5485 * (availability of ADC group injected depends on STM32 families).
5486 * @note If both groups regular and injected are selected,
5487 * specify behavior of ADC group injected interrupting
5488 * group regular: when ADC group injected is triggered,
5489 * the oversampling on ADC group regular is either
5490 * temporary stopped and continued, or resumed from start
5491 * (oversampler buffer reset).
5492 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
5493 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
5494 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
5495 * @param ADCx ADC instance
5496 * @retval Returned value can be one of the following values:
5497 * @arg @ref LL_ADC_OVS_DISABLE
5498 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
5499 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
5500 * @arg @ref LL_ADC_OVS_GRP_INJECTED
5501 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
5502 */
LL_ADC_GetOverSamplingScope(ADC_TypeDef * ADCx)5503 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
5504 {
5505 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
5506 }
5507
5508 /**
5509 * @brief Set ADC oversampling discontinuous mode (triggered mode)
5510 * on the selected ADC group.
5511 * @note Number of oversampled conversions are done either in:
5512 * - continuous mode (all conversions of oversampling ratio
5513 * are done from 1 trigger)
5514 * - discontinuous mode (each conversion of oversampling ratio
5515 * needs a trigger)
5516 * @note On this STM32 series, setting of this feature is conditioned to
5517 * ADC state:
5518 * ADC must be disabled or enabled without conversion on going
5519 * on group regular.
5520 * @note On this STM32 series, oversampling discontinuous mode
5521 * (triggered mode) can be used only when oversampling is
5522 * set on group regular only and in resumed mode.
5523 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
5524 * @param ADCx ADC instance
5525 * @param OverSamplingDiscont This parameter can be one of the following values:
5526 * @arg @ref LL_ADC_OVS_REG_CONT
5527 * @arg @ref LL_ADC_OVS_REG_DISCONT
5528 * @retval None
5529 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)5530 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
5531 {
5532 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
5533 }
5534
5535 /**
5536 * @brief Get ADC oversampling discontinuous mode (triggered mode)
5537 * on the selected ADC group.
5538 * @note Number of oversampled conversions are done either in:
5539 * - continuous mode (all conversions of oversampling ratio
5540 * are done from 1 trigger)
5541 * - discontinuous mode (each conversion of oversampling ratio
5542 * needs a trigger)
5543 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
5544 * @param ADCx ADC instance
5545 * @retval Returned value can be one of the following values:
5546 * @arg @ref LL_ADC_OVS_REG_CONT
5547 * @arg @ref LL_ADC_OVS_REG_DISCONT
5548 */
LL_ADC_GetOverSamplingDiscont(ADC_TypeDef * ADCx)5549 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
5550 {
5551 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
5552 }
5553
5554 /**
5555 * @brief Set ADC oversampling
5556 * (impacting both ADC groups regular and injected)
5557 * @note This function set the 2 items of oversampling configuration:
5558 * - ratio
5559 * - shift
5560 * @note On this STM32 series, setting of this feature is conditioned to
5561 * ADC state:
5562 * ADC must be disabled or enabled without conversion on going
5563 * on either groups regular or injected.
5564 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
5565 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
5566 * @param ADCx ADC instance
5567 * @param Ratio This parameter can be one of the following values:
5568 * @arg @ref LL_ADC_OVS_RATIO_2
5569 * @arg @ref LL_ADC_OVS_RATIO_4
5570 * @arg @ref LL_ADC_OVS_RATIO_8
5571 * @arg @ref LL_ADC_OVS_RATIO_16
5572 * @arg @ref LL_ADC_OVS_RATIO_32
5573 * @arg @ref LL_ADC_OVS_RATIO_64
5574 * @arg @ref LL_ADC_OVS_RATIO_128
5575 * @arg @ref LL_ADC_OVS_RATIO_256
5576 * @param Shift This parameter can be one of the following values:
5577 * @arg @ref LL_ADC_OVS_SHIFT_NONE
5578 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
5579 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
5580 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
5581 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
5582 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
5583 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
5584 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
5585 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
5586 * @retval None
5587 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)5588 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
5589 {
5590 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
5591 }
5592
5593 /**
5594 * @brief Get ADC oversampling ratio
5595 * (impacting both ADC groups regular and injected)
5596 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
5597 * @param ADCx ADC instance
5598 * @retval Ratio This parameter can be one of the following values:
5599 * @arg @ref LL_ADC_OVS_RATIO_2
5600 * @arg @ref LL_ADC_OVS_RATIO_4
5601 * @arg @ref LL_ADC_OVS_RATIO_8
5602 * @arg @ref LL_ADC_OVS_RATIO_16
5603 * @arg @ref LL_ADC_OVS_RATIO_32
5604 * @arg @ref LL_ADC_OVS_RATIO_64
5605 * @arg @ref LL_ADC_OVS_RATIO_128
5606 * @arg @ref LL_ADC_OVS_RATIO_256
5607 */
LL_ADC_GetOverSamplingRatio(ADC_TypeDef * ADCx)5608 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
5609 {
5610 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
5611 }
5612
5613 /**
5614 * @brief Get ADC oversampling shift
5615 * (impacting both ADC groups regular and injected)
5616 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
5617 * @param ADCx ADC instance
5618 * @retval Shift This parameter can be one of the following values:
5619 * @arg @ref LL_ADC_OVS_SHIFT_NONE
5620 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
5621 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
5622 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
5623 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
5624 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
5625 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
5626 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
5627 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
5628 */
LL_ADC_GetOverSamplingShift(ADC_TypeDef * ADCx)5629 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
5630 {
5631 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
5632 }
5633
5634 /**
5635 * @}
5636 */
5637
5638 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
5639 * @{
5640 */
5641
5642 #if defined(ADC_MULTIMODE_SUPPORT)
5643 /**
5644 * @brief Set ADC multimode configuration to operate in independent mode
5645 * or multimode (for devices with several ADC instances).
5646 * @note If multimode configuration: the selected ADC instance is
5647 * either master or slave depending on hardware.
5648 * Refer to reference manual.
5649 * @note On this STM32 series, setting of this feature is conditioned to
5650 * ADC state:
5651 * All ADC instances of the ADC common group must be disabled.
5652 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5653 * ADC instance or by using helper macro
5654 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5655 * @rmtoll CCR DUAL LL_ADC_SetMultimode
5656 * @param ADCxy_COMMON ADC common instance
5657 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5658 * @param Multimode This parameter can be one of the following values:
5659 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5660 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5661 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5662 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5663 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5664 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5665 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5666 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5667 * @retval None
5668 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)5669 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
5670 {
5671 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
5672 }
5673
5674 /**
5675 * @brief Get ADC multimode configuration to operate in independent mode
5676 * or multimode (for devices with several ADC instances).
5677 * @note If multimode configuration: the selected ADC instance is
5678 * either master or slave depending on hardware.
5679 * Refer to reference manual.
5680 * @rmtoll CCR DUAL LL_ADC_GetMultimode
5681 * @param ADCxy_COMMON ADC common instance
5682 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5683 * @retval Returned value can be one of the following values:
5684 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5685 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5686 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5687 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5688 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5689 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5690 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5691 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5692 */
LL_ADC_GetMultimode(ADC_Common_TypeDef * ADCxy_COMMON)5693 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
5694 {
5695 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
5696 }
5697
5698 /**
5699 * @brief Set ADC multimode conversion data transfer: no transfer
5700 * or transfer by DMA.
5701 * @note If ADC multimode transfer by DMA is not selected:
5702 * each ADC uses its own DMA channel, with its individual
5703 * DMA transfer settings.
5704 * If ADC multimode transfer by DMA is selected:
5705 * One DMA channel is used for both ADC (DMA of ADC master)
5706 * Specifies the DMA requests mode:
5707 * - Limited mode (One shot mode): DMA transfer requests are stopped
5708 * when number of DMA data transfers (number of
5709 * ADC conversions) is reached.
5710 * This ADC mode is intended to be used with DMA mode non-circular.
5711 * - Unlimited mode: DMA transfer requests are unlimited,
5712 * whatever number of DMA data transfers (number of
5713 * ADC conversions).
5714 * This ADC mode is intended to be used with DMA mode circular.
5715 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5716 * mode non-circular:
5717 * when DMA transfers size will be reached, DMA will stop transfers of
5718 * ADC conversions data ADC will raise an overrun error
5719 * (overrun flag and interruption if enabled).
5720 * @note How to retrieve multimode conversion data:
5721 * Whatever multimode transfer by DMA setting: using function
5722 * @ref LL_ADC_REG_ReadMultiConversionData32().
5723 * If ADC multimode transfer by DMA is selected: conversion data
5724 * is a raw data with ADC master and slave concatenated.
5725 * A macro is available to get the conversion data of
5726 * ADC master or ADC slave: see helper macro
5727 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5728 * @note On this STM32 series, setting of this feature is conditioned to
5729 * ADC state:
5730 * All ADC instances of the ADC common group must be disabled
5731 * or enabled without conversion on going on group regular.
5732 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
5733 * CCR DMACFG LL_ADC_SetMultiDMATransfer
5734 * @param ADCxy_COMMON ADC common instance
5735 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5736 * @param MultiDMATransfer This parameter can be one of the following values:
5737 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
5738 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
5739 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
5740 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
5741 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
5742 * @retval None
5743 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)5744 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
5745 {
5746 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
5747 }
5748
5749 /**
5750 * @brief Get ADC multimode conversion data transfer: no transfer
5751 * or transfer by DMA.
5752 * @note If ADC multimode transfer by DMA is not selected:
5753 * each ADC uses its own DMA channel, with its individual
5754 * DMA transfer settings.
5755 * If ADC multimode transfer by DMA is selected:
5756 * One DMA channel is used for both ADC (DMA of ADC master)
5757 * Specifies the DMA requests mode:
5758 * - Limited mode (One shot mode): DMA transfer requests are stopped
5759 * when number of DMA data transfers (number of
5760 * ADC conversions) is reached.
5761 * This ADC mode is intended to be used with DMA mode non-circular.
5762 * - Unlimited mode: DMA transfer requests are unlimited,
5763 * whatever number of DMA data transfers (number of
5764 * ADC conversions).
5765 * This ADC mode is intended to be used with DMA mode circular.
5766 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5767 * mode non-circular:
5768 * when DMA transfers size will be reached, DMA will stop transfers of
5769 * ADC conversions data ADC will raise an overrun error
5770 * (overrun flag and interruption if enabled).
5771 * @note How to retrieve multimode conversion data:
5772 * Whatever multimode transfer by DMA setting: using function
5773 * @ref LL_ADC_REG_ReadMultiConversionData32().
5774 * If ADC multimode transfer by DMA is selected: conversion data
5775 * is a raw data with ADC master and slave concatenated.
5776 * A macro is available to get the conversion data of
5777 * ADC master or ADC slave: see helper macro
5778 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5779 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
5780 * CCR DMACFG LL_ADC_GetMultiDMATransfer
5781 * @param ADCxy_COMMON ADC common instance
5782 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5783 * @retval Returned value can be one of the following values:
5784 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
5785 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
5786 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
5787 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
5788 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
5789 */
LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON)5790 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
5791 {
5792 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
5793 }
5794
5795 /**
5796 * @brief Set ADC multimode delay between 2 sampling phases.
5797 * @note The sampling delay range depends on ADC resolution:
5798 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
5799 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
5800 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
5801 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
5802 * @note On this STM32 series, setting of this feature is conditioned to
5803 * ADC state:
5804 * All ADC instances of the ADC common group must be disabled.
5805 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5806 * ADC instance or by using helper macro helper macro
5807 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5808 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
5809 * @param ADCxy_COMMON ADC common instance
5810 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5811 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
5812 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
5813 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
5814 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
5815 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
5816 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
5817 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
5818 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
5819 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
5820 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
5821 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
5822 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
5823 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
5824 *
5825 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
5826 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
5827 * (3) Parameter available only if ADC resolution is 12 bits.
5828 * @retval None
5829 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)5830 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
5831 {
5832 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
5833 }
5834
5835 /**
5836 * @brief Get ADC multimode delay between 2 sampling phases.
5837 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
5838 * @param ADCxy_COMMON ADC common instance
5839 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5840 * @retval Returned value can be one of the following values:
5841 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
5842 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
5843 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
5844 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
5845 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
5846 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
5847 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
5848 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
5849 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
5850 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
5851 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
5852 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
5853 *
5854 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
5855 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
5856 * (3) Parameter available only if ADC resolution is 12 bits.
5857 */
LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON)5858 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
5859 {
5860 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
5861 }
5862 #endif /* ADC_MULTIMODE_SUPPORT */
5863
5864 /**
5865 * @}
5866 */
5867 /** @defgroup ADC_LL_EF_Configuration_Leg_Functions Configuration of ADC alternate functions name
5868 * @{
5869 */
5870 /* Old functions name kept for legacy purpose, to be replaced by the */
5871 /* current functions name. */
LL_ADC_REG_SetTrigSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)5872 __STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
5873 {
5874 LL_ADC_REG_SetTriggerSource(ADCx, TriggerSource);
5875 }
LL_ADC_INJ_SetTrigSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)5876 __STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
5877 {
5878 LL_ADC_INJ_SetTriggerSource(ADCx, TriggerSource);
5879 }
5880
5881 /**
5882 * @}
5883 */
5884
5885 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
5886 * @{
5887 */
5888
5889 /**
5890 * @brief Put ADC instance in deep power down state.
5891 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
5892 * state, the internal analog calibration is lost. After exiting from
5893 * deep power down, calibration must be relaunched or calibration factor
5894 * (preliminarily saved) must be set back into calibration register.
5895 * @note On this STM32 series, setting of this feature is conditioned to
5896 * ADC state:
5897 * ADC must be ADC disabled.
5898 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
5899 * @param ADCx ADC instance
5900 * @retval None
5901 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)5902 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
5903 {
5904 /* Note: Write register with some additional bits forced to state reset */
5905 /* instead of modifying only the selected bit for this function, */
5906 /* to not interfere with bits with HW property "rs". */
5907 MODIFY_REG(ADCx->CR,
5908 ADC_CR_BITS_PROPERTY_RS,
5909 ADC_CR_DEEPPWD);
5910 }
5911
5912 /**
5913 * @brief Disable ADC deep power down mode.
5914 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
5915 * state, the internal analog calibration is lost. After exiting from
5916 * deep power down, calibration must be relaunched or calibration factor
5917 * (preliminarily saved) must be set back into calibration register.
5918 * @note On this STM32 series, setting of this feature is conditioned to
5919 * ADC state:
5920 * ADC must be ADC disabled.
5921 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
5922 * @param ADCx ADC instance
5923 * @retval None
5924 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)5925 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
5926 {
5927 /* Note: Write register with some additional bits forced to state reset */
5928 /* instead of modifying only the selected bit for this function, */
5929 /* to not interfere with bits with HW property "rs". */
5930 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
5931 }
5932
5933 /**
5934 * @brief Get the selected ADC instance deep power down state.
5935 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
5936 * @param ADCx ADC instance
5937 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
5938 */
LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef * ADCx)5939 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
5940 {
5941 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
5942 }
5943
5944 /**
5945 * @brief Enable ADC instance internal voltage regulator.
5946 * @note On this STM32 series, after ADC internal voltage regulator enable,
5947 * a delay for ADC internal voltage regulator stabilization
5948 * is required before performing a ADC calibration or ADC enable.
5949 * Refer to device datasheet, parameter tADCVREG_STUP.
5950 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
5951 * @note On this STM32 series, setting of this feature is conditioned to
5952 * ADC state:
5953 * ADC must be ADC disabled.
5954 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
5955 * @param ADCx ADC instance
5956 * @retval None
5957 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)5958 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
5959 {
5960 /* Note: Write register with some additional bits forced to state reset */
5961 /* instead of modifying only the selected bit for this function, */
5962 /* to not interfere with bits with HW property "rs". */
5963 MODIFY_REG(ADCx->CR,
5964 ADC_CR_BITS_PROPERTY_RS,
5965 ADC_CR_ADVREGEN);
5966 }
5967
5968 /**
5969 * @brief Disable ADC internal voltage regulator.
5970 * @note On this STM32 series, setting of this feature is conditioned to
5971 * ADC state:
5972 * ADC must be ADC disabled.
5973 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
5974 * @param ADCx ADC instance
5975 * @retval None
5976 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)5977 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
5978 {
5979 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
5980 }
5981
5982 /**
5983 * @brief Get the selected ADC instance internal voltage regulator state.
5984 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
5985 * @param ADCx ADC instance
5986 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
5987 */
LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef * ADCx)5988 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
5989 {
5990 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
5991 }
5992
5993 /**
5994 * @brief Enable the selected ADC instance.
5995 * @note On this STM32 series, after ADC enable, a delay for
5996 * ADC internal analog stabilization is required before performing a
5997 * ADC conversion start.
5998 * Refer to device datasheet, parameter tSTAB.
5999 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6000 * is enabled and when conversion clock is active.
6001 * (not only core clock: this ADC has a dual clock domain)
6002 * @note On this STM32 series, setting of this feature is conditioned to
6003 * ADC state:
6004 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
6005 * @rmtoll CR ADEN LL_ADC_Enable
6006 * @param ADCx ADC instance
6007 * @retval None
6008 */
LL_ADC_Enable(ADC_TypeDef * ADCx)6009 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6010 {
6011 /* Note: Write register with some additional bits forced to state reset */
6012 /* instead of modifying only the selected bit for this function, */
6013 /* to not interfere with bits with HW property "rs". */
6014 MODIFY_REG(ADCx->CR,
6015 ADC_CR_BITS_PROPERTY_RS,
6016 ADC_CR_ADEN);
6017 }
6018
6019 /**
6020 * @brief Disable the selected ADC instance.
6021 * @note On this STM32 series, setting of this feature is conditioned to
6022 * ADC state:
6023 * ADC must be not disabled. Must be enabled without conversion on going
6024 * on either groups regular or injected.
6025 * @rmtoll CR ADDIS LL_ADC_Disable
6026 * @param ADCx ADC instance
6027 * @retval None
6028 */
LL_ADC_Disable(ADC_TypeDef * ADCx)6029 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6030 {
6031 /* Note: Write register with some additional bits forced to state reset */
6032 /* instead of modifying only the selected bit for this function, */
6033 /* to not interfere with bits with HW property "rs". */
6034 MODIFY_REG(ADCx->CR,
6035 ADC_CR_BITS_PROPERTY_RS,
6036 ADC_CR_ADDIS);
6037 }
6038
6039 /**
6040 * @brief Get the selected ADC instance enable state.
6041 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6042 * is enabled and when conversion clock is active.
6043 * (not only core clock: this ADC has a dual clock domain)
6044 * @rmtoll CR ADEN LL_ADC_IsEnabled
6045 * @param ADCx ADC instance
6046 * @retval 0: ADC is disabled, 1: ADC is enabled.
6047 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)6048 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
6049 {
6050 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6051 }
6052
6053 /**
6054 * @brief Get the selected ADC instance disable state.
6055 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
6056 * @param ADCx ADC instance
6057 * @retval 0: no ADC disable command on going.
6058 */
LL_ADC_IsDisableOngoing(ADC_TypeDef * ADCx)6059 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
6060 {
6061 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6062 }
6063
6064 /**
6065 * @brief Start ADC calibration in the mode single-ended
6066 * or differential (for devices with differential mode available).
6067 * @note On this STM32 series, a minimum number of ADC clock cycles
6068 * are required between ADC end of calibration and ADC enable.
6069 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6070 * @note For devices with differential mode available:
6071 * Calibration of offset is specific to each of
6072 * single-ended and differential modes
6073 * (calibration run must be performed for each of these
6074 * differential modes, if used afterwards and if the application
6075 * requires their calibration).
6076 * @note On this STM32 series, setting of this feature is conditioned to
6077 * ADC state:
6078 * ADC must be ADC disabled.
6079 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6080 * CR ADCALDIF LL_ADC_StartCalibration
6081 * @param ADCx ADC instance
6082 * @param SingleDiff This parameter can be one of the following values:
6083 * @arg @ref LL_ADC_SINGLE_ENDED
6084 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6085 * @retval None
6086 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t SingleDiff)6087 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
6088 {
6089 /* Note: Write register with some additional bits forced to state reset */
6090 /* instead of modifying only the selected bit for this function, */
6091 /* to not interfere with bits with HW property "rs". */
6092 MODIFY_REG(ADCx->CR,
6093 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6094 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6095 }
6096
6097 /**
6098 * @brief Get ADC calibration state.
6099 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
6100 * @param ADCx ADC instance
6101 * @retval 0: calibration complete, 1: calibration in progress.
6102 */
LL_ADC_IsCalibrationOnGoing(ADC_TypeDef * ADCx)6103 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
6104 {
6105 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6106 }
6107
6108 /**
6109 * @}
6110 */
6111
6112 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
6113 * @{
6114 */
6115
6116 /**
6117 * @brief Start ADC group regular conversion.
6118 * @note On this STM32 series, this function is relevant for both
6119 * internal trigger (SW start) and external trigger:
6120 * - If ADC trigger has been set to software start, ADC conversion
6121 * starts immediately.
6122 * - If ADC trigger has been set to external trigger, ADC conversion
6123 * will start at next trigger event (on the selected trigger edge)
6124 * following the ADC start conversion command.
6125 * @note On this STM32 series, setting of this feature is conditioned to
6126 * ADC state:
6127 * ADC must be enabled without conversion on going on group regular,
6128 * without conversion stop command on going on group regular,
6129 * without ADC disable command on going.
6130 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
6131 * @param ADCx ADC instance
6132 * @retval None
6133 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)6134 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6135 {
6136 /* Note: Write register with some additional bits forced to state reset */
6137 /* instead of modifying only the selected bit for this function, */
6138 /* to not interfere with bits with HW property "rs". */
6139 MODIFY_REG(ADCx->CR,
6140 ADC_CR_BITS_PROPERTY_RS,
6141 ADC_CR_ADSTART);
6142 }
6143
6144 /**
6145 * @brief Stop ADC group regular conversion.
6146 * @note On this STM32 series, setting of this feature is conditioned to
6147 * ADC state:
6148 * ADC must be enabled with conversion on going on group regular,
6149 * without ADC disable command on going.
6150 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
6151 * @param ADCx ADC instance
6152 * @retval None
6153 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)6154 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6155 {
6156 /* Note: Write register with some additional bits forced to state reset */
6157 /* instead of modifying only the selected bit for this function, */
6158 /* to not interfere with bits with HW property "rs". */
6159 MODIFY_REG(ADCx->CR,
6160 ADC_CR_BITS_PROPERTY_RS,
6161 ADC_CR_ADSTP);
6162 }
6163
6164 /**
6165 * @brief Get ADC group regular conversion state.
6166 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6167 * @param ADCx ADC instance
6168 * @retval 0: no conversion is on going on ADC group regular.
6169 */
LL_ADC_REG_IsConversionOngoing(ADC_TypeDef * ADCx)6170 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
6171 {
6172 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6173 }
6174
6175 /**
6176 * @brief Get ADC group regular command of conversion stop state
6177 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6178 * @param ADCx ADC instance
6179 * @retval 0: no command of conversion stop is on going on ADC group regular.
6180 */
LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef * ADCx)6181 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6182 {
6183 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
6184 }
6185
6186 /**
6187 * @brief Get ADC group regular conversion data, range fit for
6188 * all ADC configurations: all ADC resolutions and
6189 * all oversampling increased data width (for devices
6190 * with feature oversampling).
6191 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6192 * @param ADCx ADC instance
6193 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6194 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)6195 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
6196 {
6197 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6198 }
6199
6200 /**
6201 * @brief Get ADC group regular conversion data, range fit for
6202 * ADC resolution 12 bits.
6203 * @note For devices with feature oversampling: Oversampling
6204 * can increase data width, function for extended range
6205 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6206 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
6207 * @param ADCx ADC instance
6208 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6209 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)6210 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
6211 {
6212 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6213 }
6214
6215 /**
6216 * @brief Get ADC group regular conversion data, range fit for
6217 * ADC resolution 10 bits.
6218 * @note For devices with feature oversampling: Oversampling
6219 * can increase data width, function for extended range
6220 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6221 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
6222 * @param ADCx ADC instance
6223 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6224 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)6225 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
6226 {
6227 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6228 }
6229
6230 /**
6231 * @brief Get ADC group regular conversion data, range fit for
6232 * ADC resolution 8 bits.
6233 * @note For devices with feature oversampling: Oversampling
6234 * can increase data width, function for extended range
6235 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6236 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
6237 * @param ADCx ADC instance
6238 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6239 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)6240 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
6241 {
6242 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6243 }
6244
6245 /**
6246 * @brief Get ADC group regular conversion data, range fit for
6247 * ADC resolution 6 bits.
6248 * @note For devices with feature oversampling: Oversampling
6249 * can increase data width, function for extended range
6250 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6251 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
6252 * @param ADCx ADC instance
6253 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6254 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)6255 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
6256 {
6257 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6258 }
6259
6260 #if defined(ADC_MULTIMODE_SUPPORT)
6261 /**
6262 * @brief Get ADC multimode conversion data of ADC master, ADC slave
6263 * or raw data with ADC master and slave concatenated.
6264 * @note If raw data with ADC master and slave concatenated is retrieved,
6265 * a macro is available to get the conversion data of
6266 * ADC master or ADC slave: see helper macro
6267 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6268 * (however this macro is mainly intended for multimode
6269 * transfer by DMA, because this function can do the same
6270 * by getting multimode conversion data of ADC master or ADC slave
6271 * separately).
6272 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
6273 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
6274 * @param ADCxy_COMMON ADC common instance
6275 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6276 * @param ConversionData This parameter can be one of the following values:
6277 * @arg @ref LL_ADC_MULTI_MASTER
6278 * @arg @ref LL_ADC_MULTI_SLAVE
6279 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
6280 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6281 */
LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)6282 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
6283 {
6284 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
6285 ConversionData)
6286 >> (POSITION_VAL(ConversionData) & 0x1FUL)
6287 );
6288 }
6289 #endif /* ADC_MULTIMODE_SUPPORT */
6290
6291 /**
6292 * @}
6293 */
6294
6295 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
6296 * @{
6297 */
6298
6299 /**
6300 * @brief Start ADC group injected conversion.
6301 * @note On this STM32 series, this function is relevant for both
6302 * internal trigger (SW start) and external trigger:
6303 * - If ADC trigger has been set to software start, ADC conversion
6304 * starts immediately.
6305 * - If ADC trigger has been set to external trigger, ADC conversion
6306 * will start at next trigger event (on the selected trigger edge)
6307 * following the ADC start conversion command.
6308 * @note On this STM32 series, setting of this feature is conditioned to
6309 * ADC state:
6310 * ADC must be enabled without conversion on going on group injected,
6311 * without conversion stop command on going on group injected,
6312 * without ADC disable command on going.
6313 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
6314 * @param ADCx ADC instance
6315 * @retval None
6316 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)6317 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
6318 {
6319 /* Note: Write register with some additional bits forced to state reset */
6320 /* instead of modifying only the selected bit for this function, */
6321 /* to not interfere with bits with HW property "rs". */
6322 MODIFY_REG(ADCx->CR,
6323 ADC_CR_BITS_PROPERTY_RS,
6324 ADC_CR_JADSTART);
6325 }
6326
6327 /**
6328 * @brief Stop ADC group injected conversion.
6329 * @note On this STM32 series, setting of this feature is conditioned to
6330 * ADC state:
6331 * ADC must be enabled with conversion on going on group injected,
6332 * without ADC disable command on going.
6333 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
6334 * @param ADCx ADC instance
6335 * @retval None
6336 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)6337 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
6338 {
6339 /* Note: Write register with some additional bits forced to state reset */
6340 /* instead of modifying only the selected bit for this function, */
6341 /* to not interfere with bits with HW property "rs". */
6342 MODIFY_REG(ADCx->CR,
6343 ADC_CR_BITS_PROPERTY_RS,
6344 ADC_CR_JADSTP);
6345 }
6346
6347 /**
6348 * @brief Get ADC group injected conversion state.
6349 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
6350 * @param ADCx ADC instance
6351 * @retval 0: no conversion is on going on ADC group injected.
6352 */
LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef * ADCx)6353 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
6354 {
6355 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
6356 }
6357
6358 /**
6359 * @brief Get ADC group injected command of conversion stop state
6360 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
6361 * @param ADCx ADC instance
6362 * @retval 0: no command of conversion stop is on going on ADC group injected.
6363 */
LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef * ADCx)6364 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6365 {
6366 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
6367 }
6368
6369 /**
6370 * @brief Get ADC group injected conversion data, range fit for
6371 * all ADC configurations: all ADC resolutions and
6372 * all oversampling increased data width (for devices
6373 * with feature oversampling).
6374 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
6375 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
6376 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
6377 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
6378 * @param ADCx ADC instance
6379 * @param Rank This parameter can be one of the following values:
6380 * @arg @ref LL_ADC_INJ_RANK_1
6381 * @arg @ref LL_ADC_INJ_RANK_2
6382 * @arg @ref LL_ADC_INJ_RANK_3
6383 * @arg @ref LL_ADC_INJ_RANK_4
6384 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6385 */
LL_ADC_INJ_ReadConversionData32(ADC_TypeDef * ADCx,uint32_t Rank)6386 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
6387 {
6388 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6389
6390 return (uint32_t)(READ_BIT(*preg,
6391 ADC_JDR1_JDATA)
6392 );
6393 }
6394
6395 /**
6396 * @brief Get ADC group injected conversion data, range fit for
6397 * ADC resolution 12 bits.
6398 * @note For devices with feature oversampling: Oversampling
6399 * can increase data width, function for extended range
6400 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6401 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
6402 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
6403 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
6404 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
6405 * @param ADCx ADC instance
6406 * @param Rank This parameter can be one of the following values:
6407 * @arg @ref LL_ADC_INJ_RANK_1
6408 * @arg @ref LL_ADC_INJ_RANK_2
6409 * @arg @ref LL_ADC_INJ_RANK_3
6410 * @arg @ref LL_ADC_INJ_RANK_4
6411 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6412 */
LL_ADC_INJ_ReadConversionData12(ADC_TypeDef * ADCx,uint32_t Rank)6413 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
6414 {
6415 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6416
6417 return (uint16_t)(READ_BIT(*preg,
6418 ADC_JDR1_JDATA)
6419 );
6420 }
6421
6422 /**
6423 * @brief Get ADC group injected conversion data, range fit for
6424 * ADC resolution 10 bits.
6425 * @note For devices with feature oversampling: Oversampling
6426 * can increase data width, function for extended range
6427 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6428 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
6429 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
6430 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
6431 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
6432 * @param ADCx ADC instance
6433 * @param Rank This parameter can be one of the following values:
6434 * @arg @ref LL_ADC_INJ_RANK_1
6435 * @arg @ref LL_ADC_INJ_RANK_2
6436 * @arg @ref LL_ADC_INJ_RANK_3
6437 * @arg @ref LL_ADC_INJ_RANK_4
6438 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6439 */
LL_ADC_INJ_ReadConversionData10(ADC_TypeDef * ADCx,uint32_t Rank)6440 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
6441 {
6442 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6443
6444 return (uint16_t)(READ_BIT(*preg,
6445 ADC_JDR1_JDATA)
6446 );
6447 }
6448
6449 /**
6450 * @brief Get ADC group injected conversion data, range fit for
6451 * ADC resolution 8 bits.
6452 * @note For devices with feature oversampling: Oversampling
6453 * can increase data width, function for extended range
6454 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6455 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
6456 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
6457 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
6458 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
6459 * @param ADCx ADC instance
6460 * @param Rank This parameter can be one of the following values:
6461 * @arg @ref LL_ADC_INJ_RANK_1
6462 * @arg @ref LL_ADC_INJ_RANK_2
6463 * @arg @ref LL_ADC_INJ_RANK_3
6464 * @arg @ref LL_ADC_INJ_RANK_4
6465 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6466 */
LL_ADC_INJ_ReadConversionData8(ADC_TypeDef * ADCx,uint32_t Rank)6467 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
6468 {
6469 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6470
6471 return (uint8_t)(READ_BIT(*preg,
6472 ADC_JDR1_JDATA)
6473 );
6474 }
6475
6476 /**
6477 * @brief Get ADC group injected conversion data, range fit for
6478 * ADC resolution 6 bits.
6479 * @note For devices with feature oversampling: Oversampling
6480 * can increase data width, function for extended range
6481 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6482 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
6483 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
6484 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
6485 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
6486 * @param ADCx ADC instance
6487 * @param Rank This parameter can be one of the following values:
6488 * @arg @ref LL_ADC_INJ_RANK_1
6489 * @arg @ref LL_ADC_INJ_RANK_2
6490 * @arg @ref LL_ADC_INJ_RANK_3
6491 * @arg @ref LL_ADC_INJ_RANK_4
6492 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6493 */
LL_ADC_INJ_ReadConversionData6(ADC_TypeDef * ADCx,uint32_t Rank)6494 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
6495 {
6496 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6497
6498 return (uint8_t)(READ_BIT(*preg,
6499 ADC_JDR1_JDATA)
6500 );
6501 }
6502
6503 /**
6504 * @}
6505 */
6506
6507 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
6508 * @{
6509 */
6510
6511 /**
6512 * @brief Get flag ADC ready.
6513 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6514 * is enabled and when conversion clock is active.
6515 * (not only core clock: this ADC has a dual clock domain)
6516 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
6517 * @param ADCx ADC instance
6518 * @retval State of bit (1 or 0).
6519 */
LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef * ADCx)6520 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
6521 {
6522 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
6523 }
6524
6525 /**
6526 * @brief Get flag ADC group regular end of unitary conversion.
6527 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
6528 * @param ADCx ADC instance
6529 * @retval State of bit (1 or 0).
6530 */
LL_ADC_IsActiveFlag_EOC(ADC_TypeDef * ADCx)6531 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
6532 {
6533 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
6534 }
6535
6536 /**
6537 * @brief Get flag ADC group regular end of sequence conversions.
6538 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
6539 * @param ADCx ADC instance
6540 * @retval State of bit (1 or 0).
6541 */
LL_ADC_IsActiveFlag_EOS(ADC_TypeDef * ADCx)6542 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
6543 {
6544 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
6545 }
6546
6547 /**
6548 * @brief Get flag ADC group regular overrun.
6549 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
6550 * @param ADCx ADC instance
6551 * @retval State of bit (1 or 0).
6552 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)6553 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
6554 {
6555 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
6556 }
6557
6558 /**
6559 * @brief Get flag ADC group regular end of sampling phase.
6560 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
6561 * @param ADCx ADC instance
6562 * @retval State of bit (1 or 0).
6563 */
LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef * ADCx)6564 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
6565 {
6566 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
6567 }
6568
6569 /**
6570 * @brief Get flag ADC group injected end of unitary conversion.
6571 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
6572 * @param ADCx ADC instance
6573 * @retval State of bit (1 or 0).
6574 */
LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef * ADCx)6575 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
6576 {
6577 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
6578 }
6579
6580 /**
6581 * @brief Get flag ADC group injected end of sequence conversions.
6582 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
6583 * @param ADCx ADC instance
6584 * @retval State of bit (1 or 0).
6585 */
LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef * ADCx)6586 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
6587 {
6588 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
6589 }
6590
6591 /**
6592 * @brief Get flag ADC group injected contexts queue overflow.
6593 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
6594 * @param ADCx ADC instance
6595 * @retval State of bit (1 or 0).
6596 */
LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef * ADCx)6597 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
6598 {
6599 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
6600 }
6601
6602 /**
6603 * @brief Get flag ADC analog watchdog 1 flag
6604 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
6605 * @param ADCx ADC instance
6606 * @retval State of bit (1 or 0).
6607 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)6608 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
6609 {
6610 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
6611 }
6612
6613 /**
6614 * @brief Get flag ADC analog watchdog 2.
6615 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
6616 * @param ADCx ADC instance
6617 * @retval State of bit (1 or 0).
6618 */
LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef * ADCx)6619 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
6620 {
6621 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
6622 }
6623
6624 /**
6625 * @brief Get flag ADC analog watchdog 3.
6626 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
6627 * @param ADCx ADC instance
6628 * @retval State of bit (1 or 0).
6629 */
LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef * ADCx)6630 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
6631 {
6632 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
6633 }
6634
6635 /**
6636 * @brief Clear flag ADC ready.
6637 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6638 * is enabled and when conversion clock is active.
6639 * (not only core clock: this ADC has a dual clock domain)
6640 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
6641 * @param ADCx ADC instance
6642 * @retval None
6643 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)6644 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
6645 {
6646 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
6647 }
6648
6649 /**
6650 * @brief Clear flag ADC group regular end of unitary conversion.
6651 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
6652 * @param ADCx ADC instance
6653 * @retval None
6654 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)6655 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
6656 {
6657 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
6658 }
6659
6660 /**
6661 * @brief Clear flag ADC group regular end of sequence conversions.
6662 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
6663 * @param ADCx ADC instance
6664 * @retval None
6665 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)6666 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
6667 {
6668 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
6669 }
6670
6671 /**
6672 * @brief Clear flag ADC group regular overrun.
6673 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
6674 * @param ADCx ADC instance
6675 * @retval None
6676 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)6677 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
6678 {
6679 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
6680 }
6681
6682 /**
6683 * @brief Clear flag ADC group regular end of sampling phase.
6684 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
6685 * @param ADCx ADC instance
6686 * @retval None
6687 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)6688 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
6689 {
6690 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
6691 }
6692
6693 /**
6694 * @brief Clear flag ADC group injected end of unitary conversion.
6695 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
6696 * @param ADCx ADC instance
6697 * @retval None
6698 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)6699 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
6700 {
6701 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
6702 }
6703
6704 /**
6705 * @brief Clear flag ADC group injected end of sequence conversions.
6706 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
6707 * @param ADCx ADC instance
6708 * @retval None
6709 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)6710 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
6711 {
6712 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
6713 }
6714
6715 /**
6716 * @brief Clear flag ADC group injected contexts queue overflow.
6717 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
6718 * @param ADCx ADC instance
6719 * @retval None
6720 */
LL_ADC_ClearFlag_JQOVF(ADC_TypeDef * ADCx)6721 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
6722 {
6723 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
6724 }
6725
6726 /**
6727 * @brief Clear flag ADC analog watchdog 1.
6728 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
6729 * @param ADCx ADC instance
6730 * @retval None
6731 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)6732 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
6733 {
6734 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
6735 }
6736
6737 /**
6738 * @brief Clear flag ADC analog watchdog 2.
6739 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
6740 * @param ADCx ADC instance
6741 * @retval None
6742 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)6743 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
6744 {
6745 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
6746 }
6747
6748 /**
6749 * @brief Clear flag ADC analog watchdog 3.
6750 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
6751 * @param ADCx ADC instance
6752 * @retval None
6753 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)6754 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
6755 {
6756 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
6757 }
6758
6759 #if defined(ADC_MULTIMODE_SUPPORT)
6760 /**
6761 * @brief Get flag multimode ADC ready of the ADC master.
6762 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
6763 * @param ADCxy_COMMON ADC common instance
6764 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6765 * @retval State of bit (1 or 0).
6766 */
LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef * ADCxy_COMMON)6767 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
6768 {
6769 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
6770 }
6771
6772 /**
6773 * @brief Get flag multimode ADC ready of the ADC slave.
6774 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
6775 * @param ADCxy_COMMON ADC common instance
6776 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6777 * @retval State of bit (1 or 0).
6778 */
LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef * ADCxy_COMMON)6779 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
6780 {
6781 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
6782 }
6783
6784 /**
6785 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
6786 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
6787 * @param ADCxy_COMMON ADC common instance
6788 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6789 * @retval State of bit (1 or 0).
6790 */
LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef * ADCxy_COMMON)6791 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
6792 {
6793 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
6794 }
6795
6796 /**
6797 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
6798 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
6799 * @param ADCxy_COMMON ADC common instance
6800 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6801 * @retval State of bit (1 or 0).
6802 */
LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef * ADCxy_COMMON)6803 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
6804 {
6805 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
6806 }
6807
6808 /**
6809 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
6810 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
6811 * @param ADCxy_COMMON ADC common instance
6812 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6813 * @retval State of bit (1 or 0).
6814 */
LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef * ADCxy_COMMON)6815 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
6816 {
6817 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
6818 }
6819
6820 /**
6821 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
6822 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
6823 * @param ADCxy_COMMON ADC common instance
6824 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6825 * @retval State of bit (1 or 0).
6826 */
LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef * ADCxy_COMMON)6827 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
6828 {
6829 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
6830 }
6831
6832 /**
6833 * @brief Get flag multimode ADC group regular overrun of the ADC master.
6834 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
6835 * @param ADCxy_COMMON ADC common instance
6836 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6837 * @retval State of bit (1 or 0).
6838 */
LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef * ADCxy_COMMON)6839 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
6840 {
6841 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
6842 }
6843
6844 /**
6845 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
6846 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
6847 * @param ADCxy_COMMON ADC common instance
6848 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6849 * @retval State of bit (1 or 0).
6850 */
LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef * ADCxy_COMMON)6851 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
6852 {
6853 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
6854 }
6855
6856 /**
6857 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
6858 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
6859 * @param ADCxy_COMMON ADC common instance
6860 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6861 * @retval State of bit (1 or 0).
6862 */
LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef * ADCxy_COMMON)6863 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
6864 {
6865 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
6866 }
6867
6868 /**
6869 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
6870 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
6871 * @param ADCxy_COMMON ADC common instance
6872 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6873 * @retval State of bit (1 or 0).
6874 */
LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef * ADCxy_COMMON)6875 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
6876 {
6877 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
6878 }
6879
6880 /**
6881 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
6882 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
6883 * @param ADCxy_COMMON ADC common instance
6884 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6885 * @retval State of bit (1 or 0).
6886 */
LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef * ADCxy_COMMON)6887 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
6888 {
6889 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
6890 }
6891
6892 /**
6893 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
6894 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
6895 * @param ADCxy_COMMON ADC common instance
6896 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6897 * @retval State of bit (1 or 0).
6898 */
LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef * ADCxy_COMMON)6899 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
6900 {
6901 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
6902 }
6903
6904 /**
6905 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
6906 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
6907 * @param ADCxy_COMMON ADC common instance
6908 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6909 * @retval State of bit (1 or 0).
6910 */
LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)6911 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
6912 {
6913 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
6914 }
6915
6916 /**
6917 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
6918 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
6919 * @param ADCxy_COMMON ADC common instance
6920 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6921 * @retval State of bit (1 or 0).
6922 */
LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)6923 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
6924 {
6925 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
6926 }
6927
6928 /**
6929 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
6930 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
6931 * @param ADCxy_COMMON ADC common instance
6932 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6933 * @retval State of bit (1 or 0).
6934 */
LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef * ADCxy_COMMON)6935 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
6936 {
6937 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
6938 }
6939
6940 /**
6941 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
6942 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
6943 * @param ADCxy_COMMON ADC common instance
6944 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6945 * @retval State of bit (1 or 0).
6946 */
LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef * ADCxy_COMMON)6947 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
6948 {
6949 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
6950 }
6951
6952 /**
6953 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
6954 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
6955 * @param ADCxy_COMMON ADC common instance
6956 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6957 * @retval State of bit (1 or 0).
6958 */
LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)6959 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
6960 {
6961 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
6962 }
6963
6964 /**
6965 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
6966 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
6967 * @param ADCxy_COMMON ADC common instance
6968 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6969 * @retval State of bit (1 or 0).
6970 */
LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)6971 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
6972 {
6973 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
6974 }
6975
6976 /**
6977 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
6978 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
6979 * @param ADCxy_COMMON ADC common instance
6980 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6981 * @retval State of bit (1 or 0).
6982 */
LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef * ADCxy_COMMON)6983 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
6984 {
6985 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
6986 }
6987
6988 /**
6989 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
6990 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
6991 * @param ADCxy_COMMON ADC common instance
6992 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6993 * @retval State of bit (1 or 0).
6994 */
LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef * ADCxy_COMMON)6995 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
6996 {
6997 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
6998 }
6999
7000 /**
7001 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
7002 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
7003 * @param ADCxy_COMMON ADC common instance
7004 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7005 * @retval State of bit (1 or 0).
7006 */
LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef * ADCxy_COMMON)7007 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
7008 {
7009 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
7010 }
7011
7012 /**
7013 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
7014 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
7015 * @param ADCxy_COMMON ADC common instance
7016 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7017 * @retval State of bit (1 or 0).
7018 */
LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef * ADCxy_COMMON)7019 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
7020 {
7021 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
7022 }
7023 #endif /* ADC_MULTIMODE_SUPPORT */
7024
7025 /**
7026 * @}
7027 */
7028
7029 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
7030 * @{
7031 */
7032
7033 /**
7034 * @brief Enable ADC ready.
7035 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
7036 * @param ADCx ADC instance
7037 * @retval None
7038 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)7039 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
7040 {
7041 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7042 }
7043
7044 /**
7045 * @brief Enable interruption ADC group regular end of unitary conversion.
7046 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
7047 * @param ADCx ADC instance
7048 * @retval None
7049 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)7050 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
7051 {
7052 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
7053 }
7054
7055 /**
7056 * @brief Enable interruption ADC group regular end of sequence conversions.
7057 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
7058 * @param ADCx ADC instance
7059 * @retval None
7060 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)7061 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
7062 {
7063 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
7064 }
7065
7066 /**
7067 * @brief Enable ADC group regular interruption overrun.
7068 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
7069 * @param ADCx ADC instance
7070 * @retval None
7071 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)7072 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
7073 {
7074 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
7075 }
7076
7077 /**
7078 * @brief Enable interruption ADC group regular end of sampling.
7079 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
7080 * @param ADCx ADC instance
7081 * @retval None
7082 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)7083 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7084 {
7085 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7086 }
7087
7088 /**
7089 * @brief Enable interruption ADC group injected end of unitary conversion.
7090 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
7091 * @param ADCx ADC instance
7092 * @retval None
7093 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)7094 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7095 {
7096 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7097 }
7098
7099 /**
7100 * @brief Enable interruption ADC group injected end of sequence conversions.
7101 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
7102 * @param ADCx ADC instance
7103 * @retval None
7104 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)7105 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7106 {
7107 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7108 }
7109
7110 /**
7111 * @brief Enable interruption ADC group injected context queue overflow.
7112 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
7113 * @param ADCx ADC instance
7114 * @retval None
7115 */
LL_ADC_EnableIT_JQOVF(ADC_TypeDef * ADCx)7116 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
7117 {
7118 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7119 }
7120
7121 /**
7122 * @brief Enable interruption ADC analog watchdog 1.
7123 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
7124 * @param ADCx ADC instance
7125 * @retval None
7126 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)7127 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7128 {
7129 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7130 }
7131
7132 /**
7133 * @brief Enable interruption ADC analog watchdog 2.
7134 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
7135 * @param ADCx ADC instance
7136 * @retval None
7137 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)7138 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
7139 {
7140 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7141 }
7142
7143 /**
7144 * @brief Enable interruption ADC analog watchdog 3.
7145 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
7146 * @param ADCx ADC instance
7147 * @retval None
7148 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)7149 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
7150 {
7151 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7152 }
7153
7154 /**
7155 * @brief Disable interruption ADC ready.
7156 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
7157 * @param ADCx ADC instance
7158 * @retval None
7159 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)7160 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
7161 {
7162 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7163 }
7164
7165 /**
7166 * @brief Disable interruption ADC group regular end of unitary conversion.
7167 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
7168 * @param ADCx ADC instance
7169 * @retval None
7170 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)7171 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
7172 {
7173 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7174 }
7175
7176 /**
7177 * @brief Disable interruption ADC group regular end of sequence conversions.
7178 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7179 * @param ADCx ADC instance
7180 * @retval None
7181 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)7182 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7183 {
7184 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7185 }
7186
7187 /**
7188 * @brief Disable interruption ADC group regular overrun.
7189 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7190 * @param ADCx ADC instance
7191 * @retval None
7192 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)7193 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7194 {
7195 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7196 }
7197
7198 /**
7199 * @brief Disable interruption ADC group regular end of sampling.
7200 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
7201 * @param ADCx ADC instance
7202 * @retval None
7203 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)7204 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
7205 {
7206 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7207 }
7208
7209 /**
7210 * @brief Disable interruption ADC group regular end of unitary conversion.
7211 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
7212 * @param ADCx ADC instance
7213 * @retval None
7214 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)7215 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
7216 {
7217 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7218 }
7219
7220 /**
7221 * @brief Disable interruption ADC group injected end of sequence conversions.
7222 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
7223 * @param ADCx ADC instance
7224 * @retval None
7225 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)7226 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
7227 {
7228 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7229 }
7230
7231 /**
7232 * @brief Disable interruption ADC group injected context queue overflow.
7233 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
7234 * @param ADCx ADC instance
7235 * @retval None
7236 */
LL_ADC_DisableIT_JQOVF(ADC_TypeDef * ADCx)7237 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
7238 {
7239 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7240 }
7241
7242 /**
7243 * @brief Disable interruption ADC analog watchdog 1.
7244 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
7245 * @param ADCx ADC instance
7246 * @retval None
7247 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)7248 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
7249 {
7250 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7251 }
7252
7253 /**
7254 * @brief Disable interruption ADC analog watchdog 2.
7255 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
7256 * @param ADCx ADC instance
7257 * @retval None
7258 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)7259 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
7260 {
7261 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7262 }
7263
7264 /**
7265 * @brief Disable interruption ADC analog watchdog 3.
7266 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
7267 * @param ADCx ADC instance
7268 * @retval None
7269 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)7270 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
7271 {
7272 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7273 }
7274
7275 /**
7276 * @brief Get state of interruption ADC ready
7277 * (0: interrupt disabled, 1: interrupt enabled).
7278 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
7279 * @param ADCx ADC instance
7280 * @retval State of bit (1 or 0).
7281 */
LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef * ADCx)7282 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
7283 {
7284 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
7285 }
7286
7287 /**
7288 * @brief Get state of interruption ADC group regular end of unitary conversion
7289 * (0: interrupt disabled, 1: interrupt enabled).
7290 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
7291 * @param ADCx ADC instance
7292 * @retval State of bit (1 or 0).
7293 */
LL_ADC_IsEnabledIT_EOC(ADC_TypeDef * ADCx)7294 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
7295 {
7296 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
7297 }
7298
7299 /**
7300 * @brief Get state of interruption ADC group regular end of sequence conversions
7301 * (0: interrupt disabled, 1: interrupt enabled).
7302 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
7303 * @param ADCx ADC instance
7304 * @retval State of bit (1 or 0).
7305 */
LL_ADC_IsEnabledIT_EOS(ADC_TypeDef * ADCx)7306 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
7307 {
7308 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
7309 }
7310
7311 /**
7312 * @brief Get state of interruption ADC group regular overrun
7313 * (0: interrupt disabled, 1: interrupt enabled).
7314 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
7315 * @param ADCx ADC instance
7316 * @retval State of bit (1 or 0).
7317 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)7318 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
7319 {
7320 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
7321 }
7322
7323 /**
7324 * @brief Get state of interruption ADC group regular end of sampling
7325 * (0: interrupt disabled, 1: interrupt enabled).
7326 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
7327 * @param ADCx ADC instance
7328 * @retval State of bit (1 or 0).
7329 */
LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef * ADCx)7330 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
7331 {
7332 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
7333 }
7334
7335 /**
7336 * @brief Get state of interruption ADC group injected end of unitary conversion
7337 * (0: interrupt disabled, 1: interrupt enabled).
7338 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
7339 * @param ADCx ADC instance
7340 * @retval State of bit (1 or 0).
7341 */
LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef * ADCx)7342 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
7343 {
7344 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
7345 }
7346
7347 /**
7348 * @brief Get state of interruption ADC group injected end of sequence conversions
7349 * (0: interrupt disabled, 1: interrupt enabled).
7350 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
7351 * @param ADCx ADC instance
7352 * @retval State of bit (1 or 0).
7353 */
LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef * ADCx)7354 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
7355 {
7356 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
7357 }
7358
7359 /**
7360 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
7361 * (0: interrupt disabled, 1: interrupt enabled).
7362 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
7363 * @param ADCx ADC instance
7364 * @retval State of bit (1 or 0).
7365 */
LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef * ADCx)7366 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
7367 {
7368 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
7369 }
7370
7371 /**
7372 * @brief Get state of interruption ADC analog watchdog 1
7373 * (0: interrupt disabled, 1: interrupt enabled).
7374 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
7375 * @param ADCx ADC instance
7376 * @retval State of bit (1 or 0).
7377 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)7378 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
7379 {
7380 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
7381 }
7382
7383 /**
7384 * @brief Get state of interruption Get ADC analog watchdog 2
7385 * (0: interrupt disabled, 1: interrupt enabled).
7386 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
7387 * @param ADCx ADC instance
7388 * @retval State of bit (1 or 0).
7389 */
LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef * ADCx)7390 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
7391 {
7392 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
7393 }
7394
7395 /**
7396 * @brief Get state of interruption Get ADC analog watchdog 3
7397 * (0: interrupt disabled, 1: interrupt enabled).
7398 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
7399 * @param ADCx ADC instance
7400 * @retval State of bit (1 or 0).
7401 */
LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef * ADCx)7402 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
7403 {
7404 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
7405 }
7406
7407 /**
7408 * @}
7409 */
7410
7411 #if defined(USE_FULL_LL_DRIVER)
7412 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
7413 * @{
7414 */
7415
7416 /* Initialization of some features of ADC common parameters and multimode */
7417 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
7418 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7419 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7420
7421 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
7422 /* (availability of ADC group injected depends on STM32 families) */
7423 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
7424
7425 /* Initialization of some features of ADC instance */
7426 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
7427 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
7428
7429 /* Initialization of some features of ADC instance and ADC group regular */
7430 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7431 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7432
7433 /* Initialization of some features of ADC instance and ADC group injected */
7434 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7435 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7436
7437 /**
7438 * @}
7439 */
7440 #endif /* USE_FULL_LL_DRIVER */
7441
7442 /**
7443 * @}
7444 */
7445
7446 /**
7447 * @}
7448 */
7449
7450 #endif /* ADC1 || ADC2 || ADC3 */
7451
7452 /**
7453 * @}
7454 */
7455
7456 #ifdef __cplusplus
7457 }
7458 #endif
7459
7460 #endif /* STM32L4xx_LL_ADC_H */
7461
