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Searched refs:GTZC_CFGR2_SPI1_Pos (Results 1 – 14 of 14) sorted by relevance

/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_gtzc.h260 #define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos)
/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gtzc.h224 #define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos)
/hal_stm32-3.4.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h17928 #define GTZC_CFGR2_SPI1_Pos (1U) macro
17929 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
18100 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18220 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18340 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18510 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18680 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u545xx.h18438 #define GTZC_CFGR2_SPI1_Pos (1U) macro
18439 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
18610 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18730 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18850 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19020 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19190 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u575xx.h19504 #define GTZC_CFGR2_SPI1_Pos (1U) macro
19505 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
19700 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19836 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19972 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20168 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20364 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u585xx.h20063 #define GTZC_CFGR2_SPI1_Pos (1U) macro
20064 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
20259 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20395 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20531 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20727 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20923 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u5a5xx.h21240 #define GTZC_CFGR2_SPI1_Pos (1U) macro
21241 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
21452 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21598 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21744 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21956 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
22168 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u595xx.h20681 #define GTZC_CFGR2_SPI1_Pos (1U) macro
20682 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
20893 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21039 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21185 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21397 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21609 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u599xx.h24455 #define GTZC_CFGR2_SPI1_Pos (1U) macro
24456 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
24677 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
24833 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
24989 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25211 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25433 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u5a9xx.h25014 #define GTZC_CFGR2_SPI1_Pos (1U) macro
25015 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
25236 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25392 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25548 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25770 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25992 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
/hal_stm32-3.4.0/stm32cube/stm32h5xx/soc/
Dstm32h562xx.h17041 #define GTZC_CFGR2_SPI1_Pos (9U) macro
17042 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
17230 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
17374 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
17518 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
17707 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
17895 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32h563xx.h19139 #define GTZC_CFGR2_SPI1_Pos (9U) macro
19140 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
19334 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19484 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19634 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19829 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20023 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32h573xx.h19696 #define GTZC_CFGR2_SPI1_Pos (9U) macro
19697 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
19899 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20055 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20211 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20414 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20616 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32h503xx.h11277 #define GTZC_CFGR2_SPI1_Pos (9U) macro
11278 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
11378 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos