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Searched refs:FMC_Bank1_R (Results 1 – 25 of 94) sorted by relevance

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/hal_stm32-3.4.0/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_fmc.h109 #define FMC_NORSRAM_DEVICE FMC_Bank1_R
446 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
452 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_fmc.h136 #define FMC_NORSRAM_DEVICE FMC_Bank1_R
621 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
627 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
/hal_stm32-3.4.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_fmc.h182 #define FMC_NORSRAM_DEVICE FMC_Bank1_R
870 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
876 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_fmc.h186 #define FMC_NORSRAM_DEVICE FMC_Bank1_R
902 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
908 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
Dstm32h5xx_hal_gtzc.h352 #if defined (FMC_Bank1_R)
/hal_stm32-3.4.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal.c1068 MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig); in HAL_SetFMCMemorySwappingConfig()
1078 return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP); in HAL_GetFMCMemorySwappingConfig()
/hal_stm32-3.4.0/stm32cube/stm32h7xx/soc/
Dsystem_stm32h7xx_dualcore_bootcm4_cm7gated.c267 FMC_Bank1_R->BTCR[0] = 0x000030D2; in SystemInit()
Dsystem_stm32h7xx_dualcore_bootcm7_cm4gated.c272 FMC_Bank1_R->BTCR[0] = 0x000030D2; in SystemInit()
Dsystem_stm32h7xx_dualcore_boot_cm4_cm7.c274 FMC_Bank1_R->BTCR[0] = 0x000030D2; in SystemInit()
Dsystem_stm32h7xx_singlecore.c271 FMC_Bank1_R->BTCR[0] = 0x000030D2; in SystemInit()
Dsystem_stm32h7xx.c293 FMC_Bank1_R->BTCR[0] = 0x000030D2; in SystemInit()
/hal_stm32-3.4.0/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_fmc.h136 #define FMC_NORSRAM_DEVICE FMC_Bank1_R
/hal_stm32-3.4.0/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_fmc.h145 #define FMC_NORSRAM_DEVICE FMC_Bank1_R
Dstm32g4xx_ll_bus.h122 #if defined(FMC_Bank1_R)
Dstm32g4xx_ll_system.h90 #if defined(FMC_Bank1_R)
/hal_stm32-3.4.0/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_fmc.h151 #define FMC_NORSRAM_DEVICE FMC_Bank1_R
Dstm32l4xx_ll_bus.h150 #if defined(FMC_Bank1_R)
Dstm32l4xx_ll_system.h88 #if defined(FMC_Bank1_R)
/hal_stm32-3.4.0/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h2473 #define FMC_Bank1_R FMC_Bank1_R_S macro
2887 #define FMC_Bank1_R FMC_Bank1_R_NS macro
Dstm32l562xx.h2596 #define FMC_Bank1_R FMC_Bank1_R_S macro
3031 #define FMC_Bank1_R FMC_Bank1_R_NS macro
/hal_stm32-3.4.0/stm32cube/stm32h5xx/soc/
Dstm32h562xx.h2768 #define FMC_Bank1_R FMC_Bank1_R_S macro
3174 #define FMC_Bank1_R FMC_Bank1_R_NS macro
Dstm32h563xx.h2974 #define FMC_Bank1_R FMC_Bank1_R_S macro
3391 #define FMC_Bank1_R FMC_Bank1_R_NS macro
Dstm32h573xx.h3110 #define FMC_Bank1_R FMC_Bank1_R_S macro
3552 #define FMC_Bank1_R FMC_Bank1_R_NS macro
/hal_stm32-3.4.0/stm32cube/stm32u5xx/soc/
Dstm32u575xx.h2784 #define FMC_Bank1_R FMC_Bank1_R_S macro
3222 #define FMC_Bank1_R FMC_Bank1_R_NS macro
Dstm32u585xx.h2957 #define FMC_Bank1_R FMC_Bank1_R_S macro
3435 #define FMC_Bank1_R FMC_Bank1_R_NS macro

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