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Searched refs:FMC_BWTR2_ADDSET_Pos (Results 1 – 25 of 48) sorted by relevance

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/hal_stm32-3.4.0/stm32cube/stm32f3xx/soc/
Dstm32f302xe.h8409 #define FMC_BWTR2_ADDSET_Pos (0U) macro
8410 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8412 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8413 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8414 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8415 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f303xe.h8972 #define FMC_BWTR2_ADDSET_Pos (0U) macro
8973 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8975 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8976 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8977 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8978 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f398xx.h8910 #define FMC_BWTR2_ADDSET_Pos (0U) macro
8911 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8913 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8914 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8915 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8916 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
/hal_stm32-3.4.0/stm32cube/stm32f7xx/soc/
Dstm32f722xx.h7010 #define FMC_BWTR2_ADDSET_Pos (0U) macro
7011 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7013 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7014 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7015 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7016 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f723xx.h7026 #define FMC_BWTR2_ADDSET_Pos (0U) macro
7027 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7029 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7030 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7031 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7032 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f732xx.h7224 #define FMC_BWTR2_ADDSET_Pos (0U) macro
7225 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7227 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7228 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7229 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7230 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f730xx.h7240 #define FMC_BWTR2_ADDSET_Pos (0U) macro
7241 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7243 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7244 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7245 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7246 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f733xx.h7240 #define FMC_BWTR2_ADDSET_Pos (0U) macro
7241 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7243 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7244 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7245 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7246 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f756xx.h8044 #define FMC_BWTR2_ADDSET_Pos (0U) macro
8045 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8047 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8048 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8049 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8050 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f765xx.h8314 #define FMC_BWTR2_ADDSET_Pos (0U) macro
8315 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8317 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8318 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8319 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8320 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f745xx.h7801 #define FMC_BWTR2_ADDSET_Pos (0U) macro
7802 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7804 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7805 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7806 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7807 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f750xx.h8044 #define FMC_BWTR2_ADDSET_Pos (0U) macro
8045 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8047 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8048 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8049 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8050 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f746xx.h7856 #define FMC_BWTR2_ADDSET_Pos (0U) macro
7857 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7859 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7860 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7861 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7862 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f777xx.h8596 #define FMC_BWTR2_ADDSET_Pos (0U) macro
8597 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8599 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8600 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8601 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8602 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f767xx.h8408 #define FMC_BWTR2_ADDSET_Pos (0U) macro
8409 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8411 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8412 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8413 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8414 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f769xx.h8491 #define FMC_BWTR2_ADDSET_Pos (0U) macro
8492 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8494 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8495 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8496 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8497 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f779xx.h8679 #define FMC_BWTR2_ADDSET_Pos (0U) macro
8680 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8682 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8683 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8684 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8685 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
/hal_stm32-3.4.0/stm32cube/stm32f4xx/soc/
Dstm32f427xx.h7755 #define FMC_BWTR2_ADDSET_Pos (0U) macro
7756 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7758 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7759 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7760 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7761 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f446xx.h7524 #define FMC_BWTR2_ADDSET_Pos (0U) macro
7525 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7527 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7528 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7529 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7530 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f429xx.h7814 #define FMC_BWTR2_ADDSET_Pos (0U) macro
7815 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7817 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7818 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7819 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7820 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f437xx.h7947 #define FMC_BWTR2_ADDSET_Pos (0U) macro
7948 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7950 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7951 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7952 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7953 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f439xx.h8001 #define FMC_BWTR2_ADDSET_Pos (0U) macro
8002 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8004 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8005 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8006 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8007 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f479xx.h11154 #define FMC_BWTR2_ADDSET_Pos (0U) macro
11155 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
11157 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
11158 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
11159 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
11160 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
Dstm32f469xx.h10964 #define FMC_BWTR2_ADDSET_Pos (0U) macro
10965 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
10967 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
10968 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
10969 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
10970 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
/hal_stm32-3.4.0/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_cm4.h18520 #define FMC_BWTR2_ADDSET_Pos (0U) macro
18521 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
18523 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
18524 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
18525 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
18526 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */

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