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Searched refs:EWCR (Results 1 – 25 of 40) sorted by relevance

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/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_iwdg.h285 MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time); in LL_IWDG_SetEwiTime()
296 return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT)); in LL_IWDG_GetEwiTime()
307 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_EnableIT_EWI()
318 CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_DisableIT_EWI()
329 return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL); in LL_IWDG_IsEnabledIT_EWI()
417 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIC); in LL_IWDG_ClearFlag_EWIF()
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_iwdg.h285 MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time); in LL_IWDG_SetEwiTime()
296 return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT)); in LL_IWDG_GetEwiTime()
307 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_EnableIT_EWI()
318 CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_DisableIT_EWI()
329 return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL); in LL_IWDG_IsEnabledIT_EWI()
428 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIC); in LL_IWDG_ClearFlag_EWIF()
/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_iwdg.c232 hiwdg->Instance->EWCR = IWDG_EWCR_EWIC; in HAL_IWDG_Init()
239 hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI; in HAL_IWDG_Init()
427 hiwdg->Instance->EWCR |= IWDG_EWCR_EWIC; in HAL_IWDG_IRQHandler()
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_iwdg.c248 hiwdg->Instance->EWCR = IWDG_EWCR_EWIC; in HAL_IWDG_Init()
255 hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI; in HAL_IWDG_Init()
465 hiwdg->Instance->EWCR |= IWDG_EWCR_EWIC; in HAL_IWDG_IRQHandler()
/hal_stm32-3.4.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h1093 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32h562xx.h1459 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32h563xx.h1637 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32h573xx.h1714 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
/hal_stm32-3.4.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h1344 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32u545xx.h1422 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32u575xx.h1550 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32u585xx.h1629 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32u5a5xx.h1676 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32u595xx.h1597 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32u599xx.h1778 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32u5a9xx.h1857 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
/hal_stm32-3.4.0/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_cm4.h1270 __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ member
Dstm32mp151axx_ca7.h1304 __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ member
Dstm32mp151axx_cm4.h1270 __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ member
Dstm32mp151cxx_ca7.h1304 __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ member
Dstm32mp151cxx_cm4.h1270 __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ member
Dstm32mp151fxx_cm4.h1270 __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ member
Dstm32mp151fxx_ca7.h1304 __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ member
Dstm32mp151dxx_ca7.h1304 __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ member
Dstm32mp153cxx_ca7.h1405 __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ member

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