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Searched refs:CTR1 (Results 1 – 21 of 21) sorted by relevance

/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h1946 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, in LL_DMA_ConfigTransfer()
1982 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, in LL_DMA_ConfigBurstLength()
2022 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, in LL_DMA_ConfigChannelSecure()
2053 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_D… in LL_DMA_EnableChannelDestSecure()
2083 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1… in LL_DMA_DisableChannelDestSecure()
2113 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, … in LL_DMA_IsEnabledChannelDestSecure()
2144 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_S… in LL_DMA_EnableChannelSrcSecure()
2174 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1… in LL_DMA_DisableChannelSrcSecure()
2204 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, … in LL_DMA_IsEnabledChannelSrcSecure()
2239 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR… in LL_DMA_SetDestAllocatedPort()
[all …]
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h2202 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, in LL_DMA_ConfigTransfer()
2238 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, in LL_DMA_ConfigBurstLength()
2278 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, in LL_DMA_ConfigChannelSecure()
2309 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_D… in LL_DMA_EnableChannelDestSecure()
2339 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1… in LL_DMA_DisableChannelDestSecure()
2369 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, … in LL_DMA_IsEnabledChannelDestSecure()
2400 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_S… in LL_DMA_EnableChannelSrcSecure()
2430 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1… in LL_DMA_DisableChannelSrcSecure()
2460 …return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, … in LL_DMA_IsEnabledChannelSrcSecure()
2495 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR… in LL_DMA_SetDestAllocatedPort()
[all …]
/hal_stm32-3.4.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_dma.c357 hdma->Instance->CTR1 = 0U; in HAL_DMA_DeInit()
1433 hdma->Instance->CTR1 |= DMA_CTR1_SSEC; in HAL_DMA_ConfigChannelAttributes()
1437 hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC); in HAL_DMA_ConfigChannelAttributes()
1447 hdma->Instance->CTR1 |= DMA_CTR1_DSEC; in HAL_DMA_ConfigChannelAttributes()
1451 hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC); in HAL_DMA_ConfigChannelAttributes()
1493 …attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_… in HAL_DMA_GetConfigChannelAttributes()
1496 …attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL… in HAL_DMA_GetConfigChannelAttributes()
1642 MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); in DMA_Init()
1644 WRITE_REG(hdma->Instance->CTR1, tmpreg); in DMA_Init()
Dstm32h5xx_hal_dma_ex.c713 hdma->Instance->CTR1 = 0U; in HAL_DMAEx_List_DeInit()
3265 MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), in HAL_DMAEx_ConfigDataHandling()
3668 WRITE_REG(hdma->Instance->CTR1, 0U); in DMA_List_Init()
Dstm32h5xx_ll_dma.c320 LL_DMA_WriteReg(tmp, CTR1, 0U); in LL_DMA_DeInit()
/hal_stm32-3.4.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dma.c357 hdma->Instance->CTR1 = 0U; in HAL_DMA_DeInit()
1433 hdma->Instance->CTR1 |= DMA_CTR1_SSEC; in HAL_DMA_ConfigChannelAttributes()
1437 hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC); in HAL_DMA_ConfigChannelAttributes()
1447 hdma->Instance->CTR1 |= DMA_CTR1_DSEC; in HAL_DMA_ConfigChannelAttributes()
1451 hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC); in HAL_DMA_ConfigChannelAttributes()
1493 …attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_… in HAL_DMA_GetConfigChannelAttributes()
1496 …attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL… in HAL_DMA_GetConfigChannelAttributes()
1639 MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); in DMA_Init()
Dstm32u5xx_hal_dma_ex.c713 hdma->Instance->CTR1 = 0U; in HAL_DMAEx_List_DeInit()
3265 MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), in HAL_DMAEx_ConfigDataHandling()
3668 WRITE_REG(hdma->Instance->CTR1, 0U); in DMA_List_Init()
Dstm32u5xx_ll_dma.c319 LL_DMA_WriteReg(tmp, CTR1, 0U); in LL_DMA_DeInit()
Dstm32u5xx_hal_ospi.c1536 MODIFY_REG(hospi->hdma->Instance->CTR1, (DMA_CTR1_SINC | DMA_CTR1_DINC), \ in HAL_OSPI_Transmit_DMA()
1721 MODIFY_REG(hospi->hdma->Instance->CTR1, (DMA_CTR1_SINC | DMA_CTR1_DINC), \ in HAL_OSPI_Receive_DMA()
/hal_stm32-3.4.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h410 …__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: … member
Dstm32h562xx.h489 …__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: … member
Dstm32h563xx.h494 …__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: … member
Dstm32h573xx.h532 …__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: … member
/hal_stm32-3.4.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h399 …__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: … member
Dstm32u545xx.h438 …__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: … member
Dstm32u575xx.h410 …__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: … member
Dstm32u585xx.h450 …__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: … member
Dstm32u5a5xx.h456 …__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: … member
Dstm32u595xx.h416 …__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: … member
Dstm32u599xx.h423 …__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: … member
Dstm32u5a9xx.h463 …__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: … member