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Searched refs:tmpr (Results 1 – 10 of 10) sorted by relevance

/hal_stm32-2.7.6/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_fsmc.c131 uint32_t tmpr = 0U; in FSMC_NORSRAM_Init() local
157 tmpr = Device->BTCR[Init->NSBank]; in FSMC_NORSRAM_Init()
162 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ in FSMC_NORSRAM_Init()
168 tmpr |= (uint32_t)(Init->DataAddressMux |\ in FSMC_NORSRAM_Init()
185 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ in FSMC_NORSRAM_Init()
192 tmpr |= (uint32_t)(Init->DataAddressMux |\ in FSMC_NORSRAM_Init()
210 tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE; in FSMC_NORSRAM_Init()
213 Device->BTCR[Init->NSBank] = tmpr; in FSMC_NORSRAM_Init()
277 uint32_t tmpr = 0U; in FSMC_NORSRAM_Timing_Init() local
291 tmpr = Device->BTCR[Bank + 1U]; in FSMC_NORSRAM_Timing_Init()
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Dstm32f4xx_ll_fmc.c135 uint32_t tmpr = 0U; in FMC_NORSRAM_Init() local
161 tmpr = Device->BTCR[Init->NSBank]; in FMC_NORSRAM_Init()
166 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ in FMC_NORSRAM_Init()
174 tmpr |= (uint32_t)(Init->DataAddressMux |\ in FMC_NORSRAM_Init()
191 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ in FMC_NORSRAM_Init()
199 tmpr |= (uint32_t)(Init->DataAddressMux |\ in FMC_NORSRAM_Init()
217 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; in FMC_NORSRAM_Init()
220 Device->BTCR[Init->NSBank] = tmpr; in FMC_NORSRAM_Init()
283 uint32_t tmpr = 0U; in FMC_NORSRAM_Timing_Init() local
297 tmpr = Device->BTCR[Bank + 1U]; in FMC_NORSRAM_Timing_Init()
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/hal_stm32-2.7.6/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_fmc.c134 uint32_t tmpr = 0; in FMC_NORSRAM_Init() local
155 tmpr = Device->BTCR[Init->NSBank]; in FMC_NORSRAM_Init()
159 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ in FMC_NORSRAM_Init()
166 tmpr |= (uint32_t)(Init->DataAddressMux |\ in FMC_NORSRAM_Init()
183 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; in FMC_NORSRAM_Init()
186 Device->BTCR[Init->NSBank] = tmpr; in FMC_NORSRAM_Init()
248 uint32_t tmpr = 0; in FMC_NORSRAM_Timing_Init() local
262 tmpr = Device->BTCR[Bank + 1]; in FMC_NORSRAM_Timing_Init()
265 tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \ in FMC_NORSRAM_Timing_Init()
270 tmpr |= (uint32_t)(Timing->AddressSetupTime |\ in FMC_NORSRAM_Timing_Init()
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/hal_stm32-2.7.6/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_fmc.c337 uint32_t tmpr; in FMC_NORSRAM_Timing_Init() local
364 …tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTR1_CLKDIV_Pos… in FMC_NORSRAM_Timing_Init()
365 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
366 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-2.7.6/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_fmc.c363 uint32_t tmpr; in FMC_NORSRAM_Timing_Init() local
390 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
391 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
392 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-2.7.6/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_fmc.c363 uint32_t tmpr; in FMC_NORSRAM_Timing_Init() local
390 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
391 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
392 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-2.7.6/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_fmc.c374 uint32_t tmpr; in FMC_NORSRAM_Timing_Init() local
401 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
402 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
403 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-2.7.6/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_fmc.c401 uint32_t tmpr; in FMC_NORSRAM_Timing_Init() local
440 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
441 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
442 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-2.7.6/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_fmc.c328 uint32_t tmpr; in FMC_NORSRAM_Timing_Init() local
353 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
354 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
355 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-2.7.6/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_fmc.c326 uint32_t tmpr; in FMC_NORSRAM_Timing_Init() local
351 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
352 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
353 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()