1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_RCC_H 21 #define STM32U5xx_HAL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup RCC_Exported_Types RCC Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief RCC PLL configuration structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PLLState; /*!< The new state of the PLL. 49 This parameter can be a value of @ref RCC_PLL_Config */ 50 51 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 52 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 53 54 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 55 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 56 57 uint32_t PLLMBOOST; /*!< PLLMBOOST: Prescaler for EPOD booster input clock. 58 This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider */ 59 60 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 61 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 62 63 uint32_t PLLP; /*!< PLLP: Division factor for system clock. 64 This parameter must be a number between Min_Data = 1 and Max_Data = 128 65 odd division factors are not allowed */ 66 67 uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. 68 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 69 70 uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. 71 This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ 72 73 uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range 74 This parameter must be a value of @ref RCC_PLL_VCI_Range */ 75 76 uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for 77 PLL1 VCO It should be a value between 0 and 32767 */ 78 79 } RCC_PLLInitTypeDef; 80 81 /** 82 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 83 */ 84 typedef struct 85 { 86 uint32_t OscillatorType; /*!< The oscillators to be configured. 87 This parameter can be a value of @ref RCC_Oscillator_Type */ 88 89 uint32_t HSEState; /*!< The new state of the HSE. 90 This parameter can be a value of @ref RCC_HSE_Config */ 91 92 uint32_t LSEState; /*!< The new state of the LSE. 93 This parameter can be a value of @ref RCC_LSE_Config */ 94 95 uint32_t HSIState; /*!< The new state of the HSI. 96 This parameter can be a value of @ref RCC_HSI_Config */ 97 98 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 99 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F 100 on the other devices */ 101 102 uint32_t LSIState; /*!< The new state of the LSI. 103 This parameter can be a value of @ref RCC_LSI_Config */ 104 105 uint32_t LSIDiv; /*!< The division factor of the LSI. 106 This parameter can be a value of @ref RCC_LSI_Div */ 107 108 uint32_t MSIState; /*!< The new state of the MSI. 109 This parameter can be a value of @ref RCC_MSI_Config */ 110 111 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 112 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 113 114 uint32_t MSIClockRange; /*!< The MSI frequency range. 115 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 116 117 uint32_t MSIKClockRange; /*!< The MSIK frequency range. 118 This parameter can be a value of @ref RCC_MSIk_Clock_Range */ 119 120 uint32_t HSI48State; /*!< The new state of the HSI48. 121 This parameter can be a value of @ref RCC_HSI48_Config */ 122 123 uint32_t SHSIState; /*!< The new state of the SHSI. 124 This parameter can be a value of @ref RCC_SHSI_Config */ 125 126 uint32_t MSIKState; /*!< The new state of the MSIK. 127 This parameter can be a value of @ref RCC_MSIK_Config */ 128 129 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 130 131 } RCC_OscInitTypeDef; 132 133 /** 134 * @brief RCC System, AHB and APB busses clock configuration structure definition 135 */ 136 typedef struct 137 { 138 uint32_t ClockType; /*!< The clock to be configured. 139 This parameter can be a value of @ref RCC_System_Clock_Type */ 140 141 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 142 This parameter can be a value of @ref RCC_System_Clock_Source */ 143 144 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock 145 (SYSCLK). 146 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 147 148 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 149 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 150 151 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 152 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 153 154 uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). 155 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 156 } RCC_ClkInitTypeDef; 157 158 /** 159 * @} 160 */ 161 162 /* Exported constants --------------------------------------------------------*/ 163 /** @defgroup RCC_Exported_Constants RCC Exported Constants 164 * @{ 165 */ 166 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 167 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 168 #define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 169 170 /* Defines used for Flags */ 171 #define CR_REG_INDEX (1U) 172 #define BDCR_REG_INDEX (2U) 173 #define CSR_REG_INDEX (3U) 174 #define CRRCR_REG_INDEX (4U) 175 176 #define RCC_FLAG_MASK (0x1FU) 177 /** 178 * @} 179 */ 180 181 /** @defgroup RCC_Reset_Flag Reset Flag 182 * @{ 183 */ 184 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 185 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 186 #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 187 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 188 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 189 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 190 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 191 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 192 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 193 RCC_RESET_FLAG_LPWR) 194 /** 195 * @} 196 */ 197 198 /** @defgroup RCC_Timeout_Value Timeout Values 199 * @{ 200 */ 201 #define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 202 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 203 /** 204 * @} 205 */ 206 207 /** @defgroup RCC_Oscillator_Type Oscillator Type 208 * @{ 209 */ 210 #define RCC_OSCILLATORTYPE_NONE 0x0UL /*!< Oscillator configuration unchanged */ 211 #define RCC_OSCILLATORTYPE_HSE 0x1UL /*!< HSE to configure */ 212 #define RCC_OSCILLATORTYPE_HSI 0x2UL /*!< HSI to configure */ 213 #define RCC_OSCILLATORTYPE_LSE 0x4UL /*!< LSE to configure */ 214 #define RCC_OSCILLATORTYPE_LSI 0x8UL /*!< LSI to configure */ 215 #define RCC_OSCILLATORTYPE_MSI 0x10UL /*!< MSI to configure */ 216 #define RCC_OSCILLATORTYPE_HSI48 0x20UL /*!< HSI48 to configure */ 217 #define RCC_OSCILLATORTYPE_MSIK 0x040U /*!< MSIK to configure */ 218 #define RCC_OSCILLATORTYPE_SHSI 0x80UL /*!< SHSI to configure */ 219 /* Defines Oscillator Masks */ 220 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | \ 221 RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_MSIK | \ 222 RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_SHSI) /*!< All Oscillator to configure */ 223 /** 224 * @} 225 */ 226 227 /** @defgroup RCC_HSE_Config HSE Config 228 * @{ 229 */ 230 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 231 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 232 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ 233 #define RCC_HSE_BYPASS_DIGITAL (RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON) 234 /** 235 * @} 236 */ 237 238 /** @defgroup RCC_LSE_Config LSE Config 239 * @{ 240 */ 241 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 242 #define RCC_LSE_ON_RTC_ONLY RCC_BDCR_LSEON /*!< LSE clock activation for RTC only */ 243 #define RCC_LSE_ON (RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< LSE clock activation for RCC and peripherals */ 244 #define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 245 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup RCC_HSI_Config HSI Config 251 * @{ 252 */ 253 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 254 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 255 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 256 /** 257 * @} 258 */ 259 260 /** @defgroup RCC_LSI_Config LSI Config 261 * @{ 262 */ 263 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 264 #define RCC_LSI_ON RCC_BDCR_LSION /*!< LSI clock activation */ 265 /** 266 * @} 267 */ 268 269 /** @defgroup RCC_LSI_Div LSI Div 270 * @{ 271 */ 272 #define RCC_LSI_DIV1 0U /*!< LSI clock is not divided */ 273 #define RCC_LSI_DIV128 RCC_BDCR_LSIPREDIV /*!< LSI clock is divided by 128 */ 274 /** 275 * @} 276 */ 277 278 /** @defgroup RCC_MSI_Config MSI Config 279 * @{ 280 */ 281 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 282 #define RCC_MSI_ON RCC_CR_MSISON /*!< MSI clock activation */ 283 284 #define RCC_MSICALIBRATION_DEFAULT 0x10U /*!< Default MSI calibration trimming value */ 285 /** 286 * @} 287 */ 288 289 /** @defgroup RCC_HSI48_Config HSI48 Config 290 * @{ 291 */ 292 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 293 #define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ 294 /** 295 * @} 296 */ 297 298 /** @defgroup RCC_MSIK_Config MSIK Config 299 * @{ 300 */ 301 #define RCC_MSIK_OFF 0x00000000U /*!< MSIK clock deactivation */ 302 #define RCC_MSIK_ON RCC_CR_MSIKON /*!< MSIK clock activation */ 303 /** 304 * @} 305 */ 306 307 /** @defgroup RCC_SHSI_Config SHSI Config 308 * @{ 309 */ 310 #define RCC_SHSI_OFF 0x00000000U /*!< SHSI clock deactivation */ 311 #define RCC_SHSI_ON RCC_CR_SHSION /*!< SHSI clock activation */ 312 /** 313 * @} 314 */ 315 316 /** @defgroup RCC_PLL_Config RCC PLL Config 317 * @{ 318 */ 319 #define RCC_PLL_NONE 0x00000000U 320 #define RCC_PLL_OFF 0x00000001U 321 #define RCC_PLL_ON 0x00000002U 322 /** 323 * @} 324 */ 325 326 /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output 327 * @{ 328 */ 329 #define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN 330 #define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN 331 #define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN 332 /** 333 * @} 334 */ 335 336 /** @defgroup RCC_PLLMBOOST_EPOD_Clock_Divider PLLMBOOST EPOD Clock Divider 337 * @{ 338 */ 339 #define RCC_PLLMBOOST_DIV1 0x00000000U 340 #define RCC_PLLMBOOST_DIV2 RCC_PLL1CFGR_PLL1MBOOST_0 341 #define RCC_PLLMBOOST_DIV4 RCC_PLL1CFGR_PLL1MBOOST_1 342 #define RCC_PLLMBOOST_DIV6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0) 343 #define RCC_PLLMBOOST_DIV8 RCC_PLL1CFGR_PLL1MBOOST_2 344 #define RCC_PLLMBOOST_DIV10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0) 345 #define RCC_PLLMBOOST_DIV12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1) 346 #define RCC_PLLMBOOST_DIV14 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1| RCC_PLL1CFGR_PLL1MBOOST_0) 347 #define RCC_PLLMBOOST_DIV16 RCC_PLL1CFGR_PLL1MBOOST_3 348 /** 349 * @} 350 */ 351 352 /** @defgroup RCC_PLL_VCI_Range RCC PLL1 VCI Range 353 * @{ 354 */ 355 #define RCC_PLLVCIRANGE_0 0x00000000U 356 #define RCC_PLLVCIRANGE_1 (RCC_PLL1CFGR_PLL1RGE_1 | RCC_PLL1CFGR_PLL1RGE_0) 357 /** 358 * @} 359 */ 360 361 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source 362 * @{ 363 */ 364 #define RCC_PLLSOURCE_NONE 0x00000000U 365 #define RCC_PLLSOURCE_MSI RCC_PLL1CFGR_PLL1SRC_0 366 #define RCC_PLLSOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 367 #define RCC_PLLSOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) 368 /** 369 * @} 370 */ 371 372 373 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 374 * @{ 375 */ 376 #define RCC_MSIRANGE_0 0x00000000U /*!< MSI = 48 MHz */ 377 #define RCC_MSIRANGE_1 RCC_ICSCR1_MSISRANGE_0 /*!< MSI = 24 MHz */ 378 #define RCC_MSIRANGE_2 RCC_ICSCR1_MSISRANGE_1 /*!< MSI = 16 MHz */ 379 #define RCC_MSIRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1) /*!< MSI = 12 MHz */ 380 #define RCC_MSIRANGE_4 RCC_ICSCR1_MSISRANGE_2 /*!< MSI = 4 MHz */ 381 #define RCC_MSIRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 2 MHz */ 382 #define RCC_MSIRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1.33 MHz */ 383 #define RCC_MSIRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1 MHz */ 384 #define RCC_MSIRANGE_8 RCC_ICSCR1_MSISRANGE_3 /*!< MSI = 3.072 MHz */ 385 #define RCC_MSIRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.536 MHz */ 386 #define RCC_MSIRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.024 MHz */ 387 #define RCC_MSIRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 768 KHz */ 388 #define RCC_MSIRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 400 KHz */ 389 #define RCC_MSIRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 200 KHz */ 390 #define RCC_MSIRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 133 KHz */ 391 #define RCC_MSIRANGE_15 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 |\ 392 RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 100 KHz */ 393 /** 394 * @} 395 */ 396 397 /** @defgroup RCC_MSIk_Clock_Range MSIK Clock Range 398 * @{ 399 */ 400 #define RCC_MSIKRANGE_0 0x00000000U /*!< MSIk = 48 MHz */ 401 #define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIk = 24 MHz */ 402 #define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIk = 16 MHz */ 403 #define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIk = 12 MHz */ 404 #define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIk = 4 MHz */ 405 #define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 2 MHz */ 406 #define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 1.33 MHz */ 407 #define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 1 MHz */ 408 #define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIk = 3.072 MHz */ 409 #define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 1.536 MHz */ 410 #define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 1.024 MHz */ 411 #define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 768 KHz */ 412 #define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 400 KHz */ 413 #define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 200 KHz */ 414 #define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 133 KHz */ 415 #define RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 |\ 416 RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 100 KHz */ 417 /** 418 * @} 419 */ 420 421 /** @defgroup RCC_System_Clock_Type System Clock Type 422 * @{ 423 */ 424 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 425 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 426 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 427 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 428 #define RCC_CLOCKTYPE_PCLK3 0x00000010U /*!< PCLK3 to configure */ 429 /** 430 * @} 431 */ 432 433 /** @defgroup RCC_System_Clock_Source System Clock Source 434 * @{ 435 */ 436 #define RCC_SYSCLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */ 437 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR1_SW_0 /*!< HSI selection as system clock */ 438 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ 439 #define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_0 | RCC_CFGR1_SW_1) /*!< PLL1 selection as system clock */ 440 /** 441 * @} 442 */ 443 444 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 445 * @{ 446 */ 447 #define RCC_SYSCLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */ 448 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0 /*!< HSI used as system clock */ 449 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ 450 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1) /*!< PLL1 used as system clock */ 451 /** 452 * @} 453 */ 454 455 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 456 * @{ 457 */ 458 #define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ 459 #define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ 460 #define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */ 461 #define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */ 462 #define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */ 463 #define RCC_SYSCLK_DIV64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */ 464 #define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */ 465 #define RCC_SYSCLK_DIV256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */ 466 #define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */ 467 /** 468 * @} 469 */ 470 471 /** @defgroup RCC_APB1_APB2_APB3_Clock_Source APB1 APB2 APB3 Clock Source 472 * @{ 473 */ 474 #define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ 475 #define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ 476 #define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */ 477 #define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */ 478 #define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */ 479 /** 480 * @} 481 */ 482 483 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 484 * @{ 485 */ 486 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock used as RTC clock */ 487 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 488 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 489 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 490 /** 491 * @} 492 */ 493 494 /** @defgroup RCC_MCO_Index MCO Index 495 * @{ 496 */ 497 #define RCC_MCO1 0x00000000U 498 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 499 /** 500 * @} 501 */ 502 503 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 504 * @{ 505 */ 506 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 507 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 508 #define RCC_MCO1SOURCE_MSI RCC_CFGR1_MCOSEL_1 /*!< MSI selection as MCO1 source */ 509 #define RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */ 510 #define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */ 511 #define RCC_MCO1SOURCE_PLL1CLK (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_2) /*!< PLL1CLK selection as MCO1 source */ 512 #define RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */ 513 #define RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSE selection as MCO1 source */ 514 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ 515 #define RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_3) /*!< MSIK selection as MCO1 source */ 516 /** 517 * @} 518 */ 519 520 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 521 * @{ 522 */ 523 #define RCC_MCODIV_1 0x00000000U /*!< MCO is divided by 1 */ 524 #define RCC_MCODIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO is divided by 2 */ 525 #define RCC_MCODIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO is divided by 4 */ 526 #define RCC_MCODIV_8 (RCC_CFGR1_MCOPRE_0 | RCC_CFGR1_MCOPRE_1)/*!< MCO is divided by 8 */ 527 #define RCC_MCODIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO is divided by 16 */ 528 /** 529 * @} 530 */ 531 532 /** @defgroup RCC_Interrupt Interrupts 533 * @{ 534 */ 535 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 536 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 537 #define RCC_IT_MSIRDY RCC_CIFR_MSISRDYF /*!< MSI Ready Interrupt flag */ 538 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 539 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 540 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 541 #define RCC_IT_PLLRDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ 542 #define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ 543 #define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt flag */ 544 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 545 #define RCC_IT_MSIKRDY RCC_CIFR_MSIKRDYF /*!< MSIK Ready Interrupt flag */ 546 #define RCC_IT_SHSIRDY RCC_CIFR_SHSIRDYF /*!< SHSI Ready Interrupt flag */ 547 /** 548 * @} 549 */ 550 551 /** @defgroup RCC_Flag Flags 552 * Elements values convention: XXXYYYYYb 553 * - YYYYY : Flag position in the register 554 * - XXX : Register index 555 * - 001: CR register 556 * - 010: BDCR register 557 * - 011: CSR register 558 * - 100: CRRCR register 559 * @{ 560 */ 561 /* Flags in the CR register */ 562 #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSISRDY_Pos)) /*!< MSI Ready flag */ 563 #define RCC_FLAG_MSIKRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIKRDY_Pos)) /*!< MSI Ready flag */ 564 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ 565 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ 566 #define RCC_FLAG_PLL1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos)) /*!< PLL Ready flag */ 567 #define RCC_FLAG_PLL2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) /*!< PLL2 Ready flag */ 568 #define RCC_FLAG_PLL3RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /*!< PLL3 Ready flag */ 569 #define RCC_FLAG_SHSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_SHSIRDY_Pos)) /*!< SHSI Ready flag */ 570 #define RCC_FLAG_HSI48RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ 571 572 /* Flags in the BDCR register */ 573 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ 574 #define RCC_FLAG_LSESYSRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSESYSRDY_Pos)) /*!< LSESYS Ready flag */ 575 #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ 576 #define RCC_FLAG_LSIRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */ 577 578 /* Flags in the CSR register */ 579 #define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */ 580 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */ 581 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ 582 #define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)) /*!< BOR reset flag */ 583 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ 584 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ 585 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ 586 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ 587 588 /** 589 * @} 590 */ 591 592 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 593 * @{ 594 */ 595 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 596 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 597 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 598 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 599 /** 600 * @} 601 */ 602 603 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 604 * @{ 605 */ 606 #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ 607 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK /*!< HSI selection after wake-up from STOP */ 608 /** 609 * @} 610 */ 611 612 /** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock 613 * @{ 614 */ 615 #define RCC_STOP_KERWAKEUPCLOCK_MSI 0x00000000U /*!< MSI kernel clock selection after wake-up from STOP */ 616 #define RCC_STOP_KERWAKEUPCLOCK_HSI RCC_CFGR1_STOPKERWUCK /*!< HSI kernel clock selection after wake-up from STOP */ 617 618 /** 619 * @} 620 */ 621 622 /** @defgroup RCC_items RCC items 623 * @brief RCC items to configure attributes on 624 * @{ 625 */ 626 #define RCC_HSI RCC_SECCFGR_HSISEC 627 #define RCC_HSE RCC_SECCFGR_HSESEC 628 #define RCC_MSI RCC_SECCFGR_MSISEC 629 #define RCC_LSI RCC_SECCFGR_LSISEC 630 #define RCC_LSE RCC_SECCFGR_LSESEC 631 #define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC 632 #define RCC_PRESC RCC_SECCFGR_PRESCSEC 633 #define RCC_PLL1 RCC_SECCFGR_PLL1SEC 634 #define RCC_PLL2 RCC_SECCFGR_PLL2SEC 635 #define RCC_PLL3 RCC_SECCFGR_PLL3SEC 636 #define RCC_CLK48M RCC_SECCFGR_CLK48MSEC 637 #define RCC_HSI48 RCC_SECCFGR_HSI48SEC 638 #define RCC_RMVF RCC_SECCFGR_RMVFSEC 639 #define RCC_ALL (RCC_HSI|RCC_HSE|RCC_MSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ 640 RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ 641 RCC_PLL3|RCC_CLK48M|RCC_RMVF) 642 /** 643 * @} 644 */ 645 646 /** @defgroup RCC_attributes RCC attributes 647 * @brief RCC privilege/non-privilege and secure/non-secure attributes 648 * @{ 649 */ 650 #define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ 651 #define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ 652 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 653 #define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ 654 #define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ 655 #endif /* __ARM_FEATURE_CMSE */ 656 /** 657 * @} 658 */ 659 660 /* Exported macros -----------------------------------------------------------*/ 661 662 /** @defgroup RCC_Exported_Macros RCC Exported Macros 663 * @{ 664 */ 665 666 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 667 * @brief Enable or disable the AHB1 peripheral clock. 668 * @note After reset, the peripheral clock (used for registers read/write access) 669 * is disabled and the application software has to enable this clock before 670 * using it. 671 * @{ 672 */ 673 #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ 674 __IO uint32_t tmpreg; \ 675 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 676 /* Delay after an RCC peripheral clock enabling */ \ 677 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 678 UNUSED(tmpreg); \ 679 } while(0) 680 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ 681 __IO uint32_t tmpreg; \ 682 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 683 /* Delay after an RCC peripheral clock enabling */ \ 684 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 685 UNUSED(tmpreg); \ 686 } while(0) 687 #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ 688 __IO uint32_t tmpreg; \ 689 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 690 /* Delay after an RCC peripheral clock enabling */ \ 691 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 692 UNUSED(tmpreg); \ 693 } while(0) 694 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 695 __IO uint32_t tmpreg; \ 696 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 697 /* Delay after an RCC peripheral clock enabling */ \ 698 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 699 UNUSED(tmpreg); \ 700 } while(0) 701 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 702 __IO uint32_t tmpreg; \ 703 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 704 /* Delay after an RCC peripheral clock enabling */ \ 705 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 706 UNUSED(tmpreg); \ 707 } while(0) 708 #define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ 709 __IO uint32_t tmpreg; \ 710 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 711 /* Delay after an RCC peripheral clock enabling */ \ 712 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 713 UNUSED(tmpreg); \ 714 } while(0) 715 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 716 __IO uint32_t tmpreg; \ 717 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 718 /* Delay after an RCC peripheral clock enabling */ \ 719 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 720 UNUSED(tmpreg); \ 721 } while(0) 722 723 #define __HAL_RCC_MDF1_CLK_ENABLE() do { \ 724 __IO uint32_t tmpreg; \ 725 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ 726 /* Delay after an RCC peripheral clock enabling */ \ 727 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ 728 UNUSED(tmpreg); \ 729 } while(0) 730 731 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 732 __IO uint32_t tmpreg; \ 733 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 734 /* Delay after an RCC peripheral clock enabling */ \ 735 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 736 UNUSED(tmpreg); \ 737 } while(0) 738 739 #define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ 740 __IO uint32_t tmpreg; \ 741 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ 742 /* Delay after an RCC peripheral clock enabling */ \ 743 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ 744 UNUSED(tmpreg); \ 745 } while(0) 746 747 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 748 __IO uint32_t tmpreg; \ 749 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ 750 /* Delay after an RCC peripheral clock enabling */ \ 751 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ 752 UNUSED(tmpreg); \ 753 } while(0) 754 755 #define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ 756 __IO uint32_t tmpreg; \ 757 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 758 /* Delay after an RCC peripheral clock enabling */ \ 759 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 760 UNUSED(tmpreg); \ 761 } while(0) 762 763 #define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ 764 __IO uint32_t tmpreg; \ 765 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 766 /* Delay after an RCC peripheral clock enabling */ \ 767 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 768 UNUSED(tmpreg); \ 769 } while(0) 770 771 #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) 772 773 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) 774 775 #define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) 776 777 #define __HAL_RCC_MDF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) 778 779 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 780 781 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 782 783 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 784 785 #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) 786 787 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) 788 789 #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) 790 791 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) 792 793 #define __HAL_RCC_DCACHE1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) 794 795 #define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) 796 /** 797 * @} 798 */ 799 800 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 801 * @brief Enable or disable the AHB2 peripheral clock. 802 * @note After reset, the peripheral clock (used for registers read/write access) 803 * is disabled and the application software has to enable this clock before 804 * using it. 805 * @{ 806 */ 807 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 808 __IO uint32_t tmpreg; \ 809 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ 810 /* Delay after an RCC peripheral clock enabling */ \ 811 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ 812 UNUSED(tmpreg); \ 813 } while(0) 814 815 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 816 __IO uint32_t tmpreg; \ 817 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ 818 /* Delay after an RCC peripheral clock enabling */ \ 819 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ 820 UNUSED(tmpreg); \ 821 } while(0) 822 823 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 824 __IO uint32_t tmpreg; \ 825 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ 826 /* Delay after an RCC peripheral clock enabling */ \ 827 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ 828 UNUSED(tmpreg); \ 829 } while(0) 830 831 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 832 __IO uint32_t tmpreg; \ 833 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ 834 /* Delay after an RCC peripheral clock enabling */ \ 835 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ 836 UNUSED(tmpreg); \ 837 } while(0) 838 839 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 840 __IO uint32_t tmpreg; \ 841 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ 842 /* Delay after an RCC peripheral clock enabling */ \ 843 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ 844 UNUSED(tmpreg); \ 845 } while(0) 846 847 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 848 __IO uint32_t tmpreg; \ 849 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ 850 /* Delay after an RCC peripheral clock enabling */ \ 851 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ 852 UNUSED(tmpreg); \ 853 } while(0) 854 855 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 856 __IO uint32_t tmpreg; \ 857 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ 858 /* Delay after an RCC peripheral clock enabling */ \ 859 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ 860 UNUSED(tmpreg); \ 861 } while(0) 862 863 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 864 __IO uint32_t tmpreg; \ 865 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ 866 /* Delay after an RCC peripheral clock enabling */ \ 867 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ 868 UNUSED(tmpreg); \ 869 } while(0) 870 871 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 872 __IO uint32_t tmpreg; \ 873 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ 874 /* Delay after an RCC peripheral clock enabling */ \ 875 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ 876 UNUSED(tmpreg); \ 877 } while(0) 878 879 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 880 __IO uint32_t tmpreg; \ 881 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN); \ 882 /* Delay after an RCC peripheral clock enabling */ \ 883 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN); \ 884 UNUSED(tmpreg); \ 885 } while(0) 886 887 #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ 888 __IO uint32_t tmpreg; \ 889 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ 890 /* Delay after an RCC peripheral clock enabling */ \ 891 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ 892 UNUSED(tmpreg); \ 893 } while(0) 894 895 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 896 __IO uint32_t tmpreg; \ 897 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ 898 /* Delay after an RCC peripheral clock enabling */ \ 899 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ 900 UNUSED(tmpreg); \ 901 } while(0) 902 903 #if defined(AES) 904 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 905 __IO uint32_t tmpreg; \ 906 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ 907 /* Delay after an RCC peripheral clock enabling */ \ 908 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ 909 UNUSED(tmpreg); \ 910 } while(0) 911 #endif /* AES */ 912 913 #if defined(HASH) 914 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 915 __IO uint32_t tmpreg; \ 916 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ 917 /* Delay after an RCC peripheral clock enabling */ \ 918 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ 919 UNUSED(tmpreg); \ 920 } while(0) 921 #endif /* HASH */ 922 923 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 924 __IO uint32_t tmpreg; \ 925 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ 926 /* Delay after an RCC peripheral clock enabling */ \ 927 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ 928 UNUSED(tmpreg); \ 929 } while(0) 930 931 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 932 __IO uint32_t tmpreg; \ 933 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ 934 /* Delay after an RCC peripheral clock enabling */ \ 935 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ 936 UNUSED(tmpreg); \ 937 } while(0) 938 939 #define __HAL_RCC_SAES_CLK_ENABLE() do { \ 940 __IO uint32_t tmpreg; \ 941 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ 942 /* Delay after an RCC peripheral clock enabling */ \ 943 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ 944 UNUSED(tmpreg); \ 945 } while(0) 946 947 #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ 948 __IO uint32_t tmpreg; \ 949 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ 950 /* Delay after an RCC peripheral clock enabling */ \ 951 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ 952 UNUSED(tmpreg); \ 953 } while(0) 954 955 #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ 956 __IO uint32_t tmpreg; \ 957 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ 958 /* Delay after an RCC peripheral clock enabling */ \ 959 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ 960 UNUSED(tmpreg); \ 961 } while(0) 962 963 #define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ 964 __IO uint32_t tmpreg; \ 965 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ 966 /* Delay after an RCC peripheral clock enabling */ \ 967 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ 968 UNUSED(tmpreg); \ 969 } while(0) 970 971 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 972 __IO uint32_t tmpreg; \ 973 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ 974 /* Delay after an RCC peripheral clock enabling */ \ 975 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ 976 UNUSED(tmpreg); \ 977 } while(0) 978 979 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 980 __IO uint32_t tmpreg; \ 981 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ 982 /* Delay after an RCC peripheral clock enabling */ \ 983 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ 984 UNUSED(tmpreg); \ 985 } while(0) 986 987 #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ 988 __IO uint32_t tmpreg; \ 989 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ 990 /* Delay after an RCC peripheral clock enabling */ \ 991 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ 992 UNUSED(tmpreg); \ 993 } while(0) 994 995 #define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ 996 __IO uint32_t tmpreg; \ 997 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ 998 /* Delay after an RCC peripheral clock enabling */ \ 999 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ 1000 UNUSED(tmpreg); \ 1001 } while(0) 1002 1003 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1004 __IO uint32_t tmpreg; \ 1005 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ 1006 /* Delay after an RCC peripheral clock enabling */ \ 1007 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ 1008 UNUSED(tmpreg); \ 1009 } while(0) 1010 1011 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 1012 __IO uint32_t tmpreg; \ 1013 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ 1014 /* Delay after an RCC peripheral clock enabling */ \ 1015 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ 1016 UNUSED(tmpreg); \ 1017 } while(0) 1018 1019 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ 1020 __IO uint32_t tmpreg; \ 1021 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ 1022 /* Delay after an RCC peripheral clock enabling */ \ 1023 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ 1024 UNUSED(tmpreg); \ 1025 } while(0) 1026 1027 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) 1028 1029 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) 1030 1031 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) 1032 1033 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) 1034 1035 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) 1036 1037 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) 1038 1039 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) 1040 1041 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) 1042 1043 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) 1044 1045 #define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) 1046 1047 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) 1048 1049 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) 1050 1051 #if defined(AES) 1052 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) 1053 #endif /* AES */ 1054 1055 #if defined(HASH) 1056 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) 1057 #endif /* HASH */ 1058 1059 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) 1060 1061 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) 1062 1063 #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) 1064 1065 #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) 1066 1067 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) 1068 1069 #define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) 1070 1071 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) 1072 1073 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) 1074 1075 #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) 1076 1077 #define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) 1078 1079 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) 1080 1081 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) 1082 1083 #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) 1084 /** 1085 * @} 1086 */ 1087 1088 /** @defgroup BUS AHB APB Peripheral Clock Enable Disable 1089 * @{ 1090 */ 1091 #define __HAL_RCC_AHB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); 1092 1093 #define __HAL_RCC_AHB2_1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); 1094 1095 #define __HAL_RCC_AHB2_2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); 1096 1097 #define __HAL_RCC_AHB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); 1098 1099 #define __HAL_RCC_APB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); 1100 1101 #define __HAL_RCC_APB2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); 1102 1103 #define __HAL_RCC_APB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); 1104 1105 #define __HAL_RCC_AHB1_CLK_ENABLE() do { \ 1106 __IO uint32_t tmpreg; \ 1107 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 1108 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 1109 UNUSED(tmpreg); \ 1110 } while(0) 1111 1112 #define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \ 1113 __IO uint32_t tmpreg; \ 1114 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ 1115 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ 1116 UNUSED(tmpreg); \ 1117 } while(0) 1118 1119 #define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \ 1120 __IO uint32_t tmpreg; \ 1121 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ 1122 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ 1123 UNUSED(tmpreg); \ 1124 } while(0) 1125 1126 1127 #define __HAL_RCC_AHB3_CLK_ENABLE() do { \ 1128 __IO uint32_t tmpreg; \ 1129 CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ 1130 tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ 1131 UNUSED(tmpreg); \ 1132 } while(0) 1133 1134 #define __HAL_RCC_APB1_CLK_ENABLE() do { \ 1135 __IO uint32_t tmpreg; \ 1136 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 1137 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 1138 UNUSED(tmpreg); \ 1139 } while(0) 1140 1141 #define __HAL_RCC_APB2_CLK_ENABLE() do { \ 1142 __IO uint32_t tmpreg; \ 1143 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 1144 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 1145 UNUSED(tmpreg); \ 1146 } while(0) 1147 1148 #define __HAL_RCC_APB3_CLK_ENABLE() do { \ 1149 __IO uint32_t tmpreg; \ 1150 CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ 1151 tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ 1152 UNUSED(tmpreg); \ 1153 } while(0) 1154 1155 /** 1156 * @} 1157 */ 1158 1159 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3ENR Peripheral Clock Enable Disable 1160 * @brief Enable or disable the AHB3ENR peripheral clock. 1161 * @note After reset, the peripheral clock (used for registers read/write access) 1162 * is disabled and the application software has to enable this clock before 1163 * using it. 1164 * @{ 1165 */ 1166 #define __HAL_RCC_LPGPIO1_CLK_ENABLE() do { \ 1167 __IO uint32_t tmpreg; \ 1168 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ 1169 /* Delay after an RCC peripheral clock enabling */ \ 1170 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ 1171 UNUSED(tmpreg); \ 1172 } while(0) 1173 1174 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 1175 __IO uint32_t tmpreg; \ 1176 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ 1177 /* Delay after an RCC peripheral clock enabling */ \ 1178 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ 1179 UNUSED(tmpreg); \ 1180 } while(0) 1181 1182 #define __HAL_RCC_ADC4_CLK_ENABLE() do { \ 1183 __IO uint32_t tmpreg; \ 1184 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ 1185 /* Delay after an RCC peripheral clock enabling */ \ 1186 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ 1187 UNUSED(tmpreg); \ 1188 } while(0) 1189 1190 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 1191 __IO uint32_t tmpreg; \ 1192 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ 1193 /* Delay after an RCC peripheral clock enabling */ \ 1194 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ 1195 UNUSED(tmpreg); \ 1196 } while(0) 1197 1198 #define __HAL_RCC_LPDMA1_CLK_ENABLE() do { \ 1199 __IO uint32_t tmpreg; \ 1200 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ 1201 /* Delay after an RCC peripheral clock enabling */ \ 1202 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ 1203 UNUSED(tmpreg); \ 1204 } while(0) 1205 1206 #define __HAL_RCC_ADF1_CLK_ENABLE() do { \ 1207 __IO uint32_t tmpreg; \ 1208 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ 1209 /* Delay after an RCC peripheral clock enabling */ \ 1210 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ 1211 UNUSED(tmpreg); \ 1212 } while(0) 1213 1214 #define __HAL_RCC_GTZC2_CLK_ENABLE() do { \ 1215 __IO uint32_t tmpreg; \ 1216 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ 1217 /* Delay after an RCC peripheral clock enabling */ \ 1218 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ 1219 UNUSED(tmpreg); \ 1220 } while(0) 1221 1222 #define __HAL_RCC_SRAM4_CLK_ENABLE() do { \ 1223 __IO uint32_t tmpreg; \ 1224 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ 1225 /* Delay after an RCC peripheral clock enabling */ \ 1226 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ 1227 UNUSED(tmpreg); \ 1228 } while(0) 1229 1230 #define __HAL_RCC_LPGPIO1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) 1231 1232 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) 1233 1234 #define __HAL_RCC_ADC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) 1235 1236 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) 1237 1238 #define __HAL_RCC_LPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) 1239 1240 #define __HAL_RCC_ADF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) 1241 1242 #define __HAL_RCC_GTZC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) 1243 1244 #define __HAL_RCC_SRAM4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) 1245 /** 1246 * @} 1247 */ 1248 1249 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1250 * @brief Enable or disable the APB1 peripheral clock. 1251 * @note After reset, the peripheral clock (used for registers read/write access) 1252 * is disabled and the application software has to enable this clock before 1253 * using it. 1254 * @{ 1255 */ 1256 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1257 __IO uint32_t tmpreg; \ 1258 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1259 /* Delay after an RCC peripheral clock enabling */ \ 1260 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1261 UNUSED(tmpreg); \ 1262 } while(0) 1263 1264 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1265 __IO uint32_t tmpreg; \ 1266 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1267 /* Delay after an RCC peripheral clock enabling */ \ 1268 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1269 UNUSED(tmpreg); \ 1270 } while(0) 1271 1272 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1273 __IO uint32_t tmpreg; \ 1274 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1275 /* Delay after an RCC peripheral clock enabling */ \ 1276 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1277 UNUSED(tmpreg); \ 1278 } while(0) 1279 1280 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 1281 __IO uint32_t tmpreg; \ 1282 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1283 /* Delay after an RCC peripheral clock enabling */ \ 1284 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1285 UNUSED(tmpreg); \ 1286 } while(0) 1287 1288 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1289 __IO uint32_t tmpreg; \ 1290 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1291 /* Delay after an RCC peripheral clock enabling */ \ 1292 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1293 UNUSED(tmpreg); \ 1294 } while(0) 1295 1296 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1297 __IO uint32_t tmpreg; \ 1298 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1299 /* Delay after an RCC peripheral clock enabling */ \ 1300 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1301 UNUSED(tmpreg); \ 1302 } while(0) 1303 1304 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 1305 __IO uint32_t tmpreg; \ 1306 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1307 /* Delay after an RCC peripheral clock enabling */ \ 1308 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1309 UNUSED(tmpreg); \ 1310 } while(0) 1311 1312 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1313 __IO uint32_t tmpreg; \ 1314 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1315 /* Delay after an RCC peripheral clock enabling */ \ 1316 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1317 UNUSED(tmpreg); \ 1318 } while(0) 1319 1320 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1321 __IO uint32_t tmpreg; \ 1322 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1323 /* Delay after an RCC peripheral clock enabling */ \ 1324 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1325 UNUSED(tmpreg); \ 1326 } while(0) 1327 1328 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1329 __IO uint32_t tmpreg; \ 1330 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1331 /* Delay after an RCC peripheral clock enabling */ \ 1332 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1333 UNUSED(tmpreg); \ 1334 } while(0) 1335 1336 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1337 __IO uint32_t tmpreg; \ 1338 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1339 /* Delay after an RCC peripheral clock enabling */ \ 1340 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1341 UNUSED(tmpreg); \ 1342 } while(0) 1343 1344 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1345 __IO uint32_t tmpreg; \ 1346 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1347 /* Delay after an RCC peripheral clock enabling */ \ 1348 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1349 UNUSED(tmpreg); \ 1350 } while(0) 1351 1352 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1353 __IO uint32_t tmpreg; \ 1354 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1355 /* Delay after an RCC peripheral clock enabling */ \ 1356 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1357 UNUSED(tmpreg); \ 1358 } while(0) 1359 1360 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1361 __IO uint32_t tmpreg; \ 1362 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1363 /* Delay after an RCC peripheral clock enabling */ \ 1364 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1365 UNUSED(tmpreg); \ 1366 } while(0) 1367 1368 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1369 __IO uint32_t tmpreg; \ 1370 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1371 /* Delay after an RCC peripheral clock enabling */ \ 1372 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1373 UNUSED(tmpreg); \ 1374 } while(0) 1375 1376 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1377 __IO uint32_t tmpreg; \ 1378 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1379 /* Delay after an RCC peripheral clock enabling */ \ 1380 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1381 UNUSED(tmpreg); \ 1382 } while(0) 1383 1384 #define __HAL_RCC_DTS_CLK_ENABLE() do { \ 1385 __IO uint32_t tmpreg; \ 1386 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN); \ 1387 /* Delay after an RCC peripheral clock enabling */ \ 1388 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN); \ 1389 UNUSED(tmpreg); \ 1390 } while(0) 1391 1392 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1393 __IO uint32_t tmpreg; \ 1394 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1395 /* Delay after an RCC peripheral clock enabling */ \ 1396 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1397 UNUSED(tmpreg); \ 1398 } while(0) 1399 1400 #define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ 1401 __IO uint32_t tmpreg; \ 1402 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ 1403 /* Delay after an RCC peripheral clock enabling */ \ 1404 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ 1405 UNUSED(tmpreg); \ 1406 } while(0) 1407 1408 #define __HAL_RCC_UCPD_CLK_ENABLE() do { \ 1409 __IO uint32_t tmpreg; \ 1410 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1411 /* Delay after an RCC peripheral clock enabling */ \ 1412 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1413 UNUSED(tmpreg); \ 1414 } while(0) 1415 1416 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 1417 1418 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 1419 1420 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 1421 1422 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 1423 1424 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 1425 1426 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 1427 1428 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) 1429 1430 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 1431 1432 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 1433 1434 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 1435 1436 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 1437 1438 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 1439 1440 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 1441 1442 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 1443 1444 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) 1445 1446 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) 1447 1448 #define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2 , RCC_APB1ENR2_DTSEN) 1449 1450 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 1451 1452 #define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) 1453 1454 #define __HAL_RCC_UCPD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) 1455 /** 1456 * @} 1457 */ 1458 1459 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1460 * @brief Enable or disable the APB2 peripheral clock. 1461 * @note After reset, the peripheral clock (used for registers read/write access) 1462 * is disabled and the application software has to enable this clock before 1463 * using it. 1464 * @{ 1465 */ 1466 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1467 __IO uint32_t tmpreg; \ 1468 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1469 /* Delay after an RCC peripheral clock enabling */ \ 1470 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1471 UNUSED(tmpreg); \ 1472 } while(0) 1473 1474 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1475 __IO uint32_t tmpreg; \ 1476 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1477 /* Delay after an RCC peripheral clock enabling */ \ 1478 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1479 UNUSED(tmpreg); \ 1480 } while(0) 1481 1482 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1483 __IO uint32_t tmpreg; \ 1484 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1485 /* Delay after an RCC peripheral clock enabling */ \ 1486 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1487 UNUSED(tmpreg); \ 1488 } while(0) 1489 1490 1491 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1492 __IO uint32_t tmpreg; \ 1493 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1494 /* Delay after an RCC peripheral clock enabling */ \ 1495 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1496 UNUSED(tmpreg); \ 1497 } while(0) 1498 1499 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1500 __IO uint32_t tmpreg; \ 1501 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1502 /* Delay after an RCC peripheral clock enabling */ \ 1503 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1504 UNUSED(tmpreg); \ 1505 } while(0) 1506 1507 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1508 __IO uint32_t tmpreg; \ 1509 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1510 /* Delay after an RCC peripheral clock enabling */ \ 1511 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1512 UNUSED(tmpreg); \ 1513 } while(0) 1514 1515 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1516 __IO uint32_t tmpreg; \ 1517 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1518 /* Delay after an RCC peripheral clock enabling */ \ 1519 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1520 UNUSED(tmpreg); \ 1521 } while(0) 1522 1523 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1524 __IO uint32_t tmpreg; \ 1525 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1526 /* Delay after an RCC peripheral clock enabling */ \ 1527 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1528 UNUSED(tmpreg); \ 1529 } while(0) 1530 1531 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1532 __IO uint32_t tmpreg; \ 1533 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1534 /* Delay after an RCC peripheral clock enabling */ \ 1535 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1536 UNUSED(tmpreg); \ 1537 } while(0) 1538 1539 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1540 1541 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1542 1543 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1544 1545 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1546 1547 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1548 1549 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1550 1551 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1552 1553 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1554 1555 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1556 /** 1557 * @} 1558 */ 1559 1560 /** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable 1561 * @brief Enable or disable the APB3 peripheral clock. 1562 * @note After reset, the peripheral clock (used for registers read/write access) 1563 * is disabled and the application software has to enable this clock before 1564 * using it. 1565 * @{ 1566 */ 1567 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1568 __IO uint32_t tmpreg; \ 1569 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ 1570 /* Delay after an RCC peripheral clock enabling */ \ 1571 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ 1572 UNUSED(tmpreg); \ 1573 } while(0) 1574 1575 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1576 __IO uint32_t tmpreg; \ 1577 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ 1578 /* Delay after an RCC peripheral clock enabling */ \ 1579 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ 1580 UNUSED(tmpreg); \ 1581 } while(0) 1582 1583 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1584 __IO uint32_t tmpreg; \ 1585 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1586 /* Delay after an RCC peripheral clock enabling */ \ 1587 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1588 UNUSED(tmpreg); \ 1589 } while(0) 1590 1591 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1592 __IO uint32_t tmpreg; \ 1593 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1594 /* Delay after an RCC peripheral clock enabling */ \ 1595 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1596 UNUSED(tmpreg); \ 1597 } while(0) 1598 1599 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1600 __IO uint32_t tmpreg; \ 1601 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1602 /* Delay after an RCC peripheral clock enabling */ \ 1603 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1604 UNUSED(tmpreg); \ 1605 } while(0) 1606 1607 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 1608 __IO uint32_t tmpreg; \ 1609 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1610 /* Delay after an RCC peripheral clock enabling */ \ 1611 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1612 UNUSED(tmpreg); \ 1613 } while(0) 1614 1615 #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ 1616 __IO uint32_t tmpreg; \ 1617 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1618 /* Delay after an RCC peripheral clock enabling */ \ 1619 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1620 UNUSED(tmpreg); \ 1621 } while(0) 1622 1623 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1624 __IO uint32_t tmpreg; \ 1625 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ 1626 /* Delay after an RCC peripheral clock enabling */ \ 1627 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ 1628 UNUSED(tmpreg); \ 1629 } while(0) 1630 1631 #define __HAL_RCC_COMP_CLK_ENABLE() do { \ 1632 __IO uint32_t tmpreg; \ 1633 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ 1634 /* Delay after an RCC peripheral clock enabling */ \ 1635 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ 1636 UNUSED(tmpreg); \ 1637 } while(0) 1638 1639 #define __HAL_RCC_VREF_CLK_ENABLE() do { \ 1640 __IO uint32_t tmpreg; \ 1641 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1642 /* Delay after an RCC peripheral clock enabling */ \ 1643 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1644 UNUSED(tmpreg); \ 1645 } while(0) 1646 1647 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 1648 __IO uint32_t tmpreg; \ 1649 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1650 /* Delay after an RCC peripheral clock enabling */ \ 1651 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1652 UNUSED(tmpreg); \ 1653 } while(0) 1654 1655 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) 1656 1657 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) 1658 1659 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) 1660 1661 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) 1662 1663 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) 1664 1665 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) 1666 1667 #define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) 1668 1669 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) 1670 1671 #define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) 1672 1673 #define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) 1674 1675 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) 1676 /** 1677 * @} 1678 */ 1679 1680 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1681 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1682 * @note After reset, the peripheral clock (used for registers read/write access) 1683 * is disabled and the application software has to enable this clock before 1684 * using it. 1685 * @{ 1686 */ 1687 #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) 1688 1689 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) 1690 1691 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) 1692 1693 #define __HAL_RCC_MDF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) != 0U) 1694 1695 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) 1696 1697 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 1698 1699 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) 1700 1701 #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) 1702 1703 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) 1704 1705 #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U) 1706 1707 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) != 0U) 1708 1709 #define __HAL_RCC_DCACHE1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) != 0U) 1710 1711 #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) 1712 1713 #define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) 1714 1715 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) 1716 1717 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) 1718 1719 #define __HAL_RCC_MDF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) == 0U) 1720 1721 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) 1722 1723 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 1724 1725 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) 1726 1727 #define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) 1728 1729 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) 1730 1731 #define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) == 0U) 1732 1733 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) == 0U) 1734 1735 #define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U) 1736 1737 #define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U) 1738 /** 1739 * @} 1740 */ 1741 1742 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1743 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1744 * @note After reset, the peripheral clock (used for registers read/write access) 1745 * is disabled and the application software has to enable this clock before 1746 * using it. 1747 * @{ 1748 */ 1749 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) != 0U) 1750 1751 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) != 0U) 1752 1753 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) != 0U) 1754 1755 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) != 0U) 1756 1757 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) != 0U) 1758 1759 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) != 0U) 1760 1761 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) != 0U) 1762 1763 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) != 0U) 1764 1765 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) != 0U) 1766 1767 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) != 0U) 1768 1769 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) != 0U) 1770 1771 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) 1772 1773 #if defined(AES) 1774 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) != 0U) 1775 #endif /* AES */ 1776 1777 #if defined(HASH) 1778 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) != 0U) 1779 #endif /* HASH */ 1780 1781 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) != 0U) 1782 1783 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) != 0U) 1784 1785 #define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U) 1786 1787 #define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) != 0U) 1788 1789 #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) != 0U) 1790 1791 #define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) != 0U) 1792 1793 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) != 0U) 1794 1795 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) != 0U) 1796 1797 #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U) 1798 1799 #define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U) 1800 1801 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) != 0U) 1802 1803 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U) 1804 1805 #define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U) 1806 1807 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) == 0U) 1808 1809 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) == 0U) 1810 1811 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) == 0U) 1812 1813 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) == 0U) 1814 1815 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) == 0U) 1816 1817 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) == 0U) 1818 1819 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) == 0U) 1820 1821 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) == 0U) 1822 1823 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) == 0U) 1824 1825 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) == 0U) 1826 1827 #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) == 0U) 1828 1829 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) 1830 1831 #if defined(AES) 1832 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) == 0U) 1833 #endif /* AES */ 1834 1835 #if defined(HASH) 1836 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) == 0U) 1837 #endif /* HASH */ 1838 1839 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) == 0U) 1840 1841 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) == 0U) 1842 1843 #define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) == 0U) 1844 1845 #define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) == 0U) 1846 1847 #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) == 0U) 1848 1849 #define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) == 0U) 1850 1851 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) == 0U) 1852 1853 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) == 0U) 1854 1855 #define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) == 0U) 1856 1857 #define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) == 0U) 1858 1859 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U) 1860 1861 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U) 1862 1863 #define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U) 1864 /** 1865 * @} 1866 */ 1867 1868 /** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1869 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1870 * @note After reset, the peripheral clock (used for registers read/write access) 1871 * is disabled and the application software has to enable this clock before 1872 * using it. 1873 * @{ 1874 */ 1875 #define __HAL_RCC_LPGPIO1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) != 0U) 1876 1877 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) != 0U) 1878 1879 #define __HAL_RCC_ADC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) != 0U) 1880 1881 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) != 0U) 1882 1883 #define __HAL_RCC_LPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) != 0U) 1884 1885 #define __HAL_RCC_ADF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) != 0U) 1886 1887 #define __HAL_RCC_GTZC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) != 0U) 1888 1889 #define __HAL_RCC_SRAM4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) != 0U) 1890 1891 #define __HAL_RCC_LPGPIO1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) == 0U) 1892 1893 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) == 0U) 1894 1895 #define __HAL_RCC_ADC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) == 0U) 1896 1897 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) == 0U) 1898 1899 #define __HAL_RCC_LPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) == 0U) 1900 1901 #define __HAL_RCC_ADF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) == 0U) 1902 1903 #define __HAL_RCC_GTZC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) == 0U) 1904 1905 #define __HAL_RCC_SRAM4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) == 0U) 1906 /** 1907 * @} 1908 */ 1909 1910 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1911 * @brief Check whether the APB1 peripheral clock is enabled or not. 1912 * @note After reset, the peripheral clock (used for registers read/write access) 1913 * is disabled and the application software has to enable this clock before 1914 * using it. 1915 * @{ 1916 */ 1917 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 1918 1919 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 1920 1921 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) 1922 1923 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) 1924 1925 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) 1926 1927 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) 1928 1929 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 1930 1931 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) 1932 1933 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 1934 1935 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) 1936 1937 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) 1938 1939 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) 1940 1941 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) 1942 1943 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) 1944 1945 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) 1946 1947 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) 1948 1949 #define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN) != 0U) 1950 1951 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) 1952 1953 #define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) != 0U) 1954 1955 #define __HAL_RCC_UCPD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) 1956 1957 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) 1958 1959 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) 1960 1961 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) 1962 1963 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) 1964 1965 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) 1966 1967 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) 1968 1969 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) 1970 1971 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) 1972 1973 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) 1974 1975 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) 1976 1977 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) 1978 1979 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) 1980 1981 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) 1982 1983 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) 1984 1985 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) 1986 1987 #define __HAL_RCC_DTS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN) == 0U) 1988 1989 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) 1990 1991 #define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) == 0U) 1992 1993 #define __HAL_RCC_UCPD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U) 1994 /** 1995 * @} 1996 */ 1997 1998 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 1999 * @brief Check whether the APB2 peripheral clock is enabled or not. 2000 * @note After reset, the peripheral clock (used for registers read/write access) 2001 * is disabled and the application software has to enable this clock before 2002 * using it. 2003 * @{ 2004 */ 2005 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 2006 2007 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 2008 2009 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 2010 2011 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 2012 2013 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 2014 2015 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 2016 2017 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 2018 2019 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 2020 2021 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 2022 2023 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 2024 2025 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 2026 2027 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 2028 2029 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 2030 2031 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 2032 2033 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 2034 2035 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 2036 2037 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 2038 2039 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 2040 /** 2041 * @} 2042 */ 2043 2044 /** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status 2045 * @brief Check whether the APB3 peripheral clock is enabled or not. 2046 * @note After reset, the peripheral clock (used for registers read/write access) 2047 * is disabled and the application software has to enable this clock before 2048 * using it. 2049 * @{ 2050 */ 2051 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) != 0U) 2052 2053 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) != 0U) 2054 2055 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) != 0U) 2056 2057 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) != 0U) 2058 2059 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) != 0U) 2060 2061 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) != 0U) 2062 2063 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) != 0U) 2064 2065 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) != 0U) 2066 2067 #define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) != 0U) 2068 2069 #define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) != 0U) 2070 2071 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) 2072 2073 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) == 0U) 2074 2075 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) == 0U) 2076 2077 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) == 0U) 2078 2079 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) == 0U) 2080 2081 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) == 0U) 2082 2083 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) == 0U) 2084 2085 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) == 0U) 2086 2087 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) == 0U) 2088 2089 #define __HAL_RCC_COMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) == 0U) 2090 2091 #define __HAL_RCC_VREF_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) == 0U) 2092 2093 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) 2094 /** 2095 * @} 2096 */ 2097 2098 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 2099 * @brief Force or release AHB1 peripheral reset. 2100 * @{ 2101 */ 2102 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x0007100FU) 2103 2104 #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2105 2106 #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2107 2108 #define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2109 2110 #define __HAL_RCC_MDF1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) 2111 2112 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2113 2114 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2115 2116 #define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2117 2118 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2119 2120 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 2121 2122 #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2123 2124 #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2125 2126 #define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2127 2128 #define __HAL_RCC_MDF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) 2129 2130 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2131 2132 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2133 2134 #define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2135 2136 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2137 /** 2138 * @} 2139 */ 2140 2141 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 2142 * @brief Force or release AHB2 peripheral reset. 2143 * @{ 2144 */ 2145 #define __HAL_RCC_AHB2_FORCE_RESET() do{\ 2146 WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\ 2147 WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\ 2148 }while(0) 2149 2150 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) 2151 2152 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) 2153 2154 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) 2155 2156 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) 2157 2158 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) 2159 2160 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) 2161 2162 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) 2163 2164 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) 2165 2166 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) 2167 2168 #define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC1RST) 2169 2170 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) 2171 2172 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) 2173 2174 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) 2175 2176 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) 2177 2178 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) 2179 2180 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) 2181 2182 #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) 2183 2184 #define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) 2185 2186 #define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) 2187 2188 #define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) 2189 2190 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) 2191 2192 #define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) 2193 2194 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) 2195 2196 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) 2197 2198 #define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) 2199 2200 #define __HAL_RCC_AHB2_RELEASE_RESET() do{\ 2201 WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\ 2202 WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\ 2203 }while(0) 2204 2205 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) 2206 2207 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) 2208 2209 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) 2210 2211 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) 2212 2213 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) 2214 2215 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) 2216 2217 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) 2218 2219 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) 2220 2221 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) 2222 2223 #define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC1RST) 2224 2225 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) 2226 2227 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) 2228 2229 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) 2230 2231 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) 2232 2233 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) 2234 2235 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) 2236 2237 #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) 2238 2239 #define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) 2240 2241 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) 2242 2243 #define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) 2244 2245 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) 2246 2247 #define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) 2248 2249 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) 2250 2251 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) 2252 2253 #define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) 2254 /** 2255 * @} 2256 */ 2257 2258 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 2259 * @brief Force or release AHB3 peripheral reset. 2260 * @{ 2261 */ 2262 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000661U) 2263 2264 #define __HAL_RCC_LPGPIO1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST) 2265 2266 #define __HAL_RCC_ADC4_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST) 2267 2268 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST) 2269 2270 #define __HAL_RCC_LPDMA1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) 2271 2272 #define __HAL_RCC_ADF1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) 2273 2274 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) 2275 2276 #define __HAL_RCC_LPGPIO1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST) 2277 2278 #define __HAL_RCC_ADC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST) 2279 2280 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST) 2281 2282 #define __HAL_RCC_LPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) 2283 2284 #define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) 2285 /** 2286 * @} 2287 */ 2288 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 2289 * @brief Force or release APB1 peripheral reset. 2290 * @{ 2291 */ 2292 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 2293 WRITE_REG(RCC->APB1RSTR1, 0x027E403FU); \ 2294 WRITE_REG(RCC->APB1RSTR2, 0x00800222U); \ 2295 } while(0) 2296 2297 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2298 2299 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2300 2301 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2302 2303 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2304 2305 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2306 2307 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2308 2309 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2310 2311 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2312 2313 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2314 2315 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2316 2317 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2318 2319 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2320 2321 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2322 2323 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2324 2325 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2326 2327 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2328 2329 #define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) 2330 2331 #define __HAL_RCC_UCPD_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 2332 2333 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 2334 WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \ 2335 WRITE_REG(RCC->APB1RSTR2, 0x00000000U); \ 2336 } while(0) 2337 2338 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2339 2340 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2341 2342 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2343 2344 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2345 2346 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2347 2348 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2349 2350 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2351 2352 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2353 2354 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2355 2356 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2357 2358 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2359 2360 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2361 2362 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2363 2364 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2365 2366 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2367 2368 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2369 2370 #define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) 2371 2372 #define __HAL_RCC_UCPD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 2373 /** 2374 * @} 2375 */ 2376 2377 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 2378 * @brief Force or release APB2 peripheral reset. 2379 * @{ 2380 */ 2381 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00677800U) 2382 2383 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 2384 2385 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 2386 2387 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 2388 2389 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 2390 2391 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 2392 2393 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 2394 2395 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 2396 2397 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 2398 2399 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 2400 2401 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 2402 2403 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 2404 2405 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 2406 2407 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 2408 2409 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 2410 2411 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 2412 2413 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 2414 2415 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 2416 2417 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 2418 2419 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 2420 /** 2421 * @} 2422 */ 2423 2424 /** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset 2425 * @brief Force or release APB3 peripheral reset. 2426 * @{ 2427 */ 2428 #define __HAL_RCC_APB3_FORCE_RESET() WRITE_REG(RCC->APB3RSTR, 0x0010F8E2U) 2429 2430 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST) 2431 2432 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST) 2433 2434 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 2435 2436 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 2437 2438 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 2439 2440 #define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 2441 2442 #define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 2443 2444 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST) 2445 2446 #define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) 2447 2448 #define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 2449 2450 #define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) 2451 2452 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST) 2453 2454 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST) 2455 2456 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 2457 2458 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 2459 2460 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 2461 2462 #define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 2463 2464 #define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 2465 2466 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST) 2467 2468 #define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) 2469 2470 #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 2471 /** 2472 * @} 2473 */ 2474 2475 /** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 2476 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep and Stop) mode. 2477 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 2478 * power consumption. 2479 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 2480 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 2481 * is enabled only when a peripheral requests AHB clock. 2482 * @{ 2483 */ 2484 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) 2485 2486 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) 2487 2488 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) 2489 2490 #define __HAL_RCC_MDF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN) 2491 2492 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2493 2494 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2495 2496 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2497 2498 #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) 2499 2500 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 2501 2502 #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) 2503 2504 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN) 2505 2506 #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 2507 2508 #define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) 2509 2510 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2511 2512 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) 2513 2514 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) 2515 2516 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) 2517 2518 #define __HAL_RCC_MDF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN) 2519 2520 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2521 2522 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2523 2524 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2525 2526 #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) 2527 2528 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 2529 2530 #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) 2531 2532 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN) 2533 2534 #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 2535 2536 #define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) 2537 2538 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2539 /** 2540 * @} 2541 */ 2542 2543 /** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 2544 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep and Stop) mode. 2545 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 2546 * power consumption. 2547 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 2548 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 2549 * is enabled only when a peripheral requests AHB clock. 2550 * @{ 2551 */ 2552 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) 2553 2554 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN) 2555 2556 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN) 2557 2558 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN) 2559 2560 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) 2561 2562 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) 2563 2564 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) 2565 2566 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) 2567 2568 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) 2569 2570 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC1SMEN) 2571 2572 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) 2573 2574 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) 2575 2576 #if defined(AES) 2577 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN); 2578 #endif /* AES */ 2579 2580 #if defined(HASH) 2581 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN) 2582 #endif /* HASH */ 2583 2584 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) 2585 2586 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) 2587 2588 #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) 2589 2590 #define __HAL_RCC_OCTOSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) 2591 2592 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) 2593 2594 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) 2595 2596 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) 2597 2598 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) 2599 2600 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) 2601 2602 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) 2603 2604 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) 2605 2606 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) 2607 2608 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) 2609 2610 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) 2611 2612 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN) 2613 2614 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN) 2615 2616 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN) 2617 2618 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) 2619 2620 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) 2621 2622 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) 2623 2624 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) 2625 2626 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) 2627 2628 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC1SMEN) 2629 2630 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) 2631 2632 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) 2633 2634 #if defined(AES) 2635 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN); 2636 #endif /* AES */ 2637 2638 #if defined(HASH) 2639 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN) 2640 #endif /* HASH */ 2641 2642 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) 2643 2644 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) 2645 2646 #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) 2647 2648 #define __HAL_RCC_OCTOSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) 2649 2650 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) 2651 2652 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) 2653 2654 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) 2655 2656 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) 2657 2658 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) 2659 2660 #define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) 2661 2662 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) 2663 2664 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) 2665 2666 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) 2667 /** 2668 * @} 2669 */ 2670 2671 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3SMENR Peripheral Clock Sleep Enable Disable 2672 * @brief Enable or disable the AHB3SMENR peripheral clock during Low Power (Sleep and STOP ) mode. 2673 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 2674 * power consumption. 2675 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 2676 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 2677 * is enabled only when a peripheral requests AHB clock. 2678 * @{ 2679 */ 2680 #define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) 2681 2682 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) 2683 2684 #define __HAL_RCC_ADC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN) 2685 2686 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) 2687 2688 #define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) 2689 2690 #define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) 2691 2692 #define __HAL_RCC_GTZC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) 2693 2694 #define __HAL_RCC_SRAM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) 2695 2696 #define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) 2697 2698 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) 2699 2700 #define __HAL_RCC_ADC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN) 2701 2702 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) 2703 2704 #define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) 2705 2706 #define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) 2707 2708 #define __HAL_RCC_GTZC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) 2709 2710 #define __HAL_RCC_SRAM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) 2711 /** 2712 * @} 2713 */ 2714 2715 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 2716 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep and Stop) mode. 2717 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 2718 * power consumption. 2719 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 2720 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 2721 * is enabled only when a peripheral requests APB clock. 2722 * @{ 2723 */ 2724 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 2725 2726 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 2727 2728 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 2729 2730 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 2731 2732 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 2733 2734 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 2735 2736 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 2737 2738 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 2739 2740 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 2741 2742 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 2743 2744 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 2745 2746 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 2747 2748 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 2749 2750 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 2751 2752 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 2753 2754 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 2755 2756 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 2757 2758 #define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) 2759 2760 #define __HAL_RCC_UCPD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 2761 2762 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 2763 2764 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 2765 2766 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 2767 2768 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 2769 2770 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 2771 2772 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 2773 2774 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 2775 2776 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 2777 2778 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 2779 2780 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 2781 2782 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 2783 2784 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 2785 2786 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 2787 2788 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 2789 2790 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 2791 2792 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 2793 2794 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 2795 2796 #define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) 2797 2798 #define __HAL_RCC_UCPD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 2799 /** 2800 * @} 2801 */ 2802 2803 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 2804 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep and Stop) mode. 2805 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 2806 * power consumption. 2807 * @note After wakeup from SLEEP or STOP mode, the pseripheral clock is enabled again. 2808 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 2809 * is enabled only when a peripheral requests APB clock. 2810 * @{ 2811 */ 2812 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 2813 2814 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 2815 2816 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 2817 2818 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 2819 2820 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 2821 2822 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 2823 2824 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 2825 2826 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 2827 2828 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 2829 2830 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 2831 2832 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 2833 2834 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 2835 2836 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 2837 2838 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 2839 2840 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 2841 2842 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 2843 2844 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 2845 2846 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 2847 2848 /** 2849 * @} 2850 */ 2851 2852 /** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable 2853 * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep and Stop) mode. 2854 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 2855 * power consumption. 2856 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 2857 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 2858 * is enabled only when a peripheral requests APB clock. 2859 * @{ 2860 */ 2861 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN) 2862 2863 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN) 2864 2865 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN) 2866 2867 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN) 2868 2869 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN) 2870 2871 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN) 2872 2873 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN) 2874 2875 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN) 2876 2877 #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN) 2878 2879 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) 2880 2881 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) 2882 2883 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN) 2884 2885 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN) 2886 2887 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN) 2888 2889 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN) 2890 2891 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN) 2892 2893 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN) 2894 2895 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN) 2896 2897 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN) 2898 2899 #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN) 2900 2901 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) 2902 2903 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) 2904 /** 2905 * @} 2906 */ 2907 2908 /** @brief Enable or disable peripheral bus clock when SRD domain is in DRUN 2909 * @note After reset, peripheral clock is disabled when CPUs are in CSTOP 2910 * @{ 2911 */ 2912 #define __HAL_RCC_SPI3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) 2913 2914 #define __HAL_RCC_LPUART1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) 2915 2916 #define __HAL_RCC_I2C3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN) 2917 2918 #define __HAL_RCC_LPTIM1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN) 2919 2920 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN) 2921 2922 #define __HAL_RCC_LPTIM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN) 2923 2924 #define __HAL_RCC_OPAMP_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN) 2925 2926 #define __HAL_RCC_COMP12_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN) 2927 2928 #define __HAL_RCC_ADC4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN) 2929 2930 #define __HAL_RCC_VREF_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN) 2931 2932 #define __HAL_RCC_RTCAPB_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN) 2933 2934 #define __HAL_RCC_LPGPIO1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN) 2935 2936 #define __HAL_RCC_DAC1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN) 2937 2938 #define __HAL_RCC_LPDMA1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN) 2939 2940 #define __HAL_RCC_ADF1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) 2941 2942 #define __HAL_RCC_SRAM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) 2943 2944 2945 #define __HAL_RCC_SPI3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) 2946 2947 #define __HAL_RCC_LPUART1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) 2948 2949 #define __HAL_RCC_I2C3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN) 2950 2951 #define __HAL_RCC_LPTIM1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN) 2952 2953 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN) 2954 2955 #define __HAL_RCC_LPTIM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN) 2956 2957 #define __HAL_RCC_OPAMP_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN) 2958 2959 #define __HAL_RCC_COMP12_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN) 2960 2961 #define __HAL_RCC_ADC4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN) 2962 2963 #define __HAL_RCC_VREF_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN) 2964 2965 #define __HAL_RCC_RTCAPB_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN) 2966 2967 #define __HAL_RCC_LPGPIO1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN) 2968 2969 #define __HAL_RCC_DAC1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN) 2970 2971 #define __HAL_RCC_LPDMA1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN) 2972 2973 #define __HAL_RCC_ADF1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) 2974 2975 #define __HAL_RCC_SRAM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) 2976 /** 2977 * @} 2978 */ 2979 2980 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 2981 * @{ 2982 */ 2983 2984 /** @brief Macros to force or release the Backup domain reset. 2985 * @note This function resets the RTC peripheral (including the backup registers) 2986 * and the RTC clock source selection in RCC_CSR register. 2987 * @note The BKPSRAM is not affected by this reset. 2988 * @retval None 2989 */ 2990 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2991 2992 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2993 2994 /** 2995 * @} 2996 */ 2997 2998 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 2999 * @{ 3000 */ 3001 3002 /** @brief Macros to enable or disable the RTC clock. 3003 * @note As the RTC is in the Backup domain and write access is denied to 3004 * this domain after reset, you have to enable write access using 3005 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 3006 * (to be done once after reset). 3007 * @note These macros must be used after the RTC clock source was selected. 3008 * @retval None 3009 */ 3010 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3011 3012 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3013 3014 /** 3015 * @} 3016 */ 3017 3018 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 3019 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 3020 * It is used (enabled by hardware) as system clock source after startup 3021 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 3022 * of the HSE used directly or indirectly as system clock (if the Clock 3023 * Security System CSS is enabled). 3024 * @note HSI can not be stopped if it is used as system clock source. In this case, 3025 * you have to select another source of the system clock then stop the HSI. 3026 * @note After enabling the HSI, the application software should wait on HSIRDY 3027 * flag to be set indicating that HSI clock is stable and can be used as 3028 * system clock source. 3029 * This parameter can be: ENABLE or DISABLE. 3030 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 3031 * clock cycles. 3032 * @retval None 3033 */ 3034 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 3035 3036 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 3037 3038 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 3039 * @note The calibration is used to compensate for the variations in voltage 3040 * and temperature that influence the frequency of the internal HSI RC. 3041 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value 3042 * (default is RCC_HSICALIBRATION_DEFAULT). 3043 * This parameter must be a number between 0 and 0x20. 3044 * @retval None 3045 */ 3046 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 3047 MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR3_HSITRIM_Pos) 3048 3049 3050 /** 3051 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 3052 * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. 3053 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 3054 * speed because of the HSI startup time. 3055 * @note The enable of this function has not effect on the HSION bit. 3056 * This parameter can be: ENABLE or DISABLE. 3057 * @retval None 3058 */ 3059 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 3060 3061 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 3062 3063 /** 3064 * @brief Macros to enable or disable the force of the Internal Multi Speed kernel oscillator (MSIK) 3065 * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. 3066 * @note Keeping the MSIK ON in STOP mode allows to avoid slowing down the communication 3067 * speed because of the MSIK startup time. 3068 * @note The enable of this function has not effect on the MSIKON bit. 3069 * @note The MSIKERON must be configured at 0 before entreing stop 3 mode. 3070 * This parameter can be: ENABLE or DISABLE. 3071 * @retval None 3072 */ 3073 #define __HAL_RCC_MSIKSTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKERON) 3074 3075 #define __HAL_RCC_MSIKSTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKERON) 3076 3077 /** 3078 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 3079 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 3080 * It is used (enabled by hardware) as system clock source after 3081 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 3082 * of failure of the HSE used directly or indirectly as system clock 3083 * (if the Clock Security System CSS is enabled). 3084 * @note MSI can not be stopped if it is used as system clock source. 3085 * In this case, you have to select another source of the system 3086 * clock then stop the MSI. 3087 * @note After enabling the MSI, the application software should wait on 3088 * MSIRDY flag to be set indicating that MSI clock is stable and can 3089 * be used as system clock source. 3090 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 3091 * clock cycles. 3092 * @retval None 3093 */ 3094 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSISON) 3095 3096 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSISON) 3097 3098 /** 3099 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 3100 * @note After restart from Reset , the MSI clock is around 4 MHz. 3101 * After stop the startup clock can be MSI (at any of its possible 3102 * frequencies, the one that was used before entering stop mode) or HSI. 3103 * After Standby its frequency can be selected between 4 possible values 3104 * (1, 3.072, 4 or 8 MHz). 3105 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 3106 * (MSIRDY=1). 3107 * @note The MSI clock range after reset can be modified on the fly. 3108 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 3109 * This parameter must be one of the following values: 3110 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 3111 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz 3112 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 3113 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 3114 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) 3115 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3116 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 3117 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 3118 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 3119 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz 3120 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz 3121 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz 3122 * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz 3123 * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz 3124 * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz 3125 * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz 3126 * @retval None 3127 */ 3128 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 3129 do { \ 3130 SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ 3131 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, (__MSIRANGEVALUE__)); \ 3132 } while(0) 3133 /** 3134 * @brief Macro configures the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode 3135 * @note After restart from Reset , the MSIK clock is around 4 MHz. 3136 * After stop the startup clock can be MSIK (at any of its possible 3137 * frequencies, the one that was used before entering stop mode) or HSI. 3138 * After Standby its frequency can be selected between 4 possible values 3139 * (1, 3.072, 4 or 8 MHz). 3140 * @note MSIKRANGE can be modified when MSIK is OFF (MSIKON=0) or when MSIK is ready 3141 * (MSIKRDY=1). 3142 * @note The MSI clock range after reset can be modified on the fly. 3143 * @param __MSIKRANGEVALUE__: specifies the MSI clock range. 3144 * @arg @ref RCC_MSIKRANGE_0 MSIK clock is around 48 MHz 3145 * @arg @ref RCC_MSIKRANGE_1 MSIK clock is around 24 KHz 3146 * @arg @ref RCC_MSIKRANGE_2 MSIK clock is around 16 MHz 3147 * @arg @ref RCC_MSIKRANGE_3 MSIK clock is around 12 MHz 3148 * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset) 3149 * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz 3150 * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz 3151 * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz 3152 * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz 3153 * @arg @ref RCC_MSIKRANGE_9 MSIK clock is around 1.536 MHz 3154 * @arg @ref RCC_MSIKRANGE_10 MSIK clock is around 1.024 MHz 3155 * @arg @ref RCC_MSIKRANGE_11 MSIK clock is around 768 KHz 3156 * @arg @ref RCC_MSIKRANGE_12 MSIK clock is around 400 KHz 3157 * @arg @ref RCC_MSIKRANGE_13 MSIK clock is around 200 KHz 3158 * @arg @ref RCC_MSIKRANGE_14 MSIK clock is around 133 KHz 3159 * @arg @ref RCC_MSIKRANGE_15 MSIK clock is around 100 KHz 3160 * @retval None 3161 */ 3162 #define __HAL_RCC_MSIK_RANGE_CONFIG(__MSIKRANGEVALUE__) \ 3163 do { \ 3164 SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ 3165 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, (__MSIKRANGEVALUE__)); \ 3166 } while(0) 3167 3168 /** @brief Macros to enable or disable the MSI bias mode selection. 3169 * @note By default the MSI bias is in continuous mode in order to maintain 3170 * the output clocks accuracy. 3171 * @note Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy. 3172 * @retval None 3173 */ 3174 #define __HAL_RCC_MSIBIAS_SELECTION_ENABLE() SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS) 3175 3176 #define __HAL_RCC_MSIBIAS_SELECTION_DISABLE() CLEAR_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS) 3177 3178 /** @brief Macros to enable or disable LSE clock glitch filter . 3179 * @note The glitches on LSE can be filtred by setting the LSEGFON. 3180 * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). 3181 * @retval None 3182 */ 3183 3184 #define __HAL_RCC_LSE_GLITCHFILTER_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) 3185 3186 #define __HAL_RCC_LSE_GLITCHFILTER_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) 3187 /** 3188 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 3189 * After Standby its frequency can be selected between 5 possible values (4, 2, 1.5, 1, or 3.072 MHz). 3190 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 3191 * This parameter must be one of the following values: 3192 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) 3193 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3194 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz 3195 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 3196 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 3197 * @retval None 3198 */ 3199 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL);\ 3200 MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\ 3201 (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\ 3202 RCC_CSR_MSISSRANGE_Pos));\ 3203 } while(0) 3204 /** 3205 * @brief Macro configures the Internal Multi Speed oscillator (MSIK) clock range after Standby mode 3206 * After Standby its frequency can be selected between 5 possible values (4, 2, 1.5, 1, or 3.072 MHz). 3207 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 3208 * This parameter must be one of the following values: 3209 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) 3210 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3211 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz 3212 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 3213 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 3214 * @retval None 3215 */ 3216 #define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ 3217 MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\ 3218 (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\ 3219 RCC_CSR_MSISSRANGE_Pos));\ 3220 } while(0) 3221 3222 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 3223 * @retval MSI clock range. 3224 * This parameter must be one of the following values: 3225 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 3226 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz 3227 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 3228 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 3229 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz 3230 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3231 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 3232 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 3233 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 3234 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz 3235 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz 3236 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz 3237 * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz 3238 * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz 3239 * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz 3240 * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz 3241 */ 3242 #define __HAL_RCC_GET_MSI_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \ 3243 (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE)) : \ 3244 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE) << \ 3245 (RCC_ICSCR1_MSISRANGE_Pos - RCC_CSR_MSISSRANGE_Pos))) 3246 3247 /** @brief Macro to get the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode 3248 * @retval MSIK clock range. 3249 * This parameter must be one of the following values: 3250 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 3251 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz 3252 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 3253 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 3254 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz 3255 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3256 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 3257 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 3258 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 3259 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz 3260 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz 3261 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz 3262 * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz 3263 * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz 3264 * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz 3265 * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz 3266 */ 3267 #define __HAL_RCC_GET_MSIK_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \ 3268 (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE)) : \ 3269 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSIKSRANGE) << \ 3270 (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos))) 3271 3272 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 3273 * @note After enabling the LSI, the application software should wait on 3274 * LSIRDY flag to be set indicating that LSI clock is stable and can 3275 * be used to clock the IWDG and/or the RTC. 3276 * @note LSI can not be disabled if the IWDG is running. 3277 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 3278 * clock cycles. 3279 * @retval None 3280 */ 3281 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSION) 3282 3283 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION|RCC_BDCR_LSIPREDIV) 3284 3285 /** 3286 * @brief Macro to configure the External High Speed oscillator (HSE). 3287 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 3288 * supported by this macro. User should request a transition to HSE Off 3289 * first and then HSE On or HSE Bypass. 3290 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 3291 * software should wait on HSERDY flag to be set indicating that HSE clock 3292 * is stable and can be used to clock the PLL and/or system clock. 3293 * @note HSE state can not be changed if it is used directly or through the 3294 * PLL as system clock. In this case, you have to select another source 3295 * of the system clock then change the HSE state (ex. disable it). 3296 * @note The HSE is stopped by hardware when entering STOP and STANDBY or shutdown modes. 3297 * @param __STATE__: specifies the new state of the HSE. 3298 * This parameter can be one of the following values: 3299 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 3300 * 6 HSE oscillator clock cycles. 3301 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 3302 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 3303 * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed through I/O Schmitt trigger . 3304 * @retval None 3305 */ 3306 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 3307 do { \ 3308 if((__STATE__) == RCC_HSE_ON) \ 3309 { \ 3310 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 3311 } \ 3312 else if((__STATE__) == RCC_HSE_BYPASS) \ 3313 { \ 3314 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 3315 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 3316 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 3317 } \ 3318 else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ 3319 { \ 3320 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 3321 SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ 3322 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 3323 } \ 3324 else \ 3325 { \ 3326 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 3327 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 3328 } \ 3329 } while(0) 3330 3331 /** @brief Macro to enable or disable the LSE system clock. 3332 * @note This clock can be used by any peripheral when its source clock is the LSE or at system 3333 * in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. 3334 * @note The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by 3335 * the CSS on LSE, by a peripheral or any other source clock using LSE. 3336 * @retval None 3337 */ 3338 #define __HAL_RCC_LSESYS_ENABLE() SET_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) 3339 3340 #define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) 3341 3342 3343 /** @brief Macro to set Low-speed clock (LSI) divider. 3344 * @note This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). 3345 * The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. 3346 * 3347 * @param __DIVIDER__ : specifies the divider value 3348 * This parameter can be one of the following values 3349 * @arg @ref RCC_LSI_DIV1 3350 * @arg @ref RCC_LSI_DIV128 3351 * @retval None 3352 */ 3353 #define __HAL_RCC_LSI_DIV_CONFIG(__DIVIDER__) \ 3354 do { \ 3355 if((__DIVIDER__) == RCC_LSI_DIV128) \ 3356 { \ 3357 SET_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \ 3358 } \ 3359 else \ 3360 { \ 3361 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \ 3362 } \ 3363 } while(0) 3364 3365 /** 3366 * @brief Macro to configure the External Low Speed oscillator (LSE). 3367 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 3368 * supported by this macro. User should request a transition to LSE Off 3369 * first and then LSE On or LSE Bypass. 3370 * @note As the LSE is in the Backup domain and write access is denied to 3371 * this domain after reset, you have to enable write access using 3372 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3373 * (to be done once after reset). 3374 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 3375 * software should wait on LSERDY flag to be set indicating that LSE clock 3376 * is stable and can be used to clock the RTC. 3377 * @param __STATE__: specifies the new state of the LSE. 3378 * This parameter can be one of the following values: 3379 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 3380 * 6 LSE oscillator clock cycles. 3381 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 3382 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 3383 * @retval None 3384 */ 3385 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 3386 do { \ 3387 if((__STATE__) == RCC_LSE_ON) \ 3388 { \ 3389 SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \ 3390 } \ 3391 else if((__STATE__) == RCC_LSE_BYPASS) \ 3392 { \ 3393 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 3394 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 3395 } \ 3396 else \ 3397 { \ 3398 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 3399 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 3400 } \ 3401 } while(0) 3402 3403 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 3404 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 3405 * @note After enabling the HSI48, the application software should wait on HSI48RDY 3406 * flag to be set indicating that HSI48 clock is stable. 3407 * This parameter can be: ENABLE or DISABLE. 3408 * @retval None 3409 */ 3410 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) 3411 3412 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) 3413 3414 /** @brief Macros to enable or disable the Internal multi-speed RC oscillator clock (MSIK). 3415 * @note if the peripheral requests its kernel clock in Stop 0 or Stop 1 mode,MSIK is woken up 3416 * @note After enabling the MSIK, the application software should wait on MSIKRDY 3417 * flag to be set indicating that MSIK clock is stable. 3418 * This parameter can be: ENABLE or DISABLE. 3419 * @retval None 3420 */ 3421 #define __HAL_RCC_MSIK_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKON) 3422 3423 #define __HAL_RCC_MSIK_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKON) 3424 3425 /** @brief Macros to enable or disable the secure Internal High Speed oscillator (SHSI). 3426 * @note The SHSI is stopped by hardware when entering STOP and STANDBY modes. 3427 * @note After enabling the SHSI, the application software should wait on SHSI 3428 * flag to be set indicating that SHSI clock is stable. 3429 * This parameter can be: ENABLE or DISABLE. 3430 * @retval None 3431 */ 3432 #define __HAL_RCC_SHSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_SHSION) 3433 3434 #define __HAL_RCC_SHSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_SHSION) 3435 3436 /** @brief Macros to configure the RTC clock (RTCCLK). 3437 * @note As the RTC clock configuration bits are in the Backup domain and write 3438 * access is denied to this domain after reset, you have to enable write 3439 * access using the Power Backup Access macro before to configure 3440 * the RTC clock source (to be done once after reset). 3441 * @note Once the RTC clock is configured it cannot be changed unless the 3442 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 3443 * a Power On Reset (POR). 3444 * 3445 * @param __RTC_CLKSOURCE__: specifies the RTC clock source. 3446 * This parameter can be one of the following values: 3447 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 3448 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 3449 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 3450 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 3451 * 3452 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 3453 * work in STOP and STANDBY modes, and can be used as wakeup source. 3454 * However, when the HSE clock is used as RTC clock source, the RTC 3455 * cannot be used in STOP and STANDBY modes. 3456 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 3457 * RTC clock source). 3458 * @retval None 3459 */ 3460 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 3461 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 3462 3463 /** @brief Macro to get the RTC clock source. 3464 * @retval The returned value can be one of the following: 3465 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 3466 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 3467 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 3468 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 3469 */ 3470 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 3471 3472 /** @brief Macros to enable or disable the main PLL. 3473 * @note After enabling the main PLL, the application software should wait on 3474 * PLLRDY flag to be set indicating that PLL clock is stable and can 3475 * be used as system clock source. 3476 * @note The main PLL can not be disabled if it is used as system clock source 3477 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 3478 */ 3479 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) 3480 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) 3481 3482 /** 3483 * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK) 3484 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL, 3485 * This is mainly used to save Power. 3486 * @param __PLL1_CLOCKOUT__: specifies the PLL clock to be outputted 3487 * This parameter can be one of the following values: 3488 * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve, 3489 * high-quality audio performance on SAI interface. 3490 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz), 3491 * the random analog generator (<=48 MHz) and the OCTOSPI1/2. 3492 * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz) 3493 * @retval None 3494 * 3495 */ 3496 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 3497 3498 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 3499 3500 /** 3501 * @brief Macro to get the PLL clock output enable status. 3502 * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output. 3503 * This parameter can be one of the following values: 3504 * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve, 3505 * high-quality audio performance on SAI interface. 3506 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz), 3507 * the random analog generator (<=48 MHz) and the OCTOSPI1/2. 3508 * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz) 3509 * @retval SET / RESET 3510 */ 3511 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 3512 3513 /** 3514 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 3515 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 3516 * @retval None 3517 */ 3518 #define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 3519 3520 #define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 3521 3522 /** 3523 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 3524 * @note This function must be used only when the main PLL is disabled. 3525 * 3526 * @param __PLL1SOURCE__: specifies the PLL entry clock source. 3527 * This parameter can be one of the following values: 3528 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry 3529 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 3530 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 3531 * @note This clock source (__PLL1SOURCE__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 . 3532 * 3533 * @param __PLL1MBOOST__: specifies the division factor for the EPOD clock 3534 * This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider. 3535 * 3536 * @param __PLL1M__: specifies the division factor for PLL VCO input clock 3537 * This parameter must be a number between 1 and 63. 3538 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3539 * frequency ranges from 1 to 16 MHz. 3540 * 3541 * @param __PLL1N__: specifies the multiplication factor for PLL VCO output clock 3542 * This parameter must be a number between 4 and 512. 3543 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3544 * output frequency is between 128 and 544 MHz(Voltage range 1 or 2) 3545 * between 128 and 330 MHZ (Voltage range 3) and not allowed for Voltage range 4. 3546 * 3547 * @param __PLL1P__: specifies the division factor for system clock. 3548 * This parameter must be a number between 2 and 128 (where odd numbers not allowed) 3549 * 3550 * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks 3551 * This parameter must be a number between 1 and 128 3552 * 3553 * @param __PLL1R__: specifies the division factor for peripheral kernel clocks 3554 * This parameter must be a number between 1 and 128 3555 * 3556 * @retval None 3557 */ 3558 #define __HAL_RCC_PLL_CONFIG(__PLL1SOURCE__, __PLL1MBOOST__,__PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ 3559 do{ MODIFY_REG(RCC->PLL1CFGR,(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M|\ 3560 RCC_PLL1CFGR_PLL1MBOOST), ((__PLL1SOURCE__) << RCC_PLL1CFGR_PLL1SRC_Pos) |\ 3561 (((__PLL1M__) - 1U) << RCC_PLL1CFGR_PLL1M_Pos) | (__PLL1MBOOST__));\ 3562 MODIFY_REG(RCC->PLL1DIVR ,(RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P | RCC_PLL1DIVR_PLL1Q |\ 3563 RCC_PLL1DIVR_PLL1R), ( (((__PLL1N__) - 1U ) & RCC_PLL1DIVR_PLL1N) |\ 3564 ((((__PLL1P__) -1U ) << RCC_PLL1DIVR_PLL1P_Pos) & \ 3565 RCC_PLL1DIVR_PLL1P) | \ 3566 ((((__PLL1Q__) -1U) << RCC_PLL1DIVR_PLL1Q_Pos) & \ 3567 RCC_PLL1DIVR_PLL1Q) |\ 3568 ((((__PLL1R__)- 1U) << RCC_PLL1DIVR_PLL1R_Pos) & \ 3569 RCC_PLL1DIVR_PLL1R))); \ 3570 } while(0) 3571 3572 /** @brief Macro to configure the PLLs clock source. 3573 * @note This function must be used only when all PLLs are disabled. 3574 * @param __PLL1SOURCE__: specifies the PLLs entry clock source. 3575 * This parameter can be one of the following values: 3576 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry 3577 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 3578 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 3579 */ 3580 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLL1SOURCE__) MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLL1SOURCE__)) 3581 3582 /** 3583 * @brief Macro to configure the main PLL clock Fractional Part Of The Multiplication Factor 3584 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 3585 * @param __PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO 3586 * It should be a value between 0 and 8191 3587 * @note Warning: The software has to set correctly these bits to insure that the VCO 3588 * output frequency is between its valid frequency range, which is: 3589 * 192 to 836 MHz if PLL1VCOSEL = 0 3590 * 150 to 420 MHz if PLL1VCOSEL = 1. 3591 * @retval None 3592 */ 3593 #define __HAL_RCC_PLLFRACN_CONFIG(__PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN,\ 3594 (uint32_t)(__PLL1FRACN__) << \ 3595 RCC_PLL1FRACR_PLL1FRACN_Pos) 3596 3597 /** @brief Macro to select the PLL1 reference frequency range. 3598 * @param __PLL1VCIRange__: specifies the PLL1 input frequency range 3599 * This parameter can be one of the following values: 3600 * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz 3601 * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz 3602 * @retval None 3603 */ 3604 #define __HAL_RCC_PLL_VCIRANGE(__PLL1VCIRange__) \ 3605 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__)) 3606 3607 /** @brief Macro to get the oscillator used as PLL1 clock source. 3608 * @retval The oscillator used as PLL1 clock source. The returned value can be one 3609 * of the following: 3610 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 3611 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 3612 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 3613 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 3614 */ 3615 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC)) 3616 3617 /** 3618 * @brief Macro to configure the system clock source. 3619 * @param __SYSCLKSOURCE__: specifies the system clock source. 3620 * This parameter can be one of the following values: 3621 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. 3622 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 3623 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 3624 * - RCC_SYSCLKSOURCE_PLL1CLK: PLL1 output is used as system clock source. 3625 * @retval None 3626 */ 3627 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 3628 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__)) 3629 3630 /** @brief Macro to get the clock source used as system clock. 3631 * @retval The clock source used as system clock. The returned value can be one 3632 * of the following: 3633 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. 3634 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 3635 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 3636 * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1 used as system clock. 3637 */ 3638 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR1 & RCC_CFGR1_SWS)) 3639 3640 /** 3641 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 3642 * @note As the LSE is in the Backup domain and write access is denied to 3643 * this domain after reset, you have to enable write access using 3644 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3645 * (to be done once after reset). 3646 * @note The LSE drive can be decreased to the lower drive capability (LSEDRV = 0) 3647 * when the LSE is ON. However, once LSEDRV is selected, the drive 3648 * capability can not be increased if LSEON = 1. 3649 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 3650 * This parameter can be one of the following values: 3651 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 3652 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 3653 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 3654 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 3655 * @retval None 3656 */ 3657 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 3658 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 3659 3660 /** 3661 * @brief Macro to configure the wake up from stop clock. 3662 * @note The selected clock is also used as emergency clock for the clock security system on HSE. 3663 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. 3664 * This parameter can be one of the following values: 3665 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source and CSS backup clock 3666 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source and CSS backup clock 3667 * @retval None 3668 */ 3669 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 3670 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, (__STOPWUCLK__)) 3671 3672 /** 3673 * @brief Macro to configure the Kernel wake up from stop clock. 3674 * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop 3675 * This parameter can be one of the following values: 3676 * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI selected as Kernel clock source 3677 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source 3678 * @retval None 3679 */ 3680 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ 3681 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) 3682 3683 /** @brief Macro to configure the MCO clock. 3684 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 3685 * This parameter can be one of the following values: 3686 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 3687 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 3688 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 3689 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 3690 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 3691 * @arg @ref RCC_MCO1SOURCE_PLL1CLK Main PLL clock selected as MCO source 3692 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 3693 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 3694 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 3695 * @param __MCODIV__ specifies the MCO clock prescaler. 3696 * This parameter can be one of the following values: 3697 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 3698 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 3699 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 3700 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 3701 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 3702 */ 3703 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 3704 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 3705 3706 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 3707 * @brief macros to manage the specified RCC Flags and interrupts. 3708 * @{ 3709 */ 3710 3711 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable 3712 * the selected interrupts). 3713 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 3714 * This parameter can be any combination of the following values: 3715 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3716 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3717 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 3718 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3719 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3720 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3721 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 3722 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 3723 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3724 * @retval None 3725 */ 3726 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 3727 3728 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 3729 * the selected interrupts). 3730 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 3731 * This parameter can be any combination of the following values: 3732 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3733 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3734 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 3735 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3736 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3737 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3738 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 3739 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 3740 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3741 * @retval None 3742 */ 3743 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 3744 3745 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 3746 * bits to clear the selected interrupt pending bits. 3747 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 3748 * This parameter can be any combination of the following values: 3749 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3750 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3751 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 3752 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3753 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3754 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3755 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 3756 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 3757 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 3758 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3759 * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt 3760 * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt 3761 * @retval None 3762 */ 3763 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 3764 3765 /** @brief Check whether the RCC interrupt has occurred or not. 3766 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 3767 * This parameter can be one of the following values: 3768 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3769 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3770 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 3771 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3772 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3773 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3774 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 3775 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 3776 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 3777 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3778 * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt 3779 * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt 3780 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 3781 */ 3782 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 3783 3784 /** @brief Set RMVF bit to clear the reset flags. 3785 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 3786 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 3787 * @retval None 3788 */ 3789 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 3790 3791 /** @brief Check whether the selected RCC flag is set or not. 3792 * @param __FLAG__: specifies the flag to check. 3793 * This parameter can be one of the following values: 3794 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 3795 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 3796 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 3797 * @arg @ref RCC_FLAG_PLL1RDY Main PLL1 clock ready 3798 * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready 3799 * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready 3800 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready 3801 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 3802 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 3803 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 3804 * @arg @ref RCC_FLAG_BORRST BOR reset 3805 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 3806 * @arg @ref RCC_FLAG_PINRST Pin reset 3807 * @arg @ref RCC_FLAG_RMVF Remove reset Flag 3808 * @arg @ref RCC_FLAG_SFTRST Software reset 3809 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 3810 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 3811 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 3812 * @retval The new state of __FLAG__ (TRUE or FALSE). 3813 */ 3814 #define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 3815 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 3816 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 3817 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 3818 /** 3819 * @} 3820 */ 3821 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_MSI) || \ 3822 ((SOURCE) == RCC_PLLSOURCE_HSI) || \ 3823 ((SOURCE) == RCC_PLLSOURCE_NONE) || \ 3824 ((SOURCE) == RCC_PLLSOURCE_HSE)) 3825 3826 #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 16U)) 3827 #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 3828 #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3829 #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3830 #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3831 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) ||\ 3832 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 3833 3834 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_MSI) || \ 3835 ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) 3836 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 3837 ((__RANGE__) == RCC_MSIRANGE_1) || \ 3838 ((__RANGE__) == RCC_MSIRANGE_2) || \ 3839 ((__RANGE__) == RCC_MSIRANGE_3) || \ 3840 ((__RANGE__) == RCC_MSIRANGE_4) || \ 3841 ((__RANGE__) == RCC_MSIRANGE_5) || \ 3842 ((__RANGE__) == RCC_MSIRANGE_6) || \ 3843 ((__RANGE__) == RCC_MSIRANGE_7) || \ 3844 ((__RANGE__) == RCC_MSIRANGE_8) || \ 3845 ((__RANGE__) == RCC_MSIRANGE_9) || \ 3846 ((__RANGE__) == RCC_MSIRANGE_10) || \ 3847 ((__RANGE__) == RCC_MSIRANGE_11) || \ 3848 ((__RANGE__) == RCC_MSIRANGE_12) || \ 3849 ((__RANGE__) == RCC_MSIRANGE_13) || \ 3850 ((__RANGE__) == RCC_MSIRANGE_14) || \ 3851 ((__RANGE__) == RCC_MSIRANGE_15)) 3852 3853 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 3854 ((__RANGE__) == RCC_MSIRANGE_5) || \ 3855 ((__RANGE__) == RCC_MSIRANGE_6) || \ 3856 ((__RANGE__) == RCC_MSIRANGE_7) || \ 3857 ((__RANGE__) == RCC_MSIRANGE_8)) 3858 3859 #define IS_RCC_MSIK_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_0) || \ 3860 ((__RANGE__) == RCC_MSIKRANGE_1) || \ 3861 ((__RANGE__) == RCC_MSIKRANGE_2) || \ 3862 ((__RANGE__) == RCC_MSIKRANGE_3) || \ 3863 ((__RANGE__) == RCC_MSIKRANGE_4) || \ 3864 ((__RANGE__) == RCC_MSIKRANGE_5) || \ 3865 ((__RANGE__) == RCC_MSIKRANGE_6) || \ 3866 ((__RANGE__) == RCC_MSIKRANGE_7) || \ 3867 ((__RANGE__) == RCC_MSIKRANGE_8) || \ 3868 ((__RANGE__) == RCC_MSIKRANGE_9) || \ 3869 ((__RANGE__) == RCC_MSIKRANGE_10) || \ 3870 ((__RANGE__) == RCC_MSIKRANGE_11) || \ 3871 ((__RANGE__) == RCC_MSIKRANGE_12) || \ 3872 ((__RANGE__) == RCC_MSIKRANGE_13) || \ 3873 ((__RANGE__) == RCC_MSIKRANGE_14) || \ 3874 ((__RANGE__) == RCC_MSIKRANGE_15)) 3875 /** 3876 * @} 3877 */ 3878 3879 /* Include RCC HAL Extended module */ 3880 #include "stm32u5xx_hal_rcc_ex.h" 3881 3882 /* Exported functions --------------------------------------------------------*/ 3883 /** @addtogroup RCC_Exported_Functions 3884 * @{ 3885 */ 3886 3887 /** @addtogroup RCC_Exported_Functions_Group1 3888 * @{ 3889 */ 3890 3891 /* Initialization and de-initialization functions ******************************/ 3892 HAL_StatusTypeDef HAL_RCC_DeInit(void); 3893 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct); 3894 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency); 3895 3896 /** 3897 * @} 3898 */ 3899 3900 /** @addtogroup RCC_Exported_Functions_Group2 3901 * @{ 3902 */ 3903 3904 /* Peripheral Control functions **********************************************/ 3905 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 3906 void HAL_RCC_EnableCSS(void); 3907 uint32_t HAL_RCC_GetSysClockFreq(void); 3908 uint32_t HAL_RCC_GetHCLKFreq(void); 3909 uint32_t HAL_RCC_GetPCLK1Freq(void); 3910 uint32_t HAL_RCC_GetPCLK2Freq(void); 3911 uint32_t HAL_RCC_GetPCLK3Freq(void); 3912 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct); 3913 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct, uint32_t *pFLatency); 3914 uint32_t HAL_RCC_GetResetSource(void); 3915 /* CSS NMI IRQ handler */ 3916 void HAL_RCC_NMI_IRQHandler(void); 3917 /* User Callbacks in non blocking mode (IT mode) */ 3918 void HAL_RCC_CSSCallback(void); 3919 3920 /** 3921 * @} 3922 */ 3923 3924 /* Attributes management functions ********************************************/ 3925 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); 3926 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 3927 3928 /** 3929 * @} 3930 */ 3931 3932 /** 3933 * @} 3934 */ 3935 /** 3936 * @} 3937 */ 3938 3939 #ifdef __cplusplus 3940 } 3941 #endif 3942 3943 #endif /* STM32U5xx_HAL_RCC_H */ 3944
