1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32H7xx_HAL_RCC_EX_H 22 #define STM32H7xx_HAL_RCC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h7xx_hal_def.h" 30 31 /** @addtogroup STM32H7xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCCEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief PLL2 Clock structure definition 46 */ 47 typedef struct 48 { 49 50 uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. 51 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 52 53 uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. 54 This parameter must be a number between Min_Data = 4 and Max_Data = 512 55 or between Min_Data = 8 and Max_Data = 420(*) 56 (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ 57 58 uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. 59 This parameter must be a number between Min_Data = 2 and Max_Data = 128 60 odd division factors are not allowed */ 61 62 uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. 63 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 64 65 uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. 66 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 67 uint32_t PLL2RGE; /*!<PLL2RGE: PLL2 clock Input range 68 This parameter must be a value of @ref RCC_PLL2_VCI_Range */ 69 uint32_t PLL2VCOSEL; /*!<PLL2VCOSEL: PLL2 clock Output range 70 This parameter must be a value of @ref RCC_PLL2_VCO_Range */ 71 72 uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for 73 PLL2 VCO It should be a value between 0 and 8191 */ 74 }RCC_PLL2InitTypeDef; 75 76 /** 77 * @brief PLL3 Clock structure definition 78 */ 79 typedef struct 80 { 81 82 uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. 83 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 84 85 uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock. 86 This parameter must be a number between Min_Data = 4 and Max_Data = 512 87 or between Min_Data = 8 and Max_Data = 420(*) 88 (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ 89 90 uint32_t PLL3P; /*!< PLL3P: Division factor for system clock. 91 This parameter must be a number between Min_Data = 2 and Max_Data = 128 92 odd division factors are not allowed */ 93 94 uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks. 95 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 96 97 uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks. 98 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 99 uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range 100 This parameter must be a value of @ref RCC_PLL3_VCI_Range */ 101 uint32_t PLL3VCOSEL; /*!<PLL3VCOSEL: PLL3 clock Output range 102 This parameter must be a value of @ref RCC_PLL3_VCO_Range */ 103 104 uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for 105 PLL3 VCO It should be a value between 0 and 8191 */ 106 }RCC_PLL3InitTypeDef; 107 108 /** 109 * @brief RCC PLL1 Clocks structure definition 110 */ 111 typedef struct 112 { 113 uint32_t PLL1_P_Frequency; 114 uint32_t PLL1_Q_Frequency; 115 uint32_t PLL1_R_Frequency; 116 }PLL1_ClocksTypeDef; 117 118 /** 119 * @brief RCC PLL2 Clocks structure definition 120 */ 121 typedef struct 122 { 123 uint32_t PLL2_P_Frequency; 124 uint32_t PLL2_Q_Frequency; 125 uint32_t PLL2_R_Frequency; 126 }PLL2_ClocksTypeDef; 127 128 /** 129 * @brief RCC PLL3 Clocks structure definition 130 */ 131 typedef struct 132 { 133 uint32_t PLL3_P_Frequency; 134 uint32_t PLL3_Q_Frequency; 135 uint32_t PLL3_R_Frequency; 136 }PLL3_ClocksTypeDef; 137 138 139 /** 140 * @brief RCC extended clocks structure definition 141 */ 142 typedef struct 143 { 144 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 145 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 146 147 RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters. 148 This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */ 149 150 RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters. 151 This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */ 152 153 uint32_t FmcClockSelection; /*!< Specifies FMC clock source 154 This parameter can be a value of @ref RCCEx_FMC_Clock_Source */ 155 156 #if defined(QUADSPI) 157 uint32_t QspiClockSelection; /*!< Specifies QSPI clock source 158 This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */ 159 #endif /* QUADSPI */ 160 161 #if defined(OCTOSPI1) || defined(OCTOSPI2) 162 uint32_t OspiClockSelection; /*!< Specifies OSPI clock source 163 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 164 #endif /*(OCTOSPI1) || (OCTOSPI2)*/ 165 166 167 #if defined(DSI) 168 uint32_t DsiClockSelection; /*!< Specifies DSI clock source 169 This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ 170 #endif /* DSI */ 171 172 uint32_t SdmmcClockSelection; /*!< Specifies SDMMC clock source 173 This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */ 174 175 uint32_t CkperClockSelection; /*!< Specifies CKPER clock source 176 This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */ 177 178 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source 179 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 180 181 #if defined(SAI3) 182 uint32_t Sai23ClockSelection; /*!< Specifies SAI2/3 clock source 183 This parameter can be a value of @ref RCCEx_SAI23_Clock_Source */ 184 #endif /* SAI3 */ 185 186 #if defined(RCC_CDCCIP1R_SAI2ASEL) 187 uint32_t Sai2AClockSelection; /*!< Specifies SAI2A clock source 188 This parameter can be a value of @ref RCCEx_SAI2A_Clock_Source */ 189 #endif /* RCC_CDCCIP1R_SAI2ASEL */ 190 191 #if defined(RCC_CDCCIP1R_SAI2BSEL) 192 uint32_t Sai2BClockSelection; /*!< Specifies SAI2B clock source 193 This parameter can be a value of @ref RCCEx_SAI2B_Clock_Source */ 194 #endif /* RCC_CDCCIP1R_SAI2BSEL */ 195 196 uint32_t Spi123ClockSelection; /*!< Specifies SPI1/2/3 clock source 197 This parameter can be a value of @ref RCCEx_SPI123_Clock_Source */ 198 199 uint32_t Spi45ClockSelection; /*!< Specifies SPI4/5 clock source 200 This parameter can be a value of @ref RCCEx_SPI45_Clock_Source */ 201 202 uint32_t SpdifrxClockSelection; /*!< Specifies SPDIFRX Clock clock source 203 This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ 204 205 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock clock source 206 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ 207 208 #if defined(DFSDM2_BASE) 209 uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock clock source 210 This parameter can be a value of @ref RCCEx_DFSDM2_Clock_Source */ 211 #endif /* DFSDM2_BASE */ 212 213 #if defined(FDCAN1) || defined(FDCAN2) 214 uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source 215 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 216 #endif /*FDCAN1 || FDCAN2*/ 217 218 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 Clock clock source 219 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ 220 221 uint32_t Usart234578ClockSelection; /*!< Specifies USART2/3/4/5/7/8 clock source 222 This parameter can be a value of @ref RCCEx_USART234578_Clock_Source */ 223 224 uint32_t Usart16ClockSelection; /*!< Specifies USART1/6 clock source 225 This parameter can be a value of @ref RCCEx_USART16_Clock_Source */ 226 227 uint32_t RngClockSelection; /*!< Specifies RNG clock source 228 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 229 230 #if defined(I2C5) 231 uint32_t I2c1235ClockSelection; /*!< Specifies I2C1/2/3/5 clock source 232 This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source */ 233 #else 234 uint32_t I2c123ClockSelection; /*!< Specifies I2C1/2/3 clock source 235 This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source */ 236 #endif /*I2C5*/ 237 238 uint32_t UsbClockSelection; /*!< Specifies USB clock source 239 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 240 241 uint32_t CecClockSelection; /*!< Specifies CEC clock source 242 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 243 244 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source 245 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 246 247 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source 248 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 249 250 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source 251 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 252 253 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source 254 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 255 256 uint32_t Lptim345ClockSelection; /*!< Specifies LPTIM3/4/5 clock source 257 This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source */ 258 259 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source 260 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 261 #if defined(SAI4) 262 uint32_t Sai4AClockSelection; /*!< Specifies SAI4A clock source 263 This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source */ 264 265 uint32_t Sai4BClockSelection; /*!< Specifies SAI4B clock source 266 This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source */ 267 #endif /* SAI4 */ 268 269 uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source 270 This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */ 271 272 uint32_t RTCClockSelection; /*!< Specifies RTC Clock clock source 273 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 274 275 #if defined(HRTIM1) 276 uint32_t Hrtim1ClockSelection; /*!< Specifies HRTIM1 Clock clock source 277 This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */ 278 #endif /* HRTIM1 */ 279 280 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 281 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ 282 }RCC_PeriphCLKInitTypeDef; 283 284 /*!< Alias for Inter STM32H7 lines compatibility regarding RCC_PeriphCLKInitTypeDef field : I2C5 available on some lines only */ 285 #if defined(I2C5) 286 #define I2c123ClockSelection I2c1235ClockSelection 287 #else 288 #define I2c1235ClockSelection I2c123ClockSelection 289 #endif /*I2C5*/ 290 291 292 /** 293 * @brief RCC_CRS Init structure definition 294 */ 295 typedef struct 296 { 297 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 298 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 299 300 uint32_t Source; /*!< Specifies the SYNC signal source. 301 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 302 303 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 304 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 305 306 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 307 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 308 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 309 310 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 311 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 312 313 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 314 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 315 316 }RCC_CRSInitTypeDef; 317 318 /** 319 * @brief RCC_CRS Synchronization structure definition 320 */ 321 typedef struct 322 { 323 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 324 This parameter must be a number between 0 and 0xFFFF */ 325 326 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 327 This parameter must be a number between 0 and 0x3F */ 328 329 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 330 value latched in the time of the last SYNC event. 331 This parameter must be a number between 0 and 0xFFFF */ 332 333 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 334 frequency error counter latched in the time of the last SYNC event. 335 It shows whether the actual frequency is below or above the target. 336 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 337 338 }RCC_CRSSynchroInfoTypeDef; 339 340 /** 341 * @} 342 */ 343 344 345 /* Exported constants --------------------------------------------------------*/ 346 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 347 * @{ 348 */ 349 350 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 351 * @{ 352 */ 353 354 #if defined(UART9) && defined(USART10) 355 #define RCC_PERIPHCLK_USART16910 (0x00000001U) 356 #define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16910 357 #define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16910 358 #define RCC_PERIPHCLK_UART9 RCC_PERIPHCLK_USART16910 359 #define RCC_PERIPHCLK_USART10 RCC_PERIPHCLK_USART16910 360 /*alias*/ 361 #define RCC_PERIPHCLK_USART16 RCC_PERIPHCLK_USART16910 362 #else 363 #define RCC_PERIPHCLK_USART16 (0x00000001U) 364 #define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16 365 #define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16 366 /* alias */ 367 #define RCC_PERIPHCLK_USART16910 RCC_PERIPHCLK_USART16 368 #endif /* UART9 && USART10*/ 369 #define RCC_PERIPHCLK_USART234578 (0x00000002U) 370 #define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578 371 #define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578 372 #define RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578 373 #define RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578 374 #define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578 375 #define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578 376 #define RCC_PERIPHCLK_LPUART1 (0x00000004U) 377 #if defined(I2C5) 378 #define RCC_PERIPHCLK_I2C1235 (0x00000008U) 379 #define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C1235 380 #define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C1235 381 #define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C1235 382 /* alias */ 383 #define RCC_PERIPHCLK_I2C123 RCC_PERIPHCLK_I2C1235 384 #else 385 #define RCC_PERIPHCLK_I2C123 (0x00000008U) 386 #define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123 387 #define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123 388 #define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123 389 #endif /*I2C5*/ 390 #define RCC_PERIPHCLK_I2C4 (0x00000010U) 391 #if defined(I2C5) 392 #define RCC_PERIPHCLK_I2C5 RCC_PERIPHCLK_I2C1235 393 #endif /*I2C5*/ 394 #define RCC_PERIPHCLK_LPTIM1 (0x00000020U) 395 #define RCC_PERIPHCLK_LPTIM2 (0x00000040U) 396 #define RCC_PERIPHCLK_LPTIM345 (0x00000080U) 397 #define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345 398 #if defined(LPTIM4) 399 #define RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345 400 #endif /*LPTIM4*/ 401 #if defined(LPTIM5) 402 #define RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345 403 #endif /*LPTIM5*/ 404 #define RCC_PERIPHCLK_SAI1 (0x00000100U) 405 #if defined(SAI3) 406 #define RCC_PERIPHCLK_SAI23 (0x00000200U) 407 #define RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23 408 #define RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23 409 #endif /* SAI3 */ 410 #if defined(RCC_CDCCIP1R_SAI2ASEL_0) 411 #define RCC_PERIPHCLK_SAI2A (0x00000200U) 412 #endif /* RCC_CDCCIP1R_SAI2ASEL_0 */ 413 #if defined(RCC_CDCCIP1R_SAI2BSEL_0) 414 #define RCC_PERIPHCLK_SAI2B (0x00000400U) 415 #endif /* RCC_CDCCIP1R_SAI2BSEL_0 */ 416 #if defined(SAI4) 417 #define RCC_PERIPHCLK_SAI4A (0x00000400U) 418 #define RCC_PERIPHCLK_SAI4B (0x00000800U) 419 #endif /* SAI4 */ 420 #define RCC_PERIPHCLK_SPI123 (0x00001000U) 421 #define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123 422 #define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123 423 #define RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123 424 #define RCC_PERIPHCLK_SPI45 (0x00002000U) 425 #define RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45 426 #define RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45 427 #define RCC_PERIPHCLK_SPI6 (0x00004000U) 428 #define RCC_PERIPHCLK_FDCAN (0x00008000U) 429 #define RCC_PERIPHCLK_SDMMC (0x00010000U) 430 #define RCC_PERIPHCLK_RNG (0x00020000U) 431 #define RCC_PERIPHCLK_USB (0x00040000U) 432 #define RCC_PERIPHCLK_ADC (0x00080000U) 433 #define RCC_PERIPHCLK_SWPMI1 (0x00100000U) 434 #define RCC_PERIPHCLK_DFSDM1 (0x00200000U) 435 #if defined(DFSDM2_BASE) 436 #define RCC_PERIPHCLK_DFSDM2 (0x00000800U) 437 #endif /* DFSDM2 */ 438 #define RCC_PERIPHCLK_RTC (0x00400000U) 439 #define RCC_PERIPHCLK_CEC (0x00800000U) 440 #define RCC_PERIPHCLK_FMC (0x01000000U) 441 #if defined(QUADSPI) 442 #define RCC_PERIPHCLK_QSPI (0x02000000U) 443 #endif /* QUADSPI */ 444 #if defined(OCTOSPI1) || defined(OCTOSPI2) 445 #define RCC_PERIPHCLK_OSPI (0x02000000U) 446 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ 447 #define RCC_PERIPHCLK_DSI (0x04000000U) 448 #define RCC_PERIPHCLK_SPDIFRX (0x08000000U) 449 #if defined(HRTIM1) 450 #define RCC_PERIPHCLK_HRTIM1 (0x10000000U) 451 #endif /* HRTIM1 */ 452 #if defined(LTDC) 453 #define RCC_PERIPHCLK_LTDC (0x20000000U) 454 #endif /* LTDC */ 455 #define RCC_PERIPHCLK_TIM (0x40000000U) 456 #define RCC_PERIPHCLK_CKPER (0x80000000U) 457 458 /** 459 * @} 460 */ 461 462 463 /** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output 464 * @{ 465 */ 466 #define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN 467 #define RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN 468 #define RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN 469 470 /** 471 * @} 472 */ 473 474 /** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output 475 * @{ 476 */ 477 #define RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN 478 #define RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN 479 #define RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN 480 481 /** 482 * @} 483 */ 484 485 /** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range 486 * @{ 487 */ 488 #define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ 489 #define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ 490 #define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ 491 #define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ 492 493 /** 494 * @} 495 */ 496 497 498 /** @defgroup RCC_PLL2_VCO_Range RCC PLL2 VCO Range 499 * @{ 500 */ 501 #define RCC_PLL2VCOWIDE (0x00000000U) 502 #define RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL 503 504 /** 505 * @} 506 */ 507 508 /** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range 509 * @{ 510 */ 511 #define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ 512 #define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ 513 #define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ 514 #define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ 515 516 /** 517 * @} 518 */ 519 520 521 /** @defgroup RCC_PLL3_VCO_Range RCC PLL3 VCO Range 522 * @{ 523 */ 524 #define RCC_PLL3VCOWIDE (0x00000000U) 525 #define RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL 526 527 /** 528 * @} 529 */ 530 531 /** @defgroup RCCEx_USART16_Clock_Source RCCEx USART1/6 Clock Source 532 * @{ 533 */ 534 #if defined(RCC_D2CCIP2R_USART16SEL) 535 #define RCC_USART16CLKSOURCE_D2PCLK2 (0x00000000U) 536 /* alias */ 537 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 538 #define RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0 539 #define RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1 540 #define RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1) 541 #define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2 542 #define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2) 543 544 #elif defined(RCC_CDCCIP2R_USART16910SEL) 545 #define RCC_USART16910CLKSOURCE_CDPCLK2 (0x00000000U) 546 /* alias */ 547 #define RCC_USART16910CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_CDPCLK2 548 #define RCC_USART16910CLKSOURCE_PLL2 RCC_CDCCIP2R_USART16910SEL_0 549 #define RCC_USART16910CLKSOURCE_PLL3 RCC_CDCCIP2R_USART16910SEL_1 550 #define RCC_USART16910CLKSOURCE_HSI (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1) 551 #define RCC_USART16910CLKSOURCE_CSI RCC_CDCCIP2R_USART16910SEL_2 552 #define RCC_USART16910CLKSOURCE_LSE (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2) 553 554 /* Aliases */ 555 #define RCC_USART16CLKSOURCE_CDPCLK2 RCC_USART16910CLKSOURCE_CDPCLK2 556 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_CDPCLK2 557 #define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_CDPCLK2 558 #define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2 559 #define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3 560 #define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI 561 #define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI 562 #define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE 563 564 #else /* RCC_D2CCIP2R_USART16910SEL */ 565 #define RCC_USART16910CLKSOURCE_D2PCLK2 (0x00000000U) 566 #define RCC_USART16910CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16910SEL_0 567 #define RCC_USART16910CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16910SEL_1 568 #define RCC_USART16910CLKSOURCE_HSI (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1) 569 #define RCC_USART16910CLKSOURCE_CSI RCC_D2CCIP2R_USART16910SEL_2 570 #define RCC_USART16910CLKSOURCE_LSE (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2) 571 572 /* Aliases */ 573 #define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2 574 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2 575 #define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2 576 #define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3 577 #define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI 578 #define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI 579 #define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE 580 #endif /* RCC_D2CCIP2R_USART16SEL */ 581 /** 582 * @} 583 */ 584 585 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source 586 * @{ 587 */ 588 #define RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 589 #define RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 590 #define RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 591 #define RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 592 #define RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 593 #define RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 594 /** 595 * @} 596 */ 597 598 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source 599 * @{ 600 */ 601 #define RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 602 #define RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 603 #define RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 604 #define RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 605 #define RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 606 #define RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 607 608 /** 609 * @} 610 */ 611 612 #if defined(UART9) 613 /** @defgroup RCCEx_UART9_Clock_Source RCCEx UART9 Clock Source 614 * @{ 615 */ 616 #define RCC_UART9CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 617 #define RCC_UART9CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 618 #define RCC_UART9CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 619 #define RCC_UART9CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 620 #define RCC_UART9CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 621 #define RCC_UART9CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 622 /** 623 * @} 624 */ 625 #endif /* UART9 */ 626 627 #if defined(USART10) 628 /** @defgroup RCCEx_USART10_Clock_Source RCCEx USART10 Clock Source 629 * @{ 630 */ 631 #define RCC_USART10CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 632 #define RCC_USART10CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 633 #define RCC_USART10CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 634 #define RCC_USART10CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 635 #define RCC_USART10CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 636 #define RCC_USART10CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 637 /** 638 * @} 639 */ 640 #endif /* USART10 */ 641 642 /** @defgroup RCCEx_USART234578_Clock_Source RCCEx USART2/3/4/5/7/8 Clock Source 643 * @{ 644 */ 645 #if defined(RCC_D2CCIP2R_USART28SEL) 646 #define RCC_USART234578CLKSOURCE_D2PCLK1 (0x00000000U) 647 /* alias */ 648 #define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 649 #define RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0 650 #define RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1 651 #define RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1) 652 #define RCC_USART234578CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2 653 #define RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2) 654 #else 655 #define RCC_USART234578CLKSOURCE_CDPCLK1 (0x00000000U) 656 /* alias */ 657 #define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1 658 #define RCC_USART234578CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1 659 #define RCC_USART234578CLKSOURCE_PLL2 RCC_CDCCIP2R_USART234578SEL_0 660 #define RCC_USART234578CLKSOURCE_PLL3 RCC_CDCCIP2R_USART234578SEL_1 661 #define RCC_USART234578CLKSOURCE_HSI (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1) 662 #define RCC_USART234578CLKSOURCE_CSI RCC_CDCCIP2R_USART234578SEL_2 663 #define RCC_USART234578CLKSOURCE_LSE (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2) 664 #endif /* RCC_D2CCIP2R_USART28SEL */ 665 /** 666 * @} 667 */ 668 669 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source 670 * @{ 671 */ 672 #define RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 673 #define RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 674 #define RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 675 #define RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 676 #define RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 677 #define RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 678 679 /** 680 * @} 681 */ 682 683 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source 684 * @{ 685 */ 686 #define RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 687 #define RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 688 #define RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 689 #define RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 690 #define RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 691 #define RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 692 693 /** 694 * @} 695 */ 696 697 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source 698 * @{ 699 */ 700 #define RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 701 #define RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 702 #define RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 703 #define RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 704 #define RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 705 #define RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 706 707 /** 708 * @} 709 */ 710 711 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source 712 * @{ 713 */ 714 #define RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 715 #define RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 716 #define RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 717 #define RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 718 #define RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 719 #define RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 720 721 /** 722 * @} 723 */ 724 725 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source 726 * @{ 727 */ 728 #define RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 729 #define RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 730 #define RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 731 #define RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 732 #define RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 733 #define RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 734 735 /** 736 * @} 737 */ 738 739 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source 740 * @{ 741 */ 742 #define RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 743 #define RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 744 #define RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 745 #define RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 746 #define RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 747 #define RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 748 749 /** 750 * @} 751 */ 752 753 /** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source 754 * @{ 755 */ 756 #if defined(RCC_D3CCIPR_LPUART1SEL) 757 #define RCC_LPUART1CLKSOURCE_D3PCLK1 (0x00000000U) 758 /* alias */ 759 #define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_D3PCLK1 760 #define RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0 761 #define RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1 762 #define RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1) 763 #define RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2 764 #define RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0) 765 #else 766 #define RCC_LPUART1CLKSOURCE_SRDPCLK4 (0x00000000U) 767 /* alias*/ 768 #define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_SRDPCLK4 769 #define RCC_LPUART1CLKSOURCE_D3PCLK1 RCC_LPUART1CLKSOURCE_SRDPCLK4 770 #define RCC_LPUART1CLKSOURCE_PLL2 RCC_SRDCCIPR_LPUART1SEL_0 771 #define RCC_LPUART1CLKSOURCE_PLL3 RCC_SRDCCIPR_LPUART1SEL_1 772 #define RCC_LPUART1CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1) 773 #define RCC_LPUART1CLKSOURCE_CSI RCC_SRDCCIPR_LPUART1SEL_2 774 #define RCC_LPUART1CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0) 775 #endif /* RCC_D3CCIPR_LPUART1SEL */ 776 /** 777 * @} 778 */ 779 780 /** @defgroup RCCEx_I2C1235_Clock_Source RCCEx I2C1/2/3/5 Clock Source 781 * @{ 782 */ 783 #if defined (RCC_D2CCIP2R_I2C123SEL) 784 #define RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U) 785 #define RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0 786 #define RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1 787 #define RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1) 788 /* aliases */ 789 #define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 790 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 791 #define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 792 #define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 793 #elif defined(RCC_CDCCIP2R_I2C123SEL) 794 #define RCC_I2C123CLKSOURCE_CDPCLK1 (0x00000000U) 795 /* alias */ 796 #define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_CDPCLK1 797 #define RCC_I2C123CLKSOURCE_PLL3 RCC_CDCCIP2R_I2C123SEL_0 798 #define RCC_I2C123CLKSOURCE_HSI RCC_CDCCIP2R_I2C123SEL_1 799 #define RCC_I2C123CLKSOURCE_CSI (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1) 800 /* aliases */ 801 #define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 802 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 803 #define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 804 #define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 805 #elif defined(I2C5) 806 #define RCC_I2C1235CLKSOURCE_D2PCLK1 (0x00000000U) 807 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C1235SEL_0 808 #define RCC_I2C1235CLKSOURCE_HSI RCC_D2CCIP2R_I2C1235SEL_1 809 #define RCC_I2C1235CLKSOURCE_CSI (RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1) 810 /* aliases */ 811 #define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 812 #define RCC_I2C123CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 813 #define RCC_I2C123CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 814 #define RCC_I2C123CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 815 #endif /* RCC_D2CCIP2R_I2C123SEL */ 816 /** 817 * @} 818 */ 819 820 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source 821 * @{ 822 */ 823 #if defined(I2C5) 824 #define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 825 #define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 826 #define RCC_I2C1CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 827 #define RCC_I2C1CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 828 #else 829 #define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 830 #define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 831 #define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 832 #define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 833 #endif /*I2C5*/ 834 835 /** 836 * @} 837 */ 838 839 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source 840 * @{ 841 */ 842 #if defined(I2C5) 843 #define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 844 #define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 845 #define RCC_I2C2CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 846 #define RCC_I2C2CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 847 #else 848 #define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 849 #define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 850 #define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 851 #define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 852 #endif /*I2C5*/ 853 854 /** 855 * @} 856 */ 857 858 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source 859 * @{ 860 */ 861 #if defined(I2C5) 862 #define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 863 #define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 864 #define RCC_I2C3CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 865 #define RCC_I2C3CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 866 #else 867 #define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 868 #define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 869 #define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 870 #define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 871 #endif /*I2C5*/ 872 873 /** 874 * @} 875 */ 876 877 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source 878 * @{ 879 */ 880 #if defined(RCC_D3CCIPR_I2C4SEL) 881 #define RCC_I2C4CLKSOURCE_D3PCLK1 (0x00000000U) 882 #define RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0 883 #define RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1 884 #define RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1) 885 #else 886 #define RCC_I2C4CLKSOURCE_SRDPCLK4 (0x00000000U) 887 /* alias */ 888 #define RCC_I2C4CLKSOURCE_D3PCLK1 RCC_I2C4CLKSOURCE_SRDPCLK4 889 #define RCC_I2C4CLKSOURCE_PLL3 RCC_SRDCCIPR_I2C4SEL_0 890 #define RCC_I2C4CLKSOURCE_HSI RCC_SRDCCIPR_I2C4SEL_1 891 #define RCC_I2C4CLKSOURCE_CSI (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1) 892 #endif /* RCC_D3CCIPR_I2C4SEL */ 893 894 /** 895 * @} 896 */ 897 #if defined(I2C5) 898 /** @defgroup RCCEx_I2C5_Clock_Source RCCEx I2C5 Clock Source 899 * @{ 900 */ 901 #define RCC_I2C5CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 902 #define RCC_I2C5CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 903 #define RCC_I2C5CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI 904 #define RCC_I2C5CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI 905 906 /** 907 * @} 908 */ 909 #endif /*I2C5*/ 910 911 /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source 912 * @{ 913 */ 914 #if defined(RCC_D2CCIP2R_RNGSEL) 915 #define RCC_RNGCLKSOURCE_HSI48 (0x00000000U) 916 #define RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0 917 #define RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1 918 #define RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL 919 #else 920 #define RCC_RNGCLKSOURCE_HSI48 (0x00000000U) 921 #define RCC_RNGCLKSOURCE_PLL RCC_CDCCIP2R_RNGSEL_0 922 #define RCC_RNGCLKSOURCE_LSE RCC_CDCCIP2R_RNGSEL_1 923 #define RCC_RNGCLKSOURCE_LSI RCC_CDCCIP2R_RNGSEL 924 #endif /* RCC_D2CCIP2R_RNGSEL */ 925 926 /** 927 * @} 928 */ 929 #if defined(HRTIM1) 930 931 /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source 932 * @{ 933 */ 934 #define RCC_HRTIM1CLK_TIMCLK (0x00000000U) 935 #define RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL 936 937 /** 938 * @} 939 */ 940 #endif /*HRTIM1*/ 941 942 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source 943 * @{ 944 */ 945 #if defined(RCC_D2CCIP2R_USBSEL) 946 #define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0 947 #define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1 948 #define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL 949 #else 950 #define RCC_USBCLKSOURCE_PLL RCC_CDCCIP2R_USBSEL_0 951 #define RCC_USBCLKSOURCE_PLL3 RCC_CDCCIP2R_USBSEL_1 952 #define RCC_USBCLKSOURCE_HSI48 RCC_CDCCIP2R_USBSEL 953 #endif /* RCC_D2CCIP2R_USBSEL */ 954 955 /** 956 * @} 957 */ 958 959 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 960 * @{ 961 */ 962 #if defined(RCC_D2CCIP1R_SAI1SEL) 963 #define RCC_SAI1CLKSOURCE_PLL (0x00000000U) 964 #define RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0 965 #define RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1 966 #define RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1) 967 #define RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2 968 #else 969 #define RCC_SAI1CLKSOURCE_PLL (0x00000000U) 970 #define RCC_SAI1CLKSOURCE_PLL2 RCC_CDCCIP1R_SAI1SEL_0 971 #define RCC_SAI1CLKSOURCE_PLL3 RCC_CDCCIP1R_SAI1SEL_1 972 #define RCC_SAI1CLKSOURCE_PIN (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1) 973 #define RCC_SAI1CLKSOURCE_CLKP RCC_CDCCIP1R_SAI1SEL_2 974 #endif /* RCC_D2CCIP1R_SAI1SEL */ 975 /** 976 * @} 977 */ 978 979 #if defined(SAI3) 980 /** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source 981 * @{ 982 */ 983 #define RCC_SAI23CLKSOURCE_PLL (0x00000000U) 984 #define RCC_SAI23CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0 985 #define RCC_SAI23CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1 986 #define RCC_SAI23CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1) 987 #define RCC_SAI23CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2 988 /** 989 * @} 990 */ 991 992 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 993 * @{ 994 */ 995 #define RCC_SAI2CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL 996 #define RCC_SAI2CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2 997 #define RCC_SAI2CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3 998 #define RCC_SAI2CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN 999 #define RCC_SAI2CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP 1000 1001 /** 1002 * @} 1003 */ 1004 1005 /** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source 1006 * @{ 1007 */ 1008 #define RCC_SAI3CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL 1009 #define RCC_SAI3CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2 1010 #define RCC_SAI3CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3 1011 #define RCC_SAI3CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN 1012 #define RCC_SAI3CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP 1013 /** 1014 * @} 1015 */ 1016 #endif /* SAI3 */ 1017 1018 #if defined(RCC_CDCCIP1R_SAI2ASEL) 1019 /** @defgroup RCCEx_SAI2A_Clock_Source SAI2A Clock Source 1020 * @{ 1021 */ 1022 #define RCC_SAI2ACLKSOURCE_PLL (0x00000000U) 1023 #define RCC_SAI2ACLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2ASEL_0 1024 #define RCC_SAI2ACLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2ASEL_1 1025 #define RCC_SAI2ACLKSOURCE_PIN (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1) 1026 #define RCC_SAI2ACLKSOURCE_CLKP RCC_CDCCIP1R_SAI2ASEL_2 1027 #define RCC_SAI2ACLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2) 1028 /** 1029 * @} 1030 */ 1031 #endif /* RCC_CDCCIP1R_SAI2ASEL */ 1032 1033 #if defined(RCC_CDCCIP1R_SAI2BSEL) 1034 /** @defgroup RCCEx_SAI2B_Clock_Source SAI2B Clock Source 1035 * @{ 1036 */ 1037 #define RCC_SAI2BCLKSOURCE_PLL (0x00000000U) 1038 #define RCC_SAI2BCLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2BSEL_0 1039 #define RCC_SAI2BCLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2BSEL_1 1040 #define RCC_SAI2BCLKSOURCE_PIN (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1) 1041 #define RCC_SAI2BCLKSOURCE_CLKP RCC_CDCCIP1R_SAI2BSEL_2 1042 #define RCC_SAI2BCLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2) 1043 /** 1044 * @} 1045 */ 1046 #endif /* RCC_CDCCIP1R_SAI2BSEL */ 1047 1048 1049 /** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source 1050 * @{ 1051 */ 1052 #if defined(RCC_D2CCIP1R_SPI123SEL) 1053 #define RCC_SPI123CLKSOURCE_PLL (0x00000000U) 1054 #define RCC_SPI123CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0 1055 #define RCC_SPI123CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1 1056 #define RCC_SPI123CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1) 1057 #define RCC_SPI123CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2 1058 #else 1059 #define RCC_SPI123CLKSOURCE_PLL (0x00000000U) 1060 #define RCC_SPI123CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI123SEL_0 1061 #define RCC_SPI123CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI123SEL_1 1062 #define RCC_SPI123CLKSOURCE_PIN (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1) 1063 #define RCC_SPI123CLKSOURCE_CLKP RCC_CDCCIP1R_SPI123SEL_2 1064 #endif /* RCC_D2CCIP1R_SPI123SEL */ 1065 /** 1066 * @} 1067 */ 1068 1069 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source 1070 * @{ 1071 */ 1072 #define RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL 1073 #define RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 1074 #define RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 1075 #define RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN 1076 #define RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP 1077 1078 /** 1079 * @} 1080 */ 1081 1082 /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source 1083 * @{ 1084 */ 1085 #define RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL 1086 #define RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 1087 #define RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 1088 #define RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN 1089 #define RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP 1090 1091 /** 1092 * @} 1093 */ 1094 1095 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source 1096 * @{ 1097 */ 1098 #define RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL 1099 #define RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 1100 #define RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 1101 #define RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN 1102 #define RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP 1103 1104 /** 1105 * @} 1106 */ 1107 1108 /** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source 1109 * @{ 1110 */ 1111 #if defined(RCC_D2CCIP1R_SPI45SEL) 1112 #define RCC_SPI45CLKSOURCE_D2PCLK1 (0x00000000U) 1113 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1 1114 #define RCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0 1115 #define RCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1 1116 #define RCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1) 1117 #define RCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2 1118 #define RCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2) 1119 #else 1120 #define RCC_SPI45CLKSOURCE_CDPCLK1 (0x00000000U) 1121 /* aliases */ 1122 #define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */ 1123 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 1124 #define RCC_SPI45CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI45SEL_0 1125 #define RCC_SPI45CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI45SEL_1 1126 #define RCC_SPI45CLKSOURCE_HSI (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1) 1127 #define RCC_SPI45CLKSOURCE_CSI RCC_CDCCIP1R_SPI45SEL_2 1128 #define RCC_SPI45CLKSOURCE_HSE (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2) 1129 #endif /* RCC_D2CCIP1R_SPI45SEL */ 1130 /** 1131 * @} 1132 */ 1133 1134 /** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source 1135 * @{ 1136 */ 1137 #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1 1138 #define RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2 1139 #define RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3 1140 #define RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI 1141 #define RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI 1142 #define RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE 1143 1144 /** 1145 * @} 1146 */ 1147 1148 /** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source 1149 * @{ 1150 */ 1151 #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1 1152 #define RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2 1153 #define RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3 1154 #define RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI 1155 #define RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI 1156 #define RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE 1157 1158 /** 1159 * @} 1160 */ 1161 1162 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source 1163 * @{ 1164 */ 1165 #if defined(RCC_D3CCIPR_SPI6SEL) 1166 #define RCC_SPI6CLKSOURCE_D3PCLK1 (0x00000000U) 1167 #define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_D3PCLK1 1168 #define RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0 1169 #define RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1 1170 #define RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1) 1171 #define RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2 1172 #define RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2) 1173 #else 1174 #define RCC_SPI6CLKSOURCE_SRDPCLK4 (0x00000000U) 1175 /* alias */ 1176 #define RCC_SPI6CLKSOURCE_D3PCLK1 RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */ 1177 #define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_SRDPCLK4 1178 #define RCC_SPI6CLKSOURCE_PLL2 RCC_SRDCCIPR_SPI6SEL_0 1179 #define RCC_SPI6CLKSOURCE_PLL3 RCC_SRDCCIPR_SPI6SEL_1 1180 #define RCC_SPI6CLKSOURCE_HSI (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1) 1181 #define RCC_SPI6CLKSOURCE_CSI RCC_SRDCCIPR_SPI6SEL_2 1182 #define RCC_SPI6CLKSOURCE_HSE (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2) 1183 #define RCC_SPI6CLKSOURCE_PIN (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2) 1184 #endif /* RCC_D3CCIPR_SPI6SEL */ 1185 1186 /** 1187 * @} 1188 */ 1189 1190 1191 #if defined(SAI4_Block_A) 1192 /** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source 1193 * @{ 1194 */ 1195 #define RCC_SAI4ACLKSOURCE_PLL (0x00000000U) 1196 #define RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0 1197 #define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1 1198 #define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1) 1199 #define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2 1200 #if defined(RCC_VER_3_0) 1201 #define RCC_SAI4ACLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0) 1202 #endif /*RCC_VER_3_0*/ 1203 1204 /** 1205 * @} 1206 */ 1207 #endif /* SAI4_Block_A */ 1208 1209 1210 1211 #if defined(SAI4_Block_B) 1212 /** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source 1213 * @{ 1214 */ 1215 #define RCC_SAI4BCLKSOURCE_PLL (0x00000000U) 1216 #define RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0 1217 #define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1 1218 #define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1) 1219 #define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2 1220 #if defined(RCC_VER_3_0) 1221 #define RCC_SAI4BCLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0) 1222 #endif /* RCC_VER_3_0 */ 1223 1224 /** 1225 * @} 1226 */ 1227 #endif /* SAI4_Block_B */ 1228 1229 1230 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source 1231 * @{ 1232 */ 1233 #if defined(RCC_D2CCIP2R_LPTIM1SEL) 1234 #define RCC_LPTIM1CLKSOURCE_D2PCLK1 (0x00000000U) 1235 /* alias */ 1236 #define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_D2PCLK1 1237 #define RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0 1238 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1 1239 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1) 1240 #define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2 1241 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2) 1242 #else 1243 #define RCC_LPTIM1CLKSOURCE_CDPCLK1 (0x00000000U) 1244 /* alias */ 1245 #define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1 1246 #define RCC_LPTIM1CLKSOURCE_D2PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1 1247 #define RCC_LPTIM1CLKSOURCE_PLL2 RCC_CDCCIP2R_LPTIM1SEL_0 1248 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_CDCCIP2R_LPTIM1SEL_1 1249 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1) 1250 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CDCCIP2R_LPTIM1SEL_2 1251 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2) 1252 #endif /* RCC_D2CCIP2R_LPTIM1SEL */ 1253 1254 /** 1255 * @} 1256 */ 1257 1258 /** @defgroup RCCEx_LPTIM2_Clock_Source RCCEx LPTIM2 Clock Source 1259 * @{ 1260 */ 1261 #if defined(RCC_D3CCIPR_LPTIM2SEL) 1262 #define RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U) 1263 /* alias */ 1264 #define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_D3PCLK1 1265 #define RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0 1266 #define RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1 1267 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1) 1268 #define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2 1269 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2) 1270 #else 1271 #define RCC_LPTIM2CLKSOURCE_SRDPCLK4 (0x00000000U) 1272 /*alias*/ 1273 #define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_SRDPCLK4 1274 #define RCC_LPTIM2CLKSOURCE_D3PCLK1 RCC_LPTIM2CLKSOURCE_SRDPCLK4 1275 #define RCC_LPTIM2CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM2SEL_0 1276 #define RCC_LPTIM2CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM2SEL_1 1277 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1) 1278 #define RCC_LPTIM2CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM2SEL_2 1279 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2) 1280 #endif /* RCC_D3CCIPR_LPTIM2SEL */ 1281 /** 1282 * @} 1283 */ 1284 1285 /** @defgroup RCCEx_LPTIM345_Clock_Source RCCEx LPTIM3/4/5 Clock Source 1286 * @{ 1287 */ 1288 #if defined(RCC_D3CCIPR_LPTIM345SEL) 1289 #define RCC_LPTIM345CLKSOURCE_D3PCLK1 (0x00000000U) 1290 /* alias*/ 1291 #define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_D3PCLK1 1292 #define RCC_LPTIM345CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0 1293 #define RCC_LPTIM345CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1 1294 #define RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1) 1295 #define RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2 1296 #define RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2) 1297 #else 1298 #define RCC_LPTIM345CLKSOURCE_SRDPCLK4 (0x00000000U) 1299 /* alias */ 1300 #define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_SRDPCLK4 1301 #define RCC_LPTIM345CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_SRDPCLK4 1302 #define RCC_LPTIM345CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM3SEL_0 1303 #define RCC_LPTIM345CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM3SEL_1 1304 #define RCC_LPTIM345CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1) 1305 #define RCC_LPTIM345CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM3SEL_2 1306 #define RCC_LPTIM345CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2) 1307 #endif /* RCC_D3CCIPR_LPTIM345SEL */ 1308 /** 1309 * @} 1310 */ 1311 1312 /** @defgroup RCCEx_LPTIM3_Clock_Source RCCEx LPTIM3 Clock Source 1313 * @{ 1314 */ 1315 #define RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 1316 #define RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 1317 #define RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 1318 #define RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE 1319 #define RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI 1320 #define RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP 1321 1322 /** 1323 * @} 1324 */ 1325 #if defined(LPTIM4) 1326 /** @defgroup RCCEx_LPTIM4_Clock_Source RCCEx LPTIM4 Clock Source 1327 * @{ 1328 */ 1329 #define RCC_LPTIM4CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 1330 #define RCC_LPTIM4CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 1331 #define RCC_LPTIM4CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 1332 #define RCC_LPTIM4CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE 1333 #define RCC_LPTIM4CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI 1334 #define RCC_LPTIM4CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP 1335 /** 1336 * @} 1337 */ 1338 #endif /* LPTIM4 */ 1339 1340 #if defined(LPTIM5) 1341 /** @defgroup RCCEx_LPTIM5_Clock_Source RCCEx LPTIM5 Clock Source 1342 * @{ 1343 */ 1344 #define RCC_LPTIM5CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 1345 #define RCC_LPTIM5CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 1346 #define RCC_LPTIM5CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 1347 #define RCC_LPTIM5CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE 1348 #define RCC_LPTIM5CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI 1349 #define RCC_LPTIM5CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP 1350 1351 /** 1352 * @} 1353 */ 1354 #endif /* LPTIM5 */ 1355 1356 #if defined(QUADSPI) 1357 /** @defgroup RCCEx_QSPI_Clock_Source RCCEx QSPI Clock Source 1358 * @{ 1359 */ 1360 #define RCC_QSPICLKSOURCE_D1HCLK (0x00000000U) 1361 #define RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0 1362 #define RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1 1363 #define RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL 1364 1365 /** 1366 * @} 1367 */ 1368 #endif /* QUADSPI */ 1369 1370 1371 #if defined(OCTOSPI1) || defined(OCTOSPI2) 1372 /** @defgroup RCCEx_OSPI_Clock_Source RCCEx OSPI Clock Source 1373 * @{ 1374 */ 1375 1376 #if defined(RCC_CDCCIPR_OCTOSPISEL) 1377 #define RCC_OSPICLKSOURCE_CDHCLK (0x00000000U) 1378 /*aliases*/ 1379 #define RCC_OSPICLKSOURCE_D1HCLK RCC_OSPICLKSOURCE_CDHCLK 1380 #define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_CDHCLK 1381 #define RCC_OSPICLKSOURCE_PLL RCC_CDCCIPR_OCTOSPISEL_0 1382 #define RCC_OSPICLKSOURCE_PLL2 RCC_CDCCIPR_OCTOSPISEL_1 1383 #define RCC_OSPICLKSOURCE_CLKP RCC_CDCCIPR_OCTOSPISEL 1384 #else 1385 #define RCC_OSPICLKSOURCE_D1HCLK (0x00000000U) 1386 #define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_D1HCLK 1387 #define RCC_OSPICLKSOURCE_PLL RCC_D1CCIPR_OCTOSPISEL_0 1388 #define RCC_OSPICLKSOURCE_PLL2 RCC_D1CCIPR_OCTOSPISEL_1 1389 #define RCC_OSPICLKSOURCE_CLKP RCC_D1CCIPR_OCTOSPISEL 1390 #endif /* RCC_CDCCIPR_OCTOSPISEL */ 1391 1392 1393 /** 1394 * @} 1395 */ 1396 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ 1397 1398 #if defined(DSI) 1399 /** @defgroup RCCEx_DSI_Clock_Source RCCEx DSI Clock Source 1400 * @{ 1401 */ 1402 #define RCC_DSICLKSOURCE_PHY (0x00000000U) 1403 #define RCC_DSICLKSOURCE_PLL2 RCC_D1CCIPR_DSISEL 1404 1405 /** 1406 * @} 1407 */ 1408 #endif /* DSI */ 1409 1410 /** @defgroup RCCEx_FMC_Clock_Source RCCEx FMC Clock Source 1411 * @{ 1412 */ 1413 #if defined(RCC_D1CCIPR_FMCSEL) 1414 #define RCC_FMCCLKSOURCE_D1HCLK (0x00000000U) 1415 #define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_D1HCLK 1416 #define RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0 1417 #define RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1 1418 #define RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL 1419 #else 1420 #define RCC_FMCCLKSOURCE_CDHCLK (0x00000000U) 1421 #define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_CDHCLK 1422 /*alias*/ 1423 #define RCC_FMCCLKSOURCE_D1HCLK RCC_FMCCLKSOURCE_CDHCLK 1424 #define RCC_FMCCLKSOURCE_PLL RCC_CDCCIPR_FMCSEL_0 1425 #define RCC_FMCCLKSOURCE_PLL2 RCC_CDCCIPR_FMCSEL_1 1426 #define RCC_FMCCLKSOURCE_CLKP RCC_CDCCIPR_FMCSEL 1427 #endif /* RCC_D1CCIPR_FMCSEL */ 1428 /** 1429 * @} 1430 */ 1431 1432 #if defined(FDCAN1) || defined(FDCAN2) 1433 /** @defgroup RCCEx_FDCAN_Clock_Source RCCEx FDCAN Clock Source 1434 * @{ 1435 */ 1436 #if defined(RCC_D2CCIP1R_FDCANSEL) 1437 #define RCC_FDCANCLKSOURCE_HSE (0x00000000U) 1438 #define RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0 1439 #define RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1 1440 #else 1441 #define RCC_FDCANCLKSOURCE_HSE (0x00000000U) 1442 #define RCC_FDCANCLKSOURCE_PLL RCC_CDCCIP1R_FDCANSEL_0 1443 #define RCC_FDCANCLKSOURCE_PLL2 RCC_CDCCIP1R_FDCANSEL_1 1444 #endif /* D3_SRAM_BASE */ 1445 /** 1446 * @} 1447 */ 1448 #endif /*FDCAN1 || FDCAN2*/ 1449 1450 1451 /** @defgroup RCCEx_SDMMC_Clock_Source RCCEx SDMMC Clock Source 1452 * @{ 1453 */ 1454 #if defined(RCC_D1CCIPR_SDMMCSEL) 1455 #define RCC_SDMMCCLKSOURCE_PLL (0x00000000U) 1456 #define RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL 1457 #else 1458 #define RCC_SDMMCCLKSOURCE_PLL (0x00000000U) 1459 #define RCC_SDMMCCLKSOURCE_PLL2 RCC_CDCCIPR_SDMMCSEL 1460 #endif /* RCC_D1CCIPR_SDMMCSEL */ 1461 /** 1462 * @} 1463 */ 1464 1465 1466 /** @defgroup RCCEx_ADC_Clock_Source RCCEx ADC Clock Source 1467 * @{ 1468 */ 1469 #if defined(RCC_D3CCIPR_ADCSEL_0) 1470 #define RCC_ADCCLKSOURCE_PLL2 (0x00000000U) 1471 #define RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0 1472 #define RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1 1473 #else 1474 #define RCC_ADCCLKSOURCE_PLL2 (0x00000000U) 1475 #define RCC_ADCCLKSOURCE_PLL3 RCC_SRDCCIPR_ADCSEL_0 1476 #define RCC_ADCCLKSOURCE_CLKP RCC_SRDCCIPR_ADCSEL_1 1477 #endif /* RCC_D3CCIPR_ADCSEL_0 */ 1478 /** 1479 * @} 1480 */ 1481 1482 /** @defgroup RCCEx_SWPMI1_Clock_Source RCCEx SWPMI1 Clock Source 1483 * @{ 1484 */ 1485 #if defined(RCC_D2CCIP1R_SWPSEL) 1486 #define RCC_SWPMI1CLKSOURCE_D2PCLK1 (0x00000000U) 1487 #define RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL 1488 #else 1489 #define RCC_SWPMI1CLKSOURCE_CDPCLK1 (0x00000000U) 1490 /* alias */ 1491 #define RCC_SWPMI1CLKSOURCE_D2PCLK1 RCC_SWPMI1CLKSOURCE_CDPCLK1 1492 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CDCCIP1R_SWPSEL 1493 #endif /* RCC_D2CCIP1R_SWPSEL */ 1494 /** 1495 * @} 1496 */ 1497 1498 /** @defgroup RCCEx_DFSDM1_Clock_Source RCCEx DFSDM1 Clock Source 1499 * @{ 1500 */ 1501 #if defined(RCC_D2CCIP1R_DFSDM1SEL) 1502 #define RCC_DFSDM1CLKSOURCE_D2PCLK1 (0x00000000U) 1503 #define RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL 1504 #else 1505 #define RCC_DFSDM1CLKSOURCE_CDPCLK1 (0x00000000U) 1506 /* alias */ 1507 #define RCC_DFSDM1CLKSOURCE_D2PCLK1 RCC_DFSDM1CLKSOURCE_CDPCLK1 1508 #define RCC_DFSDM1CLKSOURCE_SYS RCC_CDCCIP1R_DFSDM1SEL 1509 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 1510 /** 1511 * @} 1512 */ 1513 1514 #if defined(DFSDM2_BASE) 1515 /** @defgroup RCCEx_DFSDM2_Clock_Source RCCEx DFSDM2 Clock Source 1516 * @{ 1517 */ 1518 #define RCC_DFSDM2CLKSOURCE_SRDPCLK4 (0x00000000U) 1519 /* alias */ 1520 #define RCC_DFSDM2CLKSOURCE_SRDPCLK1 RCC_DFSDM2CLKSOURCE_SRDPCLK4 1521 #define RCC_DFSDM2CLKSOURCE_SYS RCC_SRDCCIPR_DFSDM2SEL 1522 /** 1523 * @} 1524 */ 1525 #endif /* DFSDM2 */ 1526 1527 /** @defgroup RCCEx_SPDIFRX_Clock_Source RCCEx SPDIFRX Clock Source 1528 * @{ 1529 */ 1530 #if defined(RCC_D2CCIP1R_SPDIFSEL_0) 1531 #define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U) 1532 #define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0 1533 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1 1534 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL 1535 #else 1536 #define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U) 1537 #define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_CDCCIP1R_SPDIFSEL_0 1538 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_CDCCIP1R_SPDIFSEL_1 1539 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_CDCCIP1R_SPDIFSEL 1540 #endif /* RCC_D2CCIP1R_SPDIFSEL_0 */ 1541 /** 1542 * @} 1543 */ 1544 1545 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source 1546 * @{ 1547 */ 1548 #if defined(RCC_D2CCIP2R_CECSEL_0) 1549 #define RCC_CECCLKSOURCE_LSE (0x00000000U) 1550 #define RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0 1551 #define RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1 1552 #else 1553 #define RCC_CECCLKSOURCE_LSE (0x00000000U) 1554 #define RCC_CECCLKSOURCE_LSI RCC_CDCCIP2R_CECSEL_0 1555 #define RCC_CECCLKSOURCE_CSI RCC_CDCCIP2R_CECSEL_1 1556 #endif /* RCC_D2CCIP2R_CECSEL_0 */ 1557 /** 1558 * @} 1559 */ 1560 1561 1562 /** @defgroup RCCEx_CLKP_Clock_Source RCCEx CLKP Clock Source 1563 * @{ 1564 */ 1565 #if defined(RCC_D1CCIPR_CKPERSEL_0) 1566 #define RCC_CLKPSOURCE_HSI (0x00000000U) 1567 #define RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0 1568 #define RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1 1569 #else 1570 #define RCC_CLKPSOURCE_HSI (0x00000000U) 1571 #define RCC_CLKPSOURCE_CSI RCC_CDCCIPR_CKPERSEL_0 1572 #define RCC_CLKPSOURCE_HSE RCC_CDCCIPR_CKPERSEL_1 1573 #endif /* RCC_D1CCIPR_CKPERSEL_0 */ 1574 /** 1575 * @} 1576 */ 1577 1578 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection 1579 * @{ 1580 */ 1581 #define RCC_TIMPRES_DESACTIVATED (0x00000000U) 1582 #define RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE 1583 1584 /** 1585 * @} 1586 */ 1587 1588 #if defined(DUAL_CORE) 1589 1590 /** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx 1591 * @{ 1592 */ 1593 #define RCC_BOOT_C1 RCC_GCR_BOOT_C1 1594 #define RCC_BOOT_C2 RCC_GCR_BOOT_C2 1595 1596 /** 1597 * @} 1598 */ 1599 #endif /*DUAL_CORE*/ 1600 1601 #if defined(DUAL_CORE) 1602 /** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx 1603 * @{ 1604 */ 1605 #define RCC_WWDG1 RCC_GCR_WW1RSC 1606 #define RCC_WWDG2 RCC_GCR_WW2RSC 1607 1608 /** 1609 * @} 1610 */ 1611 1612 #else 1613 1614 /** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx 1615 * @{ 1616 */ 1617 #define RCC_WWDG1 RCC_GCR_WW1RSC 1618 1619 /** 1620 * @} 1621 */ 1622 1623 #endif /*DUAL_CORE*/ 1624 1625 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 1626 * @{ 1627 */ 1628 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */ 1629 /** 1630 * @} 1631 */ 1632 1633 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 1634 * @{ 1635 */ 1636 #define RCC_CRS_NONE (0x00000000U) 1637 #define RCC_CRS_TIMEOUT (0x00000001U) 1638 #define RCC_CRS_SYNCOK (0x00000002U) 1639 #define RCC_CRS_SYNCWARN (0x00000004U) 1640 #define RCC_CRS_SYNCERR (0x00000008U) 1641 #define RCC_CRS_SYNCMISS (0x00000010U) 1642 #define RCC_CRS_TRIMOVF (0x00000020U) 1643 /** 1644 * @} 1645 */ 1646 1647 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 1648 * @{ 1649 */ 1650 #define RCC_CRS_SYNC_SOURCE_PIN (0x00000000U) /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only */ 1651 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 1652 #define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB1 SOF (default) */ 1653 #define RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0) /*!< Synchro Signal source USB2 SOF */ 1654 1655 1656 /** 1657 * @} 1658 */ 1659 1660 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 1661 * @{ 1662 */ 1663 #define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ 1664 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 1665 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 1666 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 1667 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 1668 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 1669 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 1670 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 1671 /** 1672 * @} 1673 */ 1674 1675 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 1676 * @{ 1677 */ 1678 #define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ 1679 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 1680 /** 1681 * @} 1682 */ 1683 1684 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 1685 * @{ 1686 */ 1687 #define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 1688 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 1689 /** 1690 * @} 1691 */ 1692 1693 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 1694 * @{ 1695 */ 1696 #define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ 1697 /** 1698 * @} 1699 */ 1700 1701 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 1702 * @{ 1703 */ 1704 #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. 1705 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 1706 corresponds to a higher output frequency */ 1707 /** 1708 * @} 1709 */ 1710 1711 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 1712 * @{ 1713 */ 1714 #define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ 1715 #define RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ 1716 /** 1717 * @} 1718 */ 1719 1720 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 1721 * @{ 1722 */ 1723 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 1724 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 1725 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 1726 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 1727 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 1728 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 1729 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 1730 1731 /** 1732 * @} 1733 */ 1734 1735 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 1736 * @{ 1737 */ 1738 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 1739 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 1740 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 1741 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 1742 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 1743 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 1744 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 1745 1746 /** 1747 * @} 1748 */ 1749 1750 /** 1751 * @} 1752 */ 1753 1754 1755 1756 /* Exported macro ------------------------------------------------------------*/ 1757 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 1758 * @{ 1759 */ 1760 1761 /** @brief Macros to enable or disable PLL2. 1762 * @note After enabling PLL2, the application software should wait on 1763 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 1764 * be used as kernel clock source. 1765 * @note PLL2 is disabled by hardware when entering STOP and STANDBY modes. 1766 */ 1767 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) 1768 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) 1769 1770 /** 1771 * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) 1772 * @note Enabling/disabling those Clocks can be done only when the PLL2 is disabled, 1773 * This is mainly used to save Power. 1774 * @param __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted 1775 * This parameter can be one of the following values: 1776 * @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 1777 * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 1778 * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 1779 * 1780 * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. 1781 * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. 1782 * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. 1783 * 1784 * @retval None 1785 */ 1786 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) 1787 1788 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) 1789 1790 /** 1791 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO 1792 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 1793 * @retval None 1794 */ 1795 #define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) 1796 1797 #define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) 1798 1799 /** 1800 * @brief Macro to configures the PLL2 multiplication and division factors. 1801 * @note This function must be used only when PLL2 is disabled. 1802 * 1803 * @param __PLL2M__ specifies the division factor for PLL2 VCO input clock 1804 * This parameter must be a number between 1 and 63. 1805 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 1806 * frequency ranges from 1 to 16 MHz. 1807 * 1808 * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock 1809 * This parameter must be a number between 4 and 512 or between 8 and 420(*). 1810 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 1811 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 1812 * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) 1813 * 1814 * @param __PLL2P__ specifies the division factor for peripheral kernel clocks 1815 * This parameter must be a number between 1 and 128. 1816 * 1817 * @param __PLL2Q__ specifies the division factor for peripheral kernel clocks 1818 * This parameter must be a number between 1 and 128. 1819 * 1820 * @param __PLL2R__ specifies the division factor for peripheral kernel clocks 1821 * This parameter must be a number between 1 and 128. 1822 * 1823 * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) 1824 * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 1825 * value to __PLL2P__, __PLL2Q__ or __PLL2R__ parameters. 1826 * @retval None 1827 * 1828 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 1829 */ 1830 1831 #define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \ 1832 do{ \ 1833 MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \ 1834 WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \ 1835 ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \ 1836 } while(0) 1837 1838 /** 1839 * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor 1840 * 1841 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO 1842 * 1843 * @param __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO 1844 * It should be a value between 0 and 8191 1845 * @note Warning: the software has to set correctly these bits to insure that the VCO 1846 * output frequency is between its valid frequency range, which is: 1847 * 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 1848 * 150 to 420 MHz if PLL2VCOSEL = 1. 1849 * 1850 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 1851 * 1852 * @retval None 1853 */ 1854 #define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \ 1855 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) 1856 1857 /** @brief Macro to select the PLL2 reference frequency range. 1858 * @param __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range 1859 * This parameter can be one of the following values: 1860 * @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz 1861 * @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz 1862 * @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz 1863 * @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz 1864 * @retval None 1865 */ 1866 #define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \ 1867 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) 1868 1869 1870 /** @brief Macro to select the PLL2 reference frequency range. 1871 * @param __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range 1872 * This parameter can be one of the following values: 1873 * @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) 1874 * @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz 1875 * 1876 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 1877 * 1878 * @retval None 1879 */ 1880 #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \ 1881 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) 1882 1883 /** @brief Macros to enable or disable the main PLL3. 1884 * @note After enabling PLL3, the application software should wait on 1885 * PLL3RDY flag to be set indicating that PLL3 clock is stable and can 1886 * be used as kernel clock source. 1887 * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. 1888 */ 1889 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) 1890 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) 1891 1892 /** 1893 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO 1894 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 1895 * @retval None 1896 */ 1897 #define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) 1898 1899 #define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) 1900 1901 /** 1902 * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) 1903 * @note Enabling/disabling those Clocks can be done only when the PLL3 is disabled, 1904 * This is mainly used to save Power. 1905 * @param __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted 1906 * This parameter can be one of the following values: 1907 * @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 1908 * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 1909 * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 1910 * 1911 * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. 1912 * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. 1913 * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. 1914 * 1915 * @retval None 1916 */ 1917 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) 1918 1919 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) 1920 1921 /** 1922 * @brief Macro to configures the PLL3 multiplication and division factors. 1923 * @note This function must be used only when PLL3 is disabled. 1924 * 1925 * @param __PLL3M__ specifies the division factor for PLL3 VCO input clock 1926 * This parameter must be a number between 1 and 63. 1927 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 1928 * frequency ranges from 1 to 16 MHz. 1929 * 1930 * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock 1931 * This parameter must be a number between 4 and 512. 1932 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 1933 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 1934 * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) 1935 * 1936 * @param __PLL3P__ specifies the division factor for peripheral kernel clocks 1937 * This parameter must be a number between 2 and 128 (where odd numbers not allowed) 1938 * 1939 * @param __PLL3Q__ specifies the division factor for peripheral kernel clocks 1940 * This parameter must be a number between 1 and 128 1941 * 1942 * @param __PLL3R__ specifies the division factor for peripheral kernel clocks 1943 * This parameter must be a number between 1 and 128 1944 * 1945 * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) 1946 * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 1947 * value to __PLL3P__, __PLL3Q__ or __PLL3R__ parameters. 1948 * @retval None 1949 * 1950 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 1951 */ 1952 1953 #define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \ 1954 do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \ 1955 WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \ 1956 ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \ 1957 } while(0) 1958 1959 1960 1961 /** 1962 * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor 1963 * 1964 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO 1965 * 1966 * @param __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO 1967 * It should be a value between 0 and 8191 1968 * @note Warning: the software has to set correctly these bits to insure that the VCO 1969 * output frequency is between its valid frequency range, which is: 1970 * 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 1971 * 150 to 420 MHz if PLL3VCOSEL = 1. 1972 * 1973 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 1974 * 1975 * @retval None 1976 */ 1977 #define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) 1978 1979 /** @brief Macro to select the PLL3 reference frequency range. 1980 * @param __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range 1981 * This parameter can be one of the following values: 1982 * @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz 1983 * @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz 1984 * @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz 1985 * @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz 1986 * @retval None 1987 */ 1988 #define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \ 1989 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) 1990 1991 1992 /** @brief Macro to select the PLL3 reference frequency range. 1993 * @param __RCC_PLL3VCORange__ specifies the PLL1 input frequency range 1994 * This parameter can be one of the following values: 1995 * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) 1996 * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz 1997 * 1998 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 1999 * 2000 * @retval None 2001 */ 2002 #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \ 2003 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) 2004 /** 2005 * @brief Macro to Configure the SAI1 clock source. 2006 * @param __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived 2007 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2008 * This parameter can be one of the following values: 2009 * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL 2010 * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 2011 * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 2012 * @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC 2013 * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock 2014 * @retval None 2015 */ 2016 #if defined(RCC_D2CCIP1R_SAI1SEL) 2017 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ 2018 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) 2019 #else 2020 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ 2021 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) 2022 #endif /* RCC_D2CCIP1R_SAI1SEL */ 2023 2024 /** @brief Macro to get the SAI1 clock source. 2025 * @retval The clock source can be one of the following values: 2026 * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL 2027 * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 2028 * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 2029 * @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP 2030 * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock 2031 */ 2032 #if defined(RCC_D2CCIP1R_SAI1SEL) 2033 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL))) 2034 #else 2035 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL))) 2036 #endif /* RCC_D2CCIP1R_SAI1SEL */ 2037 2038 /** 2039 * @brief Macro to Configure the SPDIFRX clock source. 2040 * @param __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived 2041 * from system PLL, PLL2, PLL3, or internal OSC clock 2042 * This parameter can be one of the following values: 2043 * @arg RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL 2044 * @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2 2045 * @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3 2046 * @arg RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI 2047 * @retval None 2048 */ 2049 #if defined(RCC_D2CCIP1R_SPDIFSEL) 2050 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ 2051 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) 2052 #else 2053 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ 2054 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) 2055 #endif /* RCC_D2CCIP1R_SPDIFSEL */ 2056 2057 /** 2058 * @brief Macro to get the SPDIFRX clock source. 2059 * @retval None 2060 */ 2061 #if defined(RCC_D2CCIP1R_SPDIFSEL) 2062 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL))) 2063 #else 2064 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL))) 2065 #endif /* RCC_D2CCIP1R_SPDIFSEL */ 2066 2067 #if defined(SAI3) 2068 /** 2069 * @brief Macro to Configure the SAI2/3 clock source. 2070 * @param __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived 2071 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2072 * This parameter can be one of the following values: 2073 * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL 2074 * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 2075 * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 2076 * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP 2077 * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock 2078 * @retval None 2079 */ 2080 #define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\ 2081 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__)) 2082 2083 /** @brief Macro to get the SAI2/3 clock source. 2084 * @retval The clock source can be one of the following values: 2085 * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL 2086 * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 2087 * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 2088 * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP 2089 * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock 2090 */ 2091 #define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL))) 2092 2093 /** 2094 * @brief Macro to Configure the SAI2 clock source. 2095 * @param __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived 2096 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2097 * This parameter can be one of the following values: 2098 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL 2099 * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 2100 * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 2101 * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP 2102 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock 2103 * @retval None 2104 */ 2105 #define __HAL_RCC_SAI2_CONFIG __HAL_RCC_SAI23_CONFIG 2106 2107 /** @brief Macro to get the SAI2 clock source. 2108 * @retval The clock source can be one of the following values: 2109 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL 2110 * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 2111 * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 2112 * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP 2113 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock 2114 */ 2115 #define __HAL_RCC_GET_SAI2_SOURCE __HAL_RCC_GET_SAI23_SOURCE 2116 2117 /** 2118 * @brief Macro to Configure the SAI3 clock source. 2119 * @param __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived 2120 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2121 * This parameter can be one of the following values: 2122 * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL 2123 * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 2124 * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 2125 * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP 2126 * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock 2127 * @retval None 2128 */ 2129 #define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG 2130 2131 /** @brief Macro to get the SAI3 clock source. 2132 * @retval The clock source can be one of the following values: 2133 * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL 2134 * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 2135 * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 2136 * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP 2137 * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock 2138 */ 2139 #define __HAL_RCC_GET_SAI3_SOURCE __HAL_RCC_GET_SAI23_SOURCE 2140 #endif /* SAI3 */ 2141 2142 #if defined(RCC_CDCCIP1R_SAI2ASEL) 2143 /** 2144 * @brief Macro to Configure the SAI2A clock source. 2145 * @param __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived 2146 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2147 * This parameter can be one of the following values: 2148 * @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL 2149 * @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2 2150 * @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3 2151 * @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock = CLKP 2152 * @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock 2153 * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock 2154 * @retval None 2155 */ 2156 #define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\ 2157 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__)) 2158 2159 /** @brief Macro to get the SAI2A clock source. 2160 * @retval The clock source can be one of the following values: 2161 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL 2162 * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2 2163 * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3 2164 * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock = CLKP 2165 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock 2166 * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock 2167 */ 2168 #define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL))) 2169 #endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */ 2170 2171 #if defined(RCC_CDCCIP1R_SAI2BSEL) 2172 /** 2173 * @brief Macro to Configure the SAI2B clock source. 2174 * @param __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived 2175 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2176 * This parameter can be one of the following values: 2177 * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL 2178 * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 2179 * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 2180 * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP 2181 * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock 2182 * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock 2183 * @retval None 2184 */ 2185 #define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\ 2186 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__)) 2187 2188 /** @brief Macro to get the SAI2B clock source. 2189 * @retval The clock source can be one of the following values: 2190 * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL 2191 * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 2192 * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 2193 * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP 2194 * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock 2195 * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock 2196 */ 2197 #define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL))) 2198 #endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */ 2199 2200 2201 #if defined(SAI4_Block_A) 2202 /** 2203 * @brief Macro to Configure the SAI4A clock source. 2204 * @param __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived 2205 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2206 * This parameter can be one of the following values: 2207 * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL 2208 * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2 2209 * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3 2210 * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock = CLKP 2211 * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock 2212 * @retval None 2213 */ 2214 #define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\ 2215 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__)) 2216 2217 /** @brief Macro to get the SAI4A clock source. 2218 * @retval The clock source can be one of the following values: 2219 * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL 2220 * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2 2221 * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3 2222 * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock = CLKP 2223 * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock 2224 */ 2225 #define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL))) 2226 #endif /* SAI4_Block_A */ 2227 2228 #if defined(SAI4_Block_B) 2229 /** 2230 * @brief Macro to Configure the SAI4B clock source. 2231 * @param __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived 2232 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2233 * This parameter can be one of the following values: 2234 * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL 2235 * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 2236 * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 2237 * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP 2238 * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock 2239 * @retval None 2240 */ 2241 #define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\ 2242 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__)) 2243 2244 /** @brief Macro to get the SAI4B clock source. 2245 * @retval The clock source can be one of the following values: 2246 * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL 2247 * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 2248 * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 2249 * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP 2250 * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock 2251 */ 2252 #define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL))) 2253 #endif /* SAI4_Block_B */ 2254 2255 /** @brief macro to configure the I2C1/2/3/5* clock (I2C123CLK). 2256 * 2257 * @param __I2C1235CLKSource__ specifies the I2C1/2/3/5* clock source. 2258 * This parameter can be one of the following values: 2259 * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock 2260 * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock 2261 * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock 2262 * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock 2263 * 2264 * (**): Available on stm32h72xxx and stm32h73xxx family lines. 2265 */ 2266 #if defined(RCC_D2CCIP2R_I2C123SEL) 2267 #define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ 2268 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) 2269 #elif defined(RCC_CDCCIP2R_I2C123SEL) 2270 #define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ 2271 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) 2272 #else /* RCC_D2CCIP2R_I2C1235SEL */ 2273 #define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) \ 2274 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__)) 2275 /* alias */ 2276 #define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG 2277 #endif /* RCC_D2CCIP2R_I2C123SEL */ 2278 2279 /** @brief macro to get the I2C1/2/3/5* clock source. 2280 * @retval The clock source can be one of the following values: 2281 * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock 2282 * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock 2283 * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock 2284 * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock 2285 * 2286 * (**): Available on stm32h72xxx and stm32h73xxx family lines. 2287 */ 2288 #if defined(RCC_D2CCIP2R_I2C123SEL) 2289 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) 2290 #elif defined(RCC_CDCCIP2R_I2C123SEL) 2291 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL))) 2292 #else /* RCC_D2CCIP2R_I2C1235SEL */ 2293 #define __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL))) 2294 /* alias */ 2295 #define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 2296 #endif /* RCC_D2CCIP2R_I2C123SEL */ 2297 2298 /** @brief macro to configure the I2C1 clock (I2C1CLK). 2299 * 2300 * @param __I2C1CLKSource__ specifies the I2C1 clock source. 2301 * This parameter can be one of the following values: 2302 * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock 2303 * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock 2304 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock 2305 * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock 2306 */ 2307 #if defined(I2C5) 2308 #define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG 2309 #else 2310 #define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG 2311 #endif /*I2C5*/ 2312 2313 /** @brief macro to get the I2C1 clock source. 2314 * @retval The clock source can be one of the following values: 2315 * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock 2316 * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock 2317 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock 2318 * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock 2319 */ 2320 #if defined(I2C5) 2321 #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 2322 #else 2323 #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE 2324 #endif /*I2C5*/ 2325 2326 /** @brief macro to configure the I2C2 clock (I2C2CLK). 2327 * 2328 * @param __I2C2CLKSource__ specifies the I2C2 clock source. 2329 * This parameter can be one of the following values: 2330 * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock 2331 * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock 2332 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock 2333 * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock 2334 */ 2335 #if defined(I2C5) 2336 #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG 2337 #else 2338 #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG 2339 #endif /*I2C5*/ 2340 2341 /** @brief macro to get the I2C2 clock source. 2342 * @retval The clock source can be one of the following values: 2343 * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock 2344 * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock 2345 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock 2346 * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock 2347 */ 2348 #if defined(I2C5) 2349 #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 2350 #else 2351 #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE 2352 #endif /*I2C5*/ 2353 2354 /** @brief macro to configure the I2C3 clock (I2C3CLK). 2355 * 2356 * @param __I2C3CLKSource__ specifies the I2C3 clock source. 2357 * This parameter can be one of the following values: 2358 * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock 2359 * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock 2360 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock 2361 * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock 2362 */ 2363 #if defined(I2C5) 2364 #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG 2365 #else 2366 #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG 2367 #endif /*I2C5*/ 2368 2369 /** @brief macro to get the I2C3 clock source. 2370 * @retval The clock source can be one of the following values: 2371 * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock 2372 * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock 2373 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock 2374 * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock 2375 */ 2376 #if defined(I2C5) 2377 #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 2378 #else 2379 #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE 2380 #endif /*I2C5*/ 2381 2382 /** @brief macro to configure the I2C4 clock (I2C4CLK). 2383 * 2384 * @param __I2C4CLKSource__ specifies the I2C4 clock source. 2385 * This parameter can be one of the following values: 2386 * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock 2387 * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock 2388 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock 2389 * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock 2390 */ 2391 #if defined(RCC_D3CCIPR_I2C4SEL) 2392 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ 2393 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) 2394 #else 2395 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ 2396 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) 2397 #endif /* RCC_D3CCIPR_I2C4SEL */ 2398 2399 /** @brief macro to get the I2C4 clock source. 2400 * @retval The clock source can be one of the following values: 2401 * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock 2402 * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock 2403 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock 2404 * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock 2405 */ 2406 #if defined(RCC_D3CCIPR_I2C4SEL) 2407 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL))) 2408 #else 2409 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL))) 2410 #endif /* RCC_D3CCIPR_I2C4SEL */ 2411 2412 #if defined(I2C5) 2413 /** @brief macro to configure the I2C5 clock (I2C5CLK). 2414 * 2415 * @param __I2C5CLKSource__ specifies the I2C5 clock source. 2416 * This parameter can be one of the following values: 2417 * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C5 clock 2418 * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock 2419 * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock 2420 * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock 2421 */ 2422 #define __HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG 2423 #endif /* I2C5 */ 2424 2425 #if defined(I2C5) 2426 /** @brief macro to get the I2C5 clock source. 2427 * @retval The clock source can be one of the following values: 2428 * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK5 selected as I2C5 clock 2429 * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock 2430 * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock 2431 * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock 2432 */ 2433 #define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE 2434 #endif /* I2C5 */ 2435 2436 /** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK). 2437 * 2438 * @param __USART16910CLKSource__ specifies the USART1/6/9* /10* clock source. 2439 * This parameter can be one of the following values: 2440 * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock 2441 * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock 2442 * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock 2443 * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock 2444 * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock 2445 * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock 2446 * 2447 * (*) : Available on some STM32H7 lines only. 2448 */ 2449 #if defined(RCC_D2CCIP2R_USART16SEL) 2450 #define __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) \ 2451 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__)) 2452 #elif defined(RCC_CDCCIP2R_USART16910SEL) 2453 #define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ 2454 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) 2455 /* alias */ 2456 #define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG 2457 #else /* RCC_D2CCIP2R_USART16910SEL */ 2458 #define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ 2459 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) 2460 /* alias */ 2461 #define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG 2462 #endif /* RCC_D2CCIP2R_USART16SEL */ 2463 2464 /** @brief macro to get the USART1/6/9* /10* clock source. 2465 * @retval The clock source can be one of the following values: 2466 * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock 2467 * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock 2468 * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock 2469 * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock 2470 * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock 2471 * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock 2472 * 2473 * (*) : Available on some STM32H7 lines only. 2474 */ 2475 #if defined(RCC_D2CCIP2R_USART16SEL) 2476 #define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) 2477 #elif defined(RCC_CDCCIP2R_USART16910SEL) 2478 #define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL))) 2479 /* alias*/ 2480 #define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE 2481 #else /* RCC_D2CCIP2R_USART16910SEL */ 2482 #define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL))) 2483 /* alias */ 2484 #define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE 2485 #endif /* RCC_D2CCIP2R_USART16SEL */ 2486 2487 /** @brief macro to configure the USART234578 clock (USART234578CLK). 2488 * 2489 * @param __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source. 2490 * This parameter can be one of the following values: 2491 * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock 2492 * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock 2493 * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock 2494 * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock 2495 * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock 2496 * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock 2497 */ 2498 #if defined(RCC_D2CCIP2R_USART28SEL) 2499 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ 2500 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__)) 2501 #else 2502 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ 2503 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__)) 2504 #endif /* RCC_D2CCIP2R_USART28SEL */ 2505 2506 /** @brief macro to get the USART2/3/4/5/7/8 clock source. 2507 * @retval The clock source can be one of the following values: 2508 * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock 2509 * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock 2510 * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock 2511 * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock 2512 * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock 2513 * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock 2514 */ 2515 #if defined(RCC_D2CCIP2R_USART28SEL) 2516 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) 2517 #else 2518 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL))) 2519 #endif /* RCC_D2CCIP2R_USART28SEL */ 2520 2521 /** @brief macro to configure the USART1 clock (USART1CLK). 2522 * 2523 * @param __USART1CLKSource__ specifies the USART1 clock source. 2524 * This parameter can be one of the following values: 2525 * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock 2526 * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock 2527 * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock 2528 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock 2529 * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock 2530 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock 2531 */ 2532 #define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG 2533 2534 /** @brief macro to get the USART1 clock source. 2535 * @retval The clock source can be one of the following values: 2536 * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock 2537 * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock 2538 * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock 2539 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock 2540 * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock 2541 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock 2542 */ 2543 #define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE 2544 2545 /** @brief macro to configure the USART2 clock (USART2CLK). 2546 * 2547 * @param __USART2CLKSource__ specifies the USART2 clock source. 2548 * This parameter can be one of the following values: 2549 * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock 2550 * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock 2551 * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock 2552 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock 2553 * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock 2554 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock 2555 */ 2556 #define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG 2557 2558 /** @brief macro to get the USART2 clock source. 2559 * @retval The clock source can be one of the following values: 2560 * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock 2561 * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock 2562 * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock 2563 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock 2564 * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock 2565 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock 2566 */ 2567 #define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE 2568 2569 /** @brief macro to configure the USART3 clock (USART3CLK). 2570 * 2571 * @param __USART3CLKSource__ specifies the USART3 clock source. 2572 * This parameter can be one of the following values: 2573 * @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock 2574 * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock 2575 * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock 2576 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock 2577 * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock 2578 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock 2579 */ 2580 #define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG 2581 2582 /** @brief macro to get the USART3 clock source. 2583 * @retval The clock source can be one of the following values: 2584 * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock 2585 * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock 2586 * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock 2587 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock 2588 * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock 2589 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock 2590 */ 2591 #define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE 2592 2593 /** @brief macro to configure the UART4 clock (UART4CLK). 2594 * 2595 * @param __UART4CLKSource__ specifies the UART4 clock source. 2596 * This parameter can be one of the following values: 2597 * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock 2598 * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock 2599 * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock 2600 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock 2601 * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock 2602 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock 2603 */ 2604 #define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG 2605 2606 /** @brief macro to get the UART4 clock source. 2607 * @retval The clock source can be one of the following values: 2608 * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock 2609 * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock 2610 * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock 2611 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock 2612 * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock 2613 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock 2614 */ 2615 #define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE 2616 2617 /** @brief macro to configure the UART5 clock (UART5CLK). 2618 * 2619 * @param __UART5CLKSource__ specifies the UART5 clock source. 2620 * This parameter can be one of the following values: 2621 * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock 2622 * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock 2623 * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock 2624 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock 2625 * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock 2626 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock 2627 */ 2628 #define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG 2629 2630 /** @brief macro to get the UART5 clock source. 2631 * @retval The clock source can be one of the following values: 2632 * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock 2633 * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock 2634 * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock 2635 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock 2636 * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock 2637 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock 2638 */ 2639 #define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE 2640 2641 /** @brief macro to configure the USART6 clock (USART6CLK). 2642 * 2643 * @param __USART6CLKSource__ specifies the USART6 clock source. 2644 * This parameter can be one of the following values: 2645 * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock 2646 * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock 2647 * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock 2648 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 2649 * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock 2650 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock 2651 */ 2652 #define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG 2653 2654 /** @brief macro to get the USART6 clock source. 2655 * @retval The clock source can be one of the following values: 2656 * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock 2657 * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock 2658 * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock 2659 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 2660 * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock 2661 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock 2662 */ 2663 #define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE 2664 2665 /** @brief macro to configure the UART5 clock (UART7CLK). 2666 * 2667 * @param __UART7CLKSource__ specifies the UART7 clock source. 2668 * This parameter can be one of the following values: 2669 * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock 2670 * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock 2671 * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock 2672 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock 2673 * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock 2674 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock 2675 */ 2676 #define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG 2677 2678 /** @brief macro to get the UART7 clock source. 2679 * @retval The clock source can be one of the following values: 2680 * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock 2681 * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock 2682 * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock 2683 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock 2684 * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock 2685 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock 2686 */ 2687 #define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE 2688 2689 /** @brief macro to configure the UART8 clock (UART8CLK). 2690 * 2691 * @param __UART8CLKSource__ specifies the UART8 clock source. 2692 * This parameter can be one of the following values: 2693 * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock 2694 * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock 2695 * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock 2696 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock 2697 * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock 2698 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock 2699 */ 2700 #define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG 2701 2702 /** @brief macro to get the UART8 clock source. 2703 * @retval The clock source can be one of the following values: 2704 * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock 2705 * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock 2706 * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock 2707 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock 2708 * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock 2709 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock 2710 */ 2711 #define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE 2712 2713 #if defined(UART9) 2714 /** @brief macro to configure the UART9 clock (UART9CLK). 2715 * 2716 * @param __UART8CLKSource__ specifies the UART8 clock source. 2717 * This parameter can be one of the following values: 2718 * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock 2719 * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock 2720 * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock 2721 * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock 2722 * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock 2723 * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock 2724 */ 2725 #define __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG 2726 2727 /** @brief macro to get the UART9 clock source. 2728 * @retval The clock source can be one of the following values: 2729 * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock 2730 * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock 2731 * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock 2732 * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock 2733 * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock 2734 * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock 2735 */ 2736 #define __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE 2737 #endif /* UART9 */ 2738 2739 #if defined(USART10) 2740 /** @brief macro to configure the USART10 clock (USART10CLK). 2741 * 2742 * @param __UART8CLKSource__ specifies the UART8 clock source. 2743 * This parameter can be one of the following values: 2744 * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock 2745 * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock 2746 * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock 2747 * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock 2748 * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock 2749 * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock 2750 */ 2751 #define __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG 2752 2753 /** @brief macro to get the USART10 clock source. 2754 * @retval The clock source can be one of the following values: 2755 * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock 2756 * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock 2757 * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock 2758 * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock 2759 * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock 2760 * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock 2761 */ 2762 #define __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE 2763 #endif /* USART10 */ 2764 2765 /** @brief macro to configure the LPUART1 clock (LPUART1CLK). 2766 * 2767 * @param __LPUART1CLKSource__ specifies the LPUART1 clock source. 2768 * This parameter can be one of the following values: 2769 * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock 2770 * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock 2771 * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock 2772 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock 2773 * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock 2774 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock 2775 */ 2776 #if defined (RCC_D3CCIPR_LPUART1SEL) 2777 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ 2778 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) 2779 #else 2780 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ 2781 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) 2782 #endif /* RCC_D3CCIPR_LPUART1SEL */ 2783 2784 /** @brief macro to get the LPUART1 clock source. 2785 * @retval The clock source can be one of the following values: 2786 * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock 2787 * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock 2788 * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock 2789 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock 2790 * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock 2791 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock 2792 */ 2793 #if defined (RCC_D3CCIPR_LPUART1SEL) 2794 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL))) 2795 #else 2796 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL))) 2797 #endif /* RCC_D3CCIPR_LPUART1SEL */ 2798 2799 /** @brief macro to configure the LPTIM1 clock source. 2800 * 2801 * @param __LPTIM1CLKSource__ specifies the LPTIM1 clock source. 2802 * This parameter can be one of the following values: 2803 * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock 2804 * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock 2805 * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock 2806 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 2807 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock 2808 * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock 2809 */ 2810 #if defined(RCC_D2CCIP2R_LPTIM1SEL) 2811 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ 2812 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) 2813 #else 2814 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ 2815 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) 2816 #endif /* RCC_D2CCIP2R_LPTIM1SEL */ 2817 2818 /** @brief macro to get the LPTIM1 clock source. 2819 * @retval The clock source can be one of the following values: 2820 * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock 2821 * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock 2822 * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock 2823 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 2824 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock 2825 * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock 2826 */ 2827 #if defined(RCC_D2CCIP2R_LPTIM1SEL) 2828 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL))) 2829 #else 2830 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL))) 2831 #endif /* RCC_D2CCIP2R_LPTIM1SEL */ 2832 2833 /** @brief macro to configure the LPTIM2 clock source. 2834 * 2835 * @param __LPTIM2CLKSource__ specifies the LPTIM2 clock source. 2836 * This parameter can be one of the following values: 2837 * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock 2838 * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock 2839 * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock 2840 * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock 2841 * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock 2842 * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock 2843 */ 2844 #if defined(RCC_D3CCIPR_LPTIM2SEL) 2845 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ 2846 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) 2847 #else 2848 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ 2849 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) 2850 #endif /* RCC_D3CCIPR_LPTIM2SEL */ 2851 2852 /** @brief macro to get the LPTIM2 clock source. 2853 * @retval The clock source can be one of the following values: 2854 * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock 2855 * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock 2856 * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock 2857 * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock 2858 * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock 2859 * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock 2860 */ 2861 #if defined(RCC_D3CCIPR_LPTIM2SEL) 2862 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL))) 2863 #else 2864 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL))) 2865 #endif /* RCC_D3CCIPR_LPTIM2SEL */ 2866 2867 /** @brief macro to configure the LPTIM3/4/5 clock source. 2868 * 2869 * @param __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source. 2870 * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock 2871 * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock 2872 * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock 2873 * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock 2874 * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock 2875 * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock 2876 */ 2877 #if defined(RCC_D3CCIPR_LPTIM345SEL) 2878 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ 2879 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__)) 2880 #else 2881 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ 2882 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__)) 2883 #endif /* RCC_D3CCIPR_LPTIM345SEL */ 2884 2885 /** @brief macro to get the LPTIM3/4/5 clock source. 2886 * @retval The clock source can be one of the following values: 2887 * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock 2888 * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock 2889 * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock 2890 * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock 2891 * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock 2892 * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock 2893 */ 2894 #if defined(RCC_D3CCIPR_LPTIM345SEL) 2895 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) 2896 #else 2897 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL))) 2898 #endif /* RCC_D3CCIPR_LPTIM345SEL */ 2899 2900 /** @brief macro to configure the LPTIM3 clock source. 2901 * 2902 * @param __LPTIM3CLKSource__ specifies the LPTIM3 clock source. 2903 * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock 2904 * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock 2905 * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock 2906 * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock 2907 * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock 2908 * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock 2909 */ 2910 #define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG 2911 2912 /** @brief macro to get the LPTIM3 clock source. 2913 * @retval The clock source can be one of the following values: 2914 * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock 2915 * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock 2916 * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock 2917 * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock 2918 * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock 2919 * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock 2920 */ 2921 #define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE 2922 2923 #if defined(LPTIM4) 2924 /** @brief macro to configure the LPTIM4 clock source. 2925 * 2926 * @param __LPTIM4CLKSource__ specifies the LPTIM4 clock source. 2927 * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock 2928 * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock 2929 * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock 2930 * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock 2931 * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock 2932 * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock 2933 */ 2934 #define __HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG 2935 2936 2937 /** @brief macro to get the LPTIM4 clock source. 2938 * @retval The clock source can be one of the following values: 2939 * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock 2940 * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock 2941 * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock 2942 * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock 2943 * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock 2944 * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock 2945 */ 2946 #define __HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE 2947 #endif /* LPTIM4 */ 2948 2949 #if defined(LPTIM5) 2950 /** @brief macro to configure the LPTIM5 clock source. 2951 * 2952 * @param __LPTIM5CLKSource__ specifies the LPTIM5 clock source. 2953 * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock 2954 * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock 2955 * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock 2956 * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock 2957 * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock 2958 * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock 2959 */ 2960 #define __HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG 2961 2962 2963 /** @brief macro to get the LPTIM5 clock source. 2964 * @retval The clock source can be one of the following values: 2965 * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock 2966 * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock 2967 * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock 2968 * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock 2969 * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock 2970 * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock 2971 */ 2972 #define __HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE 2973 #endif /* LPTIM5 */ 2974 2975 #if defined(QUADSPI) 2976 /** @brief macro to configure the QSPI clock source. 2977 * 2978 * @param __QSPICLKSource__ specifies the QSPI clock source. 2979 * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock 2980 * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock 2981 * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock 2982 * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock 2983 */ 2984 #define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \ 2985 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__)) 2986 2987 2988 /** @brief macro to get the QSPI clock source. 2989 * @retval The clock source can be one of the following values: 2990 * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock 2991 * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock 2992 * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock 2993 * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock 2994 */ 2995 #define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL))) 2996 #endif /* QUADSPI */ 2997 2998 #if defined(OCTOSPI1) || defined(OCTOSPI2) 2999 /** @brief macro to configure the OSPI clock source. 3000 * 3001 * @param __OSPICLKSource__ specifies the OSPI clock source. 3002 * @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock 3003 * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock 3004 * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock 3005 * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock 3006 */ 3007 #if defined(RCC_CDCCIPR_OCTOSPISEL) 3008 #define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ 3009 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) 3010 #else 3011 #define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ 3012 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) 3013 #endif /* RCC_CDCCIPR_OCTOSPISEL */ 3014 3015 /** @brief macro to get the OSPI clock source. 3016 * @retval The clock source can be one of the following values: 3017 * @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock 3018 * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock 3019 * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock 3020 * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock 3021 */ 3022 #if defined(RCC_CDCCIPR_OCTOSPISEL) 3023 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL))) 3024 #else 3025 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL))) 3026 #endif /* RCC_CDCCIPR_OCTOSPISEL */ 3027 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ 3028 3029 3030 #if defined(DSI) 3031 /** @brief macro to configure the DSI clock source. 3032 * 3033 * @param __DSICLKSource__ specifies the DSI clock source. 3034 * @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock 3035 * @arg RCC_RCC_DSICLKSOURCE_PLL2 : PLL2_Q Clock clock is selected as DSI byte lane clock 3036 */ 3037 #define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \ 3038 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__)) 3039 3040 3041 /** @brief macro to get the DSI clock source. 3042 * @retval The clock source can be one of the following values: 3043 * @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock 3044 * @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock 3045 */ 3046 #define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL))) 3047 #endif /*DSI*/ 3048 3049 /** @brief macro to configure the FMC clock source. 3050 * 3051 * @param __FMCCLKSource__ specifies the FMC clock source. 3052 * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock 3053 * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock 3054 * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock 3055 * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock 3056 */ 3057 #if defined(RCC_D1CCIPR_FMCSEL) 3058 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ 3059 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) 3060 #else 3061 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ 3062 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) 3063 #endif /* RCC_D1CCIPR_FMCSEL */ 3064 3065 /** @brief macro to get the FMC clock source. 3066 * @retval The clock source can be one of the following values: 3067 * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock 3068 * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock 3069 * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock 3070 * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock 3071 */ 3072 #if defined(RCC_D1CCIPR_FMCSEL) 3073 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL))) 3074 #else 3075 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL))) 3076 #endif /* RCC_D1CCIPR_FMCSEL */ 3077 3078 /** @brief Macro to configure the USB clock (USBCLK). 3079 * @param __USBCLKSource__ specifies the USB clock source. 3080 * This parameter can be one of the following values: 3081 * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock 3082 * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock 3083 * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock 3084 */ 3085 #if defined(RCC_D2CCIP2R_USBSEL) 3086 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ 3087 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) 3088 #else 3089 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ 3090 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) 3091 #endif /* RCC_D2CCIP2R_USBSEL */ 3092 3093 /** @brief Macro to get the USB clock source. 3094 * @retval The clock source can be one of the following values: 3095 * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock 3096 * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock 3097 * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock 3098 */ 3099 #if defined(RCC_D2CCIP2R_USBSEL) 3100 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL))) 3101 #else 3102 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL))) 3103 #endif /* RCC_D2CCIP2R_USBSEL */ 3104 3105 /** @brief Macro to configure the ADC clock 3106 * @param __ADCCLKSource__ specifies the ADC digital interface clock source. 3107 * This parameter can be one of the following values: 3108 * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock 3109 * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock 3110 * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock 3111 */ 3112 #if defined(RCC_D3CCIPR_ADCSEL) 3113 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ 3114 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) 3115 #else 3116 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ 3117 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) 3118 #endif /* RCC_D3CCIPR_ADCSEL */ 3119 3120 /** @brief Macro to get the ADC clock source. 3121 * @retval The clock source can be one of the following values: 3122 * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock 3123 * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock 3124 * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock 3125 */ 3126 #if defined(RCC_D3CCIPR_ADCSEL) 3127 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL))) 3128 #else 3129 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL))) 3130 #endif /* RCC_D3CCIPR_ADCSEL */ 3131 3132 /** @brief Macro to configure the SWPMI1 clock 3133 * @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source. 3134 * This parameter can be one of the following values: 3135 * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock 3136 * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock 3137 */ 3138 #if defined(RCC_D2CCIP1R_SWPSEL) 3139 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ 3140 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) 3141 #else 3142 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ 3143 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) 3144 #endif /* RCC_D2CCIP1R_SWPSEL */ 3145 3146 /** @brief Macro to get the SWPMI1 clock source. 3147 * @retval The clock source can be one of the following values: 3148 * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock 3149 * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock 3150 */ 3151 #if defined(RCC_D2CCIP1R_SWPSEL) 3152 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL))) 3153 #else 3154 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL))) 3155 #endif /* RCC_D2CCIP1R_SWPSEL */ 3156 3157 /** @brief Macro to configure the DFSDM1 clock 3158 * @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source. 3159 * This parameter can be one of the following values: 3160 * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock 3161 * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock 3162 */ 3163 #if defined(RCC_D2CCIP1R_DFSDM1SEL) 3164 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ 3165 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) 3166 #else 3167 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ 3168 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) 3169 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 3170 3171 /** @brief Macro to get the DFSDM1 clock source. 3172 * @retval The clock source can be one of the following values: 3173 * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock 3174 * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock 3175 */ 3176 #if defined (RCC_D2CCIP1R_DFSDM1SEL) 3177 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL))) 3178 #else 3179 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL))) 3180 #endif /* RCC_D2CCIP1R_DFSDM1SEL */ 3181 3182 #if defined(DFSDM2_BASE) 3183 /** @brief Macro to configure the DFSDM2 clock 3184 * @param __DFSDM2CLKSource__ specifies the DFSDM2 clock source. 3185 * This parameter can be one of the following values: 3186 * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) selected as DFSDM2 clock 3187 * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock 3188 */ 3189 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \ 3190 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__)) 3191 3192 /** @brief Macro to get the DFSDM2 clock source. 3193 * @retval The clock source can be one of the following values: 3194 * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) Clock selected as DFSDM2 clock 3195 * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock 3196 */ 3197 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL))) 3198 #endif /* DFSDM2 */ 3199 3200 /** @brief macro to configure the CEC clock (CECCLK). 3201 * 3202 * @param __CECCLKSource__ specifies the CEC clock source. 3203 * This parameter can be one of the following values: 3204 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 3205 * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock 3206 * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock 3207 */ 3208 #if defined(RCC_D2CCIP2R_CECSEL) 3209 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 3210 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) 3211 #else 3212 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 3213 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) 3214 #endif /* RCC_D2CCIP2R_CECSEL */ 3215 3216 /** @brief macro to get the CEC clock source. 3217 * @retval The clock source can be one of the following values: 3218 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 3219 * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock 3220 * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock 3221 */ 3222 #if defined(RCC_D2CCIP2R_CECSEL) 3223 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL))) 3224 #else 3225 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL))) 3226 #endif /* RCC_D2CCIP2R_CECSEL */ 3227 3228 /** @brief Macro to configure the CLKP : Oscillator clock for peripheral 3229 * @param __CLKPSource__ specifies Oscillator clock for peripheral 3230 * This parameter can be one of the following values: 3231 * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral 3232 * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral 3233 * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral 3234 */ 3235 #if defined(RCC_D1CCIPR_CKPERSEL) 3236 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ 3237 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) 3238 #else 3239 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ 3240 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) 3241 #endif /* RCC_D1CCIPR_CKPERSEL */ 3242 3243 /** @brief Macro to get the Oscillator clock for peripheral source. 3244 * @retval The clock source can be one of the following values: 3245 * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral 3246 * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral 3247 * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral 3248 */ 3249 #if defined(RCC_D1CCIPR_CKPERSEL) 3250 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL))) 3251 #else 3252 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL))) 3253 #endif /* RCC_D1CCIPR_CKPERSEL */ 3254 3255 #if defined(FDCAN1) || defined(FDCAN2) 3256 /** @brief Macro to configure the FDCAN clock 3257 * @param __FDCANCLKSource__ specifies clock source for FDCAN 3258 * This parameter can be one of the following values: 3259 * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock 3260 * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock 3261 * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock 3262 */ 3263 #if defined(RCC_D2CCIP1R_FDCANSEL) 3264 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ 3265 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) 3266 #else 3267 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ 3268 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) 3269 #endif /* RCC_D2CCIP1R_FDCANSEL */ 3270 3271 /** @brief Macro to get the FDCAN clock 3272 * @retval The clock source can be one of the following values: 3273 * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock 3274 * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock 3275 * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock 3276 */ 3277 #if defined(RCC_D2CCIP1R_FDCANSEL) 3278 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL))) 3279 #else 3280 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL))) 3281 #endif /* RCC_D2CCIP1R_FDCANSEL */ 3282 3283 #endif /*FDCAN1 || FDCAN2*/ 3284 3285 /** 3286 * @brief Macro to Configure the SPI1/2/3 clock source. 3287 * @param __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived 3288 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 3289 * This parameter can be one of the following values: 3290 * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL 3291 * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 3292 * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 3293 * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP 3294 * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock 3295 * @retval None 3296 */ 3297 #if defined(RCC_D2CCIP1R_SPI123SEL) 3298 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ 3299 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) 3300 #else 3301 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ 3302 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) 3303 #endif /* RCC_D2CCIP1R_SPI123SEL */ 3304 3305 /** @brief Macro to get the SPI1/2/3 clock source. 3306 * @retval The clock source can be one of the following values: 3307 * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL 3308 * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 3309 * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 3310 * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP 3311 * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock 3312 */ 3313 #if defined(RCC_D2CCIP1R_SPI123SEL) 3314 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) 3315 #else 3316 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL))) 3317 #endif /* RCC_D2CCIP1R_SPI123SEL */ 3318 3319 /** 3320 * @brief Macro to Configure the SPI1 clock source. 3321 * @param __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived 3322 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 3323 * This parameter can be one of the following values: 3324 * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL 3325 * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 3326 * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 3327 * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP 3328 * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock 3329 * @retval None 3330 */ 3331 #define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG 3332 3333 /** @brief Macro to get the SPI1 clock source. 3334 * @retval The clock source can be one of the following values: 3335 * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL 3336 * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 3337 * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 3338 * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP 3339 * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock 3340 */ 3341 #define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE 3342 3343 /** 3344 * @brief Macro to Configure the SPI2 clock source. 3345 * @param __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived 3346 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 3347 * This parameter can be one of the following values: 3348 * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL 3349 * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 3350 * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 3351 * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP 3352 * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock 3353 * @retval None 3354 */ 3355 #define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG 3356 3357 /** @brief Macro to get the SPI2 clock source. 3358 * @retval The clock source can be one of the following values: 3359 * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL 3360 * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 3361 * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 3362 * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP 3363 * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock 3364 */ 3365 #define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE 3366 3367 /** 3368 * @brief Macro to Configure the SPI3 clock source. 3369 * @param __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived 3370 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 3371 * This parameter can be one of the following values: 3372 * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL 3373 * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 3374 * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 3375 * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP 3376 * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock 3377 * @retval None 3378 */ 3379 #define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG 3380 3381 /** @brief Macro to get the SPI3 clock source. 3382 * @retval The clock source can be one of the following values: 3383 * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL 3384 * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 3385 * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 3386 * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP 3387 * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock 3388 */ 3389 #define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE 3390 3391 /** 3392 * @brief Macro to Configure the SPI4/5 clock source. 3393 * @param __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived 3394 * from system PCLK, PLL2, PLL3, OSC 3395 * This parameter can be one of the following values: 3396 * @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1 3397 * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 3398 * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 3399 * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI 3400 * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI 3401 * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE 3402 * @retval None 3403 */ 3404 #if defined(RCC_D2CCIP1R_SPI45SEL) 3405 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ 3406 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) 3407 #else 3408 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ 3409 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) 3410 #endif /* RCC_D2CCIP1R_SPI45SEL */ 3411 3412 /** @brief Macro to get the SPI4/5 clock source. 3413 * @retval The clock source can be one of the following values: 3414 * @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1 3415 * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 3416 * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 3417 * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI 3418 * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI 3419 * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE 3420 */ 3421 #if defined(RCC_D2CCIP1R_SPI45SEL) 3422 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) 3423 #else 3424 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL))) 3425 #endif /* RCC_D2CCIP1R_SPI45SEL */ 3426 3427 /** 3428 * @brief Macro to Configure the SPI4 clock source. 3429 * @param __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived 3430 * from system PCLK, PLL2, PLL3, OSC 3431 * This parameter can be one of the following values: 3432 * @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1 3433 * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 3434 * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 3435 * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI 3436 * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI 3437 * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE 3438 * @retval None 3439 */ 3440 #define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG 3441 3442 /** @brief Macro to get the SPI4 clock source. 3443 * @retval The clock source can be one of the following values: 3444 * @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1 3445 * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 3446 * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 3447 * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI 3448 * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI 3449 * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE 3450 */ 3451 #define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE 3452 3453 /** 3454 * @brief Macro to Configure the SPI5 clock source. 3455 * @param __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived 3456 * from system PCLK, PLL2, PLL3, OSC 3457 * This parameter can be one of the following values: 3458 * @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1 3459 * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 3460 * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 3461 * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI 3462 * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI 3463 * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE 3464 * @retval None 3465 */ 3466 #define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG 3467 3468 /** @brief Macro to get the SPI5 clock source. 3469 * @retval The clock source can be one of the following values: 3470 * @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1 3471 * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 3472 * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 3473 * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI 3474 * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI 3475 * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE 3476 */ 3477 #define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE 3478 3479 /** 3480 * @brief Macro to Configure the SPI6 clock source. 3481 * @param __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived 3482 * from system PCLK, PLL2, PLL3, OSC 3483 * This parameter can be one of the following values: 3484 * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 3485 * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 3486 * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 3487 * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI 3488 * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI 3489 * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE 3490 * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*) 3491 * 3492 * @retval None 3493 * 3494 * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines. 3495 * 3496 */ 3497 #if defined(RCC_D3CCIPR_SPI6SEL) 3498 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ 3499 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) 3500 #else 3501 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ 3502 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) 3503 #endif /* RCC_D3CCIPR_SPI6SEL */ 3504 3505 /** @brief Macro to get the SPI6 clock source. 3506 * @retval The clock source can be one of the following values: 3507 * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 3508 * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 3509 * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 3510 * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI 3511 * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI 3512 * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE 3513 * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN 3514 */ 3515 #if defined(RCC_D3CCIPR_SPI6SEL) 3516 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL))) 3517 #else 3518 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL))) 3519 #endif /* RCC_D3CCIPR_SPI6SEL */ 3520 3521 /** @brief Macro to configure the SDMMC clock 3522 * @param __SDMMCCLKSource__ specifies clock source for SDMMC 3523 * This parameter can be one of the following values: 3524 * @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock 3525 * @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock 3526 */ 3527 #if defined(RCC_D1CCIPR_SDMMCSEL) 3528 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ 3529 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) 3530 #else 3531 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ 3532 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) 3533 #endif /* RCC_D1CCIPR_SDMMCSEL */ 3534 3535 /** @brief Macro to get the SDMMC clock 3536 */ 3537 #if defined(RCC_D1CCIPR_SDMMCSEL) 3538 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL))) 3539 #else 3540 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL))) 3541 #endif /* RCC_D1CCIPR_SDMMCSEL */ 3542 3543 /** @brief macro to configure the RNG clock (RNGCLK). 3544 * 3545 * @param __RNGCLKSource__ specifies the RNG clock source. 3546 * This parameter can be one of the following values: 3547 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 3548 * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock 3549 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 3550 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 3551 */ 3552 #if defined(RCC_D2CCIP2R_RNGSEL) 3553 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ 3554 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) 3555 #else 3556 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ 3557 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) 3558 #endif /* RCC_D2CCIP2R_RNGSEL */ 3559 3560 /** @brief macro to get the RNG clock source. 3561 * @retval The clock source can be one of the following values: 3562 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 3563 * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock 3564 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 3565 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 3566 */ 3567 #if defined(RCC_D2CCIP2R_RNGSEL) 3568 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL))) 3569 #else 3570 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL))) 3571 #endif /* RCC_D2CCIP2R_RNGSEL */ 3572 3573 #if defined(HRTIM1) 3574 /** @brief Macro to configure the HRTIM1 prescaler clock source. 3575 * @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source. 3576 * This parameter can be one of the following values: 3577 * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock 3578 * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock 3579 */ 3580 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \ 3581 MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__)) 3582 3583 /** @brief Macro to get the HRTIM1 clock source. 3584 * @retval The clock source can be one of the following values: 3585 * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock 3586 * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock 3587 */ 3588 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL))) 3589 #endif /* HRTIM1 */ 3590 3591 /** @brief Macro to configure the Timers clocks prescalers 3592 * @param __PRESC__ specifies the Timers clocks prescalers selection 3593 * This parameter can be one of the following values: 3594 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 3595 * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, 3596 * else it is equal to 2 x Frcc_pclkx_d2 (default after reset) 3597 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 3598 * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, 3599 * else it is equal to 4 x Frcc_pclkx_d2 3600 */ 3601 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\ 3602 RCC->CFGR |= (__PRESC__); \ 3603 }while(0) 3604 3605 /** 3606 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 3607 * @retval None 3608 */ 3609 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 3610 3611 /** 3612 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 3613 * @retval None 3614 */ 3615 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 3616 3617 /** 3618 * @brief Enable the RCC LSE CSS Event Line. 3619 * @retval None. 3620 */ 3621 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 3622 3623 /** 3624 * @brief Disable the RCC LSE CSS Event Line. 3625 * @retval None. 3626 */ 3627 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 3628 3629 #if defined(DUAL_CORE) 3630 /** 3631 * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4. 3632 * @retval None 3633 */ 3634 #define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) 3635 3636 /** 3637 * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4. 3638 * @retval None 3639 */ 3640 #define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) 3641 3642 /** 3643 * @brief Enable the RCC LSE CSS Event Line for CM4. 3644 * @retval None. 3645 */ 3646 #define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) 3647 3648 /** 3649 * @brief Disable the RCC LSE CSS Event Line for CM4. 3650 * @retval None. 3651 */ 3652 #define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) 3653 #endif /* DUAL_CORE */ 3654 3655 /** 3656 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 3657 * @retval None. 3658 */ 3659 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 3660 3661 3662 /** 3663 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 3664 * @retval None. 3665 */ 3666 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 3667 3668 3669 /** 3670 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 3671 * @retval None. 3672 */ 3673 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 3674 3675 /** 3676 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 3677 * @retval None. 3678 */ 3679 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 3680 3681 /** 3682 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 3683 * @retval None. 3684 */ 3685 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 3686 do { \ 3687 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 3688 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 3689 } while(0) 3690 3691 /** 3692 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 3693 * @retval None. 3694 */ 3695 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 3696 do { \ 3697 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 3698 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 3699 } while(0) 3700 3701 /** 3702 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 3703 * @retval EXTI RCC LSE CSS Line Status. 3704 */ 3705 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 3706 3707 /** 3708 * @brief Clear the RCC LSE CSS EXTI flag. 3709 * @retval None. 3710 */ 3711 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) 3712 3713 #if defined(DUAL_CORE) 3714 /** 3715 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4. 3716 * @retval EXTI RCC LSE CSS Line Status. 3717 */ 3718 #define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 3719 3720 /** 3721 * @brief Clear the RCC LSE CSS EXTI flag or not for CM4. 3722 * @retval None. 3723 */ 3724 #define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) 3725 #endif /* DUAL_CORE */ 3726 /** 3727 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 3728 * @retval None. 3729 */ 3730 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) 3731 3732 /** 3733 * @brief Enable the specified CRS interrupts. 3734 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 3735 * This parameter can be any combination of the following values: 3736 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3737 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3738 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3739 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3740 * @retval None 3741 */ 3742 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 3743 3744 /** 3745 * @brief Disable the specified CRS interrupts. 3746 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 3747 * This parameter can be any combination of the following values: 3748 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3749 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3750 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3751 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3752 * @retval None 3753 */ 3754 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 3755 3756 /** @brief Check whether the CRS interrupt has occurred or not. 3757 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 3758 * This parameter can be one of the following values: 3759 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3760 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3761 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3762 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3763 * @retval The new state of __INTERRUPT__ (SET or RESET). 3764 */ 3765 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 3766 3767 /** @brief Clear the CRS interrupt pending bits 3768 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 3769 * This parameter can be any combination of the following values: 3770 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3771 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3772 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3773 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3774 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 3775 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 3776 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 3777 */ 3778 /* CRS IT Error Mask */ 3779 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 3780 3781 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 3782 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 3783 { \ 3784 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 3785 } \ 3786 else \ 3787 { \ 3788 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 3789 } \ 3790 } while(0) 3791 3792 /** 3793 * @brief Check whether the specified CRS flag is set or not. 3794 * @param __FLAG__ specifies the flag to check. 3795 * This parameter can be one of the following values: 3796 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 3797 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 3798 * @arg @ref RCC_CRS_FLAG_ERR Error 3799 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 3800 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 3801 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 3802 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 3803 * @retval The new state of _FLAG_ (TRUE or FALSE). 3804 */ 3805 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 3806 3807 /** 3808 * @brief Clear the CRS specified FLAG. 3809 * @param __FLAG__ specifies the flag to clear. 3810 * This parameter can be one of the following values: 3811 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 3812 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 3813 * @arg @ref RCC_CRS_FLAG_ERR Error 3814 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 3815 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 3816 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 3817 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 3818 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 3819 * @retval None 3820 */ 3821 3822 /* CRS Flag Error Mask */ 3823 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 3824 3825 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 3826 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 3827 { \ 3828 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 3829 } \ 3830 else \ 3831 { \ 3832 WRITE_REG(CRS->ICR, (__FLAG__)); \ 3833 } \ 3834 } while(0) 3835 3836 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 3837 * @{ 3838 */ 3839 /** 3840 * @brief Enable the oscillator clock for frequency error counter. 3841 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 3842 * @retval None 3843 */ 3844 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 3845 3846 /** 3847 * @brief Disable the oscillator clock for frequency error counter. 3848 * @retval None 3849 */ 3850 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 3851 3852 /** 3853 * @brief Enable the automatic hardware adjustment of TRIM bits. 3854 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 3855 * @retval None 3856 */ 3857 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 3858 3859 /** 3860 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 3861 * @retval None 3862 */ 3863 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 3864 3865 /** 3866 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 3867 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 3868 * of the synchronization source after pre-scaling. It is then decreased by one in order to 3869 * reach the expected synchronization on the zero value. The formula is the following: 3870 * RELOAD = (fTARGET / fSYNC) -1 3871 * @param __FTARGET__ Target frequency (value in Hz) 3872 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 3873 * @retval None 3874 */ 3875 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 3876 3877 3878 /** 3879 * @} 3880 */ 3881 3882 3883 /** 3884 * @} 3885 */ 3886 3887 3888 /* Exported functions --------------------------------------------------------*/ 3889 /** @addtogroup RCCEx_Exported_Functions 3890 * @{ 3891 */ 3892 3893 /** @addtogroup RCCEx_Exported_Functions_Group1 3894 * @{ 3895 */ 3896 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 3897 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 3898 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 3899 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void); 3900 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void); 3901 uint32_t HAL_RCCEx_GetD1SysClockFreq(void); 3902 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks); 3903 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks); 3904 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks); 3905 /** 3906 * @} 3907 */ 3908 3909 /** @addtogroup RCCEx_Exported_Functions_Group2 3910 * @{ 3911 */ 3912 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 3913 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); 3914 void HAL_RCCEx_EnableLSECSS(void); 3915 void HAL_RCCEx_DisableLSECSS(void); 3916 void HAL_RCCEx_EnableLSECSS_IT(void); 3917 void HAL_RCCEx_LSECSS_IRQHandler(void); 3918 void HAL_RCCEx_LSECSS_Callback(void); 3919 #if defined(DUAL_CORE) 3920 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx); 3921 #endif /*DUAL_CORE*/ 3922 #if defined(RCC_GCR_WW1RSC) 3923 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx); 3924 #endif /*RCC_GCR_WW1RSC*/ 3925 /** 3926 * @} 3927 */ 3928 3929 3930 /** @addtogroup RCCEx_Exported_Functions_Group3 3931 * @{ 3932 */ 3933 3934 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 3935 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 3936 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 3937 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 3938 void HAL_RCCEx_CRS_IRQHandler(void); 3939 void HAL_RCCEx_CRS_SyncOkCallback(void); 3940 void HAL_RCCEx_CRS_SyncWarnCallback(void); 3941 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 3942 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 3943 3944 /** 3945 * @} 3946 */ 3947 3948 /** 3949 * @} 3950 */ 3951 3952 /* Private macros ------------------------------------------------------------*/ 3953 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros 3954 * @{ 3955 */ 3956 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters 3957 * @{ 3958 */ 3959 3960 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \ 3961 ((VALUE) == RCC_PLL2_DIVQ) || \ 3962 ((VALUE) == RCC_PLL2_DIVR)) 3963 3964 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \ 3965 ((VALUE) == RCC_PLL3_DIVQ) || \ 3966 ((VALUE) == RCC_PLL3_DIVR)) 3967 3968 #if defined(RCC_D2CCIP2R_USART16SEL) 3969 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ 3970 ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ 3971 ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ 3972 ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ 3973 ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ 3974 ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) 3975 #else 3976 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ 3977 ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \ 3978 ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ 3979 ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ 3980 ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ 3981 ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ 3982 ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) 3983 /* alias*/ 3984 #define IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE 3985 #endif /* RCC_D2CCIP2R_USART16SEL */ 3986 3987 #if defined(RCC_D2CCIP2R_USART28SEL) 3988 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ 3989 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ 3990 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ 3991 ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ 3992 ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ 3993 ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) 3994 #else 3995 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ 3996 ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \ 3997 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ 3998 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ 3999 ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ 4000 ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ 4001 ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) 4002 #endif /* RCC_D2CCIP2R_USART28SEL */ 4003 4004 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \ 4005 ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \ 4006 ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \ 4007 ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \ 4008 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ 4009 ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) 4010 4011 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \ 4012 ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \ 4013 ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \ 4014 ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \ 4015 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ 4016 ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) 4017 4018 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \ 4019 ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \ 4020 ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \ 4021 ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \ 4022 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ 4023 ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) 4024 4025 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \ 4026 ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \ 4027 ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \ 4028 ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \ 4029 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ 4030 ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) 4031 4032 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \ 4033 ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \ 4034 ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \ 4035 ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \ 4036 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ 4037 ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) 4038 4039 #define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \ 4040 ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \ 4041 ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \ 4042 ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \ 4043 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ 4044 ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) 4045 4046 #define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \ 4047 ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \ 4048 ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \ 4049 ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \ 4050 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ 4051 ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) 4052 4053 #define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \ 4054 ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \ 4055 ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \ 4056 ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \ 4057 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ 4058 ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) 4059 4060 #if defined(UART9) 4061 #define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \ 4062 ((SOURCE) == RCC_UART9CLKSOURCE_PLL2) || \ 4063 ((SOURCE) == RCC_UART9CLKSOURCE_PLL3) || \ 4064 ((SOURCE) == RCC_UART9CLKSOURCE_CSI) || \ 4065 ((SOURCE) == RCC_UART9CLKSOURCE_LSE) || \ 4066 ((SOURCE) == RCC_UART9CLKSOURCE_HSI)) 4067 #endif 4068 4069 #if defined(USART10) 4070 #define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \ 4071 ((SOURCE) == RCC_USART10CLKSOURCE_PLL2) || \ 4072 ((SOURCE) == RCC_USART10CLKSOURCE_PLL3) || \ 4073 ((SOURCE) == RCC_USART10CLKSOURCE_CSI) || \ 4074 ((SOURCE) == RCC_USART10CLKSOURCE_LSE) || \ 4075 ((SOURCE) == RCC_USART10CLKSOURCE_HSI)) 4076 #endif 4077 4078 #define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \ 4079 ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \ 4080 ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \ 4081 ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \ 4082 ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \ 4083 ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI)) 4084 4085 #if defined(I2C5) 4086 #define IS_RCC_I2C1235CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1235CLKSOURCE_PLL3) || \ 4087 ((SOURCE) == RCC_I2C1235CLKSOURCE_HSI) || \ 4088 ((SOURCE) == RCC_I2C1235CLKSOURCE_D2PCLK1) || \ 4089 ((SOURCE) == RCC_I2C1235CLKSOURCE_CSI)) 4090 4091 #define IS_RCC_I2C123CLKSOURCE IS_RCC_I2C1235CLKSOURCE /* For API Backward compatibility */ 4092 #else 4093 #define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \ 4094 ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \ 4095 ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \ 4096 ((SOURCE) == RCC_I2C123CLKSOURCE_CSI)) 4097 #endif /*I2C5*/ 4098 4099 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \ 4100 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ 4101 ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \ 4102 ((SOURCE) == RCC_I2C1CLKSOURCE_CSI)) 4103 4104 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \ 4105 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ 4106 ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \ 4107 ((SOURCE) == RCC_I2C2CLKSOURCE_CSI)) 4108 4109 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \ 4110 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ 4111 ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \ 4112 ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) 4113 4114 #define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \ 4115 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \ 4116 ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \ 4117 ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) 4118 4119 #if defined(I2C5) 4120 #define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \ 4121 ((SOURCE) == RCC_I2C5CLKSOURCE_HSI) || \ 4122 ((SOURCE) == RCC_I2C5CLKSOURCE_D2PCLK1)|| \ 4123 ((SOURCE) == RCC_I2C5CLKSOURCE_CSI)) 4124 #endif /*I2C5*/ 4125 4126 #define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \ 4127 ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \ 4128 ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \ 4129 ((SOURCE) == RCC_RNGCLKSOURCE_LSI)) 4130 4131 #if defined(HRTIM1) 4132 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \ 4133 ((SOURCE) == RCC_HRTIM1CLK_CPUCLK)) 4134 #endif 4135 4136 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \ 4137 ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \ 4138 ((SOURCE) == RCC_USBCLKSOURCE_HSI48)) 4139 4140 #define IS_RCC_SAI1CLK(__SOURCE__) \ 4141 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 4142 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \ 4143 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \ 4144 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \ 4145 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 4146 4147 #if defined(SAI3) 4148 #define IS_RCC_SAI23CLK(__SOURCE__) \ 4149 (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \ 4150 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \ 4151 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \ 4152 ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \ 4153 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN)) 4154 4155 #define IS_RCC_SAI2CLK(__SOURCE__) \ 4156 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 4157 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \ 4158 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \ 4159 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \ 4160 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) 4161 4162 4163 #define IS_RCC_SAI3CLK(__SOURCE__) \ 4164 (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \ 4165 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \ 4166 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \ 4167 ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \ 4168 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN)) 4169 #endif 4170 4171 #if defined(RCC_CDCCIP1R_SAI2ASEL) 4172 #define IS_RCC_SAI2ACLK(__SOURCE__) \ 4173 (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL) || \ 4174 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \ 4175 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \ 4176 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \ 4177 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \ 4178 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF)) 4179 #endif 4180 4181 #if defined(RCC_CDCCIP1R_SAI2BSEL) 4182 #define IS_RCC_SAI2BCLK(__SOURCE__) \ 4183 (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL) || \ 4184 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \ 4185 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \ 4186 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \ 4187 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \ 4188 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF)) 4189 #endif 4190 4191 #define IS_RCC_SPI123CLK(__SOURCE__) \ 4192 (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \ 4193 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \ 4194 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \ 4195 ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \ 4196 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN)) 4197 4198 #define IS_RCC_SPI1CLK(__SOURCE__) \ 4199 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \ 4200 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \ 4201 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \ 4202 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \ 4203 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN)) 4204 4205 #define IS_RCC_SPI2CLK(__SOURCE__) \ 4206 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \ 4207 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \ 4208 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \ 4209 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \ 4210 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN)) 4211 4212 #define IS_RCC_SPI3CLK(__SOURCE__) \ 4213 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \ 4214 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \ 4215 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \ 4216 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \ 4217 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN)) 4218 4219 #define IS_RCC_SPI45CLK(__SOURCE__) \ 4220 (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1) || \ 4221 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \ 4222 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \ 4223 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \ 4224 ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \ 4225 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) 4226 4227 #define IS_RCC_SPI4CLK(__SOURCE__) \ 4228 (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1) || \ 4229 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \ 4230 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \ 4231 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ 4232 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \ 4233 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) 4234 4235 #define IS_RCC_SPI5CLK(__SOURCE__) \ 4236 (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \ 4237 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \ 4238 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \ 4239 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ 4240 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \ 4241 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) 4242 4243 #if defined(RCC_D3CCIPR_SPI6SEL) 4244 #define IS_RCC_SPI6CLK(__SOURCE__) \ 4245 (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ 4246 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ 4247 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ 4248 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 4249 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 4250 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) 4251 #else 4252 #define IS_RCC_SPI6CLK(__SOURCE__) \ 4253 (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ 4254 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ 4255 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ 4256 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 4257 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 4258 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \ 4259 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN)) 4260 #endif /* RCC_D3CCIPR_SPI6SEL */ 4261 4262 #if defined(SAI4) 4263 #define IS_RCC_SAI4ACLK(__SOURCE__) \ 4264 (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \ 4265 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \ 4266 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \ 4267 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \ 4268 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN)) 4269 4270 #define IS_RCC_SAI4BCLK(__SOURCE__) \ 4271 (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || \ 4272 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \ 4273 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \ 4274 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \ 4275 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN)) 4276 #endif /*SAI4*/ 4277 4278 #define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 4279 #define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 4280 #define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4281 #define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4282 #define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4283 4284 #define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 4285 #define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 4286 #define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4287 #define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4288 #define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4289 4290 #define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) || \ 4291 ((VALUE) == RCC_PLL2VCIRANGE_1) || \ 4292 ((VALUE) == RCC_PLL2VCIRANGE_2) || \ 4293 ((VALUE) == RCC_PLL2VCIRANGE_3)) 4294 4295 #define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) || \ 4296 ((VALUE) == RCC_PLL3VCIRANGE_1) || \ 4297 ((VALUE) == RCC_PLL3VCIRANGE_2) || \ 4298 ((VALUE) == RCC_PLL3VCIRANGE_3)) 4299 4300 #define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) || \ 4301 ((VALUE) == RCC_PLL2VCOMEDIUM)) 4302 4303 #define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \ 4304 ((VALUE) == RCC_PLL3VCOMEDIUM)) 4305 4306 #define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \ 4307 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \ 4308 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \ 4309 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \ 4310 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ 4311 ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP)) 4312 4313 #define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \ 4314 ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \ 4315 ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \ 4316 ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \ 4317 ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \ 4318 ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP)) 4319 4320 #define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \ 4321 ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \ 4322 ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \ 4323 ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \ 4324 ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \ 4325 ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP)) 4326 4327 #define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1) || \ 4328 ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \ 4329 ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \ 4330 ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \ 4331 ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \ 4332 ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP)) 4333 4334 #if defined(LPTIM4) 4335 #define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \ 4336 ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \ 4337 ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \ 4338 ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \ 4339 ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \ 4340 ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP)) 4341 #endif /* LPTIM4*/ 4342 4343 #if defined(LPTIM5) 4344 #define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \ 4345 ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \ 4346 ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \ 4347 ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \ 4348 ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \ 4349 ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP)) 4350 #endif /*LPTIM5*/ 4351 4352 #if defined(QUADSPI) 4353 #define IS_RCC_QSPICLK(__SOURCE__) \ 4354 (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \ 4355 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \ 4356 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \ 4357 ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP)) 4358 #endif /*QUADSPI*/ 4359 4360 #if defined(OCTOSPI1) || defined(OCTOSPI1) 4361 #define IS_RCC_OSPICLK(__SOURCE__) \ 4362 (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK) || \ 4363 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL) || \ 4364 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2) || \ 4365 ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP)) 4366 #endif /*OCTOSPI1 || OCTOSPI1*/ 4367 4368 #if defined(DSI) 4369 #define IS_RCC_DSICLK(__SOURCE__) \ 4370 (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \ 4371 ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2)) 4372 #endif /*DSI*/ 4373 4374 #define IS_RCC_FMCCLK(__SOURCE__) \ 4375 (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \ 4376 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \ 4377 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \ 4378 ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP)) 4379 4380 #if defined(FDCAN1) || defined(FDCAN2) 4381 #define IS_RCC_FDCANCLK(__SOURCE__) \ 4382 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ 4383 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ 4384 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2)) 4385 #endif /*FDCAN1 || FDCAN2*/ 4386 4387 #define IS_RCC_SDMMC(__SOURCE__) \ 4388 (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \ 4389 ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2)) 4390 4391 #define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \ 4392 ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \ 4393 ((SOURCE) == RCC_ADCCLKSOURCE_CLKP)) 4394 4395 #define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \ 4396 ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI)) 4397 4398 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \ 4399 ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS)) 4400 4401 #if defined(DFSDM2_BASE) 4402 #define IS_RCC_DFSDM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \ 4403 ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS)) 4404 #endif /*DFSDM2*/ 4405 4406 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \ 4407 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \ 4408 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \ 4409 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI)) 4410 4411 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \ 4412 ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \ 4413 ((SOURCE) == RCC_CECCLKSOURCE_CSI)) 4414 4415 #define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \ 4416 ((SOURCE) == RCC_CLKPSOURCE_CSI) || \ 4417 ((SOURCE) == RCC_CLKPSOURCE_HSE)) 4418 #define IS_RCC_TIMPRES(VALUE) \ 4419 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ 4420 ((VALUE) == RCC_TIMPRES_ACTIVATED)) 4421 4422 #if defined(DUAL_CORE) 4423 #define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \ 4424 ((CORE) == RCC_BOOT_C2)) 4425 #endif /*DUAL_CORE*/ 4426 4427 #if defined(DUAL_CORE) 4428 #define IS_RCC_SCOPE_WWDG(WWDG) (((WWDG) == RCC_WWDG1) || \ 4429 ((WWDG) == RCC_WWDG2)) 4430 #else 4431 #define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1) 4432 4433 #endif /*DUAL_CORE*/ 4434 4435 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \ 4436 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 4437 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \ 4438 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN)) 4439 4440 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 4441 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 4442 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 4443 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 4444 4445 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 4446 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 4447 4448 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 4449 4450 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 4451 4452 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 4453 4454 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 4455 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 4456 /** 4457 * @} 4458 */ 4459 4460 /** 4461 * @} 4462 */ 4463 4464 /** 4465 * @} 4466 */ 4467 4468 /** 4469 * @} 4470 */ 4471 4472 #ifdef __cplusplus 4473 } 4474 #endif 4475 4476 #endif /* STM32H7xx_HAL_RCC_EX_H */ 4477 4478 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4479
