1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32H7xx_LL_TIM_H
22 #define __STM32H7xx_LL_TIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)
36
37 /** @defgroup TIM_LL TIM
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
44 * @{
45 */
46 static const uint8_t OFFSET_TAB_CCMRx[] =
47 {
48 0x00U, /* 0: TIMx_CH1 */
49 0x00U, /* 1: TIMx_CH1N */
50 0x00U, /* 2: TIMx_CH2 */
51 0x00U, /* 3: TIMx_CH2N */
52 0x04U, /* 4: TIMx_CH3 */
53 0x04U, /* 5: TIMx_CH3N */
54 0x04U, /* 6: TIMx_CH4 */
55 0x3CU, /* 7: TIMx_CH5 */
56 0x3CU /* 8: TIMx_CH6 */
57 };
58
59 static const uint8_t SHIFT_TAB_OCxx[] =
60 {
61 0U, /* 0: OC1M, OC1FE, OC1PE */
62 0U, /* 1: - NA */
63 8U, /* 2: OC2M, OC2FE, OC2PE */
64 0U, /* 3: - NA */
65 0U, /* 4: OC3M, OC3FE, OC3PE */
66 0U, /* 5: - NA */
67 8U, /* 6: OC4M, OC4FE, OC4PE */
68 0U, /* 7: OC5M, OC5FE, OC5PE */
69 8U /* 8: OC6M, OC6FE, OC6PE */
70 };
71
72 static const uint8_t SHIFT_TAB_ICxx[] =
73 {
74 0U, /* 0: CC1S, IC1PSC, IC1F */
75 0U, /* 1: - NA */
76 8U, /* 2: CC2S, IC2PSC, IC2F */
77 0U, /* 3: - NA */
78 0U, /* 4: CC3S, IC3PSC, IC3F */
79 0U, /* 5: - NA */
80 8U, /* 6: CC4S, IC4PSC, IC4F */
81 0U, /* 7: - NA */
82 0U /* 8: - NA */
83 };
84
85 static const uint8_t SHIFT_TAB_CCxP[] =
86 {
87 0U, /* 0: CC1P */
88 2U, /* 1: CC1NP */
89 4U, /* 2: CC2P */
90 6U, /* 3: CC2NP */
91 8U, /* 4: CC3P */
92 10U, /* 5: CC3NP */
93 12U, /* 6: CC4P */
94 16U, /* 7: CC5P */
95 20U /* 8: CC6P */
96 };
97
98 static const uint8_t SHIFT_TAB_OISx[] =
99 {
100 0U, /* 0: OIS1 */
101 1U, /* 1: OIS1N */
102 2U, /* 2: OIS2 */
103 3U, /* 3: OIS2N */
104 4U, /* 4: OIS3 */
105 5U, /* 5: OIS3N */
106 6U, /* 6: OIS4 */
107 8U, /* 7: OIS5 */
108 10U /* 8: OIS6 */
109 };
110 /**
111 * @}
112 */
113
114 /* Private constants ---------------------------------------------------------*/
115 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
116 * @{
117 */
118
119 #if defined(TIM_BREAK_INPUT_SUPPORT)
120 /* Defines used for the bit position in the register and perform offsets */
121 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
122
123 /* Generic bit definitions for TIMx_AF1 register */
124 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
125 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
126 #endif /* TIM_BREAK_INPUT_SUPPORT */
127
128
129 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
130 #define DT_DELAY_1 ((uint8_t)0x7F)
131 #define DT_DELAY_2 ((uint8_t)0x3F)
132 #define DT_DELAY_3 ((uint8_t)0x1F)
133 #define DT_DELAY_4 ((uint8_t)0x1F)
134
135 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
136 #define DT_RANGE_1 ((uint8_t)0x00)
137 #define DT_RANGE_2 ((uint8_t)0x80)
138 #define DT_RANGE_3 ((uint8_t)0xC0)
139 #define DT_RANGE_4 ((uint8_t)0xE0)
140
141
142 /**
143 * @}
144 */
145
146 /* Private macros ------------------------------------------------------------*/
147 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
148 * @{
149 */
150 /** @brief Convert channel id into channel index.
151 * @param __CHANNEL__ This parameter can be one of the following values:
152 * @arg @ref LL_TIM_CHANNEL_CH1
153 * @arg @ref LL_TIM_CHANNEL_CH1N
154 * @arg @ref LL_TIM_CHANNEL_CH2
155 * @arg @ref LL_TIM_CHANNEL_CH2N
156 * @arg @ref LL_TIM_CHANNEL_CH3
157 * @arg @ref LL_TIM_CHANNEL_CH3N
158 * @arg @ref LL_TIM_CHANNEL_CH4
159 * @arg @ref LL_TIM_CHANNEL_CH5
160 * @arg @ref LL_TIM_CHANNEL_CH6
161 * @retval none
162 */
163 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
164 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
165 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
166 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
167 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
168 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
169 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
171 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
172
173 /** @brief Calculate the deadtime sampling period(in ps).
174 * @param __TIMCLK__ timer input clock frequency (in Hz).
175 * @param __CKD__ This parameter can be one of the following values:
176 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
177 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
178 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
179 * @retval none
180 */
181 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
182 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
183 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
184 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
185 /**
186 * @}
187 */
188
189
190 /* Exported types ------------------------------------------------------------*/
191 #if defined(USE_FULL_LL_DRIVER)
192 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
193 * @{
194 */
195
196 /**
197 * @brief TIM Time Base configuration structure definition.
198 */
199 typedef struct
200 {
201 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
202 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
203
204 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
205
206 uint32_t CounterMode; /*!< Specifies the counter mode.
207 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
208
209 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
210
211 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
212 Auto-Reload Register at the next update event.
213 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
214 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
215
216 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
217
218 uint32_t ClockDivision; /*!< Specifies the clock division.
219 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
220
221 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
222
223 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
224 reaches zero, an update event is generated and counting restarts
225 from the RCR value (N).
226 This means in PWM mode that (N+1) corresponds to:
227 - the number of PWM periods in edge-aligned mode
228 - the number of half PWM period in center-aligned mode
229 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
230 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
231
232 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
233 } LL_TIM_InitTypeDef;
234
235 /**
236 * @brief TIM Output Compare configuration structure definition.
237 */
238 typedef struct
239 {
240 uint32_t OCMode; /*!< Specifies the output mode.
241 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
242
243 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
244
245 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
246 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
247
248 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
249
250 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
251 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
252
253 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
254
255 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
256 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
257
258 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
259
260 uint32_t OCPolarity; /*!< Specifies the output polarity.
261 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
262
263 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
264
265 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
266 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
267
268 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
269
270
271 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
272 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
273
274 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
275
276 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
277 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
278
279 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
280 } LL_TIM_OC_InitTypeDef;
281
282 /**
283 * @brief TIM Input Capture configuration structure definition.
284 */
285
286 typedef struct
287 {
288
289 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
290 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
291
292 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
293
294 uint32_t ICActiveInput; /*!< Specifies the input.
295 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
296
297 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
298
299 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
300 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
301
302 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
303
304 uint32_t ICFilter; /*!< Specifies the input capture filter.
305 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
306
307 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
308 } LL_TIM_IC_InitTypeDef;
309
310
311 /**
312 * @brief TIM Encoder interface configuration structure definition.
313 */
314 typedef struct
315 {
316 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
317 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
318
319 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
320
321 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
322 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
323
324 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
325
326 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
327 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
328
329 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
330
331 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
332 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
333
334 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
335
336 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
337 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
338
339 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
340
341 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
342 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
343
344 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
345
346 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
347 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
348
349 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
350
351 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
352 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
353
354 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
355
356 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
357 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
358
359 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
360
361 } LL_TIM_ENCODER_InitTypeDef;
362
363 /**
364 * @brief TIM Hall sensor interface configuration structure definition.
365 */
366 typedef struct
367 {
368
369 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
370 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
371
372 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
373
374 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
375 Prescaler must be set to get a maximum counter period longer than the
376 time interval between 2 consecutive changes on the Hall inputs.
377 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
378
379 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
380
381 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
382 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
383
384 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
385
386 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
387 A positive pulse (TRGO event) is generated with a programmable delay every time
388 a change occurs on the Hall inputs.
389 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
390
391 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
392 } LL_TIM_HALLSENSOR_InitTypeDef;
393
394 /**
395 * @brief BDTR (Break and Dead Time) structure definition
396 */
397 typedef struct
398 {
399 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
400 This parameter can be a value of @ref TIM_LL_EC_OSSR
401
402 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
403
404 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
405
406 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
407 This parameter can be a value of @ref TIM_LL_EC_OSSI
408
409 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
410
411 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
412
413 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
414 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
415
416 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
417 has been written, their content is frozen until the next reset.*/
418
419 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
420 switching-on of the outputs.
421 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
422
423 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
424
425 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
426
427 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
428 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
429
430 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
431
432 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
433
434 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
435 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
436
437 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
438
439 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
440
441 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
442 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
443
444 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
445
446 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
447
448 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
449 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
450
451 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
452
453 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
454
455 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
456 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
457
458 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
459
460 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
461
462 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
463 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
464
465 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
466
467 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
468
469 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
470 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
471
472 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
473
474 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
475 } LL_TIM_BDTR_InitTypeDef;
476
477 /**
478 * @}
479 */
480 #endif /* USE_FULL_LL_DRIVER */
481
482 /* Exported constants --------------------------------------------------------*/
483 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
484 * @{
485 */
486
487 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
488 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
489 * @{
490 */
491 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
492 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
493 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
494 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
495 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
496 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
497 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
498 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
499 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
500 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
501 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
502 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
503 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
504 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
505 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
506 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
507 /**
508 * @}
509 */
510
511 #if defined(USE_FULL_LL_DRIVER)
512 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
513 * @{
514 */
515 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
516 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
517 /**
518 * @}
519 */
520
521 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
522 * @{
523 */
524 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
525 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
526 /**
527 * @}
528 */
529
530 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
531 * @{
532 */
533 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
534 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
535 /**
536 * @}
537 */
538 #endif /* USE_FULL_LL_DRIVER */
539
540 /** @defgroup TIM_LL_EC_IT IT Defines
541 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
542 * @{
543 */
544 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
545 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
546 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
547 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
548 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
549 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
550 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
551 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
552 /**
553 * @}
554 */
555
556 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
557 * @{
558 */
559 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
560 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
561 /**
562 * @}
563 */
564
565 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
566 * @{
567 */
568 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
569 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
570 /**
571 * @}
572 */
573
574 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
575 * @{
576 */
577 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
578 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
579 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
580 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
581 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
582 /**
583 * @}
584 */
585
586 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
587 * @{
588 */
589 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
590 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
591 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
592 /**
593 * @}
594 */
595
596 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
597 * @{
598 */
599 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
600 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
601 /**
602 * @}
603 */
604
605 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
606 * @{
607 */
608 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
609 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
610 /**
611 * @}
612 */
613
614 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
615 * @{
616 */
617 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
618 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
624 * @{
625 */
626 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
627 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
628 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
629 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
630 /**
631 * @}
632 */
633
634 /** @defgroup TIM_LL_EC_CHANNEL Channel
635 * @{
636 */
637 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
638 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
639 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
640 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
641 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
642 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
643 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
644 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
645 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
646 /**
647 * @}
648 */
649
650 #if defined(USE_FULL_LL_DRIVER)
651 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
652 * @{
653 */
654 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
655 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
656 /**
657 * @}
658 */
659 #endif /* USE_FULL_LL_DRIVER */
660
661 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
662 * @{
663 */
664 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
665 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
666 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
667 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
668 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
669 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
670 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
671 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
672 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
673 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
674 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
675 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
676 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
677 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
678 /**
679 * @}
680 */
681
682 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
683 * @{
684 */
685 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
686 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
687 /**
688 * @}
689 */
690
691 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
692 * @{
693 */
694 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
695 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
696 /**
697 * @}
698 */
699
700 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
701 * @{
702 */
703 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
704 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
705 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
706 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
707 /**
708 * @}
709 */
710
711 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
712 * @{
713 */
714 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
715 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
716 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
717 /**
718 * @}
719 */
720
721 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
722 * @{
723 */
724 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
725 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
726 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
727 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
728 /**
729 * @}
730 */
731
732 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
733 * @{
734 */
735 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
736 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
737 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
738 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
739 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
740 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
741 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
742 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
743 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
744 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
745 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
746 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
747 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
748 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
749 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
750 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
751 /**
752 * @}
753 */
754
755 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
756 * @{
757 */
758 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
759 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
760 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
761 /**
762 * @}
763 */
764
765 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
766 * @{
767 */
768 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
769 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
770 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
771 /**
772 * @}
773 */
774
775 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
776 * @{
777 */
778 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
779 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
780 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
781 /**
782 * @}
783 */
784
785 /** @defgroup TIM_LL_EC_TRGO Trigger Output
786 * @{
787 */
788 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
789 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
790 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
791 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
792 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
793 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
794 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
795 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
801 * @{
802 */
803 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
804 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
805 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
806 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
807 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
808 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
809 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
810 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
811 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
812 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
813 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
814 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
815 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
816 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
817 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
818 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
819 /**
820 * @}
821 */
822
823 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
824 * @{
825 */
826 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
827 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
828 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
829 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
830 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
831 /**
832 * @}
833 */
834
835 /** @defgroup TIM_LL_EC_TS Trigger Selection
836 * @{
837 */
838 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
839 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
840 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
841 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
842 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
843 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
844 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
845 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
846 #define LL_TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) is used as trigger input */
847 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
848 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
849 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
850 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
851 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
852 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
853 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
854 #define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */
855 #define LL_TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) is used as trigger input */
856 /**
857 * @}
858 */
859
860 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
861 * @{
862 */
863 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
864 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
865 /**
866 * @}
867 */
868
869 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
870 * @{
871 */
872 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
873 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
874 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
875 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
876 /**
877 * @}
878 */
879
880 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
881 * @{
882 */
883 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
884 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
885 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
886 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
887 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
888 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
889 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
890 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
891 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
892 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
893 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
894 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
895 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
896 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
897 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
898 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
899 /**
900 * @}
901 */
902
903 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
904 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
905 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
906 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
907 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
908 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
909 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
910 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
911 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
912
913 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
914 #define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
915 #define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
916 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
917 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */
918 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
919 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
920 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
921 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
922
923 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
924 #define LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */
925 #define LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */
926 #define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
927 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */
928 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
929
930 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
931 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */
932
933 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */
934 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
935 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
936 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */
937 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */
938
939 #define LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */
940 #define LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */
941 #define LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */
942
943 #define LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */
944 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */
945 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */
946 #define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */
947 #define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */
948
949 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
950 * @{
951 */
952 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
953 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
954 /**
955 * @}
956 */
957
958 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
959 * @{
960 */
961 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
962 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
963 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
964 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
965 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
966 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
967 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
968 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
969 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
970 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
971 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
972 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
973 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
974 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
975 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
976 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
977 /**
978 * @}
979 */
980
981 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
982 * @{
983 */
984 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
985 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
986 /**
987 * @}
988 */
989
990 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
991 * @{
992 */
993 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
994 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
995 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
996 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
997 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
998 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
999 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1000 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1001 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1002 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1003 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1004 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1005 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1006 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1007 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1008 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1009 /**
1010 * @}
1011 */
1012
1013 /** @defgroup TIM_LL_EC_OSSI OSSI
1014 * @{
1015 */
1016 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1017 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1018 /**
1019 * @}
1020 */
1021
1022 /** @defgroup TIM_LL_EC_OSSR OSSR
1023 * @{
1024 */
1025 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1026 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1027 /**
1028 * @}
1029 */
1030
1031 #if defined(TIM_BREAK_INPUT_SUPPORT)
1032 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1033 * @{
1034 */
1035 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1036 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1037 /**
1038 * @}
1039 */
1040
1041 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1042 * @{
1043 */
1044 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1045 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1046 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1047 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BK0E /*!< internal signal: DFSDM1 break output */
1048 /**
1049 * @}
1050 */
1051
1052 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1053 * @{
1054 */
1055 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1056 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1057 /**
1058 * @}
1059 */
1060 #endif /* TIM_BREAK_INPUT_SUPPORT */
1061
1062 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1063 * @{
1064 */
1065 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1066 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1067 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1068 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1069 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1070 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1071 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1072 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1073 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1074 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1075 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1076 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1077 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1078 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1079 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1080 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1081 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1082 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1083 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1084 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1085 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1086 #if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
1087 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1088 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1089 #endif /* TIM_AF1_BKINE && TIM_AF2_BKINE */
1090 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1091 /**
1092 * @}
1093 */
1094
1095 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1096 * @{
1097 */
1098 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1099 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1100 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1101 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1102 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1103 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1104 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1105 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1106 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1107 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1108 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1109 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1110 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1111 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1112 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1113 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1114 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1115 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1116 /**
1117 * @}
1118 */
1119
1120 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
1121 * @{
1122 */
1123 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /* !< TIM1 input 1 is connected to GPIO */
1124 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1 input 1 is connected to COMP1 OUT */
1125 /**
1126 * @}
1127 */
1128
1129 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap
1130 * @{
1131 */
1132 #define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /* !< TIM8 input 1 is connected to GPIO */
1133 #define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8 input 1 is connected to COMP2 OUT */
1134 /**
1135 * @}
1136 */
1137
1138 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
1139 * @{
1140 */
1141 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /* !< TIM2 input 4 is connected to GPIO */
1142 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2 input 4 is connected to COMP1 OUT */
1143 #define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2 input 4 is connected to COMP2 OUT */
1144 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
1145 /**
1146 * @}
1147 */
1148
1149 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
1150 * @{
1151 */
1152 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /* !< TIM3 input 1 is connected to GPIO */
1153 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3 input 1 is connected to COMP1 OUT */
1154 #define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3 input 1 is connected to COMP2 OUT */
1155 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
1156 /**
1157 * @}
1158 */
1159
1160 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap
1161 * @{
1162 */
1163 #define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /* !< TIM5 input 1 is connected to GPIO */
1164 #define LL_TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5 input 1 is connected to CAN TMP */
1165 #define LL_TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5 input 1 is connected to CAN RTP */
1166 /**
1167 * @}
1168 */
1169
1170 /** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 Timer Input Ch1 Remap
1171 * @{
1172 */
1173 #define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000U /* !< TIM12 input 1 is connected to GPIO */
1174 #define LL_TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 input 1 is connected to SPDIF FS */
1175 /**
1176 * @}
1177 */
1178
1179 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
1180 * @{
1181 */
1182 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /* !< TIM15 input 1 is connected to GPIO */
1183 #define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15 input 1 is connected to TIM2 CH1 */
1184 #define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15 input 1 is connected to TIM3 CH1 */
1185 #define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */
1186 #define LL_TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15 input 1 is connected to RCC LSE */
1187 #define LL_TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI */
1188 #define LL_TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */
1189 /**
1190 * @}
1191 */
1192
1193 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
1194 * @{
1195 */
1196 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /* !< TIM15 input 2 is connected to GPIO */
1197 #define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15 input 2 is connected to TIM2 CH2 */
1198 #define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM3 CH2 */
1199 #define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */
1200 /**
1201 * @}
1202 */
1203
1204 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1205 * @{
1206 */
1207 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /* !< TIM16 input 1 is connected to GPIO */
1208 #define LL_TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 input 1 is connected to RCC LSI */
1209 #define LL_TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 input 1 is connected to RCC LSE */
1210 #define LL_TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */
1211 /**
1212 * @}
1213 */
1214
1215 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1216 * @{
1217 */
1218 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /* !< TIM17 input 1 is connected to GPIO */
1219 #define LL_TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 input 1 is connected to SPDIF FS */
1220 #define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */
1221 #define LL_TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */
1222 /**
1223 * @}
1224 */
1225
1226 /** @defgroup TIM_LL_EC_TIM23_TI4_RMP TIM23 Timer Input Ch4 Remap
1227 * @{
1228 */
1229 #define LL_TIM_TIM23_TI4_RMP_GPIO 0x00000000U /* !< TIM23 input 4 is connected to GPIO */
1230 #define LL_TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23 input 4 is connected to COMP1 OUT */
1231 #define LL_TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23 input 4 is connected to COMP2 OUT */
1232 #define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
1233 /**
1234 * @}
1235 */
1236
1237 /** @defgroup TIM_LL_EC_TIM24_TI1_RMP TIM24 Timer Input Ch1 Remap
1238 * @{
1239 */
1240 #define LL_TIM_TIM24_TI1_RMP_GPIO 0x00000000U /* !< TIM24 input 1 is connected to GPIO */
1241 #define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24 input 1 is connected to CAN TMP */
1242 #define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24 input 1 is connected to CAN RTP */
1243 #define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */
1244
1245 #if defined(TIM_BREAK_INPUT_SUPPORT)
1246 /** Legacy definitions for compatibility purpose
1247 @cond 0
1248 */
1249 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1250 /**
1251 @endcond
1252 */
1253 #endif /* TIM_BREAK_INPUT_SUPPORT */
1254 /**
1255 * @}
1256 */
1257
1258 /* Exported macro ------------------------------------------------------------*/
1259 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1260 * @{
1261 */
1262
1263 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1264 * @{
1265 */
1266 /**
1267 * @brief Write a value in TIM register.
1268 * @param __INSTANCE__ TIM Instance
1269 * @param __REG__ Register to be written
1270 * @param __VALUE__ Value to be written in the register
1271 * @retval None
1272 */
1273 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1274
1275 /**
1276 * @brief Read a value in TIM register.
1277 * @param __INSTANCE__ TIM Instance
1278 * @param __REG__ Register to be read
1279 * @retval Register value
1280 */
1281 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1282 /**
1283 * @}
1284 */
1285
1286 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1287 * @{
1288 */
1289
1290 /**
1291 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1292 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1293 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1294 * to TIMx_CNT register bit 31)
1295 * @param __CNT__ Counter value
1296 * @retval UIF status bit
1297 */
1298 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1299 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1300
1301 /**
1302 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1303 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1304 * @param __TIMCLK__ timer input clock frequency (in Hz)
1305 * @param __CKD__ This parameter can be one of the following values:
1306 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1307 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1308 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1309 * @param __DT__ deadtime duration (in ns)
1310 * @retval DTG[0:7]
1311 */
1312 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1313 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1314 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1315 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1316 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1317 0U)
1318
1319 /**
1320 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1321 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1322 * @param __TIMCLK__ timer input clock frequency (in Hz)
1323 * @param __CNTCLK__ counter clock frequency (in Hz)
1324 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1325 */
1326 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1327 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
1328
1329 /**
1330 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1331 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1332 * @param __TIMCLK__ timer input clock frequency (in Hz)
1333 * @param __PSC__ prescaler
1334 * @param __FREQ__ output signal frequency (in Hz)
1335 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1336 */
1337 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1338 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1339
1340 /**
1341 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
1342 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1343 * @param __TIMCLK__ timer input clock frequency (in Hz)
1344 * @param __PSC__ prescaler
1345 * @param __DELAY__ timer output compare active/inactive delay (in us)
1346 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1347 */
1348 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1349 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1350 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1351
1352 /**
1353 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
1354 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1355 * @param __TIMCLK__ timer input clock frequency (in Hz)
1356 * @param __PSC__ prescaler
1357 * @param __DELAY__ timer output compare active/inactive delay (in us)
1358 * @param __PULSE__ pulse duration (in us)
1359 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1360 */
1361 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1362 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1363 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1364
1365 /**
1366 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1367 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1368 * @param __ICPSC__ This parameter can be one of the following values:
1369 * @arg @ref LL_TIM_ICPSC_DIV1
1370 * @arg @ref LL_TIM_ICPSC_DIV2
1371 * @arg @ref LL_TIM_ICPSC_DIV4
1372 * @arg @ref LL_TIM_ICPSC_DIV8
1373 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1374 */
1375 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1376 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1377
1378
1379 /**
1380 * @}
1381 */
1382
1383
1384 /**
1385 * @}
1386 */
1387
1388 /* Exported functions --------------------------------------------------------*/
1389 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1390 * @{
1391 */
1392
1393 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1394 * @{
1395 */
1396 /**
1397 * @brief Enable timer counter.
1398 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1399 * @param TIMx Timer instance
1400 * @retval None
1401 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1402 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1403 {
1404 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1405 }
1406
1407 /**
1408 * @brief Disable timer counter.
1409 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1410 * @param TIMx Timer instance
1411 * @retval None
1412 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1413 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1414 {
1415 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1416 }
1417
1418 /**
1419 * @brief Indicates whether the timer counter is enabled.
1420 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1421 * @param TIMx Timer instance
1422 * @retval State of bit (1 or 0).
1423 */
LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)1424 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1425 {
1426 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1427 }
1428
1429 /**
1430 * @brief Enable update event generation.
1431 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1432 * @param TIMx Timer instance
1433 * @retval None
1434 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1435 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1436 {
1437 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1438 }
1439
1440 /**
1441 * @brief Disable update event generation.
1442 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1443 * @param TIMx Timer instance
1444 * @retval None
1445 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1446 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1447 {
1448 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1449 }
1450
1451 /**
1452 * @brief Indicates whether update event generation is enabled.
1453 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1454 * @param TIMx Timer instance
1455 * @retval Inverted state of bit (0 or 1).
1456 */
LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)1457 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1458 {
1459 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1460 }
1461
1462 /**
1463 * @brief Set update event source
1464 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1465 * generate an update interrupt or DMA request if enabled:
1466 * - Counter overflow/underflow
1467 * - Setting the UG bit
1468 * - Update generation through the slave mode controller
1469 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1470 * overflow/underflow generates an update interrupt or DMA request if enabled.
1471 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1472 * @param TIMx Timer instance
1473 * @param UpdateSource This parameter can be one of the following values:
1474 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1475 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1476 * @retval None
1477 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1478 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1479 {
1480 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1481 }
1482
1483 /**
1484 * @brief Get actual event update source
1485 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1486 * @param TIMx Timer instance
1487 * @retval Returned value can be one of the following values:
1488 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1489 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1490 */
LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)1491 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1492 {
1493 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1494 }
1495
1496 /**
1497 * @brief Set one pulse mode (one shot v.s. repetitive).
1498 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1499 * @param TIMx Timer instance
1500 * @param OnePulseMode This parameter can be one of the following values:
1501 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1502 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1503 * @retval None
1504 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1505 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1506 {
1507 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1508 }
1509
1510 /**
1511 * @brief Get actual one pulse mode.
1512 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1513 * @param TIMx Timer instance
1514 * @retval Returned value can be one of the following values:
1515 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1516 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1517 */
LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)1518 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1519 {
1520 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1521 }
1522
1523 /**
1524 * @brief Set the timer counter counting mode.
1525 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1526 * check whether or not the counter mode selection feature is supported
1527 * by a timer instance.
1528 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1529 * requires a timer reset to avoid unexpected direction
1530 * due to DIR bit readonly in center aligned mode.
1531 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1532 * CR1 CMS LL_TIM_SetCounterMode
1533 * @param TIMx Timer instance
1534 * @param CounterMode This parameter can be one of the following values:
1535 * @arg @ref LL_TIM_COUNTERMODE_UP
1536 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1537 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1538 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1539 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1540 * @retval None
1541 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1542 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1543 {
1544 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1545 }
1546
1547 /**
1548 * @brief Get actual counter mode.
1549 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1550 * check whether or not the counter mode selection feature is supported
1551 * by a timer instance.
1552 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1553 * CR1 CMS LL_TIM_GetCounterMode
1554 * @param TIMx Timer instance
1555 * @retval Returned value can be one of the following values:
1556 * @arg @ref LL_TIM_COUNTERMODE_UP
1557 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1558 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1559 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1560 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1561 */
LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)1562 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1563 {
1564 uint32_t counter_mode;
1565
1566 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1567
1568 if (counter_mode == 0U)
1569 {
1570 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1571 }
1572
1573 return counter_mode;
1574 }
1575
1576 /**
1577 * @brief Enable auto-reload (ARR) preload.
1578 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1579 * @param TIMx Timer instance
1580 * @retval None
1581 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1582 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1583 {
1584 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1585 }
1586
1587 /**
1588 * @brief Disable auto-reload (ARR) preload.
1589 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1590 * @param TIMx Timer instance
1591 * @retval None
1592 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1593 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1594 {
1595 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1596 }
1597
1598 /**
1599 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1600 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1601 * @param TIMx Timer instance
1602 * @retval State of bit (1 or 0).
1603 */
LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)1604 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1605 {
1606 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1607 }
1608
1609 /**
1610 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1611 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1612 * whether or not the clock division feature is supported by the timer
1613 * instance.
1614 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1615 * @param TIMx Timer instance
1616 * @param ClockDivision This parameter can be one of the following values:
1617 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1618 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1619 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1620 * @retval None
1621 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1622 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1623 {
1624 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1625 }
1626
1627 /**
1628 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1629 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1630 * whether or not the clock division feature is supported by the timer
1631 * instance.
1632 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1633 * @param TIMx Timer instance
1634 * @retval Returned value can be one of the following values:
1635 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1636 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1637 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1638 */
LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)1639 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1640 {
1641 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1642 }
1643
1644 /**
1645 * @brief Set the counter value.
1646 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1647 * whether or not a timer instance supports a 32 bits counter.
1648 * @rmtoll CNT CNT LL_TIM_SetCounter
1649 * @param TIMx Timer instance
1650 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1651 * @retval None
1652 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1653 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1654 {
1655 WRITE_REG(TIMx->CNT, Counter);
1656 }
1657
1658 /**
1659 * @brief Get the counter value.
1660 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1661 * whether or not a timer instance supports a 32 bits counter.
1662 * @rmtoll CNT CNT LL_TIM_GetCounter
1663 * @param TIMx Timer instance
1664 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1665 */
LL_TIM_GetCounter(TIM_TypeDef * TIMx)1666 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1667 {
1668 return (uint32_t)(READ_REG(TIMx->CNT));
1669 }
1670
1671 /**
1672 * @brief Get the current direction of the counter
1673 * @rmtoll CR1 DIR LL_TIM_GetDirection
1674 * @param TIMx Timer instance
1675 * @retval Returned value can be one of the following values:
1676 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1677 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1678 */
LL_TIM_GetDirection(TIM_TypeDef * TIMx)1679 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1680 {
1681 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1682 }
1683
1684 /**
1685 * @brief Set the prescaler value.
1686 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1687 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1688 * prescaler ratio is taken into account at the next update event.
1689 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1690 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1691 * @param TIMx Timer instance
1692 * @param Prescaler between Min_Data=0 and Max_Data=65535
1693 * @retval None
1694 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1695 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1696 {
1697 WRITE_REG(TIMx->PSC, Prescaler);
1698 }
1699
1700 /**
1701 * @brief Get the prescaler value.
1702 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1703 * @param TIMx Timer instance
1704 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1705 */
LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)1706 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1707 {
1708 return (uint32_t)(READ_REG(TIMx->PSC));
1709 }
1710
1711 /**
1712 * @brief Set the auto-reload value.
1713 * @note The counter is blocked while the auto-reload value is null.
1714 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1715 * whether or not a timer instance supports a 32 bits counter.
1716 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1717 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1718 * @param TIMx Timer instance
1719 * @param AutoReload between Min_Data=0 and Max_Data=65535
1720 * @retval None
1721 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1722 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1723 {
1724 WRITE_REG(TIMx->ARR, AutoReload);
1725 }
1726
1727 /**
1728 * @brief Get the auto-reload value.
1729 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1730 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1731 * whether or not a timer instance supports a 32 bits counter.
1732 * @param TIMx Timer instance
1733 * @retval Auto-reload value
1734 */
LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)1735 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1736 {
1737 return (uint32_t)(READ_REG(TIMx->ARR));
1738 }
1739
1740 /**
1741 * @brief Set the repetition counter value.
1742 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1743 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1744 * whether or not a timer instance supports a repetition counter.
1745 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1746 * @param TIMx Timer instance
1747 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1748 * @retval None
1749 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1750 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1751 {
1752 WRITE_REG(TIMx->RCR, RepetitionCounter);
1753 }
1754
1755 /**
1756 * @brief Get the repetition counter value.
1757 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1758 * whether or not a timer instance supports a repetition counter.
1759 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1760 * @param TIMx Timer instance
1761 * @retval Repetition counter value
1762 */
LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx)1763 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1764 {
1765 return (uint32_t)(READ_REG(TIMx->RCR));
1766 }
1767
1768 /**
1769 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1770 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
1771 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1772 * @param TIMx Timer instance
1773 * @retval None
1774 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1775 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1776 {
1777 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1778 }
1779
1780 /**
1781 * @brief Disable update interrupt flag (UIF) remapping.
1782 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1783 * @param TIMx Timer instance
1784 * @retval None
1785 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1786 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1787 {
1788 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1789 }
1790
1791 /**
1792 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1793 * @param Counter Counter value
1794 * @retval State of bit (1 or 0).
1795 */
LL_TIM_IsActiveUIFCPY(uint32_t Counter)1796 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
1797 {
1798 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1799 }
1800
1801 /**
1802 * @}
1803 */
1804
1805 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1806 * @{
1807 */
1808 /**
1809 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1810 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1811 * they are updated only when a commutation event (COM) occurs.
1812 * @note Only on channels that have a complementary output.
1813 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1814 * whether or not a timer instance is able to generate a commutation event.
1815 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1816 * @param TIMx Timer instance
1817 * @retval None
1818 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1819 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1820 {
1821 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1822 }
1823
1824 /**
1825 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1826 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1827 * whether or not a timer instance is able to generate a commutation event.
1828 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1829 * @param TIMx Timer instance
1830 * @retval None
1831 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1832 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1833 {
1834 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1835 }
1836
1837 /**
1838 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1839 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1840 * whether or not a timer instance is able to generate a commutation event.
1841 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1842 * @param TIMx Timer instance
1843 * @param CCUpdateSource This parameter can be one of the following values:
1844 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1845 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1846 * @retval None
1847 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1848 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1849 {
1850 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1851 }
1852
1853 /**
1854 * @brief Set the trigger of the capture/compare DMA request.
1855 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1856 * @param TIMx Timer instance
1857 * @param DMAReqTrigger This parameter can be one of the following values:
1858 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1859 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1860 * @retval None
1861 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1862 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1863 {
1864 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1865 }
1866
1867 /**
1868 * @brief Get actual trigger of the capture/compare DMA request.
1869 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1870 * @param TIMx Timer instance
1871 * @retval Returned value can be one of the following values:
1872 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1873 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1874 */
LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx)1875 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1876 {
1877 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1878 }
1879
1880 /**
1881 * @brief Set the lock level to freeze the
1882 * configuration of several capture/compare parameters.
1883 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1884 * the lock mechanism is supported by a timer instance.
1885 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1886 * @param TIMx Timer instance
1887 * @param LockLevel This parameter can be one of the following values:
1888 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1889 * @arg @ref LL_TIM_LOCKLEVEL_1
1890 * @arg @ref LL_TIM_LOCKLEVEL_2
1891 * @arg @ref LL_TIM_LOCKLEVEL_3
1892 * @retval None
1893 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1894 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1895 {
1896 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1897 }
1898
1899 /**
1900 * @brief Enable capture/compare channels.
1901 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1902 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1903 * CCER CC2E LL_TIM_CC_EnableChannel\n
1904 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1905 * CCER CC3E LL_TIM_CC_EnableChannel\n
1906 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1907 * CCER CC4E LL_TIM_CC_EnableChannel\n
1908 * CCER CC5E LL_TIM_CC_EnableChannel\n
1909 * CCER CC6E LL_TIM_CC_EnableChannel
1910 * @param TIMx Timer instance
1911 * @param Channels This parameter can be a combination of the following values:
1912 * @arg @ref LL_TIM_CHANNEL_CH1
1913 * @arg @ref LL_TIM_CHANNEL_CH1N
1914 * @arg @ref LL_TIM_CHANNEL_CH2
1915 * @arg @ref LL_TIM_CHANNEL_CH2N
1916 * @arg @ref LL_TIM_CHANNEL_CH3
1917 * @arg @ref LL_TIM_CHANNEL_CH3N
1918 * @arg @ref LL_TIM_CHANNEL_CH4
1919 * @arg @ref LL_TIM_CHANNEL_CH5
1920 * @arg @ref LL_TIM_CHANNEL_CH6
1921 * @retval None
1922 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1923 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1924 {
1925 SET_BIT(TIMx->CCER, Channels);
1926 }
1927
1928 /**
1929 * @brief Disable capture/compare channels.
1930 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1931 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1932 * CCER CC2E LL_TIM_CC_DisableChannel\n
1933 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1934 * CCER CC3E LL_TIM_CC_DisableChannel\n
1935 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1936 * CCER CC4E LL_TIM_CC_DisableChannel\n
1937 * CCER CC5E LL_TIM_CC_DisableChannel\n
1938 * CCER CC6E LL_TIM_CC_DisableChannel
1939 * @param TIMx Timer instance
1940 * @param Channels This parameter can be a combination of the following values:
1941 * @arg @ref LL_TIM_CHANNEL_CH1
1942 * @arg @ref LL_TIM_CHANNEL_CH1N
1943 * @arg @ref LL_TIM_CHANNEL_CH2
1944 * @arg @ref LL_TIM_CHANNEL_CH2N
1945 * @arg @ref LL_TIM_CHANNEL_CH3
1946 * @arg @ref LL_TIM_CHANNEL_CH3N
1947 * @arg @ref LL_TIM_CHANNEL_CH4
1948 * @arg @ref LL_TIM_CHANNEL_CH5
1949 * @arg @ref LL_TIM_CHANNEL_CH6
1950 * @retval None
1951 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1952 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1953 {
1954 CLEAR_BIT(TIMx->CCER, Channels);
1955 }
1956
1957 /**
1958 * @brief Indicate whether channel(s) is(are) enabled.
1959 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1960 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1961 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1962 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1963 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1964 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1965 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1966 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1967 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1968 * @param TIMx Timer instance
1969 * @param Channels This parameter can be a combination of the following values:
1970 * @arg @ref LL_TIM_CHANNEL_CH1
1971 * @arg @ref LL_TIM_CHANNEL_CH1N
1972 * @arg @ref LL_TIM_CHANNEL_CH2
1973 * @arg @ref LL_TIM_CHANNEL_CH2N
1974 * @arg @ref LL_TIM_CHANNEL_CH3
1975 * @arg @ref LL_TIM_CHANNEL_CH3N
1976 * @arg @ref LL_TIM_CHANNEL_CH4
1977 * @arg @ref LL_TIM_CHANNEL_CH5
1978 * @arg @ref LL_TIM_CHANNEL_CH6
1979 * @retval State of bit (1 or 0).
1980 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)1981 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1982 {
1983 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1984 }
1985
1986 /**
1987 * @}
1988 */
1989
1990 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1991 * @{
1992 */
1993 /**
1994 * @brief Configure an output channel.
1995 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1996 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1997 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1998 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1999 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2000 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2001 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2002 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2003 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2004 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2005 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2006 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2007 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2008 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2009 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2010 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2011 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2012 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2013 * @param TIMx Timer instance
2014 * @param Channel This parameter can be one of the following values:
2015 * @arg @ref LL_TIM_CHANNEL_CH1
2016 * @arg @ref LL_TIM_CHANNEL_CH2
2017 * @arg @ref LL_TIM_CHANNEL_CH3
2018 * @arg @ref LL_TIM_CHANNEL_CH4
2019 * @arg @ref LL_TIM_CHANNEL_CH5
2020 * @arg @ref LL_TIM_CHANNEL_CH6
2021 * @param Configuration This parameter must be a combination of all the following values:
2022 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2023 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2024 * @retval None
2025 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2026 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2027 {
2028 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2029 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2030 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2031 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2032 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2033 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2034 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2035 }
2036
2037 /**
2038 * @brief Define the behavior of the output reference signal OCxREF from which
2039 * OCx and OCxN (when relevant) are derived.
2040 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2041 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2042 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2043 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2044 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2045 * CCMR3 OC6M LL_TIM_OC_SetMode
2046 * @param TIMx Timer instance
2047 * @param Channel This parameter can be one of the following values:
2048 * @arg @ref LL_TIM_CHANNEL_CH1
2049 * @arg @ref LL_TIM_CHANNEL_CH2
2050 * @arg @ref LL_TIM_CHANNEL_CH3
2051 * @arg @ref LL_TIM_CHANNEL_CH4
2052 * @arg @ref LL_TIM_CHANNEL_CH5
2053 * @arg @ref LL_TIM_CHANNEL_CH6
2054 * @param Mode This parameter can be one of the following values:
2055 * @arg @ref LL_TIM_OCMODE_FROZEN
2056 * @arg @ref LL_TIM_OCMODE_ACTIVE
2057 * @arg @ref LL_TIM_OCMODE_INACTIVE
2058 * @arg @ref LL_TIM_OCMODE_TOGGLE
2059 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2060 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2061 * @arg @ref LL_TIM_OCMODE_PWM1
2062 * @arg @ref LL_TIM_OCMODE_PWM2
2063 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2064 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2065 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2066 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2067 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2068 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2069 * @retval None
2070 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2071 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2072 {
2073 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2074 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2075 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2076 }
2077
2078 /**
2079 * @brief Get the output compare mode of an output channel.
2080 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2081 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2082 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2083 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2084 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2085 * CCMR3 OC6M LL_TIM_OC_GetMode
2086 * @param TIMx Timer instance
2087 * @param Channel This parameter can be one of the following values:
2088 * @arg @ref LL_TIM_CHANNEL_CH1
2089 * @arg @ref LL_TIM_CHANNEL_CH2
2090 * @arg @ref LL_TIM_CHANNEL_CH3
2091 * @arg @ref LL_TIM_CHANNEL_CH4
2092 * @arg @ref LL_TIM_CHANNEL_CH5
2093 * @arg @ref LL_TIM_CHANNEL_CH6
2094 * @retval Returned value can be one of the following values:
2095 * @arg @ref LL_TIM_OCMODE_FROZEN
2096 * @arg @ref LL_TIM_OCMODE_ACTIVE
2097 * @arg @ref LL_TIM_OCMODE_INACTIVE
2098 * @arg @ref LL_TIM_OCMODE_TOGGLE
2099 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2100 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2101 * @arg @ref LL_TIM_OCMODE_PWM1
2102 * @arg @ref LL_TIM_OCMODE_PWM2
2103 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2104 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2105 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2106 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2107 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2108 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2109 */
LL_TIM_OC_GetMode(TIM_TypeDef * TIMx,uint32_t Channel)2110 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
2111 {
2112 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2113 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2114 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2115 }
2116
2117 /**
2118 * @brief Set the polarity of an output channel.
2119 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2120 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2121 * CCER CC2P LL_TIM_OC_SetPolarity\n
2122 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2123 * CCER CC3P LL_TIM_OC_SetPolarity\n
2124 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2125 * CCER CC4P LL_TIM_OC_SetPolarity\n
2126 * CCER CC5P LL_TIM_OC_SetPolarity\n
2127 * CCER CC6P LL_TIM_OC_SetPolarity
2128 * @param TIMx Timer instance
2129 * @param Channel This parameter can be one of the following values:
2130 * @arg @ref LL_TIM_CHANNEL_CH1
2131 * @arg @ref LL_TIM_CHANNEL_CH1N
2132 * @arg @ref LL_TIM_CHANNEL_CH2
2133 * @arg @ref LL_TIM_CHANNEL_CH2N
2134 * @arg @ref LL_TIM_CHANNEL_CH3
2135 * @arg @ref LL_TIM_CHANNEL_CH3N
2136 * @arg @ref LL_TIM_CHANNEL_CH4
2137 * @arg @ref LL_TIM_CHANNEL_CH5
2138 * @arg @ref LL_TIM_CHANNEL_CH6
2139 * @param Polarity This parameter can be one of the following values:
2140 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2141 * @arg @ref LL_TIM_OCPOLARITY_LOW
2142 * @retval None
2143 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2144 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2145 {
2146 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2147 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2148 }
2149
2150 /**
2151 * @brief Get the polarity of an output channel.
2152 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2153 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2154 * CCER CC2P LL_TIM_OC_GetPolarity\n
2155 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2156 * CCER CC3P LL_TIM_OC_GetPolarity\n
2157 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2158 * CCER CC4P LL_TIM_OC_GetPolarity\n
2159 * CCER CC5P LL_TIM_OC_GetPolarity\n
2160 * CCER CC6P LL_TIM_OC_GetPolarity
2161 * @param TIMx Timer instance
2162 * @param Channel This parameter can be one of the following values:
2163 * @arg @ref LL_TIM_CHANNEL_CH1
2164 * @arg @ref LL_TIM_CHANNEL_CH1N
2165 * @arg @ref LL_TIM_CHANNEL_CH2
2166 * @arg @ref LL_TIM_CHANNEL_CH2N
2167 * @arg @ref LL_TIM_CHANNEL_CH3
2168 * @arg @ref LL_TIM_CHANNEL_CH3N
2169 * @arg @ref LL_TIM_CHANNEL_CH4
2170 * @arg @ref LL_TIM_CHANNEL_CH5
2171 * @arg @ref LL_TIM_CHANNEL_CH6
2172 * @retval Returned value can be one of the following values:
2173 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2174 * @arg @ref LL_TIM_OCPOLARITY_LOW
2175 */
LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)2176 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2177 {
2178 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2179 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2180 }
2181
2182 /**
2183 * @brief Set the IDLE state of an output channel
2184 * @note This function is significant only for the timer instances
2185 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2186 * can be used to check whether or not a timer instance provides
2187 * a break input.
2188 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2189 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2190 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2191 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2192 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2193 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2194 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2195 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2196 * CR2 OIS6 LL_TIM_OC_SetIdleState
2197 * @param TIMx Timer instance
2198 * @param Channel This parameter can be one of the following values:
2199 * @arg @ref LL_TIM_CHANNEL_CH1
2200 * @arg @ref LL_TIM_CHANNEL_CH1N
2201 * @arg @ref LL_TIM_CHANNEL_CH2
2202 * @arg @ref LL_TIM_CHANNEL_CH2N
2203 * @arg @ref LL_TIM_CHANNEL_CH3
2204 * @arg @ref LL_TIM_CHANNEL_CH3N
2205 * @arg @ref LL_TIM_CHANNEL_CH4
2206 * @arg @ref LL_TIM_CHANNEL_CH5
2207 * @arg @ref LL_TIM_CHANNEL_CH6
2208 * @param IdleState This parameter can be one of the following values:
2209 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2210 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2211 * @retval None
2212 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2213 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2214 {
2215 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2216 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2217 }
2218
2219 /**
2220 * @brief Get the IDLE state of an output channel
2221 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2222 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2223 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2224 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2225 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2226 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2227 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2228 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2229 * CR2 OIS6 LL_TIM_OC_GetIdleState
2230 * @param TIMx Timer instance
2231 * @param Channel This parameter can be one of the following values:
2232 * @arg @ref LL_TIM_CHANNEL_CH1
2233 * @arg @ref LL_TIM_CHANNEL_CH1N
2234 * @arg @ref LL_TIM_CHANNEL_CH2
2235 * @arg @ref LL_TIM_CHANNEL_CH2N
2236 * @arg @ref LL_TIM_CHANNEL_CH3
2237 * @arg @ref LL_TIM_CHANNEL_CH3N
2238 * @arg @ref LL_TIM_CHANNEL_CH4
2239 * @arg @ref LL_TIM_CHANNEL_CH5
2240 * @arg @ref LL_TIM_CHANNEL_CH6
2241 * @retval Returned value can be one of the following values:
2242 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2243 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2244 */
LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx,uint32_t Channel)2245 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
2246 {
2247 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2248 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2249 }
2250
2251 /**
2252 * @brief Enable fast mode for the output channel.
2253 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2254 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2255 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2256 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2257 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2258 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2259 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2260 * @param TIMx Timer instance
2261 * @param Channel This parameter can be one of the following values:
2262 * @arg @ref LL_TIM_CHANNEL_CH1
2263 * @arg @ref LL_TIM_CHANNEL_CH2
2264 * @arg @ref LL_TIM_CHANNEL_CH3
2265 * @arg @ref LL_TIM_CHANNEL_CH4
2266 * @arg @ref LL_TIM_CHANNEL_CH5
2267 * @arg @ref LL_TIM_CHANNEL_CH6
2268 * @retval None
2269 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2270 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2271 {
2272 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2273 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2274 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2275
2276 }
2277
2278 /**
2279 * @brief Disable fast mode for the output channel.
2280 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2281 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2282 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2283 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2284 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2285 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2286 * @param TIMx Timer instance
2287 * @param Channel This parameter can be one of the following values:
2288 * @arg @ref LL_TIM_CHANNEL_CH1
2289 * @arg @ref LL_TIM_CHANNEL_CH2
2290 * @arg @ref LL_TIM_CHANNEL_CH3
2291 * @arg @ref LL_TIM_CHANNEL_CH4
2292 * @arg @ref LL_TIM_CHANNEL_CH5
2293 * @arg @ref LL_TIM_CHANNEL_CH6
2294 * @retval None
2295 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2296 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2297 {
2298 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2299 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2300 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2301
2302 }
2303
2304 /**
2305 * @brief Indicates whether fast mode is enabled for the output channel.
2306 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2307 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2308 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2309 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2310 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2311 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2312 * @param TIMx Timer instance
2313 * @param Channel This parameter can be one of the following values:
2314 * @arg @ref LL_TIM_CHANNEL_CH1
2315 * @arg @ref LL_TIM_CHANNEL_CH2
2316 * @arg @ref LL_TIM_CHANNEL_CH3
2317 * @arg @ref LL_TIM_CHANNEL_CH4
2318 * @arg @ref LL_TIM_CHANNEL_CH5
2319 * @arg @ref LL_TIM_CHANNEL_CH6
2320 * @retval State of bit (1 or 0).
2321 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)2322 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2323 {
2324 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2325 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2326 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2327 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2328 }
2329
2330 /**
2331 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2332 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2333 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2334 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2335 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2336 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2337 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2338 * @param TIMx Timer instance
2339 * @param Channel This parameter can be one of the following values:
2340 * @arg @ref LL_TIM_CHANNEL_CH1
2341 * @arg @ref LL_TIM_CHANNEL_CH2
2342 * @arg @ref LL_TIM_CHANNEL_CH3
2343 * @arg @ref LL_TIM_CHANNEL_CH4
2344 * @arg @ref LL_TIM_CHANNEL_CH5
2345 * @arg @ref LL_TIM_CHANNEL_CH6
2346 * @retval None
2347 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2348 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2349 {
2350 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2351 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2352 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2353 }
2354
2355 /**
2356 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2357 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2358 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2359 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2360 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2361 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2362 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2363 * @param TIMx Timer instance
2364 * @param Channel This parameter can be one of the following values:
2365 * @arg @ref LL_TIM_CHANNEL_CH1
2366 * @arg @ref LL_TIM_CHANNEL_CH2
2367 * @arg @ref LL_TIM_CHANNEL_CH3
2368 * @arg @ref LL_TIM_CHANNEL_CH4
2369 * @arg @ref LL_TIM_CHANNEL_CH5
2370 * @arg @ref LL_TIM_CHANNEL_CH6
2371 * @retval None
2372 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2373 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2374 {
2375 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2376 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2377 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2378 }
2379
2380 /**
2381 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2382 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2383 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2384 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2385 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2386 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2387 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2388 * @param TIMx Timer instance
2389 * @param Channel This parameter can be one of the following values:
2390 * @arg @ref LL_TIM_CHANNEL_CH1
2391 * @arg @ref LL_TIM_CHANNEL_CH2
2392 * @arg @ref LL_TIM_CHANNEL_CH3
2393 * @arg @ref LL_TIM_CHANNEL_CH4
2394 * @arg @ref LL_TIM_CHANNEL_CH5
2395 * @arg @ref LL_TIM_CHANNEL_CH6
2396 * @retval State of bit (1 or 0).
2397 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)2398 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2399 {
2400 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2401 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2402 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2403 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2404 }
2405
2406 /**
2407 * @brief Enable clearing the output channel on an external event.
2408 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2409 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2410 * or not a timer instance can clear the OCxREF signal on an external event.
2411 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2412 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2413 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2414 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2415 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2416 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2417 * @param TIMx Timer instance
2418 * @param Channel This parameter can be one of the following values:
2419 * @arg @ref LL_TIM_CHANNEL_CH1
2420 * @arg @ref LL_TIM_CHANNEL_CH2
2421 * @arg @ref LL_TIM_CHANNEL_CH3
2422 * @arg @ref LL_TIM_CHANNEL_CH4
2423 * @arg @ref LL_TIM_CHANNEL_CH5
2424 * @arg @ref LL_TIM_CHANNEL_CH6
2425 * @retval None
2426 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2427 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2428 {
2429 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2430 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2431 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2432 }
2433
2434 /**
2435 * @brief Disable clearing the output channel on an external event.
2436 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2437 * or not a timer instance can clear the OCxREF signal on an external event.
2438 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2439 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2440 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2441 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2442 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2443 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2444 * @param TIMx Timer instance
2445 * @param Channel This parameter can be one of the following values:
2446 * @arg @ref LL_TIM_CHANNEL_CH1
2447 * @arg @ref LL_TIM_CHANNEL_CH2
2448 * @arg @ref LL_TIM_CHANNEL_CH3
2449 * @arg @ref LL_TIM_CHANNEL_CH4
2450 * @arg @ref LL_TIM_CHANNEL_CH5
2451 * @arg @ref LL_TIM_CHANNEL_CH6
2452 * @retval None
2453 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2454 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2455 {
2456 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2457 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2458 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2459 }
2460
2461 /**
2462 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2463 * @note This function enables clearing the output channel on an external event.
2464 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2465 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2466 * or not a timer instance can clear the OCxREF signal on an external event.
2467 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2468 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2469 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2470 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2471 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2472 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2473 * @param TIMx Timer instance
2474 * @param Channel This parameter can be one of the following values:
2475 * @arg @ref LL_TIM_CHANNEL_CH1
2476 * @arg @ref LL_TIM_CHANNEL_CH2
2477 * @arg @ref LL_TIM_CHANNEL_CH3
2478 * @arg @ref LL_TIM_CHANNEL_CH4
2479 * @arg @ref LL_TIM_CHANNEL_CH5
2480 * @arg @ref LL_TIM_CHANNEL_CH6
2481 * @retval State of bit (1 or 0).
2482 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)2483 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2484 {
2485 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2486 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2487 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2488 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2489 }
2490
2491 /**
2492 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
2493 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2494 * dead-time insertion feature is supported by a timer instance.
2495 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2496 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2497 * @param TIMx Timer instance
2498 * @param DeadTime between Min_Data=0 and Max_Data=255
2499 * @retval None
2500 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2501 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2502 {
2503 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2504 }
2505
2506 /**
2507 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2508 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2509 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2510 * whether or not a timer instance supports a 32 bits counter.
2511 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2512 * output channel 1 is supported by a timer instance.
2513 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2514 * @param TIMx Timer instance
2515 * @param CompareValue between Min_Data=0 and Max_Data=65535
2516 * @retval None
2517 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2518 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2519 {
2520 WRITE_REG(TIMx->CCR1, CompareValue);
2521 }
2522
2523 /**
2524 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2525 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2526 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2527 * whether or not a timer instance supports a 32 bits counter.
2528 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2529 * output channel 2 is supported by a timer instance.
2530 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2531 * @param TIMx Timer instance
2532 * @param CompareValue between Min_Data=0 and Max_Data=65535
2533 * @retval None
2534 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2535 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2536 {
2537 WRITE_REG(TIMx->CCR2, CompareValue);
2538 }
2539
2540 /**
2541 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2542 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2543 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2544 * whether or not a timer instance supports a 32 bits counter.
2545 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2546 * output channel is supported by a timer instance.
2547 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2548 * @param TIMx Timer instance
2549 * @param CompareValue between Min_Data=0 and Max_Data=65535
2550 * @retval None
2551 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2552 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2553 {
2554 WRITE_REG(TIMx->CCR3, CompareValue);
2555 }
2556
2557 /**
2558 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2559 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2560 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2561 * whether or not a timer instance supports a 32 bits counter.
2562 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2563 * output channel 4 is supported by a timer instance.
2564 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2565 * @param TIMx Timer instance
2566 * @param CompareValue between Min_Data=0 and Max_Data=65535
2567 * @retval None
2568 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2569 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2570 {
2571 WRITE_REG(TIMx->CCR4, CompareValue);
2572 }
2573
2574 /**
2575 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2576 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2577 * output channel 5 is supported by a timer instance.
2578 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2579 * @param TIMx Timer instance
2580 * @param CompareValue between Min_Data=0 and Max_Data=65535
2581 * @retval None
2582 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2583 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2584 {
2585 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2586 }
2587
2588 /**
2589 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2590 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2591 * output channel 6 is supported by a timer instance.
2592 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2593 * @param TIMx Timer instance
2594 * @param CompareValue between Min_Data=0 and Max_Data=65535
2595 * @retval None
2596 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2597 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2598 {
2599 WRITE_REG(TIMx->CCR6, CompareValue);
2600 }
2601
2602 /**
2603 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2604 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2605 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2606 * whether or not a timer instance supports a 32 bits counter.
2607 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2608 * output channel 1 is supported by a timer instance.
2609 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2610 * @param TIMx Timer instance
2611 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2612 */
LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)2613 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2614 {
2615 return (uint32_t)(READ_REG(TIMx->CCR1));
2616 }
2617
2618 /**
2619 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2620 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2621 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2622 * whether or not a timer instance supports a 32 bits counter.
2623 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2624 * output channel 2 is supported by a timer instance.
2625 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2626 * @param TIMx Timer instance
2627 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2628 */
LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)2629 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2630 {
2631 return (uint32_t)(READ_REG(TIMx->CCR2));
2632 }
2633
2634 /**
2635 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2636 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2637 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2638 * whether or not a timer instance supports a 32 bits counter.
2639 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2640 * output channel 3 is supported by a timer instance.
2641 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2642 * @param TIMx Timer instance
2643 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2644 */
LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)2645 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2646 {
2647 return (uint32_t)(READ_REG(TIMx->CCR3));
2648 }
2649
2650 /**
2651 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2652 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2653 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2654 * whether or not a timer instance supports a 32 bits counter.
2655 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2656 * output channel 4 is supported by a timer instance.
2657 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2658 * @param TIMx Timer instance
2659 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2660 */
LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)2661 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2662 {
2663 return (uint32_t)(READ_REG(TIMx->CCR4));
2664 }
2665
2666 /**
2667 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2668 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2669 * output channel 5 is supported by a timer instance.
2670 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2671 * @param TIMx Timer instance
2672 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2673 */
LL_TIM_OC_GetCompareCH5(TIM_TypeDef * TIMx)2674 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
2675 {
2676 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2677 }
2678
2679 /**
2680 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2681 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2682 * output channel 6 is supported by a timer instance.
2683 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2684 * @param TIMx Timer instance
2685 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2686 */
LL_TIM_OC_GetCompareCH6(TIM_TypeDef * TIMx)2687 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
2688 {
2689 return (uint32_t)(READ_REG(TIMx->CCR6));
2690 }
2691
2692 /**
2693 * @brief Select on which reference signal the OC5REF is combined to.
2694 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2695 * whether or not a timer instance supports the combined 3-phase PWM mode.
2696 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2697 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2698 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2699 * @param TIMx Timer instance
2700 * @param GroupCH5 This parameter can be a combination of the following values:
2701 * @arg @ref LL_TIM_GROUPCH5_NONE
2702 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2703 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2704 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2705 * @retval None
2706 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2707 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2708 {
2709 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2710 }
2711
2712 /**
2713 * @}
2714 */
2715
2716 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2717 * @{
2718 */
2719 /**
2720 * @brief Configure input channel.
2721 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2722 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2723 * CCMR1 IC1F LL_TIM_IC_Config\n
2724 * CCMR1 CC2S LL_TIM_IC_Config\n
2725 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2726 * CCMR1 IC2F LL_TIM_IC_Config\n
2727 * CCMR2 CC3S LL_TIM_IC_Config\n
2728 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2729 * CCMR2 IC3F LL_TIM_IC_Config\n
2730 * CCMR2 CC4S LL_TIM_IC_Config\n
2731 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2732 * CCMR2 IC4F LL_TIM_IC_Config\n
2733 * CCER CC1P LL_TIM_IC_Config\n
2734 * CCER CC1NP LL_TIM_IC_Config\n
2735 * CCER CC2P LL_TIM_IC_Config\n
2736 * CCER CC2NP LL_TIM_IC_Config\n
2737 * CCER CC3P LL_TIM_IC_Config\n
2738 * CCER CC3NP LL_TIM_IC_Config\n
2739 * CCER CC4P LL_TIM_IC_Config\n
2740 * CCER CC4NP LL_TIM_IC_Config
2741 * @param TIMx Timer instance
2742 * @param Channel This parameter can be one of the following values:
2743 * @arg @ref LL_TIM_CHANNEL_CH1
2744 * @arg @ref LL_TIM_CHANNEL_CH2
2745 * @arg @ref LL_TIM_CHANNEL_CH3
2746 * @arg @ref LL_TIM_CHANNEL_CH4
2747 * @param Configuration This parameter must be a combination of all the following values:
2748 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2749 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2750 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2751 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2752 * @retval None
2753 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2754 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2755 {
2756 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2757 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2758 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2759 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
2760 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2761 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2762 }
2763
2764 /**
2765 * @brief Set the active input.
2766 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2767 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2768 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2769 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2770 * @param TIMx Timer instance
2771 * @param Channel This parameter can be one of the following values:
2772 * @arg @ref LL_TIM_CHANNEL_CH1
2773 * @arg @ref LL_TIM_CHANNEL_CH2
2774 * @arg @ref LL_TIM_CHANNEL_CH3
2775 * @arg @ref LL_TIM_CHANNEL_CH4
2776 * @param ICActiveInput This parameter can be one of the following values:
2777 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2778 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2779 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2780 * @retval None
2781 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2782 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2783 {
2784 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2785 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2786 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2787 }
2788
2789 /**
2790 * @brief Get the current active input.
2791 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2792 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2793 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2794 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2795 * @param TIMx Timer instance
2796 * @param Channel This parameter can be one of the following values:
2797 * @arg @ref LL_TIM_CHANNEL_CH1
2798 * @arg @ref LL_TIM_CHANNEL_CH2
2799 * @arg @ref LL_TIM_CHANNEL_CH3
2800 * @arg @ref LL_TIM_CHANNEL_CH4
2801 * @retval Returned value can be one of the following values:
2802 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2803 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2804 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2805 */
LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel)2806 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2807 {
2808 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2809 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2810 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2811 }
2812
2813 /**
2814 * @brief Set the prescaler of input channel.
2815 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2816 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2817 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2818 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2819 * @param TIMx Timer instance
2820 * @param Channel This parameter can be one of the following values:
2821 * @arg @ref LL_TIM_CHANNEL_CH1
2822 * @arg @ref LL_TIM_CHANNEL_CH2
2823 * @arg @ref LL_TIM_CHANNEL_CH3
2824 * @arg @ref LL_TIM_CHANNEL_CH4
2825 * @param ICPrescaler This parameter can be one of the following values:
2826 * @arg @ref LL_TIM_ICPSC_DIV1
2827 * @arg @ref LL_TIM_ICPSC_DIV2
2828 * @arg @ref LL_TIM_ICPSC_DIV4
2829 * @arg @ref LL_TIM_ICPSC_DIV8
2830 * @retval None
2831 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2832 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2833 {
2834 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2835 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2836 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2837 }
2838
2839 /**
2840 * @brief Get the current prescaler value acting on an input channel.
2841 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2842 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2843 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2844 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2845 * @param TIMx Timer instance
2846 * @param Channel This parameter can be one of the following values:
2847 * @arg @ref LL_TIM_CHANNEL_CH1
2848 * @arg @ref LL_TIM_CHANNEL_CH2
2849 * @arg @ref LL_TIM_CHANNEL_CH3
2850 * @arg @ref LL_TIM_CHANNEL_CH4
2851 * @retval Returned value can be one of the following values:
2852 * @arg @ref LL_TIM_ICPSC_DIV1
2853 * @arg @ref LL_TIM_ICPSC_DIV2
2854 * @arg @ref LL_TIM_ICPSC_DIV4
2855 * @arg @ref LL_TIM_ICPSC_DIV8
2856 */
LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel)2857 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2858 {
2859 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2860 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2861 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2862 }
2863
2864 /**
2865 * @brief Set the input filter duration.
2866 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2867 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2868 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2869 * CCMR2 IC4F LL_TIM_IC_SetFilter
2870 * @param TIMx Timer instance
2871 * @param Channel This parameter can be one of the following values:
2872 * @arg @ref LL_TIM_CHANNEL_CH1
2873 * @arg @ref LL_TIM_CHANNEL_CH2
2874 * @arg @ref LL_TIM_CHANNEL_CH3
2875 * @arg @ref LL_TIM_CHANNEL_CH4
2876 * @param ICFilter This parameter can be one of the following values:
2877 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2878 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2879 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2880 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2881 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2882 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2883 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2884 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2885 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2886 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2887 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2888 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2889 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2890 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2891 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2892 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2893 * @retval None
2894 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2895 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2896 {
2897 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2898 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2899 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2900 }
2901
2902 /**
2903 * @brief Get the input filter duration.
2904 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2905 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2906 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2907 * CCMR2 IC4F LL_TIM_IC_GetFilter
2908 * @param TIMx Timer instance
2909 * @param Channel This parameter can be one of the following values:
2910 * @arg @ref LL_TIM_CHANNEL_CH1
2911 * @arg @ref LL_TIM_CHANNEL_CH2
2912 * @arg @ref LL_TIM_CHANNEL_CH3
2913 * @arg @ref LL_TIM_CHANNEL_CH4
2914 * @retval Returned value can be one of the following values:
2915 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2916 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2917 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2918 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2919 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2920 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2921 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2922 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2923 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2924 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2925 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2926 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2927 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2928 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2929 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2930 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2931 */
LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx,uint32_t Channel)2932 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2933 {
2934 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2935 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2936 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2937 }
2938
2939 /**
2940 * @brief Set the input channel polarity.
2941 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2942 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2943 * CCER CC2P LL_TIM_IC_SetPolarity\n
2944 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2945 * CCER CC3P LL_TIM_IC_SetPolarity\n
2946 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2947 * CCER CC4P LL_TIM_IC_SetPolarity\n
2948 * CCER CC4NP LL_TIM_IC_SetPolarity
2949 * @param TIMx Timer instance
2950 * @param Channel This parameter can be one of the following values:
2951 * @arg @ref LL_TIM_CHANNEL_CH1
2952 * @arg @ref LL_TIM_CHANNEL_CH2
2953 * @arg @ref LL_TIM_CHANNEL_CH3
2954 * @arg @ref LL_TIM_CHANNEL_CH4
2955 * @param ICPolarity This parameter can be one of the following values:
2956 * @arg @ref LL_TIM_IC_POLARITY_RISING
2957 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2958 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2959 * @retval None
2960 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2961 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2962 {
2963 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2964 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2965 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2966 }
2967
2968 /**
2969 * @brief Get the current input channel polarity.
2970 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2971 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2972 * CCER CC2P LL_TIM_IC_GetPolarity\n
2973 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2974 * CCER CC3P LL_TIM_IC_GetPolarity\n
2975 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2976 * CCER CC4P LL_TIM_IC_GetPolarity\n
2977 * CCER CC4NP LL_TIM_IC_GetPolarity
2978 * @param TIMx Timer instance
2979 * @param Channel This parameter can be one of the following values:
2980 * @arg @ref LL_TIM_CHANNEL_CH1
2981 * @arg @ref LL_TIM_CHANNEL_CH2
2982 * @arg @ref LL_TIM_CHANNEL_CH3
2983 * @arg @ref LL_TIM_CHANNEL_CH4
2984 * @retval Returned value can be one of the following values:
2985 * @arg @ref LL_TIM_IC_POLARITY_RISING
2986 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2987 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2988 */
LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)2989 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2990 {
2991 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2992 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2993 SHIFT_TAB_CCxP[iChannel]);
2994 }
2995
2996 /**
2997 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2998 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2999 * a timer instance provides an XOR input.
3000 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3001 * @param TIMx Timer instance
3002 * @retval None
3003 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3004 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3005 {
3006 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3007 }
3008
3009 /**
3010 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3011 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3012 * a timer instance provides an XOR input.
3013 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3014 * @param TIMx Timer instance
3015 * @retval None
3016 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3017 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3018 {
3019 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3020 }
3021
3022 /**
3023 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3024 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3025 * a timer instance provides an XOR input.
3026 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3027 * @param TIMx Timer instance
3028 * @retval State of bit (1 or 0).
3029 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)3030 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3031 {
3032 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3033 }
3034
3035 /**
3036 * @brief Get captured value for input channel 1.
3037 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3038 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3039 * whether or not a timer instance supports a 32 bits counter.
3040 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3041 * input channel 1 is supported by a timer instance.
3042 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3043 * @param TIMx Timer instance
3044 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3045 */
LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)3046 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
3047 {
3048 return (uint32_t)(READ_REG(TIMx->CCR1));
3049 }
3050
3051 /**
3052 * @brief Get captured value for input channel 2.
3053 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3054 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3055 * whether or not a timer instance supports a 32 bits counter.
3056 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3057 * input channel 2 is supported by a timer instance.
3058 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3059 * @param TIMx Timer instance
3060 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3061 */
LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)3062 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
3063 {
3064 return (uint32_t)(READ_REG(TIMx->CCR2));
3065 }
3066
3067 /**
3068 * @brief Get captured value for input channel 3.
3069 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3070 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3071 * whether or not a timer instance supports a 32 bits counter.
3072 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3073 * input channel 3 is supported by a timer instance.
3074 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3075 * @param TIMx Timer instance
3076 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3077 */
LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)3078 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
3079 {
3080 return (uint32_t)(READ_REG(TIMx->CCR3));
3081 }
3082
3083 /**
3084 * @brief Get captured value for input channel 4.
3085 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3086 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3087 * whether or not a timer instance supports a 32 bits counter.
3088 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3089 * input channel 4 is supported by a timer instance.
3090 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3091 * @param TIMx Timer instance
3092 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3093 */
LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)3094 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
3095 {
3096 return (uint32_t)(READ_REG(TIMx->CCR4));
3097 }
3098
3099 /**
3100 * @}
3101 */
3102
3103 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3104 * @{
3105 */
3106 /**
3107 * @brief Enable external clock mode 2.
3108 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3109 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3110 * whether or not a timer instance supports external clock mode2.
3111 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3112 * @param TIMx Timer instance
3113 * @retval None
3114 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3115 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3116 {
3117 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3118 }
3119
3120 /**
3121 * @brief Disable external clock mode 2.
3122 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3123 * whether or not a timer instance supports external clock mode2.
3124 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3125 * @param TIMx Timer instance
3126 * @retval None
3127 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3128 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3129 {
3130 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3131 }
3132
3133 /**
3134 * @brief Indicate whether external clock mode 2 is enabled.
3135 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3136 * whether or not a timer instance supports external clock mode2.
3137 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3138 * @param TIMx Timer instance
3139 * @retval State of bit (1 or 0).
3140 */
LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx)3141 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
3142 {
3143 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3144 }
3145
3146 /**
3147 * @brief Set the clock source of the counter clock.
3148 * @note when selected clock source is external clock mode 1, the timer input
3149 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3150 * function. This timer input must be configured by calling
3151 * the @ref LL_TIM_IC_Config() function.
3152 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3153 * whether or not a timer instance supports external clock mode1.
3154 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3155 * whether or not a timer instance supports external clock mode2.
3156 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3157 * SMCR ECE LL_TIM_SetClockSource
3158 * @param TIMx Timer instance
3159 * @param ClockSource This parameter can be one of the following values:
3160 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3161 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3162 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3163 * @retval None
3164 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3165 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3166 {
3167 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3168 }
3169
3170 /**
3171 * @brief Set the encoder interface mode.
3172 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3173 * whether or not a timer instance supports the encoder mode.
3174 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3175 * @param TIMx Timer instance
3176 * @param EncoderMode This parameter can be one of the following values:
3177 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3178 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3179 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3180 * @retval None
3181 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3182 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3183 {
3184 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3185 }
3186
3187 /**
3188 * @}
3189 */
3190
3191 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3192 * @{
3193 */
3194 /**
3195 * @brief Set the trigger output (TRGO) used for timer synchronization .
3196 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3197 * whether or not a timer instance can operate as a master timer.
3198 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3199 * @param TIMx Timer instance
3200 * @param TimerSynchronization This parameter can be one of the following values:
3201 * @arg @ref LL_TIM_TRGO_RESET
3202 * @arg @ref LL_TIM_TRGO_ENABLE
3203 * @arg @ref LL_TIM_TRGO_UPDATE
3204 * @arg @ref LL_TIM_TRGO_CC1IF
3205 * @arg @ref LL_TIM_TRGO_OC1REF
3206 * @arg @ref LL_TIM_TRGO_OC2REF
3207 * @arg @ref LL_TIM_TRGO_OC3REF
3208 * @arg @ref LL_TIM_TRGO_OC4REF
3209 * @retval None
3210 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3211 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3212 {
3213 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3214 }
3215
3216 /**
3217 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3218 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3219 * whether or not a timer instance can be used for ADC synchronization.
3220 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3221 * @param TIMx Timer Instance
3222 * @param ADCSynchronization This parameter can be one of the following values:
3223 * @arg @ref LL_TIM_TRGO2_RESET
3224 * @arg @ref LL_TIM_TRGO2_ENABLE
3225 * @arg @ref LL_TIM_TRGO2_UPDATE
3226 * @arg @ref LL_TIM_TRGO2_CC1F
3227 * @arg @ref LL_TIM_TRGO2_OC1
3228 * @arg @ref LL_TIM_TRGO2_OC2
3229 * @arg @ref LL_TIM_TRGO2_OC3
3230 * @arg @ref LL_TIM_TRGO2_OC4
3231 * @arg @ref LL_TIM_TRGO2_OC5
3232 * @arg @ref LL_TIM_TRGO2_OC6
3233 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3234 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3235 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3236 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3237 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3238 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3239 * @retval None
3240 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3241 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3242 {
3243 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3244 }
3245
3246 /**
3247 * @brief Set the synchronization mode of a slave timer.
3248 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3249 * a timer instance can operate as a slave timer.
3250 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3251 * @param TIMx Timer instance
3252 * @param SlaveMode This parameter can be one of the following values:
3253 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3254 * @arg @ref LL_TIM_SLAVEMODE_RESET
3255 * @arg @ref LL_TIM_SLAVEMODE_GATED
3256 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3257 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3258 * @retval None
3259 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3260 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3261 {
3262 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3263 }
3264
3265 /**
3266 * @brief Set the selects the trigger input to be used to synchronize the counter.
3267 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3268 * a timer instance can operate as a slave timer.
3269 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3270 * @param TIMx Timer instance
3271 * @param TriggerInput This parameter can be one of the following values:
3272 * @arg @ref LL_TIM_TS_ITR0
3273 * @arg @ref LL_TIM_TS_ITR1
3274 * @arg @ref LL_TIM_TS_ITR2
3275 * @arg @ref LL_TIM_TS_ITR3
3276 * @arg @ref LL_TIM_TS_TI1F_ED
3277 * @arg @ref LL_TIM_TS_TI1FP1
3278 * @arg @ref LL_TIM_TS_TI2FP2
3279 * @arg @ref LL_TIM_TS_ETRF
3280 * @arg @ref LL_TIM_TS_ITR4
3281 * @arg @ref LL_TIM_TS_ITR5
3282 * @arg @ref LL_TIM_TS_ITR6
3283 * @arg @ref LL_TIM_TS_ITR7
3284 * @arg @ref LL_TIM_TS_ITR8 (*)
3285 * @arg @ref LL_TIM_TS_ITR9 (*)
3286 * @arg @ref LL_TIM_TS_ITR10 (*)
3287 * @arg @ref LL_TIM_TS_ITR11 (*)
3288 * @arg @ref LL_TIM_TS_ITR12 (*)
3289 * @arg @ref LL_TIM_TS_ITR13 (*)
3290 *
3291 * (*) Value not defined in all devices.
3292 * @retval None
3293 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3294 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3295 {
3296 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3297 }
3298
3299 /**
3300 * @brief Enable the Master/Slave mode.
3301 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3302 * a timer instance can operate as a slave timer.
3303 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3304 * @param TIMx Timer instance
3305 * @retval None
3306 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3307 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3308 {
3309 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3310 }
3311
3312 /**
3313 * @brief Disable the Master/Slave mode.
3314 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3315 * a timer instance can operate as a slave timer.
3316 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3317 * @param TIMx Timer instance
3318 * @retval None
3319 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3320 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3321 {
3322 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3323 }
3324
3325 /**
3326 * @brief Indicates whether the Master/Slave mode is enabled.
3327 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3328 * a timer instance can operate as a slave timer.
3329 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3330 * @param TIMx Timer instance
3331 * @retval State of bit (1 or 0).
3332 */
LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx)3333 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
3334 {
3335 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3336 }
3337
3338 /**
3339 * @brief Configure the external trigger (ETR) input.
3340 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3341 * a timer instance provides an external trigger input.
3342 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3343 * SMCR ETPS LL_TIM_ConfigETR\n
3344 * SMCR ETF LL_TIM_ConfigETR
3345 * @param TIMx Timer instance
3346 * @param ETRPolarity This parameter can be one of the following values:
3347 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3348 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3349 * @param ETRPrescaler This parameter can be one of the following values:
3350 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3351 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3352 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3353 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3354 * @param ETRFilter This parameter can be one of the following values:
3355 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3356 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3357 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3358 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3359 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3360 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3361 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3362 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3363 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3364 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3365 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3366 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3367 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3368 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3369 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3370 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3371 * @retval None
3372 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3373 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3374 uint32_t ETRFilter)
3375 {
3376 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3377 }
3378
3379 /**
3380 * @brief Select the external trigger (ETR) input source.
3381 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3382 * not a timer instance supports ETR source selection.
3383 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3384 * @param TIMx Timer instance
3385 * @param ETRSource This parameter can be one of the following values:
3386 * For TIM1, the parameter is one of the following values:
3387 * @arg LL_TIM_TIM1_ETRSOURCE_GPIO: TIM1_ETR is connected to GPIO
3388 * @arg LL_TIM_TIM1_ETRSOURCE_COMP1: TIM1_ETR is connected to COMP1 output
3389 * @arg LL_TIM_TIM1_ETRSOURCE_COMP2: TIM1_ETR is connected to COMP2 output
3390 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
3391 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
3392 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
3393 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
3394 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
3395 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
3396 *
3397 * For TIM2, the parameter is one of the following values:
3398 * @arg LL_TIM_TIM2_ETRSOURCE_GPIO: TIM2_ETR is connected to GPIO
3399 * @arg LL_TIM_TIM2_ETRSOURCE_COMP1: TIM2_ETR is connected to COMP1 output
3400 * @arg LL_TIM_TIM2_ETRSOURCE_COMP2: TIM2_ETR is connected to COMP2 output
3401 * @arg LL_TIM_TIM2_ETRSOURCE_LSE: TIM2_ETR is connected to LSE
3402 * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A
3403 * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B
3404 *
3405 * For TIM3, the parameter is one of the following values:
3406 * @arg LL_TIM_TIM3_ETRSOURCE_GPIO: TIM3_ETR is connected to GPIO
3407 * @arg LL_TIM_TIM3_ETRSOURCE_COMP1: TIM3_ETR is connected to COMP1 output
3408 *
3409 * For TIM5, the parameter is one of the following values:
3410 * @arg LL_TIM_TIM5_ETRSOURCE_GPIO: TIM5_ETR is connected to GPIO
3411 * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
3412 * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
3413 * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
3414 * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
3415 *
3416 * For TIM8, the parameter is one of the following values:
3417 * @arg LL_TIM_TIM8_ETRSOURCE_GPIO: TIM8_ETR is connected to GPIO
3418 * @arg LL_TIM_TIM8_ETRSOURCE_COMP1: TIM8_ETR is connected to COMP1 output
3419 * @arg LL_TIM_TIM8_ETRSOURCE_COMP2: TIM8_ETR is connected to COMP2 output
3420 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
3421 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
3422 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
3423 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
3424 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
3425 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
3426 *
3427 * For TIM23, the parameter is one of the following values: (*)
3428 * @arg LL_TIM_TIM23_ETRSOURCE_GPIO TIM23_ETR is connected to GPIO
3429 * @arg LL_TIM_TIM23_ETRSOURCE_COMP1 TIM23_ETR is connected to COMP1 output
3430 * @arg LL_TIM_TIM23_ETRSOURCE_COMP2 TIM23_ETR is connected to COMP2 output
3431 *
3432 * For TIM24, the parameter is one of the following values: (*)
3433 * @arg LL_TIM_TIM24_ETRSOURCE_GPIO TIM24_ETR is connected to GPIO
3434 * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A
3435 * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B
3436 * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A
3437 * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B
3438 *
3439 * (*) Value not defined in all devices.
3440 * @retval None
3441 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3442 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3443 {
3444 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3445 }
3446
3447 /**
3448 * @}
3449 */
3450
3451 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3452 * @{
3453 */
3454 /**
3455 * @brief Enable the break function.
3456 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3457 * a timer instance provides a break input.
3458 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3459 * @param TIMx Timer instance
3460 * @retval None
3461 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3462 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3463 {
3464 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3465 }
3466
3467 /**
3468 * @brief Disable the break function.
3469 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3470 * @param TIMx Timer instance
3471 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3472 * a timer instance provides a break input.
3473 * @retval None
3474 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3475 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3476 {
3477 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3478 }
3479
3480 /**
3481 * @brief Configure the break input.
3482 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3483 * a timer instance provides a break input.
3484 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3485 * BDTR BKF LL_TIM_ConfigBRK
3486 * @param TIMx Timer instance
3487 * @param BreakPolarity This parameter can be one of the following values:
3488 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3489 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3490 * @param BreakFilter This parameter can be one of the following values:
3491 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3492 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3493 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3494 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3495 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3496 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3497 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3498 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3499 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3500 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3501 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3502 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3503 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3504 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3505 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3506 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3507 * @retval None
3508 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter)3509 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
3510 uint32_t BreakFilter)
3511 {
3512 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3513 }
3514
3515 /**
3516 * @brief Enable the break 2 function.
3517 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3518 * a timer instance provides a second break input.
3519 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3520 * @param TIMx Timer instance
3521 * @retval None
3522 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3523 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3524 {
3525 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3526 }
3527
3528 /**
3529 * @brief Disable the break 2 function.
3530 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3531 * a timer instance provides a second break input.
3532 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3533 * @param TIMx Timer instance
3534 * @retval None
3535 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3536 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3537 {
3538 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3539 }
3540
3541 /**
3542 * @brief Configure the break 2 input.
3543 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3544 * a timer instance provides a second break input.
3545 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3546 * BDTR BK2F LL_TIM_ConfigBRK2
3547 * @param TIMx Timer instance
3548 * @param Break2Polarity This parameter can be one of the following values:
3549 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3550 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3551 * @param Break2Filter This parameter can be one of the following values:
3552 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3553 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3554 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3555 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3556 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3557 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3558 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3559 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3560 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3561 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3562 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3563 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3564 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3565 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3566 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3567 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3568 * @retval None
3569 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter)3570 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3571 {
3572 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3573 }
3574
3575 /**
3576 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3577 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3578 * a timer instance provides a break input.
3579 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3580 * BDTR OSSR LL_TIM_SetOffStates
3581 * @param TIMx Timer instance
3582 * @param OffStateIdle This parameter can be one of the following values:
3583 * @arg @ref LL_TIM_OSSI_DISABLE
3584 * @arg @ref LL_TIM_OSSI_ENABLE
3585 * @param OffStateRun This parameter can be one of the following values:
3586 * @arg @ref LL_TIM_OSSR_DISABLE
3587 * @arg @ref LL_TIM_OSSR_ENABLE
3588 * @retval None
3589 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3590 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3591 {
3592 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3593 }
3594
3595 /**
3596 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3597 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3598 * a timer instance provides a break input.
3599 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3600 * @param TIMx Timer instance
3601 * @retval None
3602 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3603 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3604 {
3605 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3606 }
3607
3608 /**
3609 * @brief Disable automatic output (MOE can be set only by software).
3610 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3611 * a timer instance provides a break input.
3612 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3613 * @param TIMx Timer instance
3614 * @retval None
3615 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3616 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3617 {
3618 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3619 }
3620
3621 /**
3622 * @brief Indicate whether automatic output is enabled.
3623 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3624 * a timer instance provides a break input.
3625 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3626 * @param TIMx Timer instance
3627 * @retval State of bit (1 or 0).
3628 */
LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx)3629 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
3630 {
3631 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3632 }
3633
3634 /**
3635 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3636 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3637 * software and is reset in case of break or break2 event
3638 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3639 * a timer instance provides a break input.
3640 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3641 * @param TIMx Timer instance
3642 * @retval None
3643 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3644 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3645 {
3646 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3647 }
3648
3649 /**
3650 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3651 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3652 * software and is reset in case of break or break2 event.
3653 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3654 * a timer instance provides a break input.
3655 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3656 * @param TIMx Timer instance
3657 * @retval None
3658 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3659 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3660 {
3661 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3662 }
3663
3664 /**
3665 * @brief Indicates whether outputs are enabled.
3666 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3667 * a timer instance provides a break input.
3668 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3669 * @param TIMx Timer instance
3670 * @retval State of bit (1 or 0).
3671 */
LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx)3672 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
3673 {
3674 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3675 }
3676
3677 #if defined(TIM_BREAK_INPUT_SUPPORT)
3678 /**
3679 * @brief Enable the signals connected to the designated timer break input.
3680 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3681 * or not a timer instance allows for break input selection.
3682 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3683 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
3684 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
3685 * AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
3686 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3687 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3688 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3689 * AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource
3690 * @param TIMx Timer instance
3691 * @param BreakInput This parameter can be one of the following values:
3692 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3693 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3694 * @param Source This parameter can be one of the following values:
3695 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3696 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3697 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3698 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3699 * @retval None
3700 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3701 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3702 {
3703 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3704 SET_BIT(*pReg, Source);
3705 }
3706
3707 /**
3708 * @brief Disable the signals connected to the designated timer break input.
3709 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3710 * or not a timer instance allows for break input selection.
3711 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3712 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
3713 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
3714 * AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
3715 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3716 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3717 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3718 * AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource
3719 * @param TIMx Timer instance
3720 * @param BreakInput This parameter can be one of the following values:
3721 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3722 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3723 * @param Source This parameter can be one of the following values:
3724 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3725 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3726 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3727 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3728 * @retval None
3729 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3730 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3731 {
3732 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3733 CLEAR_BIT(*pReg, Source);
3734 }
3735
3736 /**
3737 * @brief Set the polarity of the break signal for the timer break input.
3738 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3739 * or not a timer instance allows for break input selection.
3740 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3741 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3742 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3743 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3744 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3745 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3746 * @param TIMx Timer instance
3747 * @param BreakInput This parameter can be one of the following values:
3748 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3749 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3750 * @param Source This parameter can be one of the following values:
3751 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3752 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3753 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3754 * @param Polarity This parameter can be one of the following values:
3755 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3756 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3757 * @retval None
3758 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3759 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3760 uint32_t Polarity)
3761 {
3762 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3763 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3764 }
3765 #endif /* TIM_BREAK_INPUT_SUPPORT */
3766 /**
3767 * @}
3768 */
3769
3770 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3771 * @{
3772 */
3773 /**
3774 * @brief Configures the timer DMA burst feature.
3775 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3776 * not a timer instance supports the DMA burst mode.
3777 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3778 * DCR DBA LL_TIM_ConfigDMABurst
3779 * @param TIMx Timer instance
3780 * @param DMABurstBaseAddress This parameter can be one of the following values:
3781 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3782 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3783 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3784 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3785 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3786 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3787 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3788 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3789 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3790 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3791 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3792 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3793 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3794 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3795 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3796 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3797 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3798 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3799 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3800 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3801 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3802 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3803 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3804 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
3805 *
3806 * @param DMABurstLength This parameter can be one of the following values:
3807 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3808 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3809 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3810 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3811 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3812 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3813 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3814 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3815 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3816 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3817 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3818 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3819 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3820 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3821 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3822 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3823 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3824 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3825 * @retval None
3826 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3827 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3828 {
3829 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3830 }
3831
3832 /**
3833 * @}
3834 */
3835
3836 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3837 * @{
3838 */
3839 /**
3840 * @brief Remap TIM inputs (input channel, internal/external triggers).
3841 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3842 * a some timer inputs can be remapped.
3843 * TIM1: one of the following values:
3844 * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
3845 * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output
3846 *
3847 * TIM2: one of the following values:
3848 * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
3849 * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output
3850 * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output
3851 * @arg LL_TIM_TIM2_TI4_RMP_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
3852 *
3853 * TIM3: one of the following values:
3854 * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
3855 * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output
3856 * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output
3857 * @arg LL_TIM_TIM3_TI1_RMP_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
3858 *
3859 * TIM5: one of the following values:
3860 * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO
3861 * @arg LL_TIM_TIM5_TI1_RMP_CAN_TMP: TIM5 TI1 is connected to CAN TMP
3862 * @arg LL_TIM_TIM5_TI1_RMP_CAN_RTP: TIM5 TI1 is connected to CAN RTP
3863 *
3864 * TIM8: one of the following values:
3865 * @arg LL_TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO
3866 * @arg LL_TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output
3867 *
3868 * TIM12: one of the following values: (*)
3869 * @arg LL_TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO
3870 * @arg LL_TIM_TIM12_TI1_RMP_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS
3871 *
3872 * TIM15: one of the following values:
3873 * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO
3874 * @arg LL_TIM_TIM15_TI1_RMP_TIM2: TIM15 TI1 is connected to TIM2 CH1
3875 * @arg LL_TIM_TIM15_TI1_RMP_TIM3: TIM15 TI1 is connected to TIM3 CH1
3876 * @arg LL_TIM_TIM15_TI1_RMP_TIM4: TIM15 TI1 is connected to TIM4 CH1
3877 * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE
3878 * @arg LL_TIM_TIM15_TI1_RMP_CSI: TIM15 TI1 is connected to CSI
3879 * @arg LL_TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2
3880 * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI2 is connected to GPIO
3881 * @arg LL_TIM_TIM15_TI2_RMP_TIM2: TIM15 TI2 is connected to TIM2 CH2
3882 * @arg LL_TIM_TIM15_TI2_RMP_TIM3: TIM15 TI2 is connected to TIM3 CH2
3883 * @arg LL_TIM_TIM15_TI2_RMP_TIM4: TIM15 TI2 is connected to TIM4 CH2
3884 *
3885 * TIM16: one of the following values:
3886 * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
3887 * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
3888 * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
3889 * @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
3890 *
3891 * TIM17: one of the following values:
3892 * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
3893 * @arg LL_TIM_TIM17_TI1_RMP_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*)
3894 * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz
3895 * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1
3896 *
3897 * TIM23: one of the following values: (*)
3898 * @arg LL_TIM_TIM23_TI4_RMP_GPIO TIM23_TI4 is connected to GPIO
3899 * @arg LL_TIM_TIM23_TI4_RMP_COMP1 TIM23_TI4 is connected to COMP1 output
3900 * @arg LL_TIM_TIM23_TI4_RMP_COMP2 TIM23_TI4 is connected to COMP2 output
3901 * @arg LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output
3902 *
3903 * TIM24: one of the following values: (*)
3904 * @arg LL_TIM_TIM24_TI1_RMP_GPIO TIM24_TI1 is connected to GPIO
3905 * @arg LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM24_TI1 is connected to CAN_TMP
3906 * @arg LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM24_TI1 is connected to CAN_RTP
3907 * @arg LL_TIM_TIM24_TI1_RMP_CAN_SOC TIM24_TI1 is connected to CAN_SOC
3908 *
3909 * (*) Value not defined in all devices. \n
3910 * @retval None
3911 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3912 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3913 {
3914 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
3915 }
3916
3917 /**
3918 * @}
3919 */
3920
3921 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3922 * @{
3923 */
3924 /**
3925 * @brief Clear the update interrupt flag (UIF).
3926 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3927 * @param TIMx Timer instance
3928 * @retval None
3929 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3930 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3931 {
3932 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3933 }
3934
3935 /**
3936 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3937 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3938 * @param TIMx Timer instance
3939 * @retval State of bit (1 or 0).
3940 */
LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)3941 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
3942 {
3943 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3944 }
3945
3946 /**
3947 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3948 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3949 * @param TIMx Timer instance
3950 * @retval None
3951 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3952 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3953 {
3954 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3955 }
3956
3957 /**
3958 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3959 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3960 * @param TIMx Timer instance
3961 * @retval State of bit (1 or 0).
3962 */
LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)3963 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
3964 {
3965 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3966 }
3967
3968 /**
3969 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3970 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3971 * @param TIMx Timer instance
3972 * @retval None
3973 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3974 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3975 {
3976 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3977 }
3978
3979 /**
3980 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3981 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3982 * @param TIMx Timer instance
3983 * @retval State of bit (1 or 0).
3984 */
LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)3985 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
3986 {
3987 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3988 }
3989
3990 /**
3991 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3992 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3993 * @param TIMx Timer instance
3994 * @retval None
3995 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3996 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3997 {
3998 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3999 }
4000
4001 /**
4002 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4003 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4004 * @param TIMx Timer instance
4005 * @retval State of bit (1 or 0).
4006 */
LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)4007 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
4008 {
4009 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4010 }
4011
4012 /**
4013 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4014 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4015 * @param TIMx Timer instance
4016 * @retval None
4017 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4018 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4019 {
4020 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4021 }
4022
4023 /**
4024 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4025 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4026 * @param TIMx Timer instance
4027 * @retval State of bit (1 or 0).
4028 */
LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)4029 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
4030 {
4031 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4032 }
4033
4034 /**
4035 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4036 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4037 * @param TIMx Timer instance
4038 * @retval None
4039 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4040 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4041 {
4042 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4043 }
4044
4045 /**
4046 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4047 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4048 * @param TIMx Timer instance
4049 * @retval State of bit (1 or 0).
4050 */
LL_TIM_IsActiveFlag_CC5(TIM_TypeDef * TIMx)4051 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
4052 {
4053 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4054 }
4055
4056 /**
4057 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4058 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4059 * @param TIMx Timer instance
4060 * @retval None
4061 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4062 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4063 {
4064 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4065 }
4066
4067 /**
4068 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4069 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4070 * @param TIMx Timer instance
4071 * @retval State of bit (1 or 0).
4072 */
LL_TIM_IsActiveFlag_CC6(TIM_TypeDef * TIMx)4073 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
4074 {
4075 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4076 }
4077
4078 /**
4079 * @brief Clear the commutation interrupt flag (COMIF).
4080 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4081 * @param TIMx Timer instance
4082 * @retval None
4083 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4084 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4085 {
4086 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4087 }
4088
4089 /**
4090 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4091 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4092 * @param TIMx Timer instance
4093 * @retval State of bit (1 or 0).
4094 */
LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx)4095 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
4096 {
4097 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4098 }
4099
4100 /**
4101 * @brief Clear the trigger interrupt flag (TIF).
4102 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4103 * @param TIMx Timer instance
4104 * @retval None
4105 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4106 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4107 {
4108 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4109 }
4110
4111 /**
4112 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4113 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4114 * @param TIMx Timer instance
4115 * @retval State of bit (1 or 0).
4116 */
LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)4117 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
4118 {
4119 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4120 }
4121
4122 /**
4123 * @brief Clear the break interrupt flag (BIF).
4124 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4125 * @param TIMx Timer instance
4126 * @retval None
4127 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4128 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4129 {
4130 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4131 }
4132
4133 /**
4134 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4135 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4136 * @param TIMx Timer instance
4137 * @retval State of bit (1 or 0).
4138 */
LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx)4139 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
4140 {
4141 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4142 }
4143
4144 /**
4145 * @brief Clear the break 2 interrupt flag (B2IF).
4146 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4147 * @param TIMx Timer instance
4148 * @retval None
4149 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4150 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4151 {
4152 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4153 }
4154
4155 /**
4156 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4157 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4158 * @param TIMx Timer instance
4159 * @retval State of bit (1 or 0).
4160 */
LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef * TIMx)4161 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
4162 {
4163 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4164 }
4165
4166 /**
4167 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4168 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4169 * @param TIMx Timer instance
4170 * @retval None
4171 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4172 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4173 {
4174 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4175 }
4176
4177 /**
4178 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
4179 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4180 * @param TIMx Timer instance
4181 * @retval State of bit (1 or 0).
4182 */
LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)4183 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
4184 {
4185 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4186 }
4187
4188 /**
4189 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4190 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4191 * @param TIMx Timer instance
4192 * @retval None
4193 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4194 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4195 {
4196 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4197 }
4198
4199 /**
4200 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
4201 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4202 * @param TIMx Timer instance
4203 * @retval State of bit (1 or 0).
4204 */
LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)4205 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
4206 {
4207 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4208 }
4209
4210 /**
4211 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4212 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4213 * @param TIMx Timer instance
4214 * @retval None
4215 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4216 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4217 {
4218 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4219 }
4220
4221 /**
4222 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
4223 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4224 * @param TIMx Timer instance
4225 * @retval State of bit (1 or 0).
4226 */
LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)4227 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
4228 {
4229 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4230 }
4231
4232 /**
4233 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4234 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4235 * @param TIMx Timer instance
4236 * @retval None
4237 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4238 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4239 {
4240 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4241 }
4242
4243 /**
4244 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
4245 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4246 * @param TIMx Timer instance
4247 * @retval State of bit (1 or 0).
4248 */
LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)4249 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
4250 {
4251 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4252 }
4253
4254 /**
4255 * @brief Clear the system break interrupt flag (SBIF).
4256 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4257 * @param TIMx Timer instance
4258 * @retval None
4259 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4260 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4261 {
4262 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4263 }
4264
4265 /**
4266 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4267 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4268 * @param TIMx Timer instance
4269 * @retval State of bit (1 or 0).
4270 */
LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef * TIMx)4271 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
4272 {
4273 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4274 }
4275
4276 /**
4277 * @}
4278 */
4279
4280 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4281 * @{
4282 */
4283 /**
4284 * @brief Enable update interrupt (UIE).
4285 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4286 * @param TIMx Timer instance
4287 * @retval None
4288 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4289 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4290 {
4291 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4292 }
4293
4294 /**
4295 * @brief Disable update interrupt (UIE).
4296 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4297 * @param TIMx Timer instance
4298 * @retval None
4299 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4300 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4301 {
4302 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4303 }
4304
4305 /**
4306 * @brief Indicates whether the update interrupt (UIE) is enabled.
4307 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4308 * @param TIMx Timer instance
4309 * @retval State of bit (1 or 0).
4310 */
LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)4311 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
4312 {
4313 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4314 }
4315
4316 /**
4317 * @brief Enable capture/compare 1 interrupt (CC1IE).
4318 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4319 * @param TIMx Timer instance
4320 * @retval None
4321 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4322 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4323 {
4324 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4325 }
4326
4327 /**
4328 * @brief Disable capture/compare 1 interrupt (CC1IE).
4329 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4330 * @param TIMx Timer instance
4331 * @retval None
4332 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4333 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4334 {
4335 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4336 }
4337
4338 /**
4339 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4340 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4341 * @param TIMx Timer instance
4342 * @retval State of bit (1 or 0).
4343 */
LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)4344 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
4345 {
4346 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4347 }
4348
4349 /**
4350 * @brief Enable capture/compare 2 interrupt (CC2IE).
4351 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4352 * @param TIMx Timer instance
4353 * @retval None
4354 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4355 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4356 {
4357 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4358 }
4359
4360 /**
4361 * @brief Disable capture/compare 2 interrupt (CC2IE).
4362 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4363 * @param TIMx Timer instance
4364 * @retval None
4365 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4366 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4367 {
4368 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4369 }
4370
4371 /**
4372 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4373 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4374 * @param TIMx Timer instance
4375 * @retval State of bit (1 or 0).
4376 */
LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)4377 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
4378 {
4379 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4380 }
4381
4382 /**
4383 * @brief Enable capture/compare 3 interrupt (CC3IE).
4384 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4385 * @param TIMx Timer instance
4386 * @retval None
4387 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4388 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4389 {
4390 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4391 }
4392
4393 /**
4394 * @brief Disable capture/compare 3 interrupt (CC3IE).
4395 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4396 * @param TIMx Timer instance
4397 * @retval None
4398 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4399 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4400 {
4401 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4402 }
4403
4404 /**
4405 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4406 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4407 * @param TIMx Timer instance
4408 * @retval State of bit (1 or 0).
4409 */
LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)4410 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
4411 {
4412 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4413 }
4414
4415 /**
4416 * @brief Enable capture/compare 4 interrupt (CC4IE).
4417 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4418 * @param TIMx Timer instance
4419 * @retval None
4420 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4421 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4422 {
4423 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4424 }
4425
4426 /**
4427 * @brief Disable capture/compare 4 interrupt (CC4IE).
4428 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4429 * @param TIMx Timer instance
4430 * @retval None
4431 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4432 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4433 {
4434 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4435 }
4436
4437 /**
4438 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4439 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4440 * @param TIMx Timer instance
4441 * @retval State of bit (1 or 0).
4442 */
LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)4443 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
4444 {
4445 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4446 }
4447
4448 /**
4449 * @brief Enable commutation interrupt (COMIE).
4450 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4451 * @param TIMx Timer instance
4452 * @retval None
4453 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4454 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4455 {
4456 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4457 }
4458
4459 /**
4460 * @brief Disable commutation interrupt (COMIE).
4461 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4462 * @param TIMx Timer instance
4463 * @retval None
4464 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4465 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4466 {
4467 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4468 }
4469
4470 /**
4471 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4472 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4473 * @param TIMx Timer instance
4474 * @retval State of bit (1 or 0).
4475 */
LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx)4476 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
4477 {
4478 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4479 }
4480
4481 /**
4482 * @brief Enable trigger interrupt (TIE).
4483 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4484 * @param TIMx Timer instance
4485 * @retval None
4486 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4487 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4488 {
4489 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4490 }
4491
4492 /**
4493 * @brief Disable trigger interrupt (TIE).
4494 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4495 * @param TIMx Timer instance
4496 * @retval None
4497 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4498 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4499 {
4500 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4501 }
4502
4503 /**
4504 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4505 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4506 * @param TIMx Timer instance
4507 * @retval State of bit (1 or 0).
4508 */
LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)4509 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
4510 {
4511 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4512 }
4513
4514 /**
4515 * @brief Enable break interrupt (BIE).
4516 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4517 * @param TIMx Timer instance
4518 * @retval None
4519 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4520 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4521 {
4522 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4523 }
4524
4525 /**
4526 * @brief Disable break interrupt (BIE).
4527 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4528 * @param TIMx Timer instance
4529 * @retval None
4530 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4531 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4532 {
4533 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4534 }
4535
4536 /**
4537 * @brief Indicates whether the break interrupt (BIE) is enabled.
4538 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4539 * @param TIMx Timer instance
4540 * @retval State of bit (1 or 0).
4541 */
LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx)4542 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
4543 {
4544 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4545 }
4546
4547 /**
4548 * @}
4549 */
4550
4551 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
4552 * @{
4553 */
4554 /**
4555 * @brief Enable update DMA request (UDE).
4556 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4557 * @param TIMx Timer instance
4558 * @retval None
4559 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4560 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4561 {
4562 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4563 }
4564
4565 /**
4566 * @brief Disable update DMA request (UDE).
4567 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4568 * @param TIMx Timer instance
4569 * @retval None
4570 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4571 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4572 {
4573 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4574 }
4575
4576 /**
4577 * @brief Indicates whether the update DMA request (UDE) is enabled.
4578 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4579 * @param TIMx Timer instance
4580 * @retval State of bit (1 or 0).
4581 */
LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)4582 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
4583 {
4584 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4585 }
4586
4587 /**
4588 * @brief Enable capture/compare 1 DMA request (CC1DE).
4589 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4590 * @param TIMx Timer instance
4591 * @retval None
4592 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4593 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4594 {
4595 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4596 }
4597
4598 /**
4599 * @brief Disable capture/compare 1 DMA request (CC1DE).
4600 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4601 * @param TIMx Timer instance
4602 * @retval None
4603 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4604 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4605 {
4606 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4607 }
4608
4609 /**
4610 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4611 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4612 * @param TIMx Timer instance
4613 * @retval State of bit (1 or 0).
4614 */
LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)4615 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
4616 {
4617 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4618 }
4619
4620 /**
4621 * @brief Enable capture/compare 2 DMA request (CC2DE).
4622 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4623 * @param TIMx Timer instance
4624 * @retval None
4625 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4626 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4627 {
4628 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4629 }
4630
4631 /**
4632 * @brief Disable capture/compare 2 DMA request (CC2DE).
4633 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4634 * @param TIMx Timer instance
4635 * @retval None
4636 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4637 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4638 {
4639 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4640 }
4641
4642 /**
4643 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4644 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4645 * @param TIMx Timer instance
4646 * @retval State of bit (1 or 0).
4647 */
LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)4648 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
4649 {
4650 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4651 }
4652
4653 /**
4654 * @brief Enable capture/compare 3 DMA request (CC3DE).
4655 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4656 * @param TIMx Timer instance
4657 * @retval None
4658 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4659 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4660 {
4661 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4662 }
4663
4664 /**
4665 * @brief Disable capture/compare 3 DMA request (CC3DE).
4666 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4667 * @param TIMx Timer instance
4668 * @retval None
4669 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4670 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4671 {
4672 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4673 }
4674
4675 /**
4676 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4677 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4678 * @param TIMx Timer instance
4679 * @retval State of bit (1 or 0).
4680 */
LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)4681 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
4682 {
4683 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4684 }
4685
4686 /**
4687 * @brief Enable capture/compare 4 DMA request (CC4DE).
4688 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4689 * @param TIMx Timer instance
4690 * @retval None
4691 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4692 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4693 {
4694 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4695 }
4696
4697 /**
4698 * @brief Disable capture/compare 4 DMA request (CC4DE).
4699 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4700 * @param TIMx Timer instance
4701 * @retval None
4702 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4703 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4704 {
4705 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4706 }
4707
4708 /**
4709 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4710 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4711 * @param TIMx Timer instance
4712 * @retval State of bit (1 or 0).
4713 */
LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)4714 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
4715 {
4716 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4717 }
4718
4719 /**
4720 * @brief Enable commutation DMA request (COMDE).
4721 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4722 * @param TIMx Timer instance
4723 * @retval None
4724 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4725 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4726 {
4727 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4728 }
4729
4730 /**
4731 * @brief Disable commutation DMA request (COMDE).
4732 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4733 * @param TIMx Timer instance
4734 * @retval None
4735 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4736 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4737 {
4738 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4739 }
4740
4741 /**
4742 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4743 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4744 * @param TIMx Timer instance
4745 * @retval State of bit (1 or 0).
4746 */
LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx)4747 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
4748 {
4749 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4750 }
4751
4752 /**
4753 * @brief Enable trigger interrupt (TDE).
4754 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4755 * @param TIMx Timer instance
4756 * @retval None
4757 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4758 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4759 {
4760 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4761 }
4762
4763 /**
4764 * @brief Disable trigger interrupt (TDE).
4765 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4766 * @param TIMx Timer instance
4767 * @retval None
4768 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4769 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4770 {
4771 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4772 }
4773
4774 /**
4775 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4776 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4777 * @param TIMx Timer instance
4778 * @retval State of bit (1 or 0).
4779 */
LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)4780 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
4781 {
4782 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4783 }
4784
4785 /**
4786 * @}
4787 */
4788
4789 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4790 * @{
4791 */
4792 /**
4793 * @brief Generate an update event.
4794 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4795 * @param TIMx Timer instance
4796 * @retval None
4797 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4798 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4799 {
4800 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4801 }
4802
4803 /**
4804 * @brief Generate Capture/Compare 1 event.
4805 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4806 * @param TIMx Timer instance
4807 * @retval None
4808 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4809 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4810 {
4811 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4812 }
4813
4814 /**
4815 * @brief Generate Capture/Compare 2 event.
4816 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4817 * @param TIMx Timer instance
4818 * @retval None
4819 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4820 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4821 {
4822 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4823 }
4824
4825 /**
4826 * @brief Generate Capture/Compare 3 event.
4827 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4828 * @param TIMx Timer instance
4829 * @retval None
4830 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4831 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4832 {
4833 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4834 }
4835
4836 /**
4837 * @brief Generate Capture/Compare 4 event.
4838 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4839 * @param TIMx Timer instance
4840 * @retval None
4841 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4842 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4843 {
4844 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4845 }
4846
4847 /**
4848 * @brief Generate commutation event.
4849 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4850 * @param TIMx Timer instance
4851 * @retval None
4852 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4853 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4854 {
4855 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4856 }
4857
4858 /**
4859 * @brief Generate trigger event.
4860 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4861 * @param TIMx Timer instance
4862 * @retval None
4863 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4864 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4865 {
4866 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4867 }
4868
4869 /**
4870 * @brief Generate break event.
4871 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4872 * @param TIMx Timer instance
4873 * @retval None
4874 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4875 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4876 {
4877 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4878 }
4879
4880 /**
4881 * @brief Generate break 2 event.
4882 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4883 * @param TIMx Timer instance
4884 * @retval None
4885 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4886 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4887 {
4888 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4889 }
4890
4891 /**
4892 * @}
4893 */
4894
4895 #if defined(USE_FULL_LL_DRIVER)
4896 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4897 * @{
4898 */
4899
4900 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
4901 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4902 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
4903 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4904 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4905 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4906 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4907 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4908 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4909 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4910 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4911 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4912 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4913 /**
4914 * @}
4915 */
4916 #endif /* USE_FULL_LL_DRIVER */
4917
4918 /**
4919 * @}
4920 */
4921
4922 /**
4923 * @}
4924 */
4925
4926 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 || TIM23 || TIM24 */
4927
4928 /**
4929 * @}
4930 */
4931
4932 #ifdef __cplusplus
4933 }
4934 #endif
4935
4936 #endif /* __STM32H7xx_LL_TIM_H */
4937 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4938
