1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SYSCFG registers
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
22 * All rights reserved.</center></h2>
23 *
24 * This software component is licensed by ST under BSD 3-Clause license,
25 * the "License"; You may not use this file except in compliance with the
26 * License. You may obtain a copy of the License at:
27 * opensource.org/licenses/BSD-3-Clause
28 *
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef __STM32F3xx_LL_SYSTEM_H
34 #define __STM32F3xx_LL_SYSTEM_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32f3xx.h"
42
43 /** @addtogroup STM32F3xx_LL_Driver
44 * @{
45 */
46
47 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
48
49 /** @defgroup SYSTEM_LL SYSTEM
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55
56 /* Private constants ---------------------------------------------------------*/
57 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
58 * @{
59 */
60
61 /* Offset used to access to SYSCFG_CFGR1 and SYSCFG_CFGR3 registers */
62 #define SYSCFG_OFFSET_CFGR1 0x00000000U
63 #define SYSCFG_OFFSET_CFGR3 0x00000050U
64
65 /* Mask used for TIM breaks functions */
66 #if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
67 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)
68 #elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
69 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)
70 #elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
71 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)
72 #else
73 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK)
74 #endif /* SYSCFG_CFGR2_PVD_LOCK && SYSCFG_CFGR2_SRAM_PARITY_LOCK */
75
76 /**
77 * @}
78 */
79
80 /* Private macros ------------------------------------------------------------*/
81
82 /* Exported types ------------------------------------------------------------*/
83 /* Exported constants --------------------------------------------------------*/
84 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
85 * @{
86 */
87
88 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
89 * @{
90 */
91 #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */
92 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */
93 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */
94 #if defined(FMC_BANK1)
95 #define LL_SYSCFG_REMAP_FMC SYSCFG_CFGR1_MEM_MODE_2 /*<! FMC Bank (Only the first two banks) */
96 #endif /* FMC_BANK1 */
97 /**
98 * @}
99 */
100
101 #if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
102 /** @defgroup SYSTEM_LL_EC_SPI1_DMA_RMP_RX SYSCFG SPI1 RX/TX DMA1 request REMAP
103 * @{
104 */
105 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH2 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< SPI1_RX mapped on DMA1 CH2 */
106 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH4 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0) /*!< SPI1_RX mapped on DMA1 CH4 */
107 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH6 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1) /*!< SPI1_RX mapped on DMA1 CH6 */
108 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH3 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< SPI1_TX mapped on DMA1 CH3 */
109 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH5 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0) /*!< SPI1_TX mapped on DMA1 CH5 */
110 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH7 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1) /*!< SPI1_TX mapped on DMA1 CH7 */
111 /**
112 * @}
113 */
114 #endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
115
116 #if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
117 /** @defgroup SYSTEM_LL_EC_I2C1_DMA_RMP_RX SYSCFG I2C1 RX/TX DMA1 request REMAP
118 * @{
119 */
120 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH7 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< I2C1_RX mapped on DMA1 CH7 */
121 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH3 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0) /*!< I2C1_RX mapped on DMA1 CH3 */
122 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH5 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1) /*!< I2C1_RX mapped on DMA1 CH5 */
123 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH6 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< I2C1_TX mapped on DMA1 CH6 */
124 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH2 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0) /*!< I2C1_TX mapped on DMA1 CH2 */
125 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH4 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1) /*!< I2C1_TX mapped on DMA1 CH4 */
126 /**
127 * @}
128 */
129
130 #endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
131
132 #if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
133 /** @defgroup SYSTEM_LL_EC_ADC24_DMA_REMAP SYSCFG ADC DMA request REMAP
134 * @{
135 */
136 #if defined (SYSCFG_CFGR1_ADC24_DMA_RMP)
137 #define LL_SYSCFG_ADC24_RMP_DMA2_CH12 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | (uint32_t)0x00000000U) /*!< ADC24 DMA requests mapped on DMA2 channels 1 and 2 */
138 #define LL_SYSCFG_ADC24_RMP_DMA2_CH34 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | SYSCFG_CFGR1_ADC24_DMA_RMP) /*!< ADC24 DMA requests mapped on DMA2 channels 3 and 4 */
139 #endif /*SYSCFG_CFGR1_ADC24_DMA_RMP*/
140 #if defined (SYSCFG_CFGR3_ADC2_DMA_RMP)
141 #define LL_SYSCFG_ADC2_RMP_DMA1_CH2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | (uint32_t)0x00000000U) /*!< ADC2 mapped on DMA1 channel 2 */
142 #define LL_SYSCFG_ADC2_RMP_DMA1_CH4 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_0) /*!< ADC2 mapped on DMA1 channel 4 */
143 #define LL_SYSCFG_ADC2_RMP_DMA2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | (uint32_t)0x00000000U) /*!< ADC2 mapped on DMA2 */
144 #define LL_SYSCFG_ADC2_RMP_DMA1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_1) /*!< ADC2 mapped on DMA1 */
145 #endif /*SYSCFG_CFGR3_ADC2_DMA_RMP*/
146 /**
147 * @}
148 */
149
150 #endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
151
152 /** @defgroup SYSTEM_LL_EC_DAC1_DMA2_REMAP SYSCFG DAC1/2 DMA1/2 request REMAP
153 * @{
154 */
155 #define LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC_CH1 DMA requests mapped on DMA2 channel 3 */
156 #define LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /*!< DAC_CH1 DMA requests mapped on DMA1 channel 3 */
157 #if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
158 #define LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC1_OUT2 DMA requests mapped on DMA2 channel 4 */
159 #define LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< DAC1_OUT2 DMA requests mapped on DMA1 channel 4 */
160 #endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
161 #if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
162 #define LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC2_OUT1 DMA requests mapped on DMA2 channel 5 */
163 #define LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< DAC2_OUT1 DMA requests mapped on DMA1 channel 5 */
164 #endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
165 #if defined(SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)
166 #define LL_SYSCFG_DAC2_CH1_RMP_NO ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< No remap */
167 #define LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_DAC2Ch1_DMA_RMP) /*!< DAC2_CH1 DMA requests mapped on DMA1 channel 5 */
168 #endif /*SYSCFG_CFGR1_DAC2Ch1_DMA_RMP*/
169 /**
170 * @}
171 */
172
173 /** @defgroup SYSTEM_LL_EC_TIM16_DMA1_REMAP SYSCFG TIM DMA request REMAP
174 * @{
175 */
176 #define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 3 */
177 #define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6 */
178 #define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 1 */
179 #define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7 */
180 #define LL_SYSCFG_TIM6_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM6 DMA requests mapped on DMA2 channel 3 */
181 #define LL_SYSCFG_TIM6_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /*!< TIM6 DMA requests mapped on DMA1 channel 3 */
182 #if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
183 #define LL_SYSCFG_TIM7_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM7 DMA requests mapped on DMA2 channel 4 */
184 #define LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< TIM7 DMA requests mapped on DMA1 channel 4 */
185 #endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
186 #if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
187 #define LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM18 DMA requests mapped on DMA2 channel 5 */
188 #define LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< TIM18 DMA requests mapped on DMA1 channel 5 */
189 #endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
190 /**
191 * @}
192 */
193
194 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
195 /** @defgroup SYSTEM_LL_EC_TIM1_ITR3_RMP_TIM4 SYSCFG TIM REMAP
196 * @{
197 */
198 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP)
199 #define LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM1_ITR3 = TIM4_TRGO */
200 #define LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | SYSCFG_CFGR1_TIM1_ITR3_RMP) /*!< TIM1_ITR3 = TIM17_OC */
201 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP */
202 #if defined(SYSCFG_CFGR1_ENCODER_MODE)
203 #define LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION ((SYSCFG_CFGR1_ENCODER_MODE << 8U) | (uint32_t)0x00000000U) /*!< No redirection */
204 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM2 ((SYSCFG_CFGR1_ENCODER_MODE_0 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_0) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
205 #if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM3)
206 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM3 ((SYSCFG_CFGR1_ENCODER_MODE_TIM3 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM3) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
207 #endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM3 */
208 #if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM4)
209 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM4 ((SYSCFG_CFGR1_ENCODER_MODE_TIM4 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM4) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
210 #endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM4 */
211 #endif /* SYSCFG_CFGR1_ENCODER_MODE */
212 /**
213 * @}
214 */
215
216 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
217
218 #if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
219 /** @defgroup SYSTEM_LL_EC_ADC12_EXT2_RMP_TIM1 SYSCFG ADC Trigger REMAP
220 * @{
221 */
222 #define LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM1_CC3 */
223 #define LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT2_RMP) /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM20_TRGO */
224 #define LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM2_CC2 */
225 #define LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT3_RMP) /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM20_TRGO2 */
226 #define LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM4_CC4 */
227 #define LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT5_RMP) /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM20_CC1 */
228 #define LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM6_TRGO */
229 #define LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT13_RMP) /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM20_CC2 */
230 #define LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM3_CC4 */
231 #define LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT15_RMP) /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM20_CC3 */
232 #define LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM2_CC1 */
233 #define LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT3_RMP) /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM20_TRGO */
234 #define LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is EXTI_LINE_15 */
235 #define LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT6_RMP) /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is TIM20_TRGO2 */
236 #define LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM3_CC1 */
237 #define LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT13_RMP) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM20_CC4 */
238 #define LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2 ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is EXTI_LINE_2 */
239 #define LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT5_RMP) /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is TIM20_TRGO */
240 #define LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM4_CC1 */
241 #define LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT6_RMP) /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM20_TRGO2 */
242 #define LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM2_CC1 */
243 #define LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT15_RMP) /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM20_CC1 */
244 #define LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3 ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM4_CC3 */
245 #define LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT5_RMP) /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM20_TRGO */
246 #define LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM1_CC3 */
247 #define LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT11_RMP) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM20_TRGO2 */
248 #define LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM7_TRGO */
249 #define LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT14_RMP) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM20_CC2 */
250 /**
251 * @}
252 */
253
254 #endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
255
256 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
257 /** @defgroup SYSTEM_LL_EC_DAC1_TRIG1_REMAP SYSCFG DAC1 Trigger REMAP
258 * @{
259 */
260 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP)
261 #define LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | (uint32_t)0x00000000U) /*!< No remap: DAC trigger TRIG1 is TIM8_TRGO */
262 #define LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | SYSCFG_CFGR1_DAC1_TRIG1_RMP) /*!< DAC trigger is TIM3_TRGO */
263 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP */
264 #if defined(SYSCFG_CFGR3_DAC1_TRG3_RMP)
265 #define LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | (uint32_t)0x00000000U) /*!< DAC trigger is TIM15_TRGO */
266 #define LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG3_RMP) /*!< DAC trigger is HRTIM1_DAC1_TRIG1 */
267 #endif /* SYSCFG_CFGR3_DAC1_TRG3_RMP */
268 #if defined(SYSCFG_CFGR3_DAC1_TRG5_RMP)
269 #define LL_SYSCFG_DAC1_TRIG5_RMP_NO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | (uint32_t)0x00000000U) /*!< No remap */
270 #define LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG5_RMP) /*!< DAC trigger is HRTIM1_DAC1_TRIG2 */
271 #endif /* SYSCFG_CFGR3_DAC1_TRG5_RMP */
272 /**
273 * @}
274 */
275
276 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
277
278 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
279 * @{
280 */
281 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< I2C PB6 Fast mode plus */
282 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< I2C PB7 Fast mode plus */
283 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< I2C PB8 Fast mode plus */
284 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< I2C PB9 Fast mode plus */
285 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< I2C1 Fast mode plus */
286 #if defined(SYSCFG_CFGR1_I2C2_FMP)
287 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< I2C2 Fast mode plus */
288 #endif /*SYSCFG_CFGR1_I2C2_FMP*/
289 #if defined(SYSCFG_CFGR1_I2C3_FMP)
290 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< I2C3 Fast mode plus */
291 #endif /*SYSCFG_CFGR1_I2C3_FMP*/
292 /**
293 * @}
294 */
295
296 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
297 * @{
298 */
299 #define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */
300 #define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */
301 #define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */
302 #define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */
303 #if defined(GPIOE)
304 #define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */
305 #endif /* GPIOE */
306 #define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */
307 #if defined(GPIOG)
308 #define LL_SYSCFG_EXTI_PORTG (uint32_t)6U /*!< EXTI PORT G */
309 #endif /* GPIOG */
310 #if defined(GPIOH)
311 #define LL_SYSCFG_EXTI_PORTH (uint32_t)7U /*!< EXTI PORT H */
312 #endif /* GPIOH */
313 /**
314 * @}
315 */
316
317 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
318 * @{
319 */
320 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */
321 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */
322 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */
323 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */
324 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */
325 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */
326 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */
327 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */
328 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */
329 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */
330 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */
331 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */
332 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */
333 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */
334 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */
335 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */
336 /**
337 * @}
338 */
339
340 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
341 * @{
342 */
343 #if defined(SYSCFG_CFGR2_PVD_LOCK)
344 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIMx Break Input and also the PVDE and PLS bits of the Power Control Interface */
345 #endif /*SYSCFG_CFGR2_PVD_LOCK*/
346 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
347 #define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
348 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
349 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMx */
350 /**
351 * @}
352 */
353
354 #if defined(SYSCFG_RCR_PAGE0)
355 /** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCM SRAM WRP
356 * @{
357 */
358 #define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
359 #define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
360 #define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
361 #define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
362 #if defined(SYSCFG_RCR_PAGE4)
363 #define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
364 #define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
365 #define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
366 #define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
367 #endif
368 #if defined(SYSCFG_RCR_PAGE8)
369 #define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_RCR_PAGE8 /*!< ICODE SRAM Write protection page 8 */
370 #define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_RCR_PAGE9 /*!< ICODE SRAM Write protection page 9 */
371 #define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_RCR_PAGE10 /*!< ICODE SRAM Write protection page 10 */
372 #define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_RCR_PAGE11 /*!< ICODE SRAM Write protection page 11 */
373 #define LL_SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_RCR_PAGE12 /*!< ICODE SRAM Write protection page 12 */
374 #define LL_SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_RCR_PAGE13 /*!< ICODE SRAM Write protection page 13 */
375 #define LL_SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_RCR_PAGE14 /*!< ICODE SRAM Write protection page 14 */
376 #define LL_SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_RCR_PAGE15 /*!< ICODE SRAM Write protection page 15 */
377 #endif
378 /**
379 * @}
380 */
381
382 #endif /* SYSCFG_RCR_PAGE0 */
383
384 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
385 * @{
386 */
387 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
388 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
389 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
390 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
391 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
392 /**
393 * @}
394 */
395
396 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
397 * @{
398 */
399 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
400 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
401 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
402 #endif /*DBGMCU_APB1_FZ_DBG_TIM3_STOP*/
403 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
404 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
405 #endif /*DBGMCU_APB1_FZ_DBG_TIM4_STOP*/
406 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
407 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
408 #endif /*DBGMCU_APB1_FZ_DBG_TIM5_STOP*/
409 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
410 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
411 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
412 #endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/
413 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
414 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
415 #endif /*DBGMCU_APB1_FZ_DBG_TIM12_STOP*/
416 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
417 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
418 #endif /*DBGMCU_APB1_FZ_DBG_TIM13_STOP*/
419 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
420 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
421 #endif /*DBGMCU_APB1_FZ_DBG_TIM14_STOP*/
422 #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
423 #define LL_DBGMCU_APB1_GRP1_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP /*!< TIM18 counter stopped when core is halted */
424 #endif /*DBGMCU_APB1_FZ_DBG_TIM18_STOP*/
425 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
426 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
427 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
428 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
429 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
430 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
431 #endif /*DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT*/
432 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
433 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
434 #endif /*DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT*/
435 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
436 #define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopped when Core is halted */
437 #endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/
438 /**
439 * @}
440 */
441
442 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
443 * @{
444 */
445 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
446 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
447 #endif /*DBGMCU_APB2_FZ_DBG_TIM1_STOP*/
448 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
449 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
450 #endif /*DBGMCU_APB2_FZ_DBG_TIM8_STOP*/
451 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
452 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
453 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
454 #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
455 #define LL_DBGMCU_APB2_GRP1_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP /*!< TIM19 counter stopped when core is halted */
456 #endif /*DBGMCU_APB2_FZ_DBG_TIM19_STOP*/
457 #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
458 #define LL_DBGMCU_APB2_GRP1_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP /*!< TIM20 counter stopped when core is halted */
459 #endif /*DBGMCU_APB2_FZ_DBG_TIM20_STOP*/
460 #if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
461 #define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP DBGMCU_APB2_FZ_DBG_HRTIM1_STOP /*!< HRTIM1 counter stopped when core is halted */
462 #endif /*DBGMCU_APB2_FZ_DBG_HRTIM1_STOP*/
463 /**
464 * @}
465 */
466
467 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
468 * @{
469 */
470 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
471 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
472 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
473 /**
474 * @}
475 */
476
477 /**
478 * @}
479 */
480
481 /* Exported macro ------------------------------------------------------------*/
482
483 /* Exported functions --------------------------------------------------------*/
484 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
485 * @{
486 */
487
488 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
489 * @{
490 */
491
492 /**
493 * @brief Set memory mapping at address 0x00000000
494 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
495 * @param Memory This parameter can be one of the following values:
496 * @arg @ref LL_SYSCFG_REMAP_FLASH
497 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
498 * @arg @ref LL_SYSCFG_REMAP_SRAM
499 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
500 *
501 * (*) value not defined in all devices.
502 * @retval None
503 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)504 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
505 {
506 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
507 }
508
509 /**
510 * @brief Get memory mapping at address 0x00000000
511 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
512 * @retval Returned value can be one of the following values:
513 * @arg @ref LL_SYSCFG_REMAP_FLASH
514 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
515 * @arg @ref LL_SYSCFG_REMAP_SRAM
516 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
517 *
518 * (*) value not defined in all devices.
519 */
LL_SYSCFG_GetRemapMemory(void)520 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
521 {
522 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
523 }
524
525 #if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
526 /**
527 * @brief Set DMA request remapping bits for SPI
528 * @rmtoll SYSCFG_CFGR3 SPI1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI\n
529 * SYSCFG_CFGR3 SPI1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
530 * @param Remap This parameter can be one of the following values:
531 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH2
532 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH4
533 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH6
534 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH3
535 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH5
536 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH7
537 * @retval None
538 */
LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)539 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
540 {
541 MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
542 }
543 #endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
544
545 #if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
546 /**
547 * @brief Set DMA request remapping bits for I2C
548 * @rmtoll SYSCFG_CFGR3 I2C1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C\n
549 * SYSCFG_CFGR3 I2C1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
550 * @param Remap This parameter can be one of the following values:
551 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH7
552 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH3
553 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH5
554 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH6
555 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH2
556 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH4
557 * @retval None
558 */
LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)559 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
560 {
561 MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
562 }
563 #endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
564
565 #if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
566 /**
567 * @brief Set DMA request remapping bits for ADC
568 * @rmtoll SYSCFG_CFGR1 ADC24_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC\n
569 * SYSCFG_CFGR3 ADC2_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
570 * @param Remap This parameter can be one of the following values:
571 * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH12 (*)
572 * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH34 (*)
573 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH2 (*)
574 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH4 (*)
575 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA2 (*)
576 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1 (*)
577 *
578 * (*) value not defined in all devices.
579 * @retval None
580 */
LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)581 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
582 {
583 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
584 MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU));
585 }
586 #endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
587
588 /**
589 * @brief Set DMA request remapping bits for DAC
590 * @rmtoll SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC\n
591 * SYSCFG_CFGR1 DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC
592 * @param Remap This parameter can be one of the following values:
593 * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3
594 * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3
595 * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 (*)
596 * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 (*)
597 * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 (*)
598 * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 (*)
599 * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_NO (*)
600 * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 (*)
601 *
602 * (*) value not defined in all devices.
603 * @retval None
604 */
LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap)605 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap)
606 {
607 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
608 }
609
610 /**
611 * @brief Set DMA request remapping bits for TIM
612 * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
613 * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
614 * SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
615 * SYSCFG_CFGR1 TIM7DAC1Ch2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
616 * SYSCFG_CFGR1 TIM18DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
617 * @param Remap This parameter can be a combination of the following values:
618 * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 or @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6
619 * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 or @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7
620 * @arg @ref LL_SYSCFG_TIM6_RMP_DMA2_CH3 or @ref LL_SYSCFG_TIM6_RMP_DMA1_CH3
621 * @arg @ref LL_SYSCFG_TIM7_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*)
622 * @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH5 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*)
623 *
624 * (*) value not defined in all devices.
625 * @retval None
626 */
LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)627 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
628 {
629 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
630 }
631
632 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
633 /**
634 * @brief Set Timer input remap
635 * @rmtoll SYSCFG_CFGR1 TIM1_ITR3_RMP LL_SYSCFG_SetRemapInput_TIM\n
636 * SYSCFG_CFGR1 ENCODER_MODE LL_SYSCFG_SetRemapInput_TIM
637 * @param Remap This parameter can be one of the following values:
638 * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO (*)
639 * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC (*)
640 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION (*)
641 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM2 (*)
642 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM3 (*)
643 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM4 (*)
644 *
645 * (*) value not defined in all devices.
646 * @retval None
647 */
LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap)648 __STATIC_INLINE void LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap)
649 {
650 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU));
651 }
652 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
653
654 #if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
655 /**
656 * @brief Set ADC Trigger remap
657 * @rmtoll SYSCFG_CFGR4 ADC12_EXT2_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
658 * SYSCFG_CFGR4 ADC12_EXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
659 * SYSCFG_CFGR4 ADC12_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
660 * SYSCFG_CFGR4 ADC12_EXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
661 * SYSCFG_CFGR4 ADC12_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
662 * SYSCFG_CFGR4 ADC12_JEXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
663 * SYSCFG_CFGR4 ADC12_JEXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
664 * SYSCFG_CFGR4 ADC12_JEXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
665 * SYSCFG_CFGR4 ADC34_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
666 * SYSCFG_CFGR4 ADC34_EXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
667 * SYSCFG_CFGR4 ADC34_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
668 * SYSCFG_CFGR4 ADC34_JEXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
669 * SYSCFG_CFGR4 ADC34_JEXT11_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
670 * SYSCFG_CFGR4 ADC34_JEXT14_RMP LL_SYSCFG_SetRemapTrigger_ADC
671 * @param Remap This parameter can be one of the following values:
672 * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3
673 * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO
674 * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2
675 * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2
676 * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4
677 * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1
678 * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO
679 * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2
680 * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4
681 * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3
682 * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1
683 * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO
684 * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15
685 * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2
686 * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1
687 * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4
688 * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2
689 * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO
690 * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1
691 * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2
692 * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1
693 * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1
694 * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3
695 * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO
696 * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3
697 * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2
698 * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO
699 * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2
700 * @retval None
701 */
LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)702 __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)
703 {
704 MODIFY_REG(SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU));
705 }
706 #endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
707
708 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
709 /**
710 * @brief Set DAC Trigger remap
711 * @rmtoll SYSCFG_CFGR1 DAC1_TRIG1_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
712 * SYSCFG_CFGR3 DAC1_TRG3_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
713 * SYSCFG_CFGR3 DAC1_TRG5_RMP LL_SYSCFG_SetRemapTrigger_DAC
714 * @param Remap This parameter can be one of the following values:
715 * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (*)
716 * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (*)
717 * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (*)
718 * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (*)
719 * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_NO (*)
720 * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (*)
721 * (*) value not defined in all devices.
722 * @retval None
723 */
LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)724 __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)
725 {
726 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
727 MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U));
728 }
729 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
730
731 #if defined(SYSCFG_CFGR1_USB_IT_RMP)
732 /**
733 * @brief Enable USB interrupt remap
734 * @note Remap the USB interrupts (USB_HP, USB_LP and USB_WKUP) on interrupt lines 74, 75 and 76
735 * respectively
736 * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_EnableRemapIT_USB
737 * @retval None
738 */
LL_SYSCFG_EnableRemapIT_USB(void)739 __STATIC_INLINE void LL_SYSCFG_EnableRemapIT_USB(void)
740 {
741 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
742 }
743
744 /**
745 * @brief Disable USB interrupt remap
746 * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_DisableRemapIT_USB
747 * @retval None
748 */
LL_SYSCFG_DisableRemapIT_USB(void)749 __STATIC_INLINE void LL_SYSCFG_DisableRemapIT_USB(void)
750 {
751 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
752 }
753 #endif /* SYSCFG_CFGR1_USB_IT_RMP */
754
755 #if defined(SYSCFG_CFGR1_VBAT)
756 /**
757 * @brief Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input)
758 * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_EnableVBATMonitoring
759 * @retval None
760 */
LL_SYSCFG_EnableVBATMonitoring(void)761 __STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring(void)
762 {
763 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
764 }
765
766 /**
767 * @brief Disable VBAT monitoring
768 * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_DisableVBATMonitoring
769 * @retval None
770 */
LL_SYSCFG_DisableVBATMonitoring(void)771 __STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring(void)
772 {
773 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
774 }
775 #endif /* SYSCFG_CFGR1_VBAT */
776
777 /**
778 * @brief Enable the I2C fast mode plus driving capability.
779 * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_EnableFastModePlus\n
780 * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_EnableFastModePlus\n
781 * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_EnableFastModePlus\n
782 * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_EnableFastModePlus\n
783 * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_EnableFastModePlus\n
784 * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_EnableFastModePlus\n
785 * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_EnableFastModePlus
786 * @param ConfigFastModePlus This parameter can be a combination of the following values:
787 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
788 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
789 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
790 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
791 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
792 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
793 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
794 *
795 * (*) value not defined in all devices.
796 * @retval None
797 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)798 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
799 {
800 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
801 }
802
803 /**
804 * @brief Disable the I2C fast mode plus driving capability.
805 * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_DisableFastModePlus\n
806 * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_DisableFastModePlus\n
807 * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_DisableFastModePlus\n
808 * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_DisableFastModePlus\n
809 * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_DisableFastModePlus\n
810 * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_DisableFastModePlus\n
811 * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_DisableFastModePlus
812 * @param ConfigFastModePlus This parameter can be a combination of the following values:
813 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
814 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
815 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
816 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
817 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
818 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
819 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
820 *
821 * (*) value not defined in all devices.
822 * @retval None
823 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)824 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
825 {
826 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
827 }
828
829 /**
830 * @brief Enable Floating Point Unit Invalid operation Interrupt
831 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
832 * @retval None
833 */
LL_SYSCFG_EnableIT_FPU_IOC(void)834 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
835 {
836 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
837 }
838
839 /**
840 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
841 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
842 * @retval None
843 */
LL_SYSCFG_EnableIT_FPU_DZC(void)844 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
845 {
846 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
847 }
848
849 /**
850 * @brief Enable Floating Point Unit Underflow Interrupt
851 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
852 * @retval None
853 */
LL_SYSCFG_EnableIT_FPU_UFC(void)854 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
855 {
856 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
857 }
858
859 /**
860 * @brief Enable Floating Point Unit Overflow Interrupt
861 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
862 * @retval None
863 */
LL_SYSCFG_EnableIT_FPU_OFC(void)864 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
865 {
866 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
867 }
868
869 /**
870 * @brief Enable Floating Point Unit Input denormal Interrupt
871 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
872 * @retval None
873 */
LL_SYSCFG_EnableIT_FPU_IDC(void)874 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
875 {
876 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
877 }
878
879 /**
880 * @brief Enable Floating Point Unit Inexact Interrupt
881 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
882 * @retval None
883 */
LL_SYSCFG_EnableIT_FPU_IXC(void)884 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
885 {
886 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
887 }
888
889 /**
890 * @brief Disable Floating Point Unit Invalid operation Interrupt
891 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
892 * @retval None
893 */
LL_SYSCFG_DisableIT_FPU_IOC(void)894 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
895 {
896 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
897 }
898
899 /**
900 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
901 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
902 * @retval None
903 */
LL_SYSCFG_DisableIT_FPU_DZC(void)904 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
905 {
906 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
907 }
908
909 /**
910 * @brief Disable Floating Point Unit Underflow Interrupt
911 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
912 * @retval None
913 */
LL_SYSCFG_DisableIT_FPU_UFC(void)914 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
915 {
916 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
917 }
918
919 /**
920 * @brief Disable Floating Point Unit Overflow Interrupt
921 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
922 * @retval None
923 */
LL_SYSCFG_DisableIT_FPU_OFC(void)924 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
925 {
926 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
927 }
928
929 /**
930 * @brief Disable Floating Point Unit Input denormal Interrupt
931 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
932 * @retval None
933 */
LL_SYSCFG_DisableIT_FPU_IDC(void)934 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
935 {
936 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
937 }
938
939 /**
940 * @brief Disable Floating Point Unit Inexact Interrupt
941 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
942 * @retval None
943 */
LL_SYSCFG_DisableIT_FPU_IXC(void)944 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
945 {
946 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
947 }
948
949 /**
950 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
951 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
952 * @retval State of bit (1 or 0).
953 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)954 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
955 {
956 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
957 }
958
959 /**
960 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
961 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
962 * @retval State of bit (1 or 0).
963 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)964 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
965 {
966 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
967 }
968
969 /**
970 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
971 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
972 * @retval State of bit (1 or 0).
973 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)974 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
975 {
976 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
977 }
978
979 /**
980 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
981 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
982 * @retval State of bit (1 or 0).
983 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)984 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
985 {
986 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
987 }
988
989 /**
990 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
991 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
992 * @retval State of bit (1 or 0).
993 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)994 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
995 {
996 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
997 }
998
999 /**
1000 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
1001 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
1002 * @retval State of bit (1 or 0).
1003 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)1004 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
1005 {
1006 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
1007 }
1008
1009 /**
1010 * @brief Configure source input for the EXTI external interrupt.
1011 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
1012 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
1013 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
1014 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
1015 * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n
1016 * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n
1017 * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n
1018 * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n
1019 * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n
1020 * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n
1021 * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n
1022 * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n
1023 * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n
1024 * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n
1025 * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n
1026 * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n
1027 * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n
1028 * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n
1029 * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n
1030 * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n
1031 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
1032 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
1033 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
1034 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
1035 * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n
1036 * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n
1037 * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n
1038 * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n
1039 * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n
1040 * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n
1041 * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n
1042 * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n
1043 * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n
1044 * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n
1045 * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n
1046 * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n
1047 * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n
1048 * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n
1049 * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n
1050 * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n
1051 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
1052 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
1053 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
1054 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
1055 * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n
1056 * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n
1057 * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n
1058 * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n
1059 * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n
1060 * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n
1061 * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n
1062 * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n
1063 * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n
1064 * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n
1065 * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n
1066 * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n
1067 * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n
1068 * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n
1069 * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n
1070 * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n
1071 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
1072 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
1073 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
1074 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
1075 * @param Port This parameter can be one of the following values:
1076 * @arg @ref LL_SYSCFG_EXTI_PORTA
1077 * @arg @ref LL_SYSCFG_EXTI_PORTB
1078 * @arg @ref LL_SYSCFG_EXTI_PORTC
1079 * @arg @ref LL_SYSCFG_EXTI_PORTD
1080 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
1081 * @arg @ref LL_SYSCFG_EXTI_PORTF
1082 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
1083 * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
1084 *
1085 * (*) value not defined in all devices.
1086 * @param Line This parameter can be one of the following values:
1087 * @arg @ref LL_SYSCFG_EXTI_LINE0
1088 * @arg @ref LL_SYSCFG_EXTI_LINE1
1089 * @arg @ref LL_SYSCFG_EXTI_LINE2
1090 * @arg @ref LL_SYSCFG_EXTI_LINE3
1091 * @arg @ref LL_SYSCFG_EXTI_LINE4
1092 * @arg @ref LL_SYSCFG_EXTI_LINE5
1093 * @arg @ref LL_SYSCFG_EXTI_LINE6
1094 * @arg @ref LL_SYSCFG_EXTI_LINE7
1095 * @arg @ref LL_SYSCFG_EXTI_LINE8
1096 * @arg @ref LL_SYSCFG_EXTI_LINE9
1097 * @arg @ref LL_SYSCFG_EXTI_LINE10
1098 * @arg @ref LL_SYSCFG_EXTI_LINE11
1099 * @arg @ref LL_SYSCFG_EXTI_LINE12
1100 * @arg @ref LL_SYSCFG_EXTI_LINE13
1101 * @arg @ref LL_SYSCFG_EXTI_LINE14
1102 * @arg @ref LL_SYSCFG_EXTI_LINE15
1103 * @retval None
1104 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)1105 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
1106 {
1107 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
1108 }
1109
1110 /**
1111 * @brief Get the configured defined for specific EXTI Line
1112 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n
1113 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n
1114 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n
1115 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n
1116 * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n
1117 * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n
1118 * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n
1119 * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n
1120 * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n
1121 * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n
1122 * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n
1123 * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n
1124 * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n
1125 * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n
1126 * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n
1127 * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n
1128 * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n
1129 * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n
1130 * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n
1131 * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n
1132 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n
1133 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n
1134 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n
1135 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n
1136 * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n
1137 * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n
1138 * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n
1139 * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n
1140 * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n
1141 * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n
1142 * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n
1143 * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n
1144 * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n
1145 * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n
1146 * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n
1147 * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n
1148 * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n
1149 * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n
1150 * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n
1151 * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n
1152 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n
1153 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n
1154 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n
1155 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n
1156 * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n
1157 * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n
1158 * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n
1159 * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n
1160 * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n
1161 * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n
1162 * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n
1163 * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n
1164 * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n
1165 * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n
1166 * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n
1167 * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n
1168 * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n
1169 * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n
1170 * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n
1171 * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n
1172 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n
1173 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n
1174 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n
1175 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource
1176 * @param Line This parameter can be one of the following values:
1177 * @arg @ref LL_SYSCFG_EXTI_LINE0
1178 * @arg @ref LL_SYSCFG_EXTI_LINE1
1179 * @arg @ref LL_SYSCFG_EXTI_LINE2
1180 * @arg @ref LL_SYSCFG_EXTI_LINE3
1181 * @arg @ref LL_SYSCFG_EXTI_LINE4
1182 * @arg @ref LL_SYSCFG_EXTI_LINE5
1183 * @arg @ref LL_SYSCFG_EXTI_LINE6
1184 * @arg @ref LL_SYSCFG_EXTI_LINE7
1185 * @arg @ref LL_SYSCFG_EXTI_LINE8
1186 * @arg @ref LL_SYSCFG_EXTI_LINE9
1187 * @arg @ref LL_SYSCFG_EXTI_LINE10
1188 * @arg @ref LL_SYSCFG_EXTI_LINE11
1189 * @arg @ref LL_SYSCFG_EXTI_LINE12
1190 * @arg @ref LL_SYSCFG_EXTI_LINE13
1191 * @arg @ref LL_SYSCFG_EXTI_LINE14
1192 * @arg @ref LL_SYSCFG_EXTI_LINE15
1193 * @retval Returned value can be one of the following values:
1194 * @arg @ref LL_SYSCFG_EXTI_PORTA
1195 * @arg @ref LL_SYSCFG_EXTI_PORTB
1196 * @arg @ref LL_SYSCFG_EXTI_PORTC
1197 * @arg @ref LL_SYSCFG_EXTI_PORTD
1198 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
1199 * @arg @ref LL_SYSCFG_EXTI_PORTF
1200 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
1201 * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
1202 *
1203 * (*) value not defined in all devices.
1204 */
LL_SYSCFG_GetEXTISource(uint32_t Line)1205 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
1206 {
1207 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
1208 }
1209
1210 /**
1211 * @brief Set connections to TIMx Break inputs
1212 * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
1213 * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
1214 * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
1215 * @param Break This parameter can be a combination of the following values:
1216 * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
1217 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
1218 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
1219 *
1220 * (*) value not defined in all devices.
1221 * @retval None
1222 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)1223 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
1224 {
1225 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break);
1226 }
1227
1228 /**
1229 * @brief Get connections to TIMx Break inputs
1230 * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
1231 * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
1232 * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
1233 * @retval Returned value can be can be a combination of the following values:
1234 * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
1235 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
1236 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
1237 *
1238 * (*) value not defined in all devices.
1239 */
LL_SYSCFG_GetTIMBreakInputs(void)1240 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
1241 {
1242 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK));
1243 }
1244
1245 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
1246 /**
1247 * @brief Disable RAM Parity Check Disable
1248 * @rmtoll SYSCFG_CFGR2 BYP_ADDR_PAR LL_SYSCFG_DisableSRAMParityCheck
1249 * @retval None
1250 */
LL_SYSCFG_DisableSRAMParityCheck(void)1251 __STATIC_INLINE void LL_SYSCFG_DisableSRAMParityCheck(void)
1252 {
1253 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR);
1254 }
1255 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
1256
1257 #if defined(SYSCFG_CFGR2_SRAM_PE)
1258 /**
1259 * @brief Check if SRAM parity error detected
1260 * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_IsActiveFlag_SP
1261 * @retval State of bit (1 or 0).
1262 */
LL_SYSCFG_IsActiveFlag_SP(void)1263 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
1264 {
1265 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE));
1266 }
1267
1268 /**
1269 * @brief Clear SRAM parity error flag
1270 * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_ClearFlag_SP
1271 * @retval None
1272 */
LL_SYSCFG_ClearFlag_SP(void)1273 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
1274 {
1275 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE);
1276 }
1277 #endif /* SYSCFG_CFGR2_SRAM_PE */
1278
1279 #if defined(SYSCFG_RCR_PAGE0)
1280 /**
1281 * @brief Enable CCM SRAM page write protection
1282 * @note Write protection is cleared only by a system reset
1283 * @rmtoll SYSCFG_RCR PAGE0 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1284 * SYSCFG_RCR PAGE1 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1285 * SYSCFG_RCR PAGE2 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1286 * SYSCFG_RCR PAGE3 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1287 * SYSCFG_RCR PAGE4 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1288 * SYSCFG_RCR PAGE5 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1289 * SYSCFG_RCR PAGE6 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1290 * SYSCFG_RCR PAGE7 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1291 * SYSCFG_RCR PAGE8 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1292 * SYSCFG_RCR PAGE9 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1293 * SYSCFG_RCR PAGE10 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1294 * SYSCFG_RCR PAGE11 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1295 * SYSCFG_RCR PAGE12 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1296 * SYSCFG_RCR PAGE13 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1297 * SYSCFG_RCR PAGE14 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1298 * SYSCFG_RCR PAGE15 LL_SYSCFG_EnableCCM_SRAMPageWRP
1299 * @param PageWRP This parameter can be a combination of the following values:
1300 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
1301 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
1302 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
1303 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
1304 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4 (*)
1305 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5 (*)
1306 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6 (*)
1307 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7 (*)
1308 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8 (*)
1309 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9 (*)
1310 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
1311 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
1312 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
1313 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
1314 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
1315 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
1316 *
1317 * (*) value not defined in all devices.
1318 * @retval None
1319 */
LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP)1320 __STATIC_INLINE void LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP)
1321 {
1322 SET_BIT(SYSCFG->RCR, PageWRP);
1323 }
1324 #endif /* SYSCFG_RCR_PAGE0 */
1325
1326 /**
1327 * @}
1328 */
1329
1330 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1331 * @{
1332 */
1333
1334 /**
1335 * @brief Return the device identifier
1336 * @note For STM32F303xC, STM32F358xx and STM32F302xC devices, the device ID is 0x422
1337 * @note For STM32F373xx and STM32F378xx devices, the device ID is 0x432
1338 * @note For STM32F303x8, STM32F334xx and STM32F328xx devices, the device ID is 0x438.
1339 * @note For STM32F302x8, STM32F301x8 and STM32F318xx devices, the device ID is 0x439
1340 * @note For STM32F303xE, STM32F398xx and STM32F302xE devices, the device ID is 0x446
1341 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1342 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1343 */
LL_DBGMCU_GetDeviceID(void)1344 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1345 {
1346 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1347 }
1348
1349 /**
1350 * @brief Return the device revision identifier
1351 * @note This field indicates the revision of the device.
1352 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1353 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1354 */
LL_DBGMCU_GetRevisionID(void)1355 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1356 {
1357 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1358 }
1359
1360 /**
1361 * @brief Enable the Debug Module during SLEEP mode
1362 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
1363 * @retval None
1364 */
LL_DBGMCU_EnableDBGSleepMode(void)1365 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1366 {
1367 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1368 }
1369
1370 /**
1371 * @brief Disable the Debug Module during SLEEP mode
1372 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
1373 * @retval None
1374 */
LL_DBGMCU_DisableDBGSleepMode(void)1375 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1376 {
1377 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1378 }
1379
1380 /**
1381 * @brief Enable the Debug Module during STOP mode
1382 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1383 * @retval None
1384 */
LL_DBGMCU_EnableDBGStopMode(void)1385 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1386 {
1387 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1388 }
1389
1390 /**
1391 * @brief Disable the Debug Module during STOP mode
1392 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1393 * @retval None
1394 */
LL_DBGMCU_DisableDBGStopMode(void)1395 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1396 {
1397 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1398 }
1399
1400 /**
1401 * @brief Enable the Debug Module during STANDBY mode
1402 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1403 * @retval None
1404 */
LL_DBGMCU_EnableDBGStandbyMode(void)1405 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1406 {
1407 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1408 }
1409
1410 /**
1411 * @brief Disable the Debug Module during STANDBY mode
1412 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1413 * @retval None
1414 */
LL_DBGMCU_DisableDBGStandbyMode(void)1415 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1416 {
1417 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1418 }
1419
1420 /**
1421 * @brief Set Trace pin assignment control
1422 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
1423 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1424 * @param PinAssignment This parameter can be one of the following values:
1425 * @arg @ref LL_DBGMCU_TRACE_NONE
1426 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1427 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1428 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1429 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1430 * @retval None
1431 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1432 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1433 {
1434 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1435 }
1436
1437 /**
1438 * @brief Get Trace pin assignment control
1439 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1440 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1441 * @retval Returned value can be one of the following values:
1442 * @arg @ref LL_DBGMCU_TRACE_NONE
1443 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1444 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1445 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1446 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1447 */
LL_DBGMCU_GetTracePinAssignment(void)1448 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1449 {
1450 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1451 }
1452
1453 /**
1454 * @brief Freeze APB1 peripherals (group1 peripherals)
1455 * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1456 * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1457 * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1458 * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1459 * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1460 * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1461 * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1462 * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1463 * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1464 * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1465 * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1466 * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1467 * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1468 * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1469 * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1470 * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1471 * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1472 * @param Periphs This parameter can be a combination of the following values:
1473 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1474 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1475 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1476 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1477 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1478 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1479 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
1480 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
1481 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
1482 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
1483 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1484 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1485 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1486 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1487 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1488 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
1489 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
1490 *
1491 * (*) value not defined in all devices.
1492 * @retval None
1493 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1494 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1495 {
1496 SET_BIT(DBGMCU->APB1FZ, Periphs);
1497 }
1498
1499 /**
1500 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1501 * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1502 * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1503 * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1504 * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1505 * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1506 * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1507 * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1508 * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1509 * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1510 * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1511 * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1512 * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1513 * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1514 * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1515 * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1516 * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1517 * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1518 * @param Periphs This parameter can be a combination of the following values:
1519 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1520 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1521 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1522 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1523 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1524 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1525 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
1526 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
1527 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
1528 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
1529 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1530 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1531 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1532 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1533 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1534 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
1535 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
1536 *
1537 * (*) value not defined in all devices.
1538 * @retval None
1539 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1540 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1541 {
1542 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
1543 }
1544
1545 /**
1546 * @brief Freeze APB2 peripherals
1547 * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1548 * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1549 * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1550 * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1551 * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1552 * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1553 * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1554 * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1555 * @param Periphs This parameter can be a combination of the following values:
1556 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
1557 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1558 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1559 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1560 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1561 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
1562 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
1563 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
1564 *
1565 * (*) value not defined in all devices.
1566 * @retval None
1567 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1568 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1569 {
1570 SET_BIT(DBGMCU->APB2FZ, Periphs);
1571 }
1572
1573 /**
1574 * @brief Unfreeze APB2 peripherals
1575 * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1576 * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1577 * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1578 * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1579 * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1580 * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1581 * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1582 * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1583 * @param Periphs This parameter can be a combination of the following values:
1584 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
1585 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1586 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1587 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1588 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1589 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
1590 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
1591 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
1592 *
1593 * (*) value not defined in all devices.
1594 * @retval None
1595 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1596 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1597 {
1598 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1599 }
1600
1601 /**
1602 * @}
1603 */
1604
1605 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1606 * @{
1607 */
1608
1609 /**
1610 * @brief Set FLASH Latency
1611 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1612 * @param Latency This parameter can be one of the following values:
1613 * @arg @ref LL_FLASH_LATENCY_0
1614 * @arg @ref LL_FLASH_LATENCY_1
1615 * @arg @ref LL_FLASH_LATENCY_2
1616 * @retval None
1617 */
LL_FLASH_SetLatency(uint32_t Latency)1618 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1619 {
1620 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1621 }
1622
1623 /**
1624 * @brief Get FLASH Latency
1625 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1626 * @retval Returned value can be one of the following values:
1627 * @arg @ref LL_FLASH_LATENCY_0
1628 * @arg @ref LL_FLASH_LATENCY_1
1629 * @arg @ref LL_FLASH_LATENCY_2
1630 */
LL_FLASH_GetLatency(void)1631 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1632 {
1633 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1634 }
1635
1636 /**
1637 * @brief Enable Prefetch
1638 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
1639 * @retval None
1640 */
LL_FLASH_EnablePrefetch(void)1641 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1642 {
1643 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
1644 }
1645
1646 /**
1647 * @brief Disable Prefetch
1648 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
1649 * @retval None
1650 */
LL_FLASH_DisablePrefetch(void)1651 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1652 {
1653 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
1654 }
1655
1656 /**
1657 * @brief Check if Prefetch buffer is enabled
1658 * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
1659 * @retval State of bit (1 or 0).
1660 */
LL_FLASH_IsPrefetchEnabled(void)1661 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1662 {
1663 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
1664 }
1665
1666 #if defined(FLASH_ACR_HLFCYA)
1667 /**
1668 * @brief Enable Flash Half Cycle Access
1669 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
1670 * @retval None
1671 */
LL_FLASH_EnableHalfCycleAccess(void)1672 __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
1673 {
1674 SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
1675 }
1676
1677 /**
1678 * @brief Disable Flash Half Cycle Access
1679 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
1680 * @retval None
1681 */
LL_FLASH_DisableHalfCycleAccess(void)1682 __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
1683 {
1684 CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
1685 }
1686
1687 /**
1688 * @brief Check if Flash Half Cycle Access is enabled or not
1689 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
1690 * @retval State of bit (1 or 0).
1691 */
LL_FLASH_IsHalfCycleAccessEnabled(void)1692 __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
1693 {
1694 return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
1695 }
1696 #endif /* FLASH_ACR_HLFCYA */
1697
1698
1699
1700 /**
1701 * @}
1702 */
1703
1704 /**
1705 * @}
1706 */
1707
1708 /**
1709 * @}
1710 */
1711
1712 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1713
1714 /**
1715 * @}
1716 */
1717
1718 #ifdef __cplusplus
1719 }
1720 #endif
1721
1722 #endif /* __STM32F3xx_LL_SYSTEM_H */
1723
1724 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1725
