1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L5xx_LL_PWR_H
22 #define STM32L5xx_LL_PWR_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l5xx.h"
30
31 /** @addtogroup STM32L5xx_LL_Driver
32 * @{
33 */
34
35 #if defined(PWR)
36
37 /** @defgroup PWR_LL PWR
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45
46 /* Private macros ------------------------------------------------------------*/
47
48 /* Exported types ------------------------------------------------------------*/
49 /* Exported constants --------------------------------------------------------*/
50 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
51 * @{
52 */
53
54 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
55 * @brief Flags defines which can be used with LL_PWR_WriteReg function
56 * @{
57 */
58 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF
59 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
60 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
61 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
62 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
63 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
64 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
65 /**
66 * @}
67 */
68
69 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
70 * @brief Flags defines which can be used with LL_PWR_ReadReg function
71 * @{
72 */
73 #define LL_PWR_SR1_SMSHPRDY PWR_SR1_SMSHPRDY
74 #define LL_PWR_SR1_EXTSMSRDY PWR_SR1_EXTSMSRDY
75 #define LL_PWR_SR1_SMSBYPRDY PWR_SR1_SMSBYPRDYY
76 #define LL_PWR_SR1_SBF PWR_SR1_SBF
77 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
78 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
79 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
80 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
81 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
82 #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
83 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
84 #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
85 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
86 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
87 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
88 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
89 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
90 /**
91 * @}
92 */
93
94 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
95 * @{
96 */
97 #define LL_PWR_REGU_VOLTAGE_SCALE0 0U
98 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
99 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
100 /**
101 * @}
102 */
103
104 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
105 * @{
106 */
107 #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
108 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
109 #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2)
110 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
111 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
112 /**
113 * @}
114 */
115
116 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
117 * @{
118 */
119 #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2 V */
120 #define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9 V */
121 #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62 V */
122 #define LL_PWR_PVM_VDDA_1_8V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 1.8 V */
123 /**
124 * @}
125 */
126
127 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
128 * @{
129 */
130 #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
131 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
132 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
133 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
134 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
135 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
136 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
137 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
138 /**
139 * @}
140 */
141
142 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
143 * @{
144 */
145 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
146 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
147 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
148 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
149 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
150 /**
151 * @}
152 */
153
154 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
155 * @{
156 */
157 #define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U)
158 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
159 /**
160 * @}
161 */
162
163 /** @defgroup PWR_LL_EC_GPIO GPIO
164 * @{
165 */
166 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
167 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
168 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
169 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
170 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
171 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
172 #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
173 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
174 /**
175 * @}
176 */
177
178 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
179 * @{
180 */
181 #define LL_PWR_GPIO_BIT_0 (0x00000001U)
182 #define LL_PWR_GPIO_BIT_1 (0x00000002U)
183 #define LL_PWR_GPIO_BIT_2 (0x00000004U)
184 #define LL_PWR_GPIO_BIT_3 (0x00000008U)
185 #define LL_PWR_GPIO_BIT_4 (0x00000010U)
186 #define LL_PWR_GPIO_BIT_5 (0x00000020U)
187 #define LL_PWR_GPIO_BIT_6 (0x00000040U)
188 #define LL_PWR_GPIO_BIT_7 (0x00000080U)
189 #define LL_PWR_GPIO_BIT_8 (0x00000100U)
190 #define LL_PWR_GPIO_BIT_9 (0x00000200U)
191 #define LL_PWR_GPIO_BIT_10 (0x00000400U)
192 #define LL_PWR_GPIO_BIT_11 (0x00000800U)
193 #define LL_PWR_GPIO_BIT_12 (0x00001000U)
194 #define LL_PWR_GPIO_BIT_13 (0x00002000U)
195 #define LL_PWR_GPIO_BIT_14 (0x00004000U)
196 #define LL_PWR_GPIO_BIT_15 (0x00008000U)
197 /**
198 * @}
199 */
200
201 /** @defgroup PWR_LL_EC_SRAM2_STANDBY_RETENTION SRAM2 STANDBY RETENTION
202 * @{
203 */
204 #define LL_PWR_SRAM2_NO_RETENTION 0x00000000U
205 #define LL_PWR_SRAM2_FULL_RETENTION (PWR_CR3_RRS_0)
206 #define LL_PWR_SRAM2_4KB_RETENTION (PWR_CR3_RRS_1)
207 /**
208 * @}
209 */
210
211 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
212 /** @defgroup PWR_LL_EC_SECURE_ATTRIBUTES SECURE ATTRIBUTES
213 * @{
214 */
215 #define LL_PWR_WAKEUP_PINS_SEC PWR_SECCFGR_WUPSEC
216 #define LL_PWR_WAKEUP_PINS_NSEC 0x00000000U
217 #define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC
218 #define LL_PWR_WAKEUP_PIN1_NSEC 0x00000000U
219 #define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC
220 #define LL_PWR_WAKEUP_PIN2_NSEC 0x00000000U
221 #define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC
222 #define LL_PWR_WAKEUP_PIN3_NSEC 0x00000000U
223 #define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC
224 #define LL_PWR_WAKEUP_PIN4_NSEC 0x00000000U
225 #define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC
226 #define LL_PWR_WAKEUP_PIN5_NSEC 0x00000000U
227 #define LL_PWR_LPM_SEC PWR_SECCFGR_LPMSEC
228 #define LL_PWR_LPM_NSEC 0x00000000U
229 #define LL_PWR_VDM_SEC PWR_SECCFGR_VDMSEC
230 #define LL_PWR_VDM_NSEC 0x00000000U
231 #define LL_PWR_VB_SEC PWR_SECCFGR_VBSEC
232 #define LL_PWR_VB_NSEC 0x00000000U
233 #define LL_PWR_APC_SEC PWR_SECCFGR_APCSEC
234 #define LL_PWR_APC_NSEC 0x00000000U
235 /**
236 * @}
237 */
238 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
239
240 /**
241 * @}
242 */
243
244 /* Exported macro ------------------------------------------------------------*/
245 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
246 * @{
247 */
248
249 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
250 * @{
251 */
252
253 /**
254 * @brief Write a value in PWR register
255 * @param __REG__ Register to be written
256 * @param __VALUE__ Value to be written in the register
257 * @retval None
258 */
259 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
260
261 /**
262 * @brief Read a value in PWR register
263 * @param __REG__ Register to be read
264 * @retval Register value
265 */
266 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
267 /**
268 * @}
269 */
270
271 /**
272 * @}
273 */
274
275
276 /* Exported functions --------------------------------------------------------*/
277 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
278 * @{
279 */
280
281 /** @defgroup PWR_LL_EF_Configuration Configuration
282 * @{
283 */
284
285 /**
286 * @brief Switch the regulator from main mode to low-power mode
287 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
288 * @retval None
289 */
LL_PWR_EnableLowPowerRunMode(void)290 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
291 {
292 SET_BIT(PWR->CR1, PWR_CR1_LPR);
293 }
294
295 /**
296 * @brief Switch the regulator from low-power mode to main mode
297 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
298 * @retval None
299 */
LL_PWR_DisableLowPowerRunMode(void)300 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
301 {
302 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
303 }
304
305 /**
306 * @brief Check if the regulator is in low-power mode
307 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
308 * @retval State of bit (1 or 0).
309 */
LL_PWR_IsEnabledLowPowerRunMode(void)310 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
311 {
312 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
313 }
314
315 /**
316 * @brief Switch from run main mode to run low-power mode.
317 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
318 * @retval None
319 */
LL_PWR_EnterLowPowerRunMode(void)320 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
321 {
322 LL_PWR_EnableLowPowerRunMode();
323 }
324
325 /**
326 * @brief Switch from run main mode to low-power mode.
327 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
328 * @retval None
329 */
LL_PWR_ExitLowPowerRunMode(void)330 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
331 {
332 LL_PWR_DisableLowPowerRunMode();
333 }
334
335 /**
336 * @brief Set the main internal regulator output voltage
337 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
338 * @param VoltageScaling This parameter can be one of the following values:
339 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
340 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
341 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
342 * @retval None
343 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)344 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
345 {
346 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
347 }
348
349 /**
350 * @brief Get the main internal regulator output voltage
351 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
352 * @retval Returned value can be one of the following values:
353 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
354 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
355 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
356 */
LL_PWR_GetRegulVoltageScaling(void)357 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
358 {
359 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
360 }
361
362 /**
363 * @brief Enable access to the backup domain
364 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
365 * @retval None
366 */
LL_PWR_EnableBkUpAccess(void)367 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
368 {
369 SET_BIT(PWR->CR1, PWR_CR1_DBP);
370 }
371
372 /**
373 * @brief Disable access to the backup domain
374 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
375 * @retval None
376 */
LL_PWR_DisableBkUpAccess(void)377 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
378 {
379 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
380 }
381
382 /**
383 * @brief Check if the backup domain is enabled
384 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
385 * @retval State of bit (1 or 0).
386 */
LL_PWR_IsEnabledBkUpAccess(void)387 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
388 {
389 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
390 }
391
392 /**
393 * @brief Set Low-Power mode
394 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
395 * @param LowPowerMode This parameter can be one of the following values:
396 * @arg @ref LL_PWR_MODE_STOP0
397 * @arg @ref LL_PWR_MODE_STOP1
398 * @arg @ref LL_PWR_MODE_STOP2
399 * @arg @ref LL_PWR_MODE_STANDBY
400 * @arg @ref LL_PWR_MODE_SHUTDOWN
401 * @retval None
402 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)403 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
404 {
405 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
406 }
407
408 /**
409 * @brief Get Low-Power mode
410 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
411 * @retval Returned value can be one of the following values:
412 * @arg @ref LL_PWR_MODE_STOP0
413 * @arg @ref LL_PWR_MODE_STOP1
414 * @arg @ref LL_PWR_MODE_STOP2
415 * @arg @ref LL_PWR_MODE_STANDBY
416 * @arg @ref LL_PWR_MODE_SHUTDOWN
417 */
LL_PWR_GetPowerMode(void)418 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
419 {
420 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
421 }
422
423 /**
424 * @brief Enable the USB Type-C and Power Delivery memorization in Standby mode.
425 * @note This function must be called just before entering Standby mode.
426 * @rmtoll CR3 UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
427 * @retval None
428 */
LL_PWR_EnableUCPDStandbyMode(void)429 __STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
430 {
431 SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
432 }
433
434 /**
435 * @brief Disable the USB Type-C and Power Delivery memorization in Standby mode.
436 * @note This function must be called after exiting Standby mode and before any
437 * UCPD configuration update.
438 * @rmtoll CR3 UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
439 * @retval None
440 */
LL_PWR_DisableUCPDStandbyMode(void)441 __STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
442 {
443 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
444 }
445
446 /**
447 * @brief Check the USB Type-C and Power Delivery Standby mode memorization state.
448 * @rmtoll CR3 UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
449 * @retval State of bit (1 or 0).
450 */
LL_PWR_IsEnabledUCPDStandbyMode(void)451 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
452 {
453
454 return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY)) ? 1UL : 0UL);
455
456 }
457
458 /**
459 * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
460 * on UCPD CC1 and CC2 pins.
461 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
462 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
463 * to disable it in all cases, either to stop this pull-down or to hand over
464 * control to the UCPD (which should therefore be initialized before doing the disable).
465 * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
466 * @retval None
467 */
LL_PWR_EnableUCPDDeadBattery(void)468 __STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
469 {
470 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
471 }
472
473 /**
474 * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
475 * on UCPD CC1 and CC2 pins.
476 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
477 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
478 * to disable it in all cases, either to stop this pull-down or to hand over
479 * control to the UCPD (which should therefore be initialized before doing the disable).
480 * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
481 * @retval None
482 */
LL_PWR_DisableUCPDDeadBattery(void)483 __STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
484 {
485 SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
486 }
487
488 /**
489 * @brief Check the USB Type-C and power delivery dead battery pull-down behavior
490 * on UCPD CC1 and CC2 pins.
491 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
492 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
493 * to disable it in all cases, either to stop this pull-down or to hand over
494 * control to the UCPD (which should therefore be initialized before doing the disable).
495 * @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
496 * @retval State of feature (1 : enabled; 0 : disabled).
497 */
LL_PWR_IsEnabledUCPDDeadBattery(void)498 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
499 {
500 return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL);
501 }
502
503 /**
504 * @brief Enable VDDUSB supply
505 * @rmtoll CR2 USV LL_PWR_EnableVddUSB
506 * @retval None
507 */
LL_PWR_EnableVddUSB(void)508 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
509 {
510 SET_BIT(PWR->CR2, PWR_CR2_USV);
511 }
512
513 /**
514 * @brief Disable VDDUSB supply
515 * @rmtoll CR2 USV LL_PWR_DisableVddUSB
516 * @retval None
517 */
LL_PWR_DisableVddUSB(void)518 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
519 {
520 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
521 }
522
523 /**
524 * @brief Check if VDDUSB supply is enabled
525 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
526 * @retval State of bit (1 or 0).
527 */
LL_PWR_IsEnabledVddUSB(void)528 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
529 {
530 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
531 }
532
533 /**
534 * @brief Enable VDDIO2 supply
535 * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
536 * @retval None
537 */
LL_PWR_EnableVddIO2(void)538 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
539 {
540 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
541 }
542
543 /**
544 * @brief Disable VDDIO2 supply
545 * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
546 * @retval None
547 */
LL_PWR_DisableVddIO2(void)548 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
549 {
550 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
551 }
552
553 /**
554 * @brief Check if VDDIO2 supply is enabled
555 * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
556 * @retval State of bit (1 or 0).
557 */
LL_PWR_IsEnabledVddIO2(void)558 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
559 {
560 return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL);
561 }
562
563 /**
564 * @brief Enable the Power Voltage Monitoring on a peripheral
565 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
566 * CR2 PVME2 LL_PWR_EnablePVM\n
567 * CR2 PVME3 LL_PWR_EnablePVM\n
568 * CR2 PVME4 LL_PWR_EnablePVM
569 * @param PeriphVoltage This parameter can be one of the following values:
570 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V
571 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V
572 * @arg @ref LL_PWR_PVM_VDDA_1_62V
573 * @arg @ref LL_PWR_PVM_VDDA_1_8V
574 * @retval None
575 */
LL_PWR_EnablePVM(uint32_t PeriphVoltage)576 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
577 {
578 SET_BIT(PWR->CR2, PeriphVoltage);
579 }
580
581 /**
582 * @brief Disable the Power Voltage Monitoring on a peripheral
583 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
584 * CR2 PVME2 LL_PWR_DisablePVM\n
585 * CR2 PVME3 LL_PWR_DisablePVM\n
586 * CR2 PVME4 LL_PWR_DisablePVM
587 * @param PeriphVoltage This parameter can be one of the following values:
588 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V
589 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V
590 * @arg @ref LL_PWR_PVM_VDDA_1_62V
591 * @arg @ref LL_PWR_PVM_VDDA_1_8V
592 * @retval None
593 */
LL_PWR_DisablePVM(uint32_t PeriphVoltage)594 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
595 {
596 CLEAR_BIT(PWR->CR2, PeriphVoltage);
597 }
598
599 /**
600 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
601 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
602 * CR2 PVME2 LL_PWR_IsEnabledPVM\n
603 * CR2 PVME3 LL_PWR_IsEnabledPVM\n
604 * CR2 PVME4 LL_PWR_IsEnabledPVM
605 * @param PeriphVoltage This parameter can be one of the following values:
606 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V
607 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V
608 * @arg @ref LL_PWR_PVM_VDDA_1_62V
609 * @arg @ref LL_PWR_PVM_VDDA_1_8V
610 * @retval State of bit (1 or 0).
611 */
LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)612 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
613 {
614 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
615 }
616
617 /**
618 * @brief Configure the voltage threshold detected by the Power Voltage Detector
619 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
620 * @param PVDLevel This parameter can be one of the following values:
621 * @arg @ref LL_PWR_PVDLEVEL_0
622 * @arg @ref LL_PWR_PVDLEVEL_1
623 * @arg @ref LL_PWR_PVDLEVEL_2
624 * @arg @ref LL_PWR_PVDLEVEL_3
625 * @arg @ref LL_PWR_PVDLEVEL_4
626 * @arg @ref LL_PWR_PVDLEVEL_5
627 * @arg @ref LL_PWR_PVDLEVEL_6
628 * @arg @ref LL_PWR_PVDLEVEL_7
629 * @retval None
630 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)631 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
632 {
633 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
634 }
635
636 /**
637 * @brief Get the voltage threshold detection
638 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
639 * @retval Returned value can be one of the following values:
640 * @arg @ref LL_PWR_PVDLEVEL_0
641 * @arg @ref LL_PWR_PVDLEVEL_1
642 * @arg @ref LL_PWR_PVDLEVEL_2
643 * @arg @ref LL_PWR_PVDLEVEL_3
644 * @arg @ref LL_PWR_PVDLEVEL_4
645 * @arg @ref LL_PWR_PVDLEVEL_5
646 * @arg @ref LL_PWR_PVDLEVEL_6
647 * @arg @ref LL_PWR_PVDLEVEL_7
648 */
LL_PWR_GetPVDLevel(void)649 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
650 {
651 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
652 }
653
654 /**
655 * @brief Enable Power Voltage Detector
656 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
657 * @retval None
658 */
LL_PWR_EnablePVD(void)659 __STATIC_INLINE void LL_PWR_EnablePVD(void)
660 {
661 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
662 }
663
664 /**
665 * @brief Disable Power Voltage Detector
666 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
667 * @retval None
668 */
LL_PWR_DisablePVD(void)669 __STATIC_INLINE void LL_PWR_DisablePVD(void)
670 {
671 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
672 }
673
674 /**
675 * @brief Check if Power Voltage Detector is enabled
676 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
677 * @retval State of bit (1 or 0).
678 */
LL_PWR_IsEnabledPVD(void)679 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
680 {
681 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
682 }
683
684 /**
685 * @brief Enable SMPS low-power mode
686 * @rmtoll CR4 SMPSLPEN LL_PWR_EnableSMPSLowPowerMode
687 * @retval None
688 */
LL_PWR_EnableSMPSLowPowerMode(void)689 __STATIC_INLINE void LL_PWR_EnableSMPSLowPowerMode(void)
690 {
691 SET_BIT(PWR->CR4, PWR_CR4_SMPSLPEN);
692 }
693
694 /**
695 * @brief Disable SMPS low-power mode
696 * @rmtoll CR4 SMPSLPEN LL_PWR_DisableSMPSLowPowerMode
697 * @retval None
698 */
LL_PWR_DisableSMPSLowPowerMode(void)699 __STATIC_INLINE void LL_PWR_DisableSMPSLowPowerMode(void)
700 {
701 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSLPEN);
702 }
703
704 /**
705 * @brief Check if SMPS low-power mode is enabled
706 * @rmtoll CR4 SMPSLPEN LL_PWR_IsEnabledSMPSLowPowerMode
707 * @retval State of bit (1 or 0).
708 */
LL_PWR_IsEnabledSMPSLowPowerMode(void)709 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSLowPowerMode(void)
710 {
711 return ((READ_BIT(PWR->CR4, PWR_CR4_SMPSLPEN) == (PWR_CR4_SMPSLPEN)) ? 1UL : 0UL);
712 }
713
714 /**
715 * @brief Enable SMPS fast start
716 * @rmtoll CR4 SMPSFSTEN LL_PWR_EnableSMPSFastStart
717 * @retval None
718 */
LL_PWR_EnableSMPSFastStart(void)719 __STATIC_INLINE void LL_PWR_EnableSMPSFastStart(void)
720 {
721 SET_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN);
722 }
723
724 /**
725 * @brief Disable SMPS fast start
726 * @rmtoll CR4 SMPSFSTEN LL_PWR_DisableSMPSFastStart
727 * @retval None
728 */
LL_PWR_DisableSMPSFastStart(void)729 __STATIC_INLINE void LL_PWR_DisableSMPSFastStart(void)
730 {
731 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN);
732 }
733
734 /**
735 * @brief Check if SMPS fast start is enabled
736 * @rmtoll CR4 SMPSFSTEN LL_PWR_IsEnabledSMPSFastStart
737 * @retval State of bit (1 or 0).
738 */
LL_PWR_IsEnabledSMPSFastStart(void)739 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSFastStart(void)
740 {
741 return ((READ_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN) == (PWR_CR4_SMPSFSTEN)) ? 1UL : 0UL);
742 }
743
744 /**
745 * @brief Enable SMPS bypass mode
746 * @rmtoll CR4 SMPSBYP LL_PWR_EnableSMPSBypassMode
747 * @retval None
748 */
LL_PWR_EnableSMPSBypassMode(void)749 __STATIC_INLINE void LL_PWR_EnableSMPSBypassMode(void)
750 {
751 SET_BIT(PWR->CR4, PWR_CR4_SMPSBYP);
752 }
753
754 /**
755 * @brief Disable SMPS bypass mode
756 * @rmtoll CR4 SMPSBYP LL_PWR_DisableSMPSBypassMode
757 * @retval None
758 */
LL_PWR_DisableSMPSBypassMode(void)759 __STATIC_INLINE void LL_PWR_DisableSMPSBypassMode(void)
760 {
761 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSBYP);
762 }
763
764 /**
765 * @brief Check if SMPS bypass mode is enabled
766 * @rmtoll CR4 SMPSBYP LL_PWR_IsEnabledSMPSBypassMode
767 * @retval State of bit (1 or 0).
768 */
LL_PWR_IsEnabledSMPSBypassMode(void)769 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSBypassMode(void)
770 {
771 return ((READ_BIT(PWR->CR4, PWR_CR4_SMPSBYP) == (PWR_CR4_SMPSBYP)) ? 1UL : 0UL);
772 }
773
774 /**
775 * @brief Enable external SMPS
776 * @rmtoll CR4 EXTSMPSEN LL_PWR_EnableExtSMPS
777 * @retval None
778 */
LL_PWR_EnableExtSMPS(void)779 __STATIC_INLINE void LL_PWR_EnableExtSMPS(void)
780 {
781 SET_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN);
782 }
783
784 /**
785 * @brief Disable external SMPS
786 * @rmtoll CR4 EXTSMPSEN LL_PWR_DisableExtSMPS
787 * @retval None
788 */
LL_PWR_DisableExtSMPS(void)789 __STATIC_INLINE void LL_PWR_DisableExtSMPS(void)
790 {
791 CLEAR_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN);
792 }
793
794 /**
795 * @brief Check if external SMPS is enabled
796 * @rmtoll CR4 EXTSMPSEN LL_PWR_IsEnabledExtSMPS
797 * @retval State of bit (1 or 0).
798 */
LL_PWR_IsEnabledExtSMPS(void)799 __STATIC_INLINE uint32_t LL_PWR_IsEnabledExtSMPS(void)
800 {
801 return ((READ_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN) == (PWR_CR4_EXTSMPSEN)) ? 1UL : 0UL);
802 }
803
804 /**
805 * @brief Enable ultra low-power mode
806 * @rmtoll CR3 UPLMEN LL_PWR_EnableUltraLowPowerMode
807 * @retval None
808 */
LL_PWR_EnableUltraLowPowerMode(void)809 __STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void)
810 {
811 SET_BIT(PWR->CR3, PWR_CR3_ULPMEN);
812 }
813
814 /**
815 * @brief Disable ultra low-power mode
816 * @rmtoll CR3 UPLMEN LL_PWR_DisableUltraLowPowerMode
817 * @retval None
818 */
LL_PWR_DisableUltraLowPowerMode(void)819 __STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void)
820 {
821 CLEAR_BIT(PWR->CR3, PWR_CR3_ULPMEN);
822 }
823
824 /**
825 * @brief Check if ultra low-power mode is enabled
826 * @rmtoll CR3 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode
827 * @retval State of bit (1 or 0).
828 */
LL_PWR_IsEnabledUltraLowPowerMode(void)829 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void)
830 {
831 return ((READ_BIT(PWR->CR3, PWR_CR3_ULPMEN) == (PWR_CR3_ULPMEN)) ? 1UL : 0UL);
832 }
833
834 /**
835 * @brief Enable pull-up and pull-down configuration
836 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
837 * @retval None
838 */
LL_PWR_EnablePUPDCfg(void)839 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
840 {
841 SET_BIT(PWR->CR3, PWR_CR3_APC);
842 }
843
844 /**
845 * @brief Disable pull-up and pull-down configuration
846 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
847 * @retval None
848 */
LL_PWR_DisablePUPDCfg(void)849 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
850 {
851 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
852 }
853
854 /**
855 * @brief Check if pull-up and pull-down configuration is enabled
856 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
857 * @retval State of bit (1 or 0).
858 */
LL_PWR_IsEnabledPUPDCfg(void)859 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
860 {
861 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
862 }
863
864 /**
865 * @brief Set the SRAM2 retention in Standby mode
866 * @rmtoll CR3 RRS LL_PWR_SetSRAM2Retention
867 * @param SRAM2Retention This parameter can be one of the following values:
868 * @arg @ref LL_PWR_SRAM2_NO_RETENTION
869 * @arg @ref LL_PWR_SRAM2_FULL_RETENTION
870 * @arg @ref LL_PWR_SRAM2_4KB_RETENTION
871 * @retval None
872 */
LL_PWR_SetSRAM2Retention(uint32_t SRAM2Retention)873 __STATIC_INLINE void LL_PWR_SetSRAM2Retention(uint32_t SRAM2Retention)
874 {
875 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2Retention);
876 }
877
878 /**
879 * @brief Get the SRAM2 retention in Standby mode
880 * @rmtoll CR3 RRS LL_PWR_GetSRAM2Retention
881 * @retval Returned value can be one of the following values:
882 * @arg @ref LL_PWR_SRAM2_NO_RETENTION
883 * @arg @ref LL_PWR_SRAM2_FULL_RETENTION
884 * @arg @ref LL_PWR_SRAM2_4KB_RETENTION
885 */
LL_PWR_GetSRAM2Retention(void)886 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2Retention(void)
887 {
888 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS));
889 }
890
891 /**
892 * @brief Enable the WakeUp PINx functionality
893 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
894 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
895 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
896 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
897 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
898 * @param WakeUpPin This parameter can be one of the following values:
899 * @arg @ref LL_PWR_WAKEUP_PIN1
900 * @arg @ref LL_PWR_WAKEUP_PIN2
901 * @arg @ref LL_PWR_WAKEUP_PIN3
902 * @arg @ref LL_PWR_WAKEUP_PIN4
903 * @arg @ref LL_PWR_WAKEUP_PIN5
904 * @retval None
905 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)906 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
907 {
908 SET_BIT(PWR->CR3, WakeUpPin);
909 }
910
911 /**
912 * @brief Disable the WakeUp PINx functionality
913 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
914 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
915 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
916 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
917 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
918 * @param WakeUpPin This parameter can be one of the following values:
919 * @arg @ref LL_PWR_WAKEUP_PIN1
920 * @arg @ref LL_PWR_WAKEUP_PIN2
921 * @arg @ref LL_PWR_WAKEUP_PIN3
922 * @arg @ref LL_PWR_WAKEUP_PIN4
923 * @arg @ref LL_PWR_WAKEUP_PIN5
924 * @retval None
925 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)926 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
927 {
928 CLEAR_BIT(PWR->CR3, WakeUpPin);
929 }
930
931 /**
932 * @brief Check if the WakeUp PINx functionality is enabled
933 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
934 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
935 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
936 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
937 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
938 * @param WakeUpPin This parameter can be one of the following values:
939 * @arg @ref LL_PWR_WAKEUP_PIN1
940 * @arg @ref LL_PWR_WAKEUP_PIN2
941 * @arg @ref LL_PWR_WAKEUP_PIN3
942 * @arg @ref LL_PWR_WAKEUP_PIN4
943 * @arg @ref LL_PWR_WAKEUP_PIN5
944 * @retval State of bit (1 or 0).
945 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)946 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
947 {
948 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
949 }
950
951 /**
952 * @brief Set the resistor impedance
953 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
954 * @param Resistor This parameter can be one of the following values:
955 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
956 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
957 * @retval None
958 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)959 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
960 {
961 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
962 }
963
964 /**
965 * @brief Get the resistor impedance
966 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
967 * @retval Returned value can be one of the following values:
968 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
969 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
970 */
LL_PWR_GetBattChargResistor(void)971 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
972 {
973 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
974 }
975
976 /**
977 * @brief Enable battery charging
978 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
979 * @retval None
980 */
LL_PWR_EnableBatteryCharging(void)981 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
982 {
983 SET_BIT(PWR->CR4, PWR_CR4_VBE);
984 }
985
986 /**
987 * @brief Disable battery charging
988 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
989 * @retval None
990 */
LL_PWR_DisableBatteryCharging(void)991 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
992 {
993 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
994 }
995
996 /**
997 * @brief Check if battery charging is enabled
998 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
999 * @retval State of bit (1 or 0).
1000 */
LL_PWR_IsEnabledBatteryCharging(void)1001 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
1002 {
1003 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
1004 }
1005
1006 /**
1007 * @brief Set the Wake-Up pin polarity low for the event detection
1008 * @rmtoll CR4 WUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
1009 * CR4 WUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
1010 * CR4 WUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
1011 * CR4 WUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
1012 * CR4 WUPP5 LL_PWR_SetWakeUpPinPolarityLow
1013 * @param WakeUpPin This parameter can be one of the following values:
1014 * @arg @ref LL_PWR_WAKEUP_PIN1
1015 * @arg @ref LL_PWR_WAKEUP_PIN2
1016 * @arg @ref LL_PWR_WAKEUP_PIN3
1017 * @arg @ref LL_PWR_WAKEUP_PIN4
1018 * @arg @ref LL_PWR_WAKEUP_PIN5
1019 * @retval None
1020 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)1021 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1022 {
1023 SET_BIT(PWR->CR4, WakeUpPin);
1024 }
1025
1026 /**
1027 * @brief Set the Wake-Up pin polarity high for the event detection
1028 * @rmtoll CR4 WUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1029 * CR4 WUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1030 * CR4 WUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1031 * CR4 WUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n
1032 * CR4 WUPP5 LL_PWR_SetWakeUpPinPolarityHigh
1033 * @param WakeUpPin This parameter can be one of the following values:
1034 * @arg @ref LL_PWR_WAKEUP_PIN1
1035 * @arg @ref LL_PWR_WAKEUP_PIN2
1036 * @arg @ref LL_PWR_WAKEUP_PIN3
1037 * @arg @ref LL_PWR_WAKEUP_PIN4
1038 * @arg @ref LL_PWR_WAKEUP_PIN5
1039 * @retval None
1040 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)1041 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1042 {
1043 CLEAR_BIT(PWR->CR4, WakeUpPin);
1044 }
1045
1046 /**
1047 * @brief Get the Wake-Up pin polarity for the event detection
1048 * @rmtoll CR4 WUPP1 LL_PWR_IsWakeUpPinPolarityLow\n
1049 * CR4 WUPP2 LL_PWR_IsWakeUpPinPolarityLow\n
1050 * CR4 WUPP3 LL_PWR_IsWakeUpPinPolarityLow\n
1051 * CR4 WUPP4 LL_PWR_IsWakeUpPinPolarityLow\n
1052 * CR4 WUPP5 LL_PWR_IsWakeUpPinPolarityLow
1053 * @param WakeUpPin This parameter can be one of the following values:
1054 * @arg @ref LL_PWR_WAKEUP_PIN1
1055 * @arg @ref LL_PWR_WAKEUP_PIN2
1056 * @arg @ref LL_PWR_WAKEUP_PIN3
1057 * @arg @ref LL_PWR_WAKEUP_PIN4
1058 * @arg @ref LL_PWR_WAKEUP_PIN5
1059 * @retval State of bit (1 or 0).
1060 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1061 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1062 {
1063 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1064 }
1065
1066 /**
1067 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
1068 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
1069 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1070 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1071 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
1072 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
1073 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
1074 * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
1075 * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp
1076 * @param GPIO This parameter can be one of the following values:
1077 * @arg @ref LL_PWR_GPIO_A
1078 * @arg @ref LL_PWR_GPIO_B
1079 * @arg @ref LL_PWR_GPIO_C
1080 * @arg @ref LL_PWR_GPIO_D
1081 * @arg @ref LL_PWR_GPIO_E
1082 * @arg @ref LL_PWR_GPIO_F
1083 * @arg @ref LL_PWR_GPIO_G
1084 * @arg @ref LL_PWR_GPIO_H
1085 * @param GPIONumber This parameter can be one of the following values:
1086 * @arg @ref LL_PWR_GPIO_BIT_0
1087 * @arg @ref LL_PWR_GPIO_BIT_1
1088 * @arg @ref LL_PWR_GPIO_BIT_2
1089 * @arg @ref LL_PWR_GPIO_BIT_3
1090 * @arg @ref LL_PWR_GPIO_BIT_4
1091 * @arg @ref LL_PWR_GPIO_BIT_5
1092 * @arg @ref LL_PWR_GPIO_BIT_6
1093 * @arg @ref LL_PWR_GPIO_BIT_7
1094 * @arg @ref LL_PWR_GPIO_BIT_8
1095 * @arg @ref LL_PWR_GPIO_BIT_9
1096 * @arg @ref LL_PWR_GPIO_BIT_10
1097 * @arg @ref LL_PWR_GPIO_BIT_11
1098 * @arg @ref LL_PWR_GPIO_BIT_12
1099 * @arg @ref LL_PWR_GPIO_BIT_13
1100 * @arg @ref LL_PWR_GPIO_BIT_14
1101 * @arg @ref LL_PWR_GPIO_BIT_15
1102 * @retval None
1103 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1104 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1105 {
1106 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1107 }
1108
1109 /**
1110 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
1111 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
1112 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
1113 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
1114 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
1115 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
1116 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
1117 * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
1118 * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp
1119 * @param GPIO This parameter can be one of the following values:
1120 * @arg @ref LL_PWR_GPIO_A
1121 * @arg @ref LL_PWR_GPIO_B
1122 * @arg @ref LL_PWR_GPIO_C
1123 * @arg @ref LL_PWR_GPIO_D
1124 * @arg @ref LL_PWR_GPIO_E
1125 * @arg @ref LL_PWR_GPIO_F
1126 * @arg @ref LL_PWR_GPIO_G
1127 * @arg @ref LL_PWR_GPIO_H
1128 * @param GPIONumber This parameter can be one of the following values:
1129 * @arg @ref LL_PWR_GPIO_BIT_0
1130 * @arg @ref LL_PWR_GPIO_BIT_1
1131 * @arg @ref LL_PWR_GPIO_BIT_2
1132 * @arg @ref LL_PWR_GPIO_BIT_3
1133 * @arg @ref LL_PWR_GPIO_BIT_4
1134 * @arg @ref LL_PWR_GPIO_BIT_5
1135 * @arg @ref LL_PWR_GPIO_BIT_6
1136 * @arg @ref LL_PWR_GPIO_BIT_7
1137 * @arg @ref LL_PWR_GPIO_BIT_8
1138 * @arg @ref LL_PWR_GPIO_BIT_9
1139 * @arg @ref LL_PWR_GPIO_BIT_10
1140 * @arg @ref LL_PWR_GPIO_BIT_11
1141 * @arg @ref LL_PWR_GPIO_BIT_12
1142 * @arg @ref LL_PWR_GPIO_BIT_13
1143 * @arg @ref LL_PWR_GPIO_BIT_14
1144 * @arg @ref LL_PWR_GPIO_BIT_15
1145 * @retval None
1146 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1147 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1148 {
1149 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1150 }
1151
1152 /**
1153 * @brief Check if GPIO pull-up state is enabled
1154 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1155 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1156 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1157 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1158 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1159 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1160 * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1161 * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp
1162 * @param GPIO This parameter can be one of the following values:
1163 * @arg @ref LL_PWR_GPIO_A
1164 * @arg @ref LL_PWR_GPIO_B
1165 * @arg @ref LL_PWR_GPIO_C
1166 * @arg @ref LL_PWR_GPIO_D
1167 * @arg @ref LL_PWR_GPIO_E
1168 * @arg @ref LL_PWR_GPIO_F
1169 * @arg @ref LL_PWR_GPIO_G
1170 * @arg @ref LL_PWR_GPIO_H
1171 * @param GPIONumber This parameter can be one of the following values:
1172 * @arg @ref LL_PWR_GPIO_BIT_0
1173 * @arg @ref LL_PWR_GPIO_BIT_1
1174 * @arg @ref LL_PWR_GPIO_BIT_2
1175 * @arg @ref LL_PWR_GPIO_BIT_3
1176 * @arg @ref LL_PWR_GPIO_BIT_4
1177 * @arg @ref LL_PWR_GPIO_BIT_5
1178 * @arg @ref LL_PWR_GPIO_BIT_6
1179 * @arg @ref LL_PWR_GPIO_BIT_7
1180 * @arg @ref LL_PWR_GPIO_BIT_8
1181 * @arg @ref LL_PWR_GPIO_BIT_9
1182 * @arg @ref LL_PWR_GPIO_BIT_10
1183 * @arg @ref LL_PWR_GPIO_BIT_11
1184 * @arg @ref LL_PWR_GPIO_BIT_12
1185 * @arg @ref LL_PWR_GPIO_BIT_13
1186 * @arg @ref LL_PWR_GPIO_BIT_14
1187 * @arg @ref LL_PWR_GPIO_BIT_15
1188 * @retval State of bit (1 or 0).
1189 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1190 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1191 {
1192 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1193 }
1194
1195 /**
1196 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
1197 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
1198 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
1199 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
1200 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
1201 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
1202 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
1203 * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
1204 * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown
1205 * @param GPIO This parameter can be one of the following values:
1206 * @arg @ref LL_PWR_GPIO_A
1207 * @arg @ref LL_PWR_GPIO_B
1208 * @arg @ref LL_PWR_GPIO_C
1209 * @arg @ref LL_PWR_GPIO_D
1210 * @arg @ref LL_PWR_GPIO_E
1211 * @arg @ref LL_PWR_GPIO_F
1212 * @arg @ref LL_PWR_GPIO_G
1213 * @arg @ref LL_PWR_GPIO_H
1214 * @param GPIONumber This parameter can be one of the following values:
1215 * @arg @ref LL_PWR_GPIO_BIT_0
1216 * @arg @ref LL_PWR_GPIO_BIT_1
1217 * @arg @ref LL_PWR_GPIO_BIT_2
1218 * @arg @ref LL_PWR_GPIO_BIT_3
1219 * @arg @ref LL_PWR_GPIO_BIT_4
1220 * @arg @ref LL_PWR_GPIO_BIT_5
1221 * @arg @ref LL_PWR_GPIO_BIT_6
1222 * @arg @ref LL_PWR_GPIO_BIT_7
1223 * @arg @ref LL_PWR_GPIO_BIT_8
1224 * @arg @ref LL_PWR_GPIO_BIT_9
1225 * @arg @ref LL_PWR_GPIO_BIT_10
1226 * @arg @ref LL_PWR_GPIO_BIT_11
1227 * @arg @ref LL_PWR_GPIO_BIT_12
1228 * @arg @ref LL_PWR_GPIO_BIT_13
1229 * @arg @ref LL_PWR_GPIO_BIT_14
1230 * @arg @ref LL_PWR_GPIO_BIT_15
1231 * @retval None
1232 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1233 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1234 {
1235 SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1236 }
1237
1238 /**
1239 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
1240 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
1241 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
1242 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
1243 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
1244 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
1245 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
1246 * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
1247 * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown
1248 * @param GPIO This parameter can be one of the following values:
1249 * @arg @ref LL_PWR_GPIO_A
1250 * @arg @ref LL_PWR_GPIO_B
1251 * @arg @ref LL_PWR_GPIO_C
1252 * @arg @ref LL_PWR_GPIO_D
1253 * @arg @ref LL_PWR_GPIO_E
1254 * @arg @ref LL_PWR_GPIO_F
1255 * @arg @ref LL_PWR_GPIO_G
1256 * @arg @ref LL_PWR_GPIO_H
1257 * @param GPIONumber This parameter can be one of the following values:
1258 * @arg @ref LL_PWR_GPIO_BIT_0
1259 * @arg @ref LL_PWR_GPIO_BIT_1
1260 * @arg @ref LL_PWR_GPIO_BIT_2
1261 * @arg @ref LL_PWR_GPIO_BIT_3
1262 * @arg @ref LL_PWR_GPIO_BIT_4
1263 * @arg @ref LL_PWR_GPIO_BIT_5
1264 * @arg @ref LL_PWR_GPIO_BIT_6
1265 * @arg @ref LL_PWR_GPIO_BIT_7
1266 * @arg @ref LL_PWR_GPIO_BIT_8
1267 * @arg @ref LL_PWR_GPIO_BIT_9
1268 * @arg @ref LL_PWR_GPIO_BIT_10
1269 * @arg @ref LL_PWR_GPIO_BIT_11
1270 * @arg @ref LL_PWR_GPIO_BIT_12
1271 * @arg @ref LL_PWR_GPIO_BIT_13
1272 * @arg @ref LL_PWR_GPIO_BIT_14
1273 * @arg @ref LL_PWR_GPIO_BIT_15
1274 * @retval None
1275 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1276 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1277 {
1278 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1279 }
1280
1281 /**
1282 * @brief Check if GPIO pull-down state is enabled
1283 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1284 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1285 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1286 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1287 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1288 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1289 * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1290 * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown
1291 * @param GPIO This parameter can be one of the following values:
1292 * @arg @ref LL_PWR_GPIO_A
1293 * @arg @ref LL_PWR_GPIO_B
1294 * @arg @ref LL_PWR_GPIO_C
1295 * @arg @ref LL_PWR_GPIO_D
1296 * @arg @ref LL_PWR_GPIO_E
1297 * @arg @ref LL_PWR_GPIO_F
1298 * @arg @ref LL_PWR_GPIO_G
1299 * @arg @ref LL_PWR_GPIO_H
1300 * @param GPIONumber This parameter can be one of the following values:
1301 * @arg @ref LL_PWR_GPIO_BIT_0
1302 * @arg @ref LL_PWR_GPIO_BIT_1
1303 * @arg @ref LL_PWR_GPIO_BIT_2
1304 * @arg @ref LL_PWR_GPIO_BIT_3
1305 * @arg @ref LL_PWR_GPIO_BIT_4
1306 * @arg @ref LL_PWR_GPIO_BIT_5
1307 * @arg @ref LL_PWR_GPIO_BIT_6
1308 * @arg @ref LL_PWR_GPIO_BIT_7
1309 * @arg @ref LL_PWR_GPIO_BIT_8
1310 * @arg @ref LL_PWR_GPIO_BIT_9
1311 * @arg @ref LL_PWR_GPIO_BIT_10
1312 * @arg @ref LL_PWR_GPIO_BIT_11
1313 * @arg @ref LL_PWR_GPIO_BIT_12
1314 * @arg @ref LL_PWR_GPIO_BIT_13
1315 * @arg @ref LL_PWR_GPIO_BIT_14
1316 * @arg @ref LL_PWR_GPIO_BIT_15
1317 * @retval State of bit (1 or 0).
1318 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1319 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1320 {
1321 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1322 }
1323
1324 /**
1325 * @}
1326 */
1327
1328 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1329 * @{
1330 */
1331
1332 /**
1333 * @brief Get SMPS High-power mode ready Flag
1334 * @rmtoll SR1 SMPSHPRDY LL_PWR_IsActiveFlag_SMPSHPRDY
1335 * @retval State of bit (1 or 0).
1336 */
LL_PWR_IsActiveFlag_SMPSHPRDY(void)1337 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSHPRDY(void)
1338 {
1339 return ((READ_BIT(PWR->SR1, PWR_SR1_SMPSHPRDY) == (PWR_SR1_SMPSHPRDY)) ? 1UL : 0UL);
1340 }
1341
1342 /**
1343 * @brief Get External SMPS mode ready Flag
1344 * @rmtoll SR1 EXTSMPSRDY LL_PWR_IsActiveFlag_EXTSMPSRDY
1345 * @retval State of bit (1 or 0).
1346 */
LL_PWR_IsActiveFlag_EXTSMPSRDY(void)1347 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_EXTSMPSRDY(void)
1348 {
1349 return ((READ_BIT(PWR->SR1, PWR_SR1_EXTSMPSRDY) == (PWR_SR1_EXTSMPSRDY)) ? 1UL : 0UL);
1350 }
1351
1352 /**
1353 * @brief Get SMPS Bypass mode ready Flag
1354 * @rmtoll SR1 SMPSBYPRDY LL_PWR_IsActiveFlag_SMPSBYPRDY
1355 * @retval State of bit (1 or 0).
1356 */
LL_PWR_IsActiveFlag_SMPSBYPRDY(void)1357 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSBYPRDY(void)
1358 {
1359 return ((READ_BIT(PWR->SR1, PWR_SR1_SMPSBYPRDY) == (PWR_SR1_SMPSBYPRDY)) ? 1UL : 0UL);
1360 }
1361
1362 /**
1363 * @brief Get Stand-By Flag
1364 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
1365 * @retval State of bit (1 or 0).
1366 */
LL_PWR_IsActiveFlag_SB(void)1367 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1368 {
1369 return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL);
1370 }
1371
1372 /**
1373 * @brief Get Wake-up Flag 5
1374 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
1375 * @retval State of bit (1 or 0).
1376 */
LL_PWR_IsActiveFlag_WU5(void)1377 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1378 {
1379 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
1380 }
1381
1382 /**
1383 * @brief Get Wake-up Flag 4
1384 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
1385 * @retval State of bit (1 or 0).
1386 */
LL_PWR_IsActiveFlag_WU4(void)1387 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1388 {
1389 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
1390 }
1391
1392 /**
1393 * @brief Get Wake-up Flag 3
1394 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1395 * @retval State of bit (1 or 0).
1396 */
LL_PWR_IsActiveFlag_WU3(void)1397 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1398 {
1399 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
1400 }
1401
1402 /**
1403 * @brief Get Wake-up Flag 2
1404 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1405 * @retval State of bit (1 or 0).
1406 */
LL_PWR_IsActiveFlag_WU2(void)1407 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1408 {
1409 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
1410 }
1411
1412 /**
1413 * @brief Get Wake-up Flag 1
1414 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1415 * @retval State of bit (1 or 0).
1416 */
LL_PWR_IsActiveFlag_WU1(void)1417 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1418 {
1419 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
1420 }
1421
1422 /**
1423 * @brief Clear Stand-By Flag
1424 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
1425 * @retval None
1426 */
LL_PWR_ClearFlag_SB(void)1427 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1428 {
1429 WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
1430 }
1431
1432 /**
1433 * @brief Clear Wake-up Flags
1434 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
1435 * @retval None
1436 */
LL_PWR_ClearFlag_WU(void)1437 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1438 {
1439 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
1440 }
1441
1442 /**
1443 * @brief Clear Wake-up Flag 5
1444 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
1445 * @retval None
1446 */
LL_PWR_ClearFlag_WU5(void)1447 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1448 {
1449 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
1450 }
1451
1452 /**
1453 * @brief Clear Wake-up Flag 4
1454 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
1455 * @retval None
1456 */
LL_PWR_ClearFlag_WU4(void)1457 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1458 {
1459 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
1460 }
1461
1462 /**
1463 * @brief Clear Wake-up Flag 3
1464 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
1465 * @retval None
1466 */
LL_PWR_ClearFlag_WU3(void)1467 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1468 {
1469 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
1470 }
1471
1472 /**
1473 * @brief Clear Wake-up Flag 2
1474 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
1475 * @retval None
1476 */
LL_PWR_ClearFlag_WU2(void)1477 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1478 {
1479 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
1480 }
1481
1482 /**
1483 * @brief Clear Wake-up Flag 1
1484 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
1485 * @retval None
1486 */
LL_PWR_ClearFlag_WU1(void)1487 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1488 {
1489 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
1490 }
1491
1492 /**
1493 * @brief Indicate whether VDDA voltage is below or above PVM4 threshold
1494 * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
1495 * @retval State of bit (1 or 0).
1496 */
LL_PWR_IsActiveFlag_PVMO4(void)1497 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
1498 {
1499 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)) ? 1UL : 0UL);
1500 }
1501
1502 /**
1503 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
1504 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
1505 * @retval State of bit (1 or 0).
1506 */
LL_PWR_IsActiveFlag_PVMO3(void)1507 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
1508 {
1509 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL);
1510 }
1511
1512 /**
1513 * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
1514 * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
1515 * @retval State of bit (1 or 0).
1516 */
LL_PWR_IsActiveFlag_PVMO2(void)1517 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
1518 {
1519 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)) ? 1UL : 0UL);
1520 }
1521
1522 /**
1523 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
1524 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
1525 * @retval State of bit (1 or 0).
1526 */
LL_PWR_IsActiveFlag_PVMO1(void)1527 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
1528 {
1529 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL);
1530 }
1531
1532 /**
1533 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
1534 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
1535 * @retval State of bit (1 or 0).
1536 */
LL_PWR_IsActiveFlag_PVDO(void)1537 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1538 {
1539 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
1540 }
1541
1542 /**
1543 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
1544 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
1545 * @retval State of bit (1 or 0).
1546 */
LL_PWR_IsActiveFlag_VOS(void)1547 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1548 {
1549 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
1550 }
1551
1552 /**
1553 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
1554 * @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
1555 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
1556 * @retval State of bit (1 or 0).
1557 */
LL_PWR_IsActiveFlag_REGLPF(void)1558 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
1559 {
1560 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
1561 }
1562
1563 /**
1564 * @brief Indicate whether or not the low-power regulator is ready
1565 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
1566 * @retval State of bit (1 or 0).
1567 */
LL_PWR_IsActiveFlag_REGLPS(void)1568 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
1569 {
1570 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
1571 }
1572
1573 /**
1574 * @}
1575 */
1576
1577 /** @defgroup PWR_LL_EF_Privilege_Management Privilege_Management
1578 * @{
1579 */
1580
1581 /**
1582 * @brief Enable Privileged mode
1583 * @rmtoll PRIVCFGR PRIV LL_PWR_EnablePrivilege
1584 * @retval None
1585 */
LL_PWR_EnablePrivilege(void)1586 __STATIC_INLINE void LL_PWR_EnablePrivilege(void)
1587 {
1588 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV);
1589 }
1590
1591 /**
1592 * @brief Disable Privileged mode
1593 * @rmtoll PRIVCFGR PRIV LL_PWR_DisablePrivilege
1594 * @retval None
1595 */
LL_PWR_DisablePrivilege(void)1596 __STATIC_INLINE void LL_PWR_DisablePrivilege(void)
1597 {
1598 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV);
1599 }
1600
1601 /**
1602 * @brief Check if Privileged mode has been enabled or not
1603 * @rmtoll PRIVCFGR PRIV LL_PWR_IsEnabledPrivilege
1604 * @retval State of bit (1 or 0).
1605 */
LL_PWR_IsEnabledPrivilege(void)1606 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPrivilege(void)
1607 {
1608 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV) == PWR_PRIVCFGR_PRIV) ? 1UL : 0UL);
1609 }
1610
1611 /**
1612 * @}
1613 */
1614
1615 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1616
1617 /** @defgroup PWR_LL_EF_Secure_Management Secure_Management
1618 * @{
1619 */
1620
1621 /**
1622 * @brief Configure Secure mode
1623 * @note Only available from secure state when system implements security (TZEN=1)
1624 * @rmtoll SECCFGR WUPSEC LL_PWR_ConfigSecure\n
1625 * SECCFGR WUP1SEC LL_PWR_ConfigSecure\n
1626 * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n
1627 * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n
1628 * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n
1629 * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n
1630 * SECCFGR LPMSEC LL_PWR_ConfigSecure\n
1631 * SECCFGR VDMSEC LL_PWR_ConfigSecure\n
1632 * SECCFGR VBSEC LL_PWR_ConfigSecure\n
1633 * SECCFGR APCSEC LL_PWR_ConfigSecure
1634 * @param Configuration This parameter shall be the full combination
1635 * of the following values:
1636 * @arg @ref LL_PWR_WAKEUP_PINS_SEC or LL_PWR_WAKEUP_PINS_NSEC
1637 * @arg @ref LL_PWR_WAKEUP_PIN1_SEC or LL_PWR_WAKEUP_PIN1_NSEC
1638 * @arg @ref LL_PWR_WAKEUP_PIN2_SEC or LL_PWR_WAKEUP_PIN2_NSEC
1639 * @arg @ref LL_PWR_WAKEUP_PIN3_SEC or LL_PWR_WAKEUP_PIN3_NSEC
1640 * @arg @ref LL_PWR_WAKEUP_PIN4_SEC or LL_PWR_WAKEUP_PIN4_NSEC
1641 * @arg @ref LL_PWR_WAKEUP_PIN5_SEC or LL_PWR_WAKEUP_PIN5_NSEC
1642 * @arg @ref LL_PWR_LPM_SEC or LL_PWR_LPM_NSEC
1643 * @arg @ref LL_PWR_VDM_SEC or LL_PWR_VDM_NSEC
1644 * @arg @ref LL_PWR_VB_SEC or LL_PWR_VB_NSEC
1645 * @arg @ref LL_PWR_APC_SEC or LL_PWR_APC_NSEC
1646 * @retval None
1647 */
LL_PWR_ConfigSecure(uint32_t Configuration)1648 __STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t Configuration)
1649 {
1650 WRITE_REG(PWR->SECCFGR, Configuration);
1651 }
1652
1653 /**
1654 * @brief Get Secure mode configuration
1655 * @note Only available from secure state when system implements security (TZEN=1)
1656 * @rmtoll SECCFGR WUPSEC LL_PWR_GetConfigSecure\n
1657 * SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n
1658 * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n
1659 * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n
1660 * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n
1661 * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n
1662 * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n
1663 * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n
1664 * SECCFGR VBSEC LL_PWR_GetConfigSecure\n
1665 * SECCFGR APCSEC LL_PWR_GetConfigSecure
1666 * @retval Returned value is the combination of the following values:
1667 * @arg @ref LL_PWR_WAKEUP_PINS_SEC or LL_PWR_WAKEUP_PINS_NSEC
1668 * @arg @ref LL_PWR_WAKEUP_PIN1_SEC or LL_PWR_WAKEUP_PIN1_NSEC
1669 * @arg @ref LL_PWR_WAKEUP_PIN2_SEC or LL_PWR_WAKEUP_PIN2_NSEC
1670 * @arg @ref LL_PWR_WAKEUP_PIN3_SEC or LL_PWR_WAKEUP_PIN3_NSEC
1671 * @arg @ref LL_PWR_WAKEUP_PIN4_SEC or LL_PWR_WAKEUP_PIN4_NSEC
1672 * @arg @ref LL_PWR_WAKEUP_PIN5_SEC or LL_PWR_WAKEUP_PIN5_NSEC
1673 * @arg @ref LL_PWR_LPM_SEC or LL_PWR_LPM_NSEC
1674 * @arg @ref LL_PWR_VDM_SEC or LL_PWR_VDM_NSEC
1675 * @arg @ref LL_PWR_VB_SEC or LL_PWR_VB_NSEC
1676 * @arg @ref LL_PWR_APC_SEC or LL_PWR_APC_NSEC
1677 */
LL_PWR_GetConfigSecure(void)1678 __STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void)
1679 {
1680 return (uint32_t)(READ_REG(PWR->SECCFGR));
1681 }
1682
1683 /**
1684 * @}
1685 */
1686 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1687
1688
1689 #if defined(USE_FULL_LL_DRIVER)
1690 /** @defgroup PWR_LL_EF_Init De-initialization function
1691 * @{
1692 */
1693 ErrorStatus LL_PWR_DeInit(void);
1694 /**
1695 * @}
1696 */
1697 #endif /* USE_FULL_LL_DRIVER */
1698
1699 /** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
1700 * @{
1701 */
1702 /* Old functions name kept for legacy purpose, to be replaced by the */
1703 /* current functions name. */
1704 #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
1705 /**
1706 * @}
1707 */
1708
1709 /**
1710 * @}
1711 */
1712
1713 /**
1714 * @}
1715 */
1716
1717 #endif /* defined(PWR) */
1718
1719 /**
1720 * @}
1721 */
1722
1723 #ifdef __cplusplus
1724 }
1725 #endif
1726
1727 #endif /* STM32L5xx_LL_PWR_H */
1728
1729 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1730
