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Searched refs:IPCC_C2SCR_CH1S_Pos (Results 1 – 25 of 36) sorted by relevance

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/hal_stm32-2.7.6/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_ipcc.h672 WRITE_REG(IPCCx->C2SCR, Channel << IPCC_C2SCR_CH1S_Pos); in LL_C2_IPCC_SetFlag_CHx()
/hal_stm32-2.7.6/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_ipcc.h672 WRITE_REG(IPCCx->C2SCR, Channel << IPCC_C2SCR_CH1S_Pos); in LL_C2_IPCC_SetFlag_CHx()
/hal_stm32-2.7.6/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_ipcc.h672 WRITE_REG(IPCCx->C2SCR, Channel << IPCC_C2SCR_CH1S_Pos); in LL_C2_IPCC_SetFlag_CHx()
/hal_stm32-2.7.6/stm32cube/stm32wlxx/soc/
Dstm32wl54xx.h9848 #define IPCC_C2SCR_CH1S_Pos (16U) macro
9849 #define IPCC_C2SCR_CH1S_Msk (0x1UL << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32wl55xx.h9848 #define IPCC_C2SCR_CH1S_Pos (16U) macro
9849 #define IPCC_C2SCR_CH1S_Msk (0x1UL << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
/hal_stm32-2.7.6/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h9949 #define IPCC_C2SCR_CH1S_Pos (16U) macro
9950 #define IPCC_C2SCR_CH1S_Msk (0x1UL << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32wb30xx.h9945 #define IPCC_C2SCR_CH1S_Pos (16U) macro
9946 #define IPCC_C2SCR_CH1S_Msk (0x1UL << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32wb35xx.h11392 #define IPCC_C2SCR_CH1S_Pos (16U) macro
11393 #define IPCC_C2SCR_CH1S_Msk (0x1UL << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32wb55xx.h12297 #define IPCC_C2SCR_CH1S_Pos (16U) macro
12298 #define IPCC_C2SCR_CH1S_Msk (0x1UL << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32wb5mxx.h12297 #define IPCC_C2SCR_CH1S_Pos (16U) macro
12298 #define IPCC_C2SCR_CH1S_Msk (0x1UL << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
/hal_stm32-2.7.6/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h9821 #define IPCC_C2SCR_CH1S_Pos (16U) macro
9822 #define IPCC_C2SCR_CH1S_Msk (0x1UL << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32wb15xx.h9938 #define IPCC_C2SCR_CH1S_Pos (16U) macro
9939 #define IPCC_C2SCR_CH1S_Msk (0x1UL << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
/hal_stm32-2.7.6/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_cm4.h21609 #define IPCC_C2SCR_CH1S_Pos (16U) macro
21610 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32mp151cxx_ca7.h21840 #define IPCC_C2SCR_CH1S_Pos (16U) macro
21841 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32mp151cxx_cm4.h21806 #define IPCC_C2SCR_CH1S_Pos (16U) macro
21807 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32mp151axx_ca7.h21643 #define IPCC_C2SCR_CH1S_Pos (16U) macro
21644 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32mp151axx_cm4.h21609 #define IPCC_C2SCR_CH1S_Pos (16U) macro
21610 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32mp151dxx_ca7.h21643 #define IPCC_C2SCR_CH1S_Pos (16U) macro
21644 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32mp151fxx_cm4.h21806 #define IPCC_C2SCR_CH1S_Pos (16U) macro
21807 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32mp151fxx_ca7.h21840 #define IPCC_C2SCR_CH1S_Pos (16U) macro
21841 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32mp157axx_cm4.h24398 #define IPCC_C2SCR_CH1S_Pos (16U) macro
24399 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32mp153axx_ca7.h23207 #define IPCC_C2SCR_CH1S_Pos (16U) macro
23208 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32mp157axx_ca7.h24432 #define IPCC_C2SCR_CH1S_Pos (16U) macro
24433 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32mp153fxx_cm4.h23370 #define IPCC_C2SCR_CH1S_Pos (16U) macro
23371 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
Dstm32mp153axx_cm4.h23173 #define IPCC_C2SCR_CH1S_Pos (16U) macro
23174 #define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */

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