Home
last modified time | relevance | path

Searched refs:CFGR2 (Results 1 – 25 of 272) sorted by relevance

1234567891011

/hal_stm32-2.7.6/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_hal_rcc_ex.c214 …if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) in HAL_RCCEx_PeriphCLKConfig()
262 if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) in HAL_RCCEx_PeriphCLKConfig()
426 … prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; in HAL_RCCEx_GetPeriphCLKFreq()
432 if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) in HAL_RCCEx_GetPeriphCLKFreq()
436 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; in HAL_RCCEx_GetPeriphCLKFreq()
437 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; in HAL_RCCEx_GetPeriphCLKFreq()
514 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; in HAL_RCCEx_GetPeriphCLKFreq()
515 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; in HAL_RCCEx_GetPeriphCLKFreq()
539 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; in HAL_RCCEx_GetPeriphCLKFreq()
540 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; in HAL_RCCEx_GetPeriphCLKFreq()
[all …]
Dstm32f1xx_hal_rcc.c320 CLEAR_REG(RCC->CFGR2); in HAL_RCC_DeInit()
605 ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) in HAL_RCC_OscConfig()
664 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); in HAL_RCC_OscConfig()
724 SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); in HAL_RCC_OscConfig()
1118 … prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; in HAL_RCC_GetSysClockFreq()
1124 if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) in HAL_RCC_GetSysClockFreq()
1128 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; in HAL_RCC_GetSysClockFreq()
1129 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; in HAL_RCC_GetSysClockFreq()
1223 RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); in HAL_RCC_GetOscConfig()
1300 RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL); in HAL_RCC_GetOscConfig()
/hal_stm32-2.7.6/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal.h538 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
545 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
552 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
559 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL)
565 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF)
569 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
587 SET_BIT(SYSCFG->CFGR2, (__PIN__));\
591 … CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\
630 SET_BIT(SYSCFG->CFGR2, (__BREAK__));\
634 CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\
Dstm32g0xx_ll_system.h1528 …MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_E… in LL_SYSCFG_SetTIMBreakInputs()
1530 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_ECCL, Break); in LL_SYSCFG_SetTIMBreakInputs()
1553 …return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL … in LL_SYSCFG_GetTIMBreakInputs()
1555 …return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_ECCL)… in LL_SYSCFG_GetTIMBreakInputs()
1566 return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL); in LL_SYSCFG_IsActiveFlag_SP()
1576 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF); in LL_SYSCFG_ClearFlag_SP()
1603 SET_BIT(SYSCFG->CFGR2, ConfigClampingDiode); in LL_SYSCFG_EnableClampingDiode()
1629 CLEAR_BIT(SYSCFG->CFGR2, ConfigClampingDiode); in LL_SYSCFG_DisableClampingDiode()
1654 return ((READ_BIT(SYSCFG->CFGR2, ConfigClampingDiode) == (ConfigClampingDiode)) ? 1UL : 0UL); in LL_SYSCFG_IsEnabledClampingDiode()
Dstm32g0xx_ll_adc.h1918 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); in LL_ADC_SetClock()
1942 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); in LL_ADC_GetClock()
2193 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode); in LL_ADC_SetTriggerFrequencyMode()
2206 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); in LL_ADC_GetTriggerFrequencyMode()
4047 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); in LL_ADC_SetOverSamplingScope()
4060 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); in LL_ADC_GetOverSamplingScope()
4084 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); in LL_ADC_SetOverSamplingDiscont()
4103 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); in LL_ADC_GetOverSamplingDiscont()
4140 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); in LL_ADC_ConfigOverSamplingRatioShift()
4159 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); in LL_ADC_GetOverSamplingRatio()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_rcc.h823 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)); in LL_RCC_HSE_GetPrediv2()
1185 MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U)); in LL_RCC_SetI2SClockSource()
1244 return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx); in LL_RCC_GetI2SClockSource()
1483 MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC), in LL_RCC_PLL_ConfigDomain_SYS()
1486 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1)); in LL_RCC_PLL_ConfigDomain_SYS()
1504 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); in LL_RCC_PLL_SetMainSource()
1524 uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); in LL_RCC_PLL_GetMainSource()
1587 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)); in LL_RCC_PLL_GetPrediv()
1667 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator); in LL_RCC_PLL_ConfigDomain_PLLI2S()
1686 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL)); in LL_RCC_PLLI2S_GetMultiplicator()
[all …]
Dstm32f1xx_hal_rcc_ex.h1591 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1,…
1611 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
1660 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
1752 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
1757 #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
1798 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
1816 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
1823 #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
1832 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
1839 #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
/hal_stm32-2.7.6/stm32cube/stm32f1xx/soc/
Dsystem_stm32f1xx.c265 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; in SystemCoreClockUpdate()
301 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; in SystemCoreClockUpdate()
302 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; in SystemCoreClockUpdate()
313 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; in SystemCoreClockUpdate()
314 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; in SystemCoreClockUpdate()
/hal_stm32-2.7.6/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal.h411 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
412 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
427 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
428 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
443 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK);…
444 … SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
458 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
Dstm32f0xx_ll_system.h1537 …MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_… in LL_SYSCFG_SetTIMBreakInputs()
1539 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break); in LL_SYSCFG_SetTIMBreakInputs()
1558 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, in LL_SYSCFG_GetTIMBreakInputs()
1561 …return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK… in LL_SYSCFG_GetTIMBreakInputs()
1572 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF)); in LL_SYSCFG_IsActiveFlag_SP()
1582 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF); in LL_SYSCFG_ClearFlag_SP()
/hal_stm32-2.7.6/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_system.h353 CLEAR_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN); in LL_SYSCFG_EnableFirewall()
363 return !(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN) == SYSCFG_CFGR2_FWDISEN); in LL_SYSCFG_IsEnabledFirewall()
387 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA, IoPinConnect); in LL_SYSCFG_SetVLCDRailConnection()
410 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA)); in LL_SYSCFG_GetVLCDRailConnection()
432 SET_BIT(SYSCFG->CFGR2, ConfigFastModePlus); in LL_SYSCFG_EnableFastModePlus()
453 CLEAR_BIT(SYSCFG->CFGR2, ConfigFastModePlus); in LL_SYSCFG_DisableFastModePlus()
Dstm32l0xx_hal.h310 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA, (uint32_t)(__SYSCFG_VLCD_CAPA__))
321 #define __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() READ_BIT(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA)
350 … SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \
360 … CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \
Dstm32l0xx_ll_adc.h1872 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); in LL_ADC_SetClock()
1896 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); in LL_ADC_GetClock()
3140 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); in LL_ADC_SetOverSamplingScope()
3153 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); in LL_ADC_GetOverSamplingScope()
3177 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); in LL_ADC_SetOverSamplingDiscont()
3196 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); in LL_ADC_GetOverSamplingDiscont()
3234 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); in LL_ADC_ConfigOverSamplingRatioShift()
3253 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); in LL_ADC_GetOverSamplingRatio()
3273 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); in LL_ADC_GetOverSamplingShift()
/hal_stm32-2.7.6/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal.h394 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
400 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
406 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
412 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
421 …SCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
426 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
/hal_stm32-2.7.6/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal.h435 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
441 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
447 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
453 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
462 …FG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
467 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
/hal_stm32-2.7.6/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc.c404 CLEAR_REG(RCC->CFGR2); in HAL_RCC_DeInit()
1451 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); in HAL_RCC_ClockConfig()
1458 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider); in HAL_RCC_ClockConfig()
1465 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4)); in HAL_RCC_ClockConfig()
1490 …SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_… in HAL_RCC_ClockConfig()
1706 …SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_… in HAL_RCC_GetHCLKFreq()
1719 …return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_P… in HAL_RCC_GetPCLK1Freq()
1731 …return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_P… in HAL_RCC_GetPCLK2Freq()
1901 pRCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_HPRE); in HAL_RCC_GetClockConfig()
1904 pRCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PPRE1); in HAL_RCC_GetClockConfig()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal.h444 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
450 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
457 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
463 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
472 …FG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
477 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
Dstm32u5xx_ll_adc.h4268 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, (TriggerFrequencyMode >> 2U)); in LL_ADC_SetTriggerFrequencyMode()
4272 MODIFY_REG(ADCx->CFGR2, ADC4_CFGR2_LFTRIG, TriggerFrequencyMode); in LL_ADC_SetTriggerFrequencyMode()
4288 return (uint32_t)((READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)) << 2U); in LL_ADC_GetTriggerFrequencyMode()
4292 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC4_CFGR2_LFTRIG)); in LL_ADC_GetTriggerFrequencyMode()
4316 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode); in LL_ADC_REG_SetSamplingMode()
4331 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG)); in LL_ADC_REG_GetSamplingMode()
4351 SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); in LL_ADC_REG_StartSamplingPhase()
4373 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); in LL_ADC_REG_StopSamplingPhase()
7347 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope); in LL_ADC_SetOverSamplingScope()
7351 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE, OvsScope); in LL_ADC_SetOverSamplingScope()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal.h500 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
506 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
512 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
518 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
527 …__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0…
531 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
/hal_stm32-2.7.6/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_adc.h1874 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); in LL_ADC_SetClock()
1898 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); in LL_ADC_GetClock()
2149 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode); in LL_ADC_SetTriggerFrequencyMode()
2162 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); in LL_ADC_GetTriggerFrequencyMode()
3993 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); in LL_ADC_SetOverSamplingScope()
4006 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); in LL_ADC_GetOverSamplingScope()
4030 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); in LL_ADC_SetOverSamplingDiscont()
4049 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); in LL_ADC_GetOverSamplingDiscont()
4086 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); in LL_ADC_ConfigOverSamplingRatioShift()
4105 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); in LL_ADC_GetOverSamplingRatio()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal.h165 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
166 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
179 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
180 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
/hal_stm32-2.7.6/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal.h734 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
735 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
750 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
751 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
766 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK);…
767 … SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
Dstm32f3xx_ll_rcc.h1674 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource); in LL_RCC_SetADCClockSource()
1716 MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU)); in LL_RCC_SetADCClockSource()
1718 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource); in LL_RCC_SetADCClockSource()
1988 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx)); in LL_RCC_GetADCClockSource()
2034 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U)); in LL_RCC_GetADCClockSource()
2036 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx)); in LL_RCC_GetADCClockSource()
2247 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); in LL_RCC_PLL_ConfigDomain_SYS()
2296 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); in LL_RCC_PLL_ConfigDomain_SYS()
2383 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); in LL_RCC_PLL_GetPrediv()
Dstm32f3xx_ll_system.h1225 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break); in LL_SYSCFG_SetTIMBreakInputs()
1242 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK)); in LL_SYSCFG_GetTIMBreakInputs()
1253 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR); in LL_SYSCFG_DisableSRAMParityCheck()
1265 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE)); in LL_SYSCFG_IsActiveFlag_SP()
1275 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE); in LL_SYSCFG_ClearFlag_SP()
/hal_stm32-2.7.6/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_adc.h2623 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); in LL_ADC_SetClock()
2647 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); in LL_ADC_GetClock()
3011 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode); in LL_ADC_SetTriggerFrequencyMode()
3024 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); in LL_ADC_GetTriggerFrequencyMode()
6355 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); in LL_ADC_SetOverSamplingScope()
6357 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope); in LL_ADC_SetOverSamplingScope()
6386 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); in LL_ADC_GetOverSamplingScope()
6388 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); in LL_ADC_GetOverSamplingScope()
6417 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); in LL_ADC_SetOverSamplingDiscont()
6419 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont); in LL_ADC_SetOverSamplingDiscont()
[all …]

1234567891011