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Searched refs:CCR (Results 1 – 25 of 479) sorted by relevance

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/hal_stm32-2.7.6/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_dma.h513 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
534 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
555 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_IsEnabledChannel()
585 …EG(((DMA_Channel_TypeDef *)(dma_base_addr + (uint32_t)(CHANNEL_OFFSET_TAB[Channel & 0x07U])))->CCR, in LL_DMA_ConfigChannelSecure()
613 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_GetConfigChannelSecure()
654 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_ConfigTransfer()
682 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_SetDataTransferDirection()
708 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_GetDataTransferDirection()
735 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CI… in LL_DMA_SetMode()
759 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_GetMode()
[all …]
Dstm32l5xx_ll_dmamux.h536 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); in LL_DMAMUX_SetRequestID()
662 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); in LL_DMAMUX_GetRequestID()
692 …MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_… in LL_DMAMUX_SetSyncRequestNb()
721 …return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR… in LL_DMAMUX_GetSyncRequestNb()
755 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); in LL_DMAMUX_SetSyncPolarity()
788 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); in LL_DMAMUX_GetSyncPolarity()
817 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_EnableEventGeneration()
846 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_DisableEventGeneration()
875 …return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL :… in LL_DMAMUX_IsEnabledEventGeneration()
904 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); in LL_DMAMUX_EnableSync()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_dma.h489 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
509 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
529 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_IsEnabledChannel()
558 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + (uint32_t)(CHANNEL_OFFSET_TAB[Channel])))->CCR, in LL_DMA_ConfigChannelSecure()
585 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_GetConfigChannelSecure()
607 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_GetConfigChannelSecure()
645 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_ConfigTransfer()
672 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_SetDataTransferDirection()
697 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_GetDataTransferDirection()
723 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CI… in LL_DMA_SetMode()
[all …]
Dstm32wlxx_ll_dmamux.h400 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); in LL_DMAMUX_SetRequestID()
472 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); in LL_DMAMUX_GetRequestID()
502 …MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_… in LL_DMAMUX_SetSyncRequestNb()
531 …return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR… in LL_DMAMUX_GetSyncRequestNb()
565 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); in LL_DMAMUX_SetSyncPolarity()
598 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); in LL_DMAMUX_GetSyncPolarity()
627 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_EnableEventGeneration()
656 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_DisableEventGeneration()
685 …return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL … in LL_DMAMUX_IsEnabledEventGeneration()
714 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); in LL_DMAMUX_EnableSync()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f0xx/drivers/src/
Dstm32f0xx_hal_dma.c162 tmp = hdma->Instance->CCR; in HAL_DMA_Init()
176 hdma->Instance->CCR = tmp; in HAL_DMA_Init()
212 hdma->Instance->CCR &= ~DMA_CCR_EN; in HAL_DMA_DeInit()
215 hdma->Instance->CCR = 0U; in HAL_DMA_DeInit()
300 hdma->Instance->CCR &= ~DMA_CCR_EN; in HAL_DMA_Start()
306 hdma->Instance->CCR |= DMA_CCR_EN; in HAL_DMA_Start()
347 hdma->Instance->CCR &= ~DMA_CCR_EN; in HAL_DMA_Start_IT()
356 hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); in HAL_DMA_Start_IT()
360 hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); in HAL_DMA_Start_IT()
361 hdma->Instance->CCR &= ~DMA_IT_HT; in HAL_DMA_Start_IT()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_hal_dma.c161 tmp = hdma->Instance->CCR; in HAL_DMA_Init()
175 hdma->Instance->CCR = tmp; in HAL_DMA_Init()
211 hdma->Instance->CCR &= ~DMA_CCR_EN; in HAL_DMA_DeInit()
214 hdma->Instance->CCR = 0U; in HAL_DMA_DeInit()
299 hdma->Instance->CCR &= ~DMA_CCR_EN; in HAL_DMA_Start()
305 hdma->Instance->CCR |= DMA_CCR_EN; in HAL_DMA_Start()
346 hdma->Instance->CCR &= ~DMA_CCR_EN; in HAL_DMA_Start_IT()
355 hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); in HAL_DMA_Start_IT()
359 hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); in HAL_DMA_Start_IT()
360 hdma->Instance->CCR &= ~DMA_IT_HT; in HAL_DMA_Start_IT()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_dma.h507 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
526 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
545 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, in LL_DMA_IsEnabledChannel()
580 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, in LL_DMA_ConfigTransfer()
606 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, in LL_DMA_SetDataTransferDirection()
630 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, in LL_DMA_GetDataTransferDirection()
655 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC, in LL_DMA_SetMode()
677 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, in LL_DMA_GetMode()
700 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC, in LL_DMA_SetPeriphIncMode()
722 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, in LL_DMA_GetPeriphIncMode()
[all …]
Dstm32wbxx_ll_dmamux.h412 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); in LL_DMAMUX_SetRequestID()
484 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); in LL_DMAMUX_GetRequestID()
516 …MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_… in LL_DMAMUX_SetSyncRequestNb()
547 …return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR… in LL_DMAMUX_GetSyncRequestNb()
583 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); in LL_DMAMUX_SetSyncPolarity()
618 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); in LL_DMAMUX_GetSyncPolarity()
649 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_EnableEventGeneration()
680 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_DisableEventGeneration()
711 …return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL … in LL_DMAMUX_IsEnabledEventGeneration()
742 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); in LL_DMAMUX_EnableSync()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_bdma.h489 …SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR… in LL_BDMA_EnableChannel()
511 …CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_C… in LL_BDMA_DisableChannel()
533 …BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN) == (B… in LL_BDMA_IsEnabledChannel()
570 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, in LL_BDMA_ConfigTransfer()
599 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, in LL_BDMA_SetDataTransferDirection()
626 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, in LL_BDMA_GetDataTransferDirection()
654 …MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_… in LL_BDMA_SetMode()
679 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, in LL_BDMA_GetMode()
705 …MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_… in LL_BDMA_SetPeriphIncMode()
730 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, in LL_BDMA_GetPeriphIncMode()
[all …]
Dstm32h7xx_hal_adc_ex.h776 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
777 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
778 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
793 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
806 ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
820 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
821 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
822 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
829 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
830 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
[all …]
Dstm32h7xx_ll_mdma.h696 …SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR… in LL_MDMA_EnableChannel()
726 …CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_C… in LL_MDMA_DisableChannel()
756 …return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR,… in LL_MDMA_IsEnabledChannel()
786 …SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR… in LL_MDMA_GenerateSWRequest()
822 MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, in LL_MDMA_ConfigXferEndianness()
856 …MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_… in LL_MDMA_SetWordEndianness()
889 …return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR,… in LL_MDMA_GetWordEndianness()
922 …MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_… in LL_MDMA_SetHalfWordEndianness()
955 …return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR,… in LL_MDMA_GetHalfWordEndianness()
988 …MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_… in LL_MDMA_SetByteEndianness()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_dma.h456 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
475 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
494 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_IsEnabledChannel()
529 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_ConfigTransfer()
555 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_SetDataTransferDirection()
579 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetDataTransferDirection()
604 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, in LL_DMA_SetMode()
626 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMode()
649 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, in LL_DMA_SetPeriphIncMode()
671 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetPeriphIncMode()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_dma.h504 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
524 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
544 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_IsEnabledChannel()
580 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_ConfigTransfer()
607 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_SetDataTransferDirection()
632 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_GetDataTransferDirection()
658 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CI… in LL_DMA_SetMode()
681 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_GetMode()
705 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PI… in LL_DMA_SetPeriphIncMode()
728 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_GetPeriphIncMode()
[all …]
Dstm32g0xx_ll_dmamux.h528 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); in LL_DMAMUX_SetRequestID()
619 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); in LL_DMAMUX_GetRequestID()
649 …MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_… in LL_DMAMUX_SetSyncRequestNb()
678 …return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR… in LL_DMAMUX_GetSyncRequestNb()
712 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); in LL_DMAMUX_SetSyncPolarity()
745 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); in LL_DMAMUX_GetSyncPolarity()
774 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_EnableEventGeneration()
803 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_DisableEventGeneration()
832 …return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL … in LL_DMAMUX_IsEnabledEventGeneration()
861 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); in LL_DMAMUX_EnableSync()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_dma.c190 tmp = hdma->Instance->CCR; in HAL_DMA_Init()
205 hdma->Instance->CCR = tmp; in HAL_DMA_Init()
219 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); in HAL_DMA_Init()
292 hdma->Instance->CCR = 0U; in HAL_DMA_DeInit()
303 hdma->DMAmuxChannel->CCR = 0U; in HAL_DMA_DeInit()
458 if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) in HAL_DMA_Start_IT()
461 hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; in HAL_DMA_Start_IT()
511 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; in HAL_DMA_Abort()
568 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; in HAL_DMA_Abort_IT()
623 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U) in HAL_DMA_PollForTransfer()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_dma.h509 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
528 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
547 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_IsEnabledChannel()
582 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_ConfigTransfer()
608 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_SetDataTransferDirection()
632 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetDataTransferDirection()
657 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, in LL_DMA_SetMode()
679 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMode()
702 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, in LL_DMA_SetPeriphIncMode()
724 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetPeriphIncMode()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_dma.h492 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
511 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
530 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_IsEnabledChannel()
565 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_ConfigTransfer()
591 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_SetDataTransferDirection()
615 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetDataTransferDirection()
640 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, in LL_DMA_SetMode()
662 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMode()
685 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, in LL_DMA_SetPeriphIncMode()
707 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetPeriphIncMode()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_dma.h493 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
512 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
531 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_IsEnabledChannel()
566 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_ConfigTransfer()
592 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_SetDataTransferDirection()
616 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetDataTransferDirection()
641 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, in LL_DMA_SetMode()
663 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMode()
686 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, in LL_DMA_SetPeriphIncMode()
708 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetPeriphIncMode()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_dma.h556 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
576 …CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
596 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_IsEnabledChannel()
632 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_ConfigTransfer()
659 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_SetDataTransferDirection()
684 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_GetDataTransferDirection()
710 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CI… in LL_DMA_SetMode()
733 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_GetMode()
757 …MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PI… in LL_DMA_SetPeriphIncMode()
780 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, in LL_DMA_GetPeriphIncMode()
[all …]
Dstm32l4xx_ll_dmamux.h650 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); in LL_DMAMUX_SetRequestID()
773 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); in LL_DMAMUX_GetRequestID()
801 …MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_… in LL_DMAMUX_SetSyncRequestNb()
828 …return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR… in LL_DMAMUX_GetSyncRequestNb()
860 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); in LL_DMAMUX_SetSyncPolarity()
891 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); in LL_DMAMUX_GetSyncPolarity()
918 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_EnableEventGeneration()
945 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_DisableEventGeneration()
972 …return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL :… in LL_DMAMUX_IsEnabledEventGeneration()
999 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); in LL_DMAMUX_EnableSync()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_dma.h521 …SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, D… in LL_DMA_EnableChannel()
543 …CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,… in LL_DMA_DisableChannel()
565 …((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, in LL_DMA_IsEnabledChannel()
603 …MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, in LL_DMA_ConfigTransfer()
632 …MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, in LL_DMA_SetDataTransferDirection()
659 … (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, in LL_DMA_GetDataTransferDirection()
687 …MA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_CIRC, in LL_DMA_SetMode()
712 … (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, in LL_DMA_GetMode()
738 …MA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PINC, in LL_DMA_SetPeriphIncMode()
763 … (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, in LL_DMA_GetPeriphIncMode()
[all …]
Dstm32g4xx_ll_dmamux.h561 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); in LL_DMAMUX_SetRequestID()
711 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); in LL_DMAMUX_GetRequestID()
741 …MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_… in LL_DMAMUX_SetSyncRequestNb()
770 …return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR… in LL_DMAMUX_GetSyncRequestNb()
804 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); in LL_DMAMUX_SetSyncPolarity()
837 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); in LL_DMAMUX_GetSyncPolarity()
866 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_EnableEventGeneration()
895 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_DisableEventGeneration()
924 …return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL :… in LL_DMAMUX_IsEnabledEventGeneration()
953 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); in LL_DMAMUX_EnableSync()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_dma.h585 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
604 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
623 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_IsEnabledChannel()
658 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_ConfigTransfer()
684 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_SetDataTransferDirection()
708 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetDataTransferDirection()
733 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, in LL_DMA_SetMode()
755 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMode()
778 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, in LL_DMA_SetPeriphIncMode()
800 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetPeriphIncMode()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_hal_dma.c190 CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ in HAL_DMA_Init()
195 SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ in HAL_DMA_Init()
212 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); in HAL_DMA_Init()
284 hdma->Instance->CCR = 0U; in HAL_DMA_DeInit()
295 hdma->DMAmuxChannel->CCR = 0U; in HAL_DMA_DeInit()
457 if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) in HAL_DMA_Start_IT()
460 hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; in HAL_DMA_Start_IT()
518 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; in HAL_DMA_Abort()
575 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; in HAL_DMA_Abort_IT()
630 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U) in HAL_DMA_PollForTransfer()
[all …]
/hal_stm32-2.7.6/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_dmamux.h538 …ypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ… in LL_DMAMUX_SetRequestID()
679 …ypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ… in LL_DMAMUX_GetRequestID()
708 …ypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_NBREQ,… in LL_DMAMUX_SetSyncRequestNb()
736 …ypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_NBREQ)… in LL_DMAMUX_GetSyncRequestNb()
769 …ypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SPOL, … in LL_DMAMUX_SetSyncPolarity()
801 …ypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SPOL)); in LL_DMAMUX_GetSyncPolarity()
829 …_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_EnableEventGeneration()
857 …_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_DisableEventGeneration()
885 …ypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE) =… in LL_DMAMUX_IsEnabledEventGeneration()
913 …l_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SE); in LL_DMAMUX_EnableSync()
[all …]

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