ADC_CFGR1_AWD1CH_1 (reference) in projects: hal_stm32-2.7.6

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Searched refs:ADC_CFGR1_AWD1CH_1 (Results 1 – 25 of 39) sorted by relevance

/hal_stm32-2.7.6/stm32cube/stm32wlxx/drivers/include/
D	stm32wlxx_ll_adc.h	119 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1) 120 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 \| ADC_CFGR1_AWD1CH_0) 123 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 \| ADC_CFGR1_AWD1CH_1) 124 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 \| ADC_CFGR1_AWD1CH_1 \| ADC_CFGR1_AWD… 127 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 \| ADC_CFGR1_AWD1CH_1) 128 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 \| ADC_CFGR1_AWD1CH_1 \| ADC_CFGR1_AWD… 131 …e ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 \| ADC_CFGR1_AWD1CH_2 \| ADC_CFGR1_AWD1CH_1) 133 ADC_CFGR1_AWD1CH_1 \| ADC_CFGR1_AWD1CH_0) 136 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 \| ADC_CFGR1_AWD1CH_1)
/hal_stm32-2.7.6/stm32cube/stm32g0xx/drivers/include/
D	stm32g0xx_ll_adc.h	119 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1) 120 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 \| ADC_CFGR1_AWD1CH_0) 123 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 \| ADC_CFGR1_AWD1CH_1) 124 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 \| ADC_CFGR1_AWD1CH_1 \| ADC_CFGR1_AWD… 127 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 \| ADC_CFGR1_AWD1CH_1) 128 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 \| ADC_CFGR1_AWD1CH_1 \| ADC_CFGR1_AWD… 131 …e ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 \| ADC_CFGR1_AWD1CH_2 \| ADC_CFGR1_AWD1CH_1) 133 ADC_CFGR1_AWD1CH_1 \| ADC_CFGR1_AWD1CH_0) 136 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 \| ADC_CFGR1_AWD1CH_1)
/hal_stm32-2.7.6/stm32cube/stm32u5xx/drivers/include/
D	stm32u5xx_ll_adc.h	275 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1) 276 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 \| ADC_CFGR1_AWD1CH_0) 279 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 \| ADC_CFGR1_AWD1CH_1) 280 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 \| ADC_CFGR1_AWD1CH_1 \| ADC_CFGR1_AWD1CH_0) 283 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 \| ADC_CFGR1_AWD1CH_1) 284 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 \| ADC_CFGR1_AWD1CH_1 \| ADC_CFGR1_AWD1CH_0) 287 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 \| ADC_CFGR1_AWD1CH_2 \| ADC_CFGR1_AWD1CH_1) 288 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 \| ADC_CFGR1_AWD1CH_2 \| ADC_CFGR1_AWD1CH_1 \| A… 291 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 \| ADC_CFGR1_AWD1CH_1) 292 #define ADC_CHANNEL_19_NUMBER (ADC_CFGR1_AWD1CH_4 \| ADC_CFGR1_AWD1CH_1 \| ADC_CFGR1_AWD1CH_0) [all …]
/hal_stm32-2.7.6/stm32cube/stm32f0xx/soc/
D	stm32f070x6.h	`727 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 738 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f030x6.h	`682 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 693 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f030x8.h	`698 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 709 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f030xc.h	`714 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 725 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f031x6.h	`692 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 703 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f038xx.h	`691 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 702 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f070xb.h	`750 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 761 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f051x8.h	`798 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 809 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f058xx.h	`797 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 808 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f071xb.h	`832 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 843 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f042x6.h	`861 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 872 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f048xx.h	`861 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 872 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f072xb.h	`936 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 947 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f078xx.h	`936 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 947 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f091xc.h	`918 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 929 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
D	stm32f098xx.h	`918 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 929 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)`
/hal_stm32-2.7.6/stm32cube/stm32wbxx/soc/Include/
D	stm32wb10xx.h	`1134 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 1204 #define ADC_CFGR_AWD1CH_1 ADC_CFGR1_AWD1CH_1`
D	stm32wb15xx.h	`1149 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro 1219 #define ADC_CFGR_AWD1CH_1 ADC_CFGR1_AWD1CH_1`
/hal_stm32-2.7.6/stm32cube/stm32g0xx/soc/
D	stm32g070xx.h	`862 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro`
D	stm32g031xx.h	`883 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro`
D	stm32g030xx.h	`840 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro`
D	stm32g050xx.h	`859 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 / macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
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