1 /** 2 ****************************************************************************** 3 * @file lps22hb_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lps22hb_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LPS22HB_REGS_H 23 #define LPS22HB_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LPS22HB 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BIG_ENDIAN */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct _stmdev_ctx_t 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 167 /** @defgroup LPS22HB_Infos 168 * @{ 169 * 170 */ 171 172 /** I2C Device Address 8 bit format: if SA0=0 -> 0xB9 if SA0=1 -> 0xBB **/ 173 #define LPS22HB_I2C_ADD_H 0xBBU 174 #define LPS22HB_I2C_ADD_L 0xB9U 175 176 /** Device Identification (Who am I) **/ 177 #define LPS22HB_ID 0xB1U 178 179 /** 180 * @} 181 * 182 */ 183 184 #define LPS22HB_INTERRUPT_CFG 0x0BU 185 typedef struct 186 { 187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 188 uint8_t pe : 2; /* ple + phe -> pe */ 189 uint8_t lir : 1; 190 uint8_t diff_en : 1; 191 uint8_t reset_az : 1; 192 uint8_t autozero : 1; 193 uint8_t reset_arp : 1; 194 uint8_t autorifp : 1; 195 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 196 uint8_t autorifp : 1; 197 uint8_t reset_arp : 1; 198 uint8_t autozero : 1; 199 uint8_t reset_az : 1; 200 uint8_t diff_en : 1; 201 uint8_t lir : 1; 202 uint8_t pe : 2; /* ple + phe -> pe */ 203 #endif /* DRV_BIG_ENDIAN */ 204 } lps22hb_interrupt_cfg_t; 205 206 #define LPS22HB_THS_P_L 0x0CU 207 #define LPS22HB_THS_P_H 0x0DU 208 #define LPS22HB_WHO_AM_I 0x0FU 209 #define LPS22HB_CTRL_REG1 0x10U 210 typedef struct 211 { 212 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 213 uint8_t sim : 1; 214 uint8_t bdu : 1; 215 uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */ 216 uint8_t odr : 3; 217 uint8_t not_used_01 : 1; 218 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 219 uint8_t not_used_01 : 1; 220 uint8_t odr : 3; 221 uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */ 222 uint8_t bdu : 1; 223 uint8_t sim : 1; 224 #endif /* DRV_BIG_ENDIAN */ 225 } lps22hb_ctrl_reg1_t; 226 227 #define LPS22HB_CTRL_REG2 0x11U 228 typedef struct 229 { 230 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 231 uint8_t one_shot : 1; 232 uint8_t not_used_01 : 1; 233 uint8_t swreset : 1; 234 uint8_t i2c_dis : 1; 235 uint8_t if_add_inc : 1; 236 uint8_t stop_on_fth : 1; 237 uint8_t fifo_en : 1; 238 uint8_t boot : 1; 239 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 240 uint8_t boot : 1; 241 uint8_t fifo_en : 1; 242 uint8_t stop_on_fth : 1; 243 uint8_t if_add_inc : 1; 244 uint8_t i2c_dis : 1; 245 uint8_t swreset : 1; 246 uint8_t not_used_01 : 1; 247 uint8_t one_shot : 1; 248 #endif /* DRV_BIG_ENDIAN */ 249 } lps22hb_ctrl_reg2_t; 250 251 #define LPS22HB_CTRL_REG3 0x12U 252 typedef struct 253 { 254 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 255 uint8_t int_s : 2; 256 uint8_t drdy : 1; 257 uint8_t f_ovr : 1; 258 uint8_t f_fth : 1; 259 uint8_t f_fss5 : 1; 260 uint8_t pp_od : 1; 261 uint8_t int_h_l : 1; 262 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 263 uint8_t int_h_l : 1; 264 uint8_t pp_od : 1; 265 uint8_t f_fss5 : 1; 266 uint8_t f_fth : 1; 267 uint8_t f_ovr : 1; 268 uint8_t drdy : 1; 269 uint8_t int_s : 2; 270 #endif /* DRV_BIG_ENDIAN */ 271 272 } lps22hb_ctrl_reg3_t; 273 274 275 #define LPS22HB_FIFO_CTRL 0x14U 276 typedef struct 277 { 278 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 279 uint8_t wtm : 5; 280 uint8_t f_mode : 3; 281 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 282 uint8_t f_mode : 3; 283 uint8_t wtm : 5; 284 #endif /* DRV_BIG_ENDIAN */ 285 286 } lps22hb_fifo_ctrl_t; 287 288 #define LPS22HB_REF_P_XL 0x15U 289 #define LPS22HB_REF_P_L 0x16U 290 #define LPS22HB_REF_P_H 0x17U 291 #define LPS22HB_RPDS_L 0x18U 292 #define LPS22HB_RPDS_H 0x19U 293 294 #define LPS22HB_RES_CONF 0x1AU 295 typedef struct 296 { 297 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 298 uint8_t lc_en : 1; 299 uint8_t not_used_01 : 7; 300 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 301 uint8_t not_used_01 : 7; 302 uint8_t lc_en : 1; 303 #endif /* DRV_BIG_ENDIAN */ 304 305 } lps22hb_res_conf_t; 306 307 #define LPS22HB_INT_SOURCE 0x25U 308 typedef struct 309 { 310 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 311 uint8_t ph : 1; 312 uint8_t pl : 1; 313 uint8_t ia : 1; 314 uint8_t not_used_01 : 4; 315 uint8_t boot_status : 1; 316 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 317 uint8_t boot_status : 1; 318 uint8_t not_used_01 : 4; 319 uint8_t ia : 1; 320 uint8_t pl : 1; 321 uint8_t ph : 1; 322 #endif /* DRV_BIG_ENDIAN */ 323 } lps22hb_int_source_t; 324 325 #define LPS22HB_FIFO_STATUS 0x26U 326 typedef struct 327 { 328 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 329 uint8_t fss : 6; 330 uint8_t ovr : 1; 331 uint8_t fth_fifo : 1; 332 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 333 uint8_t fth_fifo : 1; 334 uint8_t ovr : 1; 335 uint8_t fss : 6; 336 #endif /* DRV_BIG_ENDIAN */ 337 } lps22hb_fifo_status_t; 338 339 #define LPS22HB_STATUS 0x27U 340 typedef struct 341 { 342 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 343 uint8_t p_da : 1; 344 uint8_t t_da : 1; 345 uint8_t not_used_02 : 2; 346 uint8_t p_or : 1; 347 uint8_t t_or : 1; 348 uint8_t not_used_01 : 2; 349 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 350 uint8_t not_used_01 : 2; 351 uint8_t t_or : 1; 352 uint8_t p_or : 1; 353 uint8_t not_used_02 : 2; 354 uint8_t t_da : 1; 355 uint8_t p_da : 1; 356 #endif /* DRV_BIG_ENDIAN */ 357 } lps22hb_status_t; 358 359 #define LPS22HB_PRESS_OUT_XL 0x28U 360 #define LPS22HB_PRESS_OUT_L 0x29U 361 #define LPS22HB_PRESS_OUT_H 0x2AU 362 #define LPS22HB_TEMP_OUT_L 0x2BU 363 #define LPS22HB_TEMP_OUT_H 0x2CU 364 #define LPS22HB_LPFP_RES 0x33U 365 366 /** 367 * @defgroup LPS22HB_Register_Union 368 * @brief This union group all the registers having a bit-field 369 * description. 370 * This union is useful but it's not needed by the driver. 371 * 372 * REMOVING this union you are compliant with: 373 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 374 * 375 * @{ 376 * 377 */ 378 379 typedef union 380 { 381 lps22hb_interrupt_cfg_t interrupt_cfg; 382 lps22hb_ctrl_reg1_t ctrl_reg1; 383 lps22hb_ctrl_reg2_t ctrl_reg2; 384 lps22hb_ctrl_reg3_t ctrl_reg3; 385 lps22hb_fifo_ctrl_t fifo_ctrl; 386 lps22hb_res_conf_t res_conf; 387 lps22hb_int_source_t int_source; 388 lps22hb_fifo_status_t fifo_status; 389 lps22hb_status_t status; 390 bitwise_t bitwise; 391 uint8_t byte; 392 } lps22hb_reg_t; 393 394 /** 395 * @} 396 * 397 */ 398 399 #ifndef __weak 400 #define __weak __attribute__((weak)) 401 #endif /* __weak */ 402 403 /* 404 * These are the basic platform dependent I/O routines to read 405 * and write device registers connected on a standard bus. 406 * The driver keeps offering a default implementation based on function 407 * pointers to read/write routines for backward compatibility. 408 * The __weak directive allows the final application to overwrite 409 * them with a custom implementation. 410 */ 411 412 int32_t lps22hb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 413 uint8_t *data, 414 uint16_t len); 415 int32_t lps22hb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 416 uint8_t *data, 417 uint16_t len); 418 419 float_t lps22hb_from_lsb_to_hpa(int32_t lsb); 420 421 float_t lps22hb_from_lsb_to_kpa(int32_t lsb); 422 423 float_t lps22hb_from_lsb_to_psi(int32_t lsb); 424 425 float_t lps22hb_from_lsb_to_altitude(int32_t lsb); 426 427 float_t lps22hb_from_lsb_to_degc(int16_t lsb); 428 429 int32_t lps22hb_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val); 430 int32_t lps22hb_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); 431 432 int32_t lps22hb_autozero_set(const stmdev_ctx_t *ctx, uint8_t val); 433 int32_t lps22hb_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val); 434 435 int32_t lps22hb_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val); 436 int32_t lps22hb_pressure_snap_rst_get(const stmdev_ctx_t *ctx, 437 uint8_t *val); 438 439 int32_t lps22hb_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val); 440 int32_t lps22hb_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val); 441 442 int32_t lps22hb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 443 int32_t lps22hb_block_data_update_get(const stmdev_ctx_t *ctx, 444 uint8_t *val); 445 446 typedef enum 447 { 448 LPS22HB_LPF_ODR_DIV_2 = 0, 449 LPS22HB_LPF_ODR_DIV_9 = 2, 450 LPS22HB_LPF_ODR_DIV_20 = 3, 451 } lps22hb_lpfp_t; 452 int32_t lps22hb_low_pass_filter_mode_set(const stmdev_ctx_t *ctx, 453 lps22hb_lpfp_t val); 454 int32_t lps22hb_low_pass_filter_mode_get(const stmdev_ctx_t *ctx, 455 lps22hb_lpfp_t *val); 456 457 typedef enum 458 { 459 LPS22HB_POWER_DOWN = 0, 460 LPS22HB_ODR_1_Hz = 1, 461 LPS22HB_ODR_10_Hz = 2, 462 LPS22HB_ODR_25_Hz = 3, 463 LPS22HB_ODR_50_Hz = 4, 464 LPS22HB_ODR_75_Hz = 5, 465 } lps22hb_odr_t; 466 int32_t lps22hb_data_rate_set(const stmdev_ctx_t *ctx, lps22hb_odr_t val); 467 int32_t lps22hb_data_rate_get(const stmdev_ctx_t *ctx, lps22hb_odr_t *val); 468 469 int32_t lps22hb_one_shoot_trigger_set(const stmdev_ctx_t *ctx, uint8_t val); 470 int32_t lps22hb_one_shoot_trigger_get(const stmdev_ctx_t *ctx, 471 uint8_t *val); 472 473 int32_t lps22hb_pressure_ref_set(const stmdev_ctx_t *ctx, int32_t val); 474 int32_t lps22hb_pressure_ref_get(const stmdev_ctx_t *ctx, int32_t *val); 475 476 int32_t lps22hb_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val); 477 int32_t lps22hb_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 478 479 int32_t lps22hb_press_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 480 481 int32_t lps22hb_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 482 483 int32_t lps22hb_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *press_val, uint8_t *temp_val); 484 485 int32_t lps22hb_press_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 486 487 int32_t lps22hb_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 488 489 int32_t lps22hb_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); 490 491 int32_t lps22hb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); 492 493 typedef struct __attribute__((packed)) _lps22hb_fifo_output_data_t 494 { 495 uint8_t bytes[5]; 496 } lps22hb_fifo_output_data_t; 497 498 int32_t lps22hb_fifo_output_data_to_raw_pressure(lps22hb_fifo_output_data_t *val); 499 500 int16_t lps22hb_fifo_output_data_to_raw_temperature(lps22hb_fifo_output_data_t *val); 501 502 int32_t lps22hb_fifo_output_data_burst_get(const stmdev_ctx_t *ctx, 503 lps22hb_fifo_output_data_t *buff, uint8_t len); 504 505 int32_t lps22hb_low_pass_rst_get(const stmdev_ctx_t *ctx, uint8_t *buff); 506 507 int32_t lps22hb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 508 509 int32_t lps22hb_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 510 int32_t lps22hb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 511 512 int32_t lps22hb_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 513 int32_t lps22hb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 514 515 int32_t lps22hb_low_power_set(const stmdev_ctx_t *ctx, uint8_t val); 516 int32_t lps22hb_low_power_get(const stmdev_ctx_t *ctx, uint8_t *val); 517 518 int32_t lps22hb_boot_status_get(const stmdev_ctx_t *ctx, uint8_t *val); 519 520 typedef struct 521 { 522 lps22hb_fifo_status_t fifo_status; 523 lps22hb_status_t status; 524 } lps22hb_dev_stat_t; 525 int32_t lps22hb_dev_status_get(const stmdev_ctx_t *ctx, 526 lps22hb_dev_stat_t *val); 527 528 typedef enum 529 { 530 LPS22HB_NO_THRESHOLD = 0, 531 LPS22HB_POSITIVE = 1, 532 LPS22HB_NEGATIVE = 2, 533 LPS22HB_BOTH = 3, 534 } lps22hb_pe_t; 535 int32_t lps22hb_sign_of_int_threshold_set(const stmdev_ctx_t *ctx, 536 lps22hb_pe_t val); 537 int32_t lps22hb_sign_of_int_threshold_get(const stmdev_ctx_t *ctx, 538 lps22hb_pe_t *val); 539 540 typedef enum 541 { 542 LPS22HB_INT_PULSED = 0, 543 LPS22HB_INT_LATCHED = 1, 544 } lps22hb_lir_t; 545 int32_t lps22hb_int_notification_mode_set(const stmdev_ctx_t *ctx, 546 lps22hb_lir_t val); 547 int32_t lps22hb_int_notification_mode_get(const stmdev_ctx_t *ctx, 548 lps22hb_lir_t *val); 549 550 int32_t lps22hb_int_generation_set(const stmdev_ctx_t *ctx, uint8_t val); 551 int32_t lps22hb_int_generation_get(const stmdev_ctx_t *ctx, uint8_t *val); 552 553 int32_t lps22hb_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); 554 int32_t lps22hb_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); 555 556 typedef enum 557 { 558 LPS22HB_DRDY_OR_FIFO_FLAGS = 0, 559 LPS22HB_HIGH_PRES_INT = 1, 560 LPS22HB_LOW_PRES_INT = 2, 561 LPS22HB_EVERY_PRES_INT = 3, 562 } lps22hb_int_s_t; 563 int32_t lps22hb_int_pin_mode_set(const stmdev_ctx_t *ctx, 564 lps22hb_int_s_t val); 565 int32_t lps22hb_int_pin_mode_get(const stmdev_ctx_t *ctx, 566 lps22hb_int_s_t *val); 567 568 int32_t lps22hb_drdy_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); 569 int32_t lps22hb_drdy_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); 570 571 int32_t lps22hb_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); 572 int32_t lps22hb_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); 573 574 int32_t lps22hb_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, 575 uint8_t val); 576 int32_t lps22hb_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, 577 uint8_t *val); 578 579 int32_t lps22hb_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); 580 int32_t lps22hb_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); 581 582 typedef enum 583 { 584 LPS22HB_PUSH_PULL = 0, 585 LPS22HB_OPEN_DRAIN = 1, 586 } lps22hb_pp_od_t; 587 int32_t lps22hb_pin_mode_set(const stmdev_ctx_t *ctx, lps22hb_pp_od_t val); 588 int32_t lps22hb_pin_mode_get(const stmdev_ctx_t *ctx, lps22hb_pp_od_t *val); 589 590 typedef enum 591 { 592 LPS22HB_ACTIVE_HIGH = 0, 593 LPS22HB_ACTIVE_LOW = 1, 594 } lps22hb_int_h_l_t; 595 int32_t lps22hb_int_polarity_set(const stmdev_ctx_t *ctx, 596 lps22hb_int_h_l_t val); 597 int32_t lps22hb_int_polarity_get(const stmdev_ctx_t *ctx, 598 lps22hb_int_h_l_t *val); 599 600 int32_t lps22hb_int_source_get(const stmdev_ctx_t *ctx, 601 lps22hb_int_source_t *val); 602 603 int32_t lps22hb_int_on_press_high_get(const stmdev_ctx_t *ctx, 604 uint8_t *val); 605 606 int32_t lps22hb_int_on_press_low_get(const stmdev_ctx_t *ctx, uint8_t *val); 607 608 int32_t lps22hb_interrupt_event_get(const stmdev_ctx_t *ctx, uint8_t *val); 609 610 int32_t lps22hb_stop_on_fifo_threshold_set(const stmdev_ctx_t *ctx, 611 uint8_t val); 612 int32_t lps22hb_stop_on_fifo_threshold_get(const stmdev_ctx_t *ctx, 613 uint8_t *val); 614 615 int32_t lps22hb_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); 616 int32_t lps22hb_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); 617 618 int32_t lps22hb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 619 int32_t lps22hb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 620 621 typedef enum 622 { 623 LPS22HB_BYPASS_MODE = 0, 624 LPS22HB_FIFO_MODE = 1, 625 LPS22HB_STREAM_MODE = 2, 626 LPS22HB_STREAM_TO_FIFO_MODE = 3, 627 LPS22HB_BYPASS_TO_STREAM_MODE = 4, 628 LPS22HB_DYNAMIC_STREAM_MODE = 6, 629 LPS22HB_BYPASS_TO_FIFO_MODE = 7, 630 } lps22hb_f_mode_t; 631 int32_t lps22hb_fifo_mode_set(const stmdev_ctx_t *ctx, 632 lps22hb_f_mode_t val); 633 int32_t lps22hb_fifo_mode_get(const stmdev_ctx_t *ctx, 634 lps22hb_f_mode_t *val); 635 636 int32_t lps22hb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 637 638 int32_t lps22hb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 639 640 int32_t lps22hb_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 641 642 typedef enum 643 { 644 LPS22HB_SPI_4_WIRE = 0, 645 LPS22HB_SPI_3_WIRE = 1, 646 } lps22hb_sim_t; 647 int32_t lps22hb_spi_mode_set(const stmdev_ctx_t *ctx, lps22hb_sim_t val); 648 int32_t lps22hb_spi_mode_get(const stmdev_ctx_t *ctx, lps22hb_sim_t *val); 649 650 typedef enum 651 { 652 LPS22HB_I2C_ENABLE = 0, 653 LPS22HB_I2C_DISABLE = 1, 654 } lps22hb_i2c_dis_t; 655 int32_t lps22hb_i2c_interface_set(const stmdev_ctx_t *ctx, 656 lps22hb_i2c_dis_t val); 657 int32_t lps22hb_i2c_interface_get(const stmdev_ctx_t *ctx, 658 lps22hb_i2c_dis_t *val); 659 660 int32_t lps22hb_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val); 661 int32_t lps22hb_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val); 662 663 /** 664 *@} 665 * 666 */ 667 668 #ifdef __cplusplus 669 } 670 #endif 671 672 #endif /* LPS22HB_REGS_H */ 673 674 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 675
