1 /** 2 ****************************************************************************** 3 * @file lsm6dsrx_reg.h 4 * @author Sensor Solutions Software Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dsrx_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSRX_REGS_H 23 #define LSM6DSRX_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSRX 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 /* #define DRV_BYTE_ORDER DRV_BIG_ENDIAN */ 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DSRX Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DSRX_I2C_ADD_L 0xD5U 173 #define LSM6DSRX_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DSRX_ID 0x6BU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LSM6DSRX_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 6; 188 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 190 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 191 uint8_t not_used_01 : 6; 192 #endif /* DRV_BYTE_ORDER */ 193 } lsm6dsrx_func_cfg_access_t; 194 195 #define LSM6DSRX_PIN_CTRL 0x02U 196 typedef struct 197 { 198 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 199 uint8_t not_used_01 : 6; 200 uint8_t sdo_pu_en : 1; 201 uint8_t ois_pu_dis : 1; 202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 203 uint8_t ois_pu_dis : 1; 204 uint8_t sdo_pu_en : 1; 205 uint8_t not_used_01 : 6; 206 #endif /* DRV_BYTE_ORDER */ 207 } lsm6dsrx_pin_ctrl_t; 208 209 #define LSM6DSRX_S4S_TPH_L 0x04U 210 typedef struct 211 { 212 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 213 uint8_t tph_l : 7; 214 uint8_t tph_h_sel : 1; 215 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 216 uint8_t tph_h_sel : 1; 217 uint8_t tph_l : 7; 218 #endif /* DRV_BYTE_ORDER */ 219 } lsm6dsrx_s4s_tph_l_t; 220 221 #define LSM6DSRX_S4S_TPH_H 0x05U 222 typedef struct 223 { 224 uint8_t tph_h : 8; 225 } lsm6dsrx_s4s_tph_h_t; 226 227 #define LSM6DSRX_S4S_RR 0x06U 228 typedef struct 229 { 230 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 231 uint8_t rr : 2; 232 uint8_t not_used_01 : 6; 233 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 234 uint8_t not_used_01 : 6; 235 uint8_t rr : 2; 236 #endif /* DRV_BYTE_ORDER */ 237 } lsm6dsrx_s4s_rr_t; 238 239 #define LSM6DSRX_FIFO_CTRL1 0x07U 240 typedef struct 241 { 242 uint8_t wtm : 8; 243 } lsm6dsrx_fifo_ctrl1_t; 244 245 #define LSM6DSRX_FIFO_CTRL2 0x08U 246 typedef struct 247 { 248 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 249 uint8_t wtm : 1; 250 uint8_t uncoptr_rate : 2; 251 uint8_t not_used_01 : 1; 252 uint8_t odrchg_en : 1; 253 uint8_t not_used_02 : 1; 254 uint8_t fifo_compr_rt_en : 1; 255 uint8_t stop_on_wtm : 1; 256 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 257 uint8_t stop_on_wtm : 1; 258 uint8_t fifo_compr_rt_en : 1; 259 uint8_t not_used_02 : 1; 260 uint8_t odrchg_en : 1; 261 uint8_t not_used_01 : 1; 262 uint8_t uncoptr_rate : 2; 263 uint8_t wtm : 1; 264 #endif /* DRV_BYTE_ORDER */ 265 } lsm6dsrx_fifo_ctrl2_t; 266 267 #define LSM6DSRX_FIFO_CTRL3 0x09U 268 typedef struct 269 { 270 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 271 uint8_t bdr_xl : 4; 272 uint8_t bdr_gy : 4; 273 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 274 uint8_t bdr_gy : 4; 275 uint8_t bdr_xl : 4; 276 #endif /* DRV_BYTE_ORDER */ 277 } lsm6dsrx_fifo_ctrl3_t; 278 279 #define LSM6DSRX_FIFO_CTRL4 0x0AU 280 typedef struct 281 { 282 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 283 uint8_t fifo_mode : 3; 284 uint8_t not_used_01 : 1; 285 uint8_t odr_t_batch : 2; 286 uint8_t odr_ts_batch : 2; 287 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 288 uint8_t odr_ts_batch : 2; 289 uint8_t odr_t_batch : 2; 290 uint8_t not_used_01 : 1; 291 uint8_t fifo_mode : 3; 292 #endif /* DRV_BYTE_ORDER */ 293 } lsm6dsrx_fifo_ctrl4_t; 294 295 #define LSM6DSRX_COUNTER_BDR_REG1 0x0BU 296 typedef struct 297 { 298 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 299 uint8_t cnt_bdr_th : 3; 300 uint8_t not_used_01 : 2; 301 uint8_t trig_counter_bdr : 1; 302 uint8_t rst_counter_bdr : 1; 303 uint8_t dataready_pulsed : 1; 304 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 305 uint8_t dataready_pulsed : 1; 306 uint8_t rst_counter_bdr : 1; 307 uint8_t trig_counter_bdr : 1; 308 uint8_t not_used_01 : 2; 309 uint8_t cnt_bdr_th : 3; 310 #endif /* DRV_BYTE_ORDER */ 311 } lsm6dsrx_counter_bdr_reg1_t; 312 313 #define LSM6DSRX_COUNTER_BDR_REG2 0x0CU 314 typedef struct 315 { 316 uint8_t cnt_bdr_th : 8; 317 } lsm6dsrx_counter_bdr_reg2_t; 318 319 #define LSM6DSRX_INT1_CTRL 0x0DU 320 typedef struct 321 { 322 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 323 uint8_t int1_drdy_xl : 1; 324 uint8_t int1_drdy_g : 1; 325 uint8_t int1_boot : 1; 326 uint8_t int1_fifo_th : 1; 327 uint8_t int1_fifo_ovr : 1; 328 uint8_t int1_fifo_full : 1; 329 uint8_t int1_cnt_bdr : 1; 330 uint8_t den_drdy_flag : 1; 331 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 332 uint8_t den_drdy_flag : 1; 333 uint8_t int1_cnt_bdr : 1; 334 uint8_t int1_fifo_full : 1; 335 uint8_t int1_fifo_ovr : 1; 336 uint8_t int1_fifo_th : 1; 337 uint8_t int1_boot : 1; 338 uint8_t int1_drdy_g : 1; 339 uint8_t int1_drdy_xl : 1; 340 #endif /* DRV_BYTE_ORDER */ 341 } lsm6dsrx_int1_ctrl_t; 342 343 #define LSM6DSRX_INT2_CTRL 0x0EU 344 typedef struct 345 { 346 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 347 uint8_t int2_drdy_xl : 1; 348 uint8_t int2_drdy_g : 1; 349 uint8_t int2_drdy_temp : 1; 350 uint8_t int2_fifo_th : 1; 351 uint8_t int2_fifo_ovr : 1; 352 uint8_t int2_fifo_full : 1; 353 uint8_t int2_cnt_bdr : 1; 354 uint8_t not_used_01 : 1; 355 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 356 uint8_t not_used_01 : 1; 357 uint8_t int2_cnt_bdr : 1; 358 uint8_t int2_fifo_full : 1; 359 uint8_t int2_fifo_ovr : 1; 360 uint8_t int2_fifo_th : 1; 361 uint8_t int2_drdy_temp : 1; 362 uint8_t int2_drdy_g : 1; 363 uint8_t int2_drdy_xl : 1; 364 #endif /* DRV_BYTE_ORDER */ 365 } lsm6dsrx_int2_ctrl_t; 366 367 #define LSM6DSRX_WHO_AM_I 0x0FU 368 #define LSM6DSRX_CTRL1_XL 0x10U 369 typedef struct 370 { 371 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 372 uint8_t not_used_01 : 1; 373 uint8_t lpf2_xl_en : 1; 374 uint8_t fs_xl : 2; 375 uint8_t odr_xl : 4; 376 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 377 uint8_t odr_xl : 4; 378 uint8_t fs_xl : 2; 379 uint8_t lpf2_xl_en : 1; 380 uint8_t not_used_01 : 1; 381 #endif /* DRV_BYTE_ORDER */ 382 } lsm6dsrx_ctrl1_xl_t; 383 384 #define LSM6DSRX_CTRL2_G 0x11U 385 typedef struct 386 { 387 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 388 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 389 uint8_t odr_g : 4; 390 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 391 uint8_t odr_g : 4; 392 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 393 #endif /* DRV_BYTE_ORDER */ 394 } lsm6dsrx_ctrl2_g_t; 395 396 #define LSM6DSRX_CTRL3_C 0x12U 397 typedef struct 398 { 399 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 400 uint8_t sw_reset : 1; 401 uint8_t not_used_01 : 1; 402 uint8_t if_inc : 1; 403 uint8_t sim : 1; 404 uint8_t pp_od : 1; 405 uint8_t h_lactive : 1; 406 uint8_t bdu : 1; 407 uint8_t boot : 1; 408 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 409 uint8_t boot : 1; 410 uint8_t bdu : 1; 411 uint8_t h_lactive : 1; 412 uint8_t pp_od : 1; 413 uint8_t sim : 1; 414 uint8_t if_inc : 1; 415 uint8_t not_used_01 : 1; 416 uint8_t sw_reset : 1; 417 #endif /* DRV_BYTE_ORDER */ 418 } lsm6dsrx_ctrl3_c_t; 419 420 #define LSM6DSRX_CTRL4_C 0x13U 421 typedef struct 422 { 423 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 424 uint8_t not_used_01 : 1; 425 uint8_t lpf1_sel_g : 1; 426 uint8_t i2c_disable : 1; 427 uint8_t drdy_mask : 1; 428 uint8_t not_used_02 : 1; 429 uint8_t int2_on_int1 : 1; 430 uint8_t sleep_g : 1; 431 uint8_t not_used_03 : 1; 432 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 433 uint8_t not_used_03 : 1; 434 uint8_t sleep_g : 1; 435 uint8_t int2_on_int1 : 1; 436 uint8_t not_used_02 : 1; 437 uint8_t drdy_mask : 1; 438 uint8_t i2c_disable : 1; 439 uint8_t lpf1_sel_g : 1; 440 uint8_t not_used_01 : 1; 441 #endif /* DRV_BYTE_ORDER */ 442 } lsm6dsrx_ctrl4_c_t; 443 444 #define LSM6DSRX_CTRL5_C 0x14U 445 typedef struct 446 { 447 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 448 uint8_t st_xl : 2; 449 uint8_t st_g : 2; 450 uint8_t not_used_01 : 1; 451 uint8_t rounding : 2; 452 uint8_t not_used_02 : 1; 453 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 454 uint8_t not_used_02 : 1; 455 uint8_t rounding : 2; 456 uint8_t not_used_01 : 1; 457 uint8_t st_g : 2; 458 uint8_t st_xl : 2; 459 #endif /* DRV_BYTE_ORDER */ 460 } lsm6dsrx_ctrl5_c_t; 461 462 #define LSM6DSRX_CTRL6_C 0x15U 463 typedef struct 464 { 465 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 466 uint8_t ftype : 3; 467 uint8_t usr_off_w : 1; 468 uint8_t xl_hm_mode : 1; 469 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 470 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 471 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 472 uint8_t xl_hm_mode : 1; 473 uint8_t usr_off_w : 1; 474 uint8_t ftype : 3; 475 #endif /* DRV_BYTE_ORDER */ 476 } lsm6dsrx_ctrl6_c_t; 477 478 #define LSM6DSRX_CTRL7_G 0x16U 479 typedef struct 480 { 481 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 482 uint8_t ois_on : 1; 483 uint8_t usr_off_on_out : 1; 484 uint8_t ois_on_en : 1; 485 uint8_t not_used_01 : 1; 486 uint8_t hpm_g : 2; 487 uint8_t hp_en_g : 1; 488 uint8_t g_hm_mode : 1; 489 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 490 uint8_t g_hm_mode : 1; 491 uint8_t hp_en_g : 1; 492 uint8_t hpm_g : 2; 493 uint8_t not_used_01 : 1; 494 uint8_t ois_on_en : 1; 495 uint8_t usr_off_on_out : 1; 496 uint8_t ois_on : 1; 497 #endif /* DRV_BYTE_ORDER */ 498 } lsm6dsrx_ctrl7_g_t; 499 500 #define LSM6DSRX_CTRL8_XL 0x17U 501 typedef struct 502 { 503 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 504 uint8_t low_pass_on_6d : 1; 505 uint8_t not_used_01 : 1; 506 uint8_t hp_slope_xl_en : 1; 507 uint8_t fastsettl_mode_xl : 1; 508 uint8_t hp_ref_mode_xl : 1; 509 uint8_t hpcf_xl : 3; 510 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 511 uint8_t hpcf_xl : 3; 512 uint8_t hp_ref_mode_xl : 1; 513 uint8_t fastsettl_mode_xl : 1; 514 uint8_t hp_slope_xl_en : 1; 515 uint8_t not_used_01 : 1; 516 uint8_t low_pass_on_6d : 1; 517 #endif /* DRV_BYTE_ORDER */ 518 } lsm6dsrx_ctrl8_xl_t; 519 520 #define LSM6DSRX_CTRL9_XL 0x18U 521 typedef struct 522 { 523 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 524 uint8_t not_used_01 : 1; 525 uint8_t i3c_disable : 1; 526 uint8_t den_lh : 1; 527 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 528 uint8_t den_z : 1; 529 uint8_t den_y : 1; 530 uint8_t den_x : 1; 531 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 532 uint8_t den_x : 1; 533 uint8_t den_y : 1; 534 uint8_t den_z : 1; 535 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 536 uint8_t den_lh : 1; 537 uint8_t i3c_disable : 1; 538 uint8_t not_used_01 : 1; 539 #endif /* DRV_BYTE_ORDER */ 540 } lsm6dsrx_ctrl9_xl_t; 541 542 #define LSM6DSRX_CTRL10_C 0x19U 543 typedef struct 544 { 545 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 546 uint8_t not_used_01 : 5; 547 uint8_t timestamp_en : 1; 548 uint8_t not_used_02 : 2; 549 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 550 uint8_t not_used_02 : 2; 551 uint8_t timestamp_en : 1; 552 uint8_t not_used_01 : 5; 553 #endif /* DRV_BYTE_ORDER */ 554 } lsm6dsrx_ctrl10_c_t; 555 556 #define LSM6DSRX_ALL_INT_SRC 0x1AU 557 typedef struct 558 { 559 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 560 uint8_t ff_ia : 1; 561 uint8_t wu_ia : 1; 562 uint8_t single_tap : 1; 563 uint8_t double_tap : 1; 564 uint8_t d6d_ia : 1; 565 uint8_t sleep_change_ia : 1; 566 uint8_t not_used_01 : 1; 567 uint8_t timestamp_endcount : 1; 568 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 569 uint8_t timestamp_endcount : 1; 570 uint8_t not_used_01 : 1; 571 uint8_t sleep_change_ia : 1; 572 uint8_t d6d_ia : 1; 573 uint8_t double_tap : 1; 574 uint8_t single_tap : 1; 575 uint8_t wu_ia : 1; 576 uint8_t ff_ia : 1; 577 #endif /* DRV_BYTE_ORDER */ 578 } lsm6dsrx_all_int_src_t; 579 580 #define LSM6DSRX_WAKE_UP_SRC 0x1BU 581 typedef struct 582 { 583 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 584 uint8_t z_wu : 1; 585 uint8_t y_wu : 1; 586 uint8_t x_wu : 1; 587 uint8_t wu_ia : 1; 588 uint8_t sleep_state : 1; 589 uint8_t ff_ia : 1; 590 uint8_t sleep_change_ia : 1; 591 uint8_t not_used_01 : 1; 592 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 593 uint8_t not_used_01 : 1; 594 uint8_t sleep_change_ia : 1; 595 uint8_t ff_ia : 1; 596 uint8_t sleep_state : 1; 597 uint8_t wu_ia : 1; 598 uint8_t x_wu : 1; 599 uint8_t y_wu : 1; 600 uint8_t z_wu : 1; 601 #endif /* DRV_BYTE_ORDER */ 602 } lsm6dsrx_wake_up_src_t; 603 604 #define LSM6DSRX_TAP_SRC 0x1CU 605 typedef struct 606 { 607 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 608 uint8_t z_tap : 1; 609 uint8_t y_tap : 1; 610 uint8_t x_tap : 1; 611 uint8_t tap_sign : 1; 612 uint8_t double_tap : 1; 613 uint8_t single_tap : 1; 614 uint8_t tap_ia : 1; 615 uint8_t not_used_01 : 1; 616 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 617 uint8_t not_used_01 : 1; 618 uint8_t tap_ia : 1; 619 uint8_t single_tap : 1; 620 uint8_t double_tap : 1; 621 uint8_t tap_sign : 1; 622 uint8_t x_tap : 1; 623 uint8_t y_tap : 1; 624 uint8_t z_tap : 1; 625 #endif /* DRV_BYTE_ORDER */ 626 } lsm6dsrx_tap_src_t; 627 628 #define LSM6DSRX_D6D_SRC 0x1DU 629 typedef struct 630 { 631 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 632 uint8_t xl : 1; 633 uint8_t xh : 1; 634 uint8_t yl : 1; 635 uint8_t yh : 1; 636 uint8_t zl : 1; 637 uint8_t zh : 1; 638 uint8_t d6d_ia : 1; 639 uint8_t den_drdy : 1; 640 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 641 uint8_t den_drdy : 1; 642 uint8_t d6d_ia : 1; 643 uint8_t zh : 1; 644 uint8_t zl : 1; 645 uint8_t yh : 1; 646 uint8_t yl : 1; 647 uint8_t xh : 1; 648 uint8_t xl : 1; 649 #endif /* DRV_BYTE_ORDER */ 650 } lsm6dsrx_d6d_src_t; 651 652 #define LSM6DSRX_STATUS_REG 0x1EU 653 typedef struct 654 { 655 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 656 uint8_t xlda : 1; 657 uint8_t gda : 1; 658 uint8_t tda : 1; 659 uint8_t not_used_01 : 5; 660 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 661 uint8_t not_used_01 : 5; 662 uint8_t tda : 1; 663 uint8_t gda : 1; 664 uint8_t xlda : 1; 665 #endif /* DRV_BYTE_ORDER */ 666 } lsm6dsrx_status_reg_t; 667 668 #define LSM6DSRX_STATUS_SPIAUX 0x1EU 669 typedef struct 670 { 671 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 672 uint8_t xlda : 1; 673 uint8_t gda : 1; 674 uint8_t gyro_settling : 1; 675 uint8_t not_used_01 : 5; 676 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 677 uint8_t not_used_01 : 5; 678 uint8_t gyro_settling : 1; 679 uint8_t gda : 1; 680 uint8_t xlda : 1; 681 #endif /* DRV_BYTE_ORDER */ 682 } lsm6dsrx_status_spiaux_t; 683 684 #define LSM6DSRX_OUT_TEMP_L 0x20U 685 #define LSM6DSRX_OUT_TEMP_H 0x21U 686 #define LSM6DSRX_OUTX_L_G 0x22U 687 #define LSM6DSRX_OUTX_H_G 0x23U 688 #define LSM6DSRX_OUTY_L_G 0x24U 689 #define LSM6DSRX_OUTY_H_G 0x25U 690 #define LSM6DSRX_OUTZ_L_G 0x26U 691 #define LSM6DSRX_OUTZ_H_G 0x27U 692 #define LSM6DSRX_OUTX_L_A 0x28U 693 #define LSM6DSRX_OUTX_H_A 0x29U 694 #define LSM6DSRX_OUTY_L_A 0x2AU 695 #define LSM6DSRX_OUTY_H_A 0x2BU 696 #define LSM6DSRX_OUTZ_L_A 0x2CU 697 #define LSM6DSRX_OUTZ_H_A 0x2DU 698 699 #define LSM6DSRX_EMB_FUNC_STATUS_MAINPAGE 0x35U 700 typedef struct 701 { 702 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 703 uint8_t not_used_01 : 3; 704 uint8_t is_step_det : 1; 705 uint8_t is_tilt : 1; 706 uint8_t is_sigmot : 1; 707 uint8_t not_used_02 : 1; 708 uint8_t is_fsm_lc : 1; 709 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 710 uint8_t is_fsm_lc : 1; 711 uint8_t not_used_02 : 1; 712 uint8_t is_sigmot : 1; 713 uint8_t is_tilt : 1; 714 uint8_t is_step_det : 1; 715 uint8_t not_used_01 : 3; 716 #endif /* DRV_BYTE_ORDER */ 717 } lsm6dsrx_emb_func_status_mainpage_t; 718 719 #define LSM6DSRX_FSM_STATUS_A_MAINPAGE 0x36U 720 typedef struct 721 { 722 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 723 uint8_t is_fsm1 : 1; 724 uint8_t is_fsm2 : 1; 725 uint8_t is_fsm3 : 1; 726 uint8_t is_fsm4 : 1; 727 uint8_t is_fsm5 : 1; 728 uint8_t is_fsm6 : 1; 729 uint8_t is_fsm7 : 1; 730 uint8_t is_fsm8 : 1; 731 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 732 uint8_t is_fsm8 : 1; 733 uint8_t is_fsm7 : 1; 734 uint8_t is_fsm6 : 1; 735 uint8_t is_fsm5 : 1; 736 uint8_t is_fsm4 : 1; 737 uint8_t is_fsm3 : 1; 738 uint8_t is_fsm2 : 1; 739 uint8_t is_fsm1 : 1; 740 #endif /* DRV_BYTE_ORDER */ 741 } lsm6dsrx_fsm_status_a_mainpage_t; 742 743 #define LSM6DSRX_FSM_STATUS_B_MAINPAGE 0x37U 744 typedef struct 745 { 746 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 747 uint8_t is_fsm9 : 1; 748 uint8_t is_fsm10 : 1; 749 uint8_t is_fsm11 : 1; 750 uint8_t is_fsm12 : 1; 751 uint8_t is_fsm13 : 1; 752 uint8_t is_fsm14 : 1; 753 uint8_t is_fsm15 : 1; 754 uint8_t is_fsm16 : 1; 755 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 756 uint8_t is_fsm16 : 1; 757 uint8_t is_fsm15 : 1; 758 uint8_t is_fsm14 : 1; 759 uint8_t is_fsm13 : 1; 760 uint8_t is_fsm12 : 1; 761 uint8_t is_fsm11 : 1; 762 uint8_t is_fsm10 : 1; 763 uint8_t is_fsm9 : 1; 764 #endif /* DRV_BYTE_ORDER */ 765 } lsm6dsrx_fsm_status_b_mainpage_t; 766 767 #define LSM6DSRX_MLC_STATUS_MAINPAGE 0x38U 768 typedef struct 769 { 770 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 771 uint8_t is_mlc1 : 1; 772 uint8_t is_mlc2 : 1; 773 uint8_t is_mlc3 : 1; 774 uint8_t is_mlc4 : 1; 775 uint8_t is_mlc5 : 1; 776 uint8_t is_mlc6 : 1; 777 uint8_t is_mlc7 : 1; 778 uint8_t is_mlc8 : 1; 779 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 780 uint8_t is_mlc8 : 1; 781 uint8_t is_mlc7 : 1; 782 uint8_t is_mlc6 : 1; 783 uint8_t is_mlc5 : 1; 784 uint8_t is_mlc4 : 1; 785 uint8_t is_mlc3 : 1; 786 uint8_t is_mlc2 : 1; 787 uint8_t is_mlc1 : 1; 788 #endif /* DRV_BYTE_ORDER */ 789 } lsm6dsrx_mlc_status_mainpage_t; 790 791 #define LSM6DSRX_STATUS_MASTER_MAINPAGE 0x39U 792 typedef struct 793 { 794 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 795 uint8_t sens_hub_endop : 1; 796 uint8_t not_used_01 : 2; 797 uint8_t slave0_nack : 1; 798 uint8_t slave1_nack : 1; 799 uint8_t slave2_nack : 1; 800 uint8_t slave3_nack : 1; 801 uint8_t wr_once_done : 1; 802 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 803 uint8_t wr_once_done : 1; 804 uint8_t slave3_nack : 1; 805 uint8_t slave2_nack : 1; 806 uint8_t slave1_nack : 1; 807 uint8_t slave0_nack : 1; 808 uint8_t not_used_01 : 2; 809 uint8_t sens_hub_endop : 1; 810 #endif /* DRV_BYTE_ORDER */ 811 } lsm6dsrx_status_master_mainpage_t; 812 813 #define LSM6DSRX_FIFO_STATUS1 0x3AU 814 typedef struct 815 { 816 uint8_t diff_fifo : 8; 817 } lsm6dsrx_fifo_status1_t; 818 819 #define LSM6DSRX_FIFO_STATUS2 0x3BU 820 typedef struct 821 { 822 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 823 uint8_t diff_fifo : 2; 824 uint8_t not_used_01 : 1; 825 uint8_t over_run_latched : 1; 826 uint8_t counter_bdr_ia : 1; 827 uint8_t fifo_full_ia : 1; 828 uint8_t fifo_ovr_ia : 1; 829 uint8_t fifo_wtm_ia : 1; 830 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 831 uint8_t fifo_wtm_ia : 1; 832 uint8_t fifo_ovr_ia : 1; 833 uint8_t fifo_full_ia : 1; 834 uint8_t counter_bdr_ia : 1; 835 uint8_t over_run_latched : 1; 836 uint8_t not_used_01 : 1; 837 uint8_t diff_fifo : 2; 838 #endif /* DRV_BYTE_ORDER */ 839 } lsm6dsrx_fifo_status2_t; 840 841 #define LSM6DSRX_TIMESTAMP0 0x40U 842 #define LSM6DSRX_TIMESTAMP1 0x41U 843 #define LSM6DSRX_TIMESTAMP2 0x42U 844 #define LSM6DSRX_TIMESTAMP3 0x43U 845 #define LSM6DSRX_TAP_CFG0 0x56U 846 typedef struct 847 { 848 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 849 uint8_t lir : 1; 850 uint8_t tap_z_en : 1; 851 uint8_t tap_y_en : 1; 852 uint8_t tap_x_en : 1; 853 uint8_t slope_fds : 1; 854 uint8_t sleep_status_on_int : 1; 855 uint8_t int_clr_on_read : 1; 856 uint8_t not_used_01 : 1; 857 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 858 uint8_t not_used_01 : 1; 859 uint8_t int_clr_on_read : 1; 860 uint8_t sleep_status_on_int : 1; 861 uint8_t slope_fds : 1; 862 uint8_t tap_x_en : 1; 863 uint8_t tap_y_en : 1; 864 uint8_t tap_z_en : 1; 865 uint8_t lir : 1; 866 #endif /* DRV_BYTE_ORDER */ 867 } lsm6dsrx_tap_cfg0_t; 868 869 #define LSM6DSRX_TAP_CFG1 0x57U 870 typedef struct 871 { 872 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 873 uint8_t tap_ths_x : 5; 874 uint8_t tap_priority : 3; 875 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 876 uint8_t tap_priority : 3; 877 uint8_t tap_ths_x : 5; 878 #endif /* DRV_BYTE_ORDER */ 879 } lsm6dsrx_tap_cfg1_t; 880 881 #define LSM6DSRX_TAP_CFG2 0x58U 882 typedef struct 883 { 884 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 885 uint8_t tap_ths_y : 5; 886 uint8_t inact_en : 2; 887 uint8_t interrupts_enable : 1; 888 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 889 uint8_t interrupts_enable : 1; 890 uint8_t inact_en : 2; 891 uint8_t tap_ths_y : 5; 892 #endif /* DRV_BYTE_ORDER */ 893 } lsm6dsrx_tap_cfg2_t; 894 895 #define LSM6DSRX_TAP_THS_6D 0x59U 896 typedef struct 897 { 898 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 899 uint8_t tap_ths_z : 5; 900 uint8_t sixd_ths : 2; 901 uint8_t d4d_en : 1; 902 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 903 uint8_t d4d_en : 1; 904 uint8_t sixd_ths : 2; 905 uint8_t tap_ths_z : 5; 906 #endif /* DRV_BYTE_ORDER */ 907 } lsm6dsrx_tap_ths_6d_t; 908 909 #define LSM6DSRX_INT_DUR2 0x5AU 910 typedef struct 911 { 912 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 913 uint8_t shock : 2; 914 uint8_t quiet : 2; 915 uint8_t dur : 4; 916 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 917 uint8_t dur : 4; 918 uint8_t quiet : 2; 919 uint8_t shock : 2; 920 #endif /* DRV_BYTE_ORDER */ 921 } lsm6dsrx_int_dur2_t; 922 923 #define LSM6DSRX_WAKE_UP_THS 0x5BU 924 typedef struct 925 { 926 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 927 uint8_t wk_ths : 6; 928 uint8_t usr_off_on_wu : 1; 929 uint8_t single_double_tap : 1; 930 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 931 uint8_t single_double_tap : 1; 932 uint8_t usr_off_on_wu : 1; 933 uint8_t wk_ths : 6; 934 #endif /* DRV_BYTE_ORDER */ 935 } lsm6dsrx_wake_up_ths_t; 936 937 #define LSM6DSRX_WAKE_UP_DUR 0x5CU 938 typedef struct 939 { 940 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 941 uint8_t sleep_dur : 4; 942 uint8_t wake_ths_w : 1; 943 uint8_t wake_dur : 2; 944 uint8_t ff_dur : 1; 945 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 946 uint8_t ff_dur : 1; 947 uint8_t wake_dur : 2; 948 uint8_t wake_ths_w : 1; 949 uint8_t sleep_dur : 4; 950 #endif /* DRV_BYTE_ORDER */ 951 } lsm6dsrx_wake_up_dur_t; 952 953 #define LSM6DSRX_FREE_FALL 0x5DU 954 typedef struct 955 { 956 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 957 uint8_t ff_ths : 3; 958 uint8_t ff_dur : 5; 959 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 960 uint8_t ff_dur : 5; 961 uint8_t ff_ths : 3; 962 #endif /* DRV_BYTE_ORDER */ 963 } lsm6dsrx_free_fall_t; 964 965 #define LSM6DSRX_MD1_CFG 0x5EU 966 typedef struct 967 { 968 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 969 uint8_t int1_shub : 1; 970 uint8_t int1_emb_func : 1; 971 uint8_t int1_6d : 1; 972 uint8_t int1_double_tap : 1; 973 uint8_t int1_ff : 1; 974 uint8_t int1_wu : 1; 975 uint8_t int1_single_tap : 1; 976 uint8_t int1_sleep_change : 1; 977 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 978 uint8_t int1_sleep_change : 1; 979 uint8_t int1_single_tap : 1; 980 uint8_t int1_wu : 1; 981 uint8_t int1_ff : 1; 982 uint8_t int1_double_tap : 1; 983 uint8_t int1_6d : 1; 984 uint8_t int1_emb_func : 1; 985 uint8_t int1_shub : 1; 986 #endif /* DRV_BYTE_ORDER */ 987 } lsm6dsrx_md1_cfg_t; 988 989 #define LSM6DSRX_MD2_CFG 0x5FU 990 typedef struct 991 { 992 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 993 uint8_t int2_timestamp : 1; 994 uint8_t int2_emb_func : 1; 995 uint8_t int2_6d : 1; 996 uint8_t int2_double_tap : 1; 997 uint8_t int2_ff : 1; 998 uint8_t int2_wu : 1; 999 uint8_t int2_single_tap : 1; 1000 uint8_t int2_sleep_change : 1; 1001 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1002 uint8_t int2_sleep_change : 1; 1003 uint8_t int2_single_tap : 1; 1004 uint8_t int2_wu : 1; 1005 uint8_t int2_ff : 1; 1006 uint8_t int2_double_tap : 1; 1007 uint8_t int2_6d : 1; 1008 uint8_t int2_emb_func : 1; 1009 uint8_t int2_timestamp : 1; 1010 #endif /* DRV_BYTE_ORDER */ 1011 } lsm6dsrx_md2_cfg_t; 1012 1013 #define LSM6DSRX_S4S_ST_CMD_CODE 0x60U 1014 typedef struct 1015 { 1016 uint8_t s4s_st_cmd_code : 8; 1017 } lsm6dsrx_s4s_st_cmd_code_t; 1018 1019 #define LSM6DSRX_S4S_DT_REG 0x61U 1020 typedef struct 1021 { 1022 uint8_t dt : 8; 1023 } lsm6dsrx_s4s_dt_reg_t; 1024 1025 #define LSM6DSRX_I3C_BUS_AVB 0x62U 1026 typedef struct 1027 { 1028 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1029 uint8_t pd_dis_int1 : 1; 1030 uint8_t not_used_01 : 2; 1031 uint8_t i3c_bus_avb_sel : 2; 1032 uint8_t not_used_02 : 3; 1033 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1034 uint8_t not_used_02 : 3; 1035 uint8_t i3c_bus_avb_sel : 2; 1036 uint8_t not_used_01 : 2; 1037 uint8_t pd_dis_int1 : 1; 1038 #endif /* DRV_BYTE_ORDER */ 1039 } lsm6dsrx_i3c_bus_avb_t; 1040 1041 #define LSM6DSRX_INTERNAL_FREQ_FINE 0x63U 1042 typedef struct 1043 { 1044 uint8_t freq_fine : 8; 1045 } lsm6dsrx_internal_freq_fine_t; 1046 1047 #define LSM6DSRX_INT_OIS 0x6FU 1048 typedef struct 1049 { 1050 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1051 uint8_t st_xl_ois : 2; 1052 uint8_t not_used_01 : 3; 1053 uint8_t den_lh_ois : 1; 1054 uint8_t lvl2_ois : 1; 1055 uint8_t int2_drdy_ois : 1; 1056 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1057 uint8_t int2_drdy_ois : 1; 1058 uint8_t lvl2_ois : 1; 1059 uint8_t den_lh_ois : 1; 1060 uint8_t not_used_01 : 3; 1061 uint8_t st_xl_ois : 2; 1062 #endif /* DRV_BYTE_ORDER */ 1063 } lsm6dsrx_int_ois_t; 1064 1065 #define LSM6DSRX_CTRL1_OIS 0x70U 1066 typedef struct 1067 { 1068 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1069 uint8_t ois_en_spi2 : 1; 1070 uint8_t fs_125_ois : 1; 1071 uint8_t fs_g_ois : 2; 1072 uint8_t mode4_en : 1; 1073 uint8_t sim_ois : 1; 1074 uint8_t lvl1_ois : 1; 1075 uint8_t not_used_01 : 1; 1076 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1077 uint8_t not_used_01 : 1; 1078 uint8_t lvl1_ois : 1; 1079 uint8_t sim_ois : 1; 1080 uint8_t mode4_en : 1; 1081 uint8_t fs_g_ois : 2; 1082 uint8_t fs_125_ois : 1; 1083 uint8_t ois_en_spi2 : 1; 1084 #endif /* DRV_BYTE_ORDER */ 1085 } lsm6dsrx_ctrl1_ois_t; 1086 1087 #define LSM6DSRX_CTRL2_OIS 0x71U 1088 typedef struct 1089 { 1090 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1091 uint8_t hp_en_ois : 1; 1092 uint8_t ftype_ois : 2; 1093 uint8_t not_used_01 : 1; 1094 uint8_t hpm_ois : 2; 1095 uint8_t not_used_02 : 2; 1096 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1097 uint8_t not_used_02 : 2; 1098 uint8_t hpm_ois : 2; 1099 uint8_t not_used_01 : 1; 1100 uint8_t ftype_ois : 2; 1101 uint8_t hp_en_ois : 1; 1102 #endif /* DRV_BYTE_ORDER */ 1103 } lsm6dsrx_ctrl2_ois_t; 1104 1105 #define LSM6DSRX_CTRL3_OIS 0x72U 1106 typedef struct 1107 { 1108 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1109 uint8_t st_ois_clampdis : 1; 1110 uint8_t st_ois : 2; 1111 uint8_t filter_xl_conf_ois : 3; 1112 uint8_t fs_xl_ois : 2; 1113 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1114 uint8_t fs_xl_ois : 2; 1115 uint8_t filter_xl_conf_ois : 3; 1116 uint8_t st_ois : 2; 1117 uint8_t st_ois_clampdis : 1; 1118 #endif /* DRV_BYTE_ORDER */ 1119 } lsm6dsrx_ctrl3_ois_t; 1120 1121 #define LSM6DSRX_X_OFS_USR 0x73U 1122 #define LSM6DSRX_Y_OFS_USR 0x74U 1123 #define LSM6DSRX_Z_OFS_USR 0x75U 1124 #define LSM6DSRX_FIFO_DATA_OUT_TAG 0x78U 1125 typedef struct 1126 { 1127 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1128 uint8_t tag_parity : 1; 1129 uint8_t tag_cnt : 2; 1130 uint8_t tag_sensor : 5; 1131 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1132 uint8_t tag_sensor : 5; 1133 uint8_t tag_cnt : 2; 1134 uint8_t tag_parity : 1; 1135 #endif /* DRV_BYTE_ORDER */ 1136 } lsm6dsrx_fifo_data_out_tag_t; 1137 1138 #define LSM6DSRX_FIFO_DATA_OUT_X_L 0x79U 1139 #define LSM6DSRX_FIFO_DATA_OUT_X_H 0x7AU 1140 #define LSM6DSRX_FIFO_DATA_OUT_Y_L 0x7BU 1141 #define LSM6DSRX_FIFO_DATA_OUT_Y_H 0x7CU 1142 #define LSM6DSRX_FIFO_DATA_OUT_Z_L 0x7DU 1143 #define LSM6DSRX_FIFO_DATA_OUT_Z_H 0x7EU 1144 #define LSM6DSRX_PAGE_SEL 0x02U 1145 typedef struct 1146 { 1147 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1148 uint8_t not_used_01 : 4; 1149 uint8_t page_sel : 4; 1150 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1151 uint8_t page_sel : 4; 1152 uint8_t not_used_01 : 4; 1153 #endif /* DRV_BYTE_ORDER */ 1154 } lsm6dsrx_page_sel_t; 1155 1156 #define LSM6DSRX_EMB_FUNC_EN_A 0x04U 1157 typedef struct 1158 { 1159 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1160 uint8_t not_used_01 : 3; 1161 uint8_t pedo_en : 1; 1162 uint8_t tilt_en : 1; 1163 uint8_t sign_motion_en : 1; 1164 uint8_t not_used_02 : 2; 1165 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1166 uint8_t not_used_02 : 2; 1167 uint8_t sign_motion_en : 1; 1168 uint8_t tilt_en : 1; 1169 uint8_t pedo_en : 1; 1170 uint8_t not_used_01 : 3; 1171 #endif /* DRV_BYTE_ORDER */ 1172 } lsm6dsrx_emb_func_en_a_t; 1173 1174 #define LSM6DSRX_EMB_FUNC_EN_B 0x05U 1175 typedef struct 1176 { 1177 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1178 uint8_t fsm_en : 1; 1179 uint8_t not_used_01 : 2; 1180 uint8_t fifo_compr_en : 1; 1181 uint8_t mlc_en : 1; 1182 uint8_t not_used_02 : 3; 1183 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1184 uint8_t not_used_02 : 3; 1185 uint8_t mlc_en : 1; 1186 uint8_t fifo_compr_en : 1; 1187 uint8_t not_used_01 : 2; 1188 uint8_t fsm_en : 1; 1189 #endif /* DRV_BYTE_ORDER */ 1190 } lsm6dsrx_emb_func_en_b_t; 1191 1192 #define LSM6DSRX_PAGE_ADDRESS 0x08U 1193 typedef struct 1194 { 1195 uint8_t page_addr : 8; 1196 } lsm6dsrx_page_address_t; 1197 1198 #define LSM6DSRX_PAGE_VALUE 0x09U 1199 typedef struct 1200 { 1201 uint8_t page_value : 8; 1202 } lsm6dsrx_page_value_t; 1203 1204 #define LSM6DSRX_EMB_FUNC_INT1 0x0AU 1205 typedef struct 1206 { 1207 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1208 uint8_t not_used_01 : 3; 1209 uint8_t int1_step_detector : 1; 1210 uint8_t int1_tilt : 1; 1211 uint8_t int1_sig_mot : 1; 1212 uint8_t not_used_02 : 1; 1213 uint8_t int1_fsm_lc : 1; 1214 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1215 uint8_t int1_fsm_lc : 1; 1216 uint8_t not_used_02 : 1; 1217 uint8_t int1_sig_mot : 1; 1218 uint8_t int1_tilt : 1; 1219 uint8_t int1_step_detector : 1; 1220 uint8_t not_used_01 : 3; 1221 #endif /* DRV_BYTE_ORDER */ 1222 } lsm6dsrx_emb_func_int1_t; 1223 1224 #define LSM6DSRX_FSM_INT1_A 0x0BU 1225 typedef struct 1226 { 1227 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1228 uint8_t int1_fsm1 : 1; 1229 uint8_t int1_fsm2 : 1; 1230 uint8_t int1_fsm3 : 1; 1231 uint8_t int1_fsm4 : 1; 1232 uint8_t int1_fsm5 : 1; 1233 uint8_t int1_fsm6 : 1; 1234 uint8_t int1_fsm7 : 1; 1235 uint8_t int1_fsm8 : 1; 1236 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1237 uint8_t int1_fsm8 : 1; 1238 uint8_t int1_fsm7 : 1; 1239 uint8_t int1_fsm6 : 1; 1240 uint8_t int1_fsm5 : 1; 1241 uint8_t int1_fsm4 : 1; 1242 uint8_t int1_fsm3 : 1; 1243 uint8_t int1_fsm2 : 1; 1244 uint8_t int1_fsm1 : 1; 1245 #endif /* DRV_BYTE_ORDER */ 1246 } lsm6dsrx_fsm_int1_a_t; 1247 1248 #define LSM6DSRX_FSM_INT1_B 0x0CU 1249 typedef struct 1250 { 1251 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1252 uint8_t int1_fsm9 : 1; 1253 uint8_t int1_fsm10 : 1; 1254 uint8_t int1_fsm11 : 1; 1255 uint8_t int1_fsm12 : 1; 1256 uint8_t int1_fsm13 : 1; 1257 uint8_t int1_fsm14 : 1; 1258 uint8_t int1_fsm15 : 1; 1259 uint8_t int1_fsm16 : 1; 1260 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1261 uint8_t int1_fsm16 : 1; 1262 uint8_t int1_fsm15 : 1; 1263 uint8_t int1_fsm14 : 1; 1264 uint8_t int1_fsm13 : 1; 1265 uint8_t int1_fsm12 : 1; 1266 uint8_t int1_fsm11 : 1; 1267 uint8_t int1_fsm10 : 1; 1268 uint8_t int1_fsm9 : 1; 1269 #endif /* DRV_BYTE_ORDER */ 1270 } lsm6dsrx_fsm_int1_b_t; 1271 1272 #define LSM6DSRX_MLC_INT1 0x0DU 1273 typedef struct 1274 { 1275 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1276 uint8_t int1_mlc1 : 1; 1277 uint8_t int1_mlc2 : 1; 1278 uint8_t int1_mlc3 : 1; 1279 uint8_t int1_mlc4 : 1; 1280 uint8_t int1_mlc5 : 1; 1281 uint8_t int1_mlc6 : 1; 1282 uint8_t int1_mlc7 : 1; 1283 uint8_t int1_mlc8 : 1; 1284 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1285 uint8_t int1_mlc8 : 1; 1286 uint8_t int1_mlc7 : 1; 1287 uint8_t int1_mlc6 : 1; 1288 uint8_t int1_mlc5 : 1; 1289 uint8_t int1_mlc4 : 1; 1290 uint8_t int1_mlc3 : 1; 1291 uint8_t int1_mlc2 : 1; 1292 uint8_t int1_mlc1 : 1; 1293 #endif /* DRV_BYTE_ORDER */ 1294 } lsm6dsrx_mlc_int1_t; 1295 1296 #define LSM6DSRX_EMB_FUNC_INT2 0x0EU 1297 typedef struct 1298 { 1299 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1300 uint8_t not_used_01 : 3; 1301 uint8_t int2_step_detector : 1; 1302 uint8_t int2_tilt : 1; 1303 uint8_t int2_sig_mot : 1; 1304 uint8_t not_used_02 : 1; 1305 uint8_t int2_fsm_lc : 1; 1306 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1307 uint8_t int2_fsm_lc : 1; 1308 uint8_t not_used_02 : 1; 1309 uint8_t int2_sig_mot : 1; 1310 uint8_t int2_tilt : 1; 1311 uint8_t int2_step_detector : 1; 1312 uint8_t not_used_01 : 3; 1313 #endif /* DRV_BYTE_ORDER */ 1314 } lsm6dsrx_emb_func_int2_t; 1315 1316 #define LSM6DSRX_FSM_INT2_A 0x0FU 1317 typedef struct 1318 { 1319 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1320 uint8_t int2_fsm1 : 1; 1321 uint8_t int2_fsm2 : 1; 1322 uint8_t int2_fsm3 : 1; 1323 uint8_t int2_fsm4 : 1; 1324 uint8_t int2_fsm5 : 1; 1325 uint8_t int2_fsm6 : 1; 1326 uint8_t int2_fsm7 : 1; 1327 uint8_t int2_fsm8 : 1; 1328 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1329 uint8_t int2_fsm8 : 1; 1330 uint8_t int2_fsm7 : 1; 1331 uint8_t int2_fsm6 : 1; 1332 uint8_t int2_fsm5 : 1; 1333 uint8_t int2_fsm4 : 1; 1334 uint8_t int2_fsm3 : 1; 1335 uint8_t int2_fsm2 : 1; 1336 uint8_t int2_fsm1 : 1; 1337 #endif /* DRV_BYTE_ORDER */ 1338 } lsm6dsrx_fsm_int2_a_t; 1339 1340 #define LSM6DSRX_FSM_INT2_B 0x10U 1341 typedef struct 1342 { 1343 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1344 uint8_t int2_fsm9 : 1; 1345 uint8_t int2_fsm10 : 1; 1346 uint8_t int2_fsm11 : 1; 1347 uint8_t int2_fsm12 : 1; 1348 uint8_t int2_fsm13 : 1; 1349 uint8_t int2_fsm14 : 1; 1350 uint8_t int2_fsm15 : 1; 1351 uint8_t int2_fsm16 : 1; 1352 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1353 uint8_t int2_fsm16 : 1; 1354 uint8_t int2_fsm15 : 1; 1355 uint8_t int2_fsm14 : 1; 1356 uint8_t int2_fsm13 : 1; 1357 uint8_t int2_fsm12 : 1; 1358 uint8_t int2_fsm11 : 1; 1359 uint8_t int2_fsm10 : 1; 1360 uint8_t int2_fsm9 : 1; 1361 #endif /* DRV_BYTE_ORDER */ 1362 } lsm6dsrx_fsm_int2_b_t; 1363 1364 #define LSM6DSRX_MLC_INT2 0x11U 1365 typedef struct 1366 { 1367 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1368 uint8_t int2_mlc1 : 1; 1369 uint8_t int2_mlc2 : 1; 1370 uint8_t int2_mlc3 : 1; 1371 uint8_t int2_mlc4 : 1; 1372 uint8_t int2_mlc5 : 1; 1373 uint8_t int2_mlc6 : 1; 1374 uint8_t int2_mlc7 : 1; 1375 uint8_t int2_mlc8 : 1; 1376 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1377 uint8_t int2_mlc8 : 1; 1378 uint8_t int2_mlc7 : 1; 1379 uint8_t int2_mlc6 : 1; 1380 uint8_t int2_mlc5 : 1; 1381 uint8_t int2_mlc4 : 1; 1382 uint8_t int2_mlc3 : 1; 1383 uint8_t int2_mlc2 : 1; 1384 uint8_t int2_mlc1 : 1; 1385 #endif /* DRV_BYTE_ORDER */ 1386 } lsm6dsrx_mlc_int2_t; 1387 1388 #define LSM6DSRX_EMB_FUNC_STATUS 0x12U 1389 typedef struct 1390 { 1391 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1392 uint8_t not_used_01 : 3; 1393 uint8_t is_step_det : 1; 1394 uint8_t is_tilt : 1; 1395 uint8_t is_sigmot : 1; 1396 uint8_t not_used_02 : 1; 1397 uint8_t is_fsm_lc : 1; 1398 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1399 uint8_t is_fsm_lc : 1; 1400 uint8_t not_used_02 : 1; 1401 uint8_t is_sigmot : 1; 1402 uint8_t is_tilt : 1; 1403 uint8_t is_step_det : 1; 1404 uint8_t not_used_01 : 3; 1405 #endif /* DRV_BYTE_ORDER */ 1406 } lsm6dsrx_emb_func_status_t; 1407 1408 #define LSM6DSRX_FSM_STATUS_A 0x13U 1409 typedef struct 1410 { 1411 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1412 uint8_t is_fsm1 : 1; 1413 uint8_t is_fsm2 : 1; 1414 uint8_t is_fsm3 : 1; 1415 uint8_t is_fsm4 : 1; 1416 uint8_t is_fsm5 : 1; 1417 uint8_t is_fsm6 : 1; 1418 uint8_t is_fsm7 : 1; 1419 uint8_t is_fsm8 : 1; 1420 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1421 uint8_t is_fsm8 : 1; 1422 uint8_t is_fsm7 : 1; 1423 uint8_t is_fsm6 : 1; 1424 uint8_t is_fsm5 : 1; 1425 uint8_t is_fsm4 : 1; 1426 uint8_t is_fsm3 : 1; 1427 uint8_t is_fsm2 : 1; 1428 uint8_t is_fsm1 : 1; 1429 #endif /* DRV_BYTE_ORDER */ 1430 } lsm6dsrx_fsm_status_a_t; 1431 1432 #define LSM6DSRX_FSM_STATUS_B 0x14U 1433 typedef struct 1434 { 1435 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1436 uint8_t is_fsm9 : 1; 1437 uint8_t is_fsm10 : 1; 1438 uint8_t is_fsm11 : 1; 1439 uint8_t is_fsm12 : 1; 1440 uint8_t is_fsm13 : 1; 1441 uint8_t is_fsm14 : 1; 1442 uint8_t is_fsm15 : 1; 1443 uint8_t is_fsm16 : 1; 1444 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1445 uint8_t is_fsm16 : 1; 1446 uint8_t is_fsm15 : 1; 1447 uint8_t is_fsm14 : 1; 1448 uint8_t is_fsm13 : 1; 1449 uint8_t is_fsm12 : 1; 1450 uint8_t is_fsm11 : 1; 1451 uint8_t is_fsm10 : 1; 1452 uint8_t is_fsm9 : 1; 1453 #endif /* DRV_BYTE_ORDER */ 1454 } lsm6dsrx_fsm_status_b_t; 1455 1456 #define LSM6DSRX_MLC_STATUS 0x15U 1457 typedef struct 1458 { 1459 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1460 uint8_t is_mlc1 : 1; 1461 uint8_t is_mlc2 : 1; 1462 uint8_t is_mlc3 : 1; 1463 uint8_t is_mlc4 : 1; 1464 uint8_t is_mlc5 : 1; 1465 uint8_t is_mlc6 : 1; 1466 uint8_t is_mlc7 : 1; 1467 uint8_t is_mlc8 : 1; 1468 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1469 uint8_t is_mlc8 : 1; 1470 uint8_t is_mlc7 : 1; 1471 uint8_t is_mlc6 : 1; 1472 uint8_t is_mlc5 : 1; 1473 uint8_t is_mlc4 : 1; 1474 uint8_t is_mlc3 : 1; 1475 uint8_t is_mlc2 : 1; 1476 uint8_t is_mlc1 : 1; 1477 #endif /* DRV_BYTE_ORDER */ 1478 } lsm6dsrx_mlc_status_t; 1479 1480 #define LSM6DSRX_PAGE_RW 0x17U 1481 typedef struct 1482 { 1483 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1484 uint8_t not_used_01 : 5; 1485 uint8_t page_rw : 2; /* page_write + page_read */ 1486 uint8_t emb_func_lir : 1; 1487 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1488 uint8_t emb_func_lir : 1; 1489 uint8_t page_rw : 2; /* page_write + page_read */ 1490 uint8_t not_used_01 : 5; 1491 #endif /* DRV_BYTE_ORDER */ 1492 } lsm6dsrx_page_rw_t; 1493 1494 #define LSM6DSRX_EMB_FUNC_FIFO_CFG 0x44U 1495 typedef struct 1496 { 1497 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1498 uint8_t not_used_01 : 6; 1499 uint8_t pedo_fifo_en : 1; 1500 uint8_t not_used_02 : 1; 1501 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1502 uint8_t not_used_02 : 1; 1503 uint8_t pedo_fifo_en : 1; 1504 uint8_t not_used_01 : 6; 1505 #endif /* DRV_BYTE_ORDER */ 1506 } lsm6dsrx_emb_func_fifo_cfg_t; 1507 1508 #define LSM6DSRX_FSM_ENABLE_A 0x46U 1509 typedef struct 1510 { 1511 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1512 uint8_t fsm1_en : 1; 1513 uint8_t fsm2_en : 1; 1514 uint8_t fsm3_en : 1; 1515 uint8_t fsm4_en : 1; 1516 uint8_t fsm5_en : 1; 1517 uint8_t fsm6_en : 1; 1518 uint8_t fsm7_en : 1; 1519 uint8_t fsm8_en : 1; 1520 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1521 uint8_t fsm8_en : 1; 1522 uint8_t fsm7_en : 1; 1523 uint8_t fsm6_en : 1; 1524 uint8_t fsm5_en : 1; 1525 uint8_t fsm4_en : 1; 1526 uint8_t fsm3_en : 1; 1527 uint8_t fsm2_en : 1; 1528 uint8_t fsm1_en : 1; 1529 #endif /* DRV_BYTE_ORDER */ 1530 } lsm6dsrx_fsm_enable_a_t; 1531 1532 #define LSM6DSRX_FSM_ENABLE_B 0x47U 1533 typedef struct 1534 { 1535 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1536 uint8_t fsm9_en : 1; 1537 uint8_t fsm10_en : 1; 1538 uint8_t fsm11_en : 1; 1539 uint8_t fsm12_en : 1; 1540 uint8_t fsm13_en : 1; 1541 uint8_t fsm14_en : 1; 1542 uint8_t fsm15_en : 1; 1543 uint8_t fsm16_en : 1; 1544 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1545 uint8_t fsm16_en : 1; 1546 uint8_t fsm15_en : 1; 1547 uint8_t fsm14_en : 1; 1548 uint8_t fsm13_en : 1; 1549 uint8_t fsm12_en : 1; 1550 uint8_t fsm11_en : 1; 1551 uint8_t fsm10_en : 1; 1552 uint8_t fsm9_en : 1; 1553 #endif /* DRV_BYTE_ORDER */ 1554 } lsm6dsrx_fsm_enable_b_t; 1555 1556 #define LSM6DSRX_FSM_LONG_COUNTER_L 0x48U 1557 #define LSM6DSRX_FSM_LONG_COUNTER_H 0x49U 1558 #define LSM6DSRX_FSM_LONG_COUNTER_CLEAR 0x4AU 1559 typedef struct 1560 { 1561 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1562 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1563 uint8_t not_used_01 : 6; 1564 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1565 uint8_t not_used_01 : 6; 1566 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1567 #endif /* DRV_BYTE_ORDER */ 1568 } lsm6dsrx_fsm_long_counter_clear_t; 1569 1570 #define LSM6DSRX_FSM_OUTS1 0x4CU 1571 typedef struct 1572 { 1573 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1574 uint8_t n_v : 1; 1575 uint8_t p_v : 1; 1576 uint8_t n_z : 1; 1577 uint8_t p_z : 1; 1578 uint8_t n_y : 1; 1579 uint8_t p_y : 1; 1580 uint8_t n_x : 1; 1581 uint8_t p_x : 1; 1582 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1583 uint8_t p_x : 1; 1584 uint8_t n_x : 1; 1585 uint8_t p_y : 1; 1586 uint8_t n_y : 1; 1587 uint8_t p_z : 1; 1588 uint8_t n_z : 1; 1589 uint8_t p_v : 1; 1590 uint8_t n_v : 1; 1591 #endif /* DRV_BYTE_ORDER */ 1592 } lsm6dsrx_fsm_outs1_t; 1593 1594 #define LSM6DSRX_FSM_OUTS2 0x4DU 1595 typedef struct 1596 { 1597 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1598 uint8_t n_v : 1; 1599 uint8_t p_v : 1; 1600 uint8_t n_z : 1; 1601 uint8_t p_z : 1; 1602 uint8_t n_y : 1; 1603 uint8_t p_y : 1; 1604 uint8_t n_x : 1; 1605 uint8_t p_x : 1; 1606 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1607 uint8_t p_x : 1; 1608 uint8_t n_x : 1; 1609 uint8_t p_y : 1; 1610 uint8_t n_y : 1; 1611 uint8_t p_z : 1; 1612 uint8_t n_z : 1; 1613 uint8_t p_v : 1; 1614 uint8_t n_v : 1; 1615 #endif /* DRV_BYTE_ORDER */ 1616 } lsm6dsrx_fsm_outs2_t; 1617 1618 #define LSM6DSRX_FSM_OUTS3 0x4EU 1619 typedef struct 1620 { 1621 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1622 uint8_t n_v : 1; 1623 uint8_t p_v : 1; 1624 uint8_t n_z : 1; 1625 uint8_t p_z : 1; 1626 uint8_t n_y : 1; 1627 uint8_t p_y : 1; 1628 uint8_t n_x : 1; 1629 uint8_t p_x : 1; 1630 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1631 uint8_t p_x : 1; 1632 uint8_t n_x : 1; 1633 uint8_t p_y : 1; 1634 uint8_t n_y : 1; 1635 uint8_t p_z : 1; 1636 uint8_t n_z : 1; 1637 uint8_t p_v : 1; 1638 uint8_t n_v : 1; 1639 #endif /* DRV_BYTE_ORDER */ 1640 } lsm6dsrx_fsm_outs3_t; 1641 1642 #define LSM6DSRX_FSM_OUTS4 0x4FU 1643 typedef struct 1644 { 1645 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1646 uint8_t n_v : 1; 1647 uint8_t p_v : 1; 1648 uint8_t n_z : 1; 1649 uint8_t p_z : 1; 1650 uint8_t n_y : 1; 1651 uint8_t p_y : 1; 1652 uint8_t n_x : 1; 1653 uint8_t p_x : 1; 1654 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1655 uint8_t p_x : 1; 1656 uint8_t n_x : 1; 1657 uint8_t p_y : 1; 1658 uint8_t n_y : 1; 1659 uint8_t p_z : 1; 1660 uint8_t n_z : 1; 1661 uint8_t p_v : 1; 1662 uint8_t n_v : 1; 1663 #endif /* DRV_BYTE_ORDER */ 1664 } lsm6dsrx_fsm_outs4_t; 1665 1666 #define LSM6DSRX_FSM_OUTS5 0x50U 1667 typedef struct 1668 { 1669 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1670 uint8_t n_v : 1; 1671 uint8_t p_v : 1; 1672 uint8_t n_z : 1; 1673 uint8_t p_z : 1; 1674 uint8_t n_y : 1; 1675 uint8_t p_y : 1; 1676 uint8_t n_x : 1; 1677 uint8_t p_x : 1; 1678 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1679 uint8_t p_x : 1; 1680 uint8_t n_x : 1; 1681 uint8_t p_y : 1; 1682 uint8_t n_y : 1; 1683 uint8_t p_z : 1; 1684 uint8_t n_z : 1; 1685 uint8_t p_v : 1; 1686 uint8_t n_v : 1; 1687 #endif /* DRV_BYTE_ORDER */ 1688 } lsm6dsrx_fsm_outs5_t; 1689 1690 #define LSM6DSRX_FSM_OUTS6 0x51U 1691 typedef struct 1692 { 1693 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1694 uint8_t n_v : 1; 1695 uint8_t p_v : 1; 1696 uint8_t n_z : 1; 1697 uint8_t p_z : 1; 1698 uint8_t n_y : 1; 1699 uint8_t p_y : 1; 1700 uint8_t n_x : 1; 1701 uint8_t p_x : 1; 1702 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1703 uint8_t p_x : 1; 1704 uint8_t n_x : 1; 1705 uint8_t p_y : 1; 1706 uint8_t n_y : 1; 1707 uint8_t p_z : 1; 1708 uint8_t n_z : 1; 1709 uint8_t p_v : 1; 1710 uint8_t n_v : 1; 1711 #endif /* DRV_BYTE_ORDER */ 1712 } lsm6dsrx_fsm_outs6_t; 1713 1714 #define LSM6DSRX_FSM_OUTS7 0x52U 1715 typedef struct 1716 { 1717 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1718 uint8_t n_v : 1; 1719 uint8_t p_v : 1; 1720 uint8_t n_z : 1; 1721 uint8_t p_z : 1; 1722 uint8_t n_y : 1; 1723 uint8_t p_y : 1; 1724 uint8_t n_x : 1; 1725 uint8_t p_x : 1; 1726 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1727 uint8_t p_x : 1; 1728 uint8_t n_x : 1; 1729 uint8_t p_y : 1; 1730 uint8_t n_y : 1; 1731 uint8_t p_z : 1; 1732 uint8_t n_z : 1; 1733 uint8_t p_v : 1; 1734 uint8_t n_v : 1; 1735 #endif /* DRV_BYTE_ORDER */ 1736 } lsm6dsrx_fsm_outs7_t; 1737 1738 #define LSM6DSRX_FSM_OUTS8 0x53U 1739 typedef struct 1740 { 1741 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1742 uint8_t n_v : 1; 1743 uint8_t p_v : 1; 1744 uint8_t n_z : 1; 1745 uint8_t p_z : 1; 1746 uint8_t n_y : 1; 1747 uint8_t p_y : 1; 1748 uint8_t n_x : 1; 1749 uint8_t p_x : 1; 1750 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1751 uint8_t p_x : 1; 1752 uint8_t n_x : 1; 1753 uint8_t p_y : 1; 1754 uint8_t n_y : 1; 1755 uint8_t p_z : 1; 1756 uint8_t n_z : 1; 1757 uint8_t p_v : 1; 1758 uint8_t n_v : 1; 1759 #endif /* DRV_BYTE_ORDER */ 1760 } lsm6dsrx_fsm_outs8_t; 1761 1762 #define LSM6DSRX_FSM_OUTS9 0x54U 1763 typedef struct 1764 { 1765 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1766 uint8_t n_v : 1; 1767 uint8_t p_v : 1; 1768 uint8_t n_z : 1; 1769 uint8_t p_z : 1; 1770 uint8_t n_y : 1; 1771 uint8_t p_y : 1; 1772 uint8_t n_x : 1; 1773 uint8_t p_x : 1; 1774 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1775 uint8_t p_x : 1; 1776 uint8_t n_x : 1; 1777 uint8_t p_y : 1; 1778 uint8_t n_y : 1; 1779 uint8_t p_z : 1; 1780 uint8_t n_z : 1; 1781 uint8_t p_v : 1; 1782 uint8_t n_v : 1; 1783 #endif /* DRV_BYTE_ORDER */ 1784 } lsm6dsrx_fsm_outs9_t; 1785 1786 #define LSM6DSRX_FSM_OUTS10 0x55U 1787 typedef struct 1788 { 1789 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1790 uint8_t n_v : 1; 1791 uint8_t p_v : 1; 1792 uint8_t n_z : 1; 1793 uint8_t p_z : 1; 1794 uint8_t n_y : 1; 1795 uint8_t p_y : 1; 1796 uint8_t n_x : 1; 1797 uint8_t p_x : 1; 1798 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1799 uint8_t p_x : 1; 1800 uint8_t n_x : 1; 1801 uint8_t p_y : 1; 1802 uint8_t n_y : 1; 1803 uint8_t p_z : 1; 1804 uint8_t n_z : 1; 1805 uint8_t p_v : 1; 1806 uint8_t n_v : 1; 1807 #endif /* DRV_BYTE_ORDER */ 1808 } lsm6dsrx_fsm_outs10_t; 1809 1810 #define LSM6DSRX_FSM_OUTS11 0x56U 1811 typedef struct 1812 { 1813 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1814 uint8_t n_v : 1; 1815 uint8_t p_v : 1; 1816 uint8_t n_z : 1; 1817 uint8_t p_z : 1; 1818 uint8_t n_y : 1; 1819 uint8_t p_y : 1; 1820 uint8_t n_x : 1; 1821 uint8_t p_x : 1; 1822 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1823 uint8_t p_x : 1; 1824 uint8_t n_x : 1; 1825 uint8_t p_y : 1; 1826 uint8_t n_y : 1; 1827 uint8_t p_z : 1; 1828 uint8_t n_z : 1; 1829 uint8_t p_v : 1; 1830 uint8_t n_v : 1; 1831 #endif /* DRV_BYTE_ORDER */ 1832 } lsm6dsrx_fsm_outs11_t; 1833 1834 #define LSM6DSRX_FSM_OUTS12 0x57U 1835 typedef struct 1836 { 1837 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1838 uint8_t n_v : 1; 1839 uint8_t p_v : 1; 1840 uint8_t n_z : 1; 1841 uint8_t p_z : 1; 1842 uint8_t n_y : 1; 1843 uint8_t p_y : 1; 1844 uint8_t n_x : 1; 1845 uint8_t p_x : 1; 1846 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1847 uint8_t p_x : 1; 1848 uint8_t n_x : 1; 1849 uint8_t p_y : 1; 1850 uint8_t n_y : 1; 1851 uint8_t p_z : 1; 1852 uint8_t n_z : 1; 1853 uint8_t p_v : 1; 1854 uint8_t n_v : 1; 1855 #endif /* DRV_BYTE_ORDER */ 1856 } lsm6dsrx_fsm_outs12_t; 1857 1858 #define LSM6DSRX_FSM_OUTS13 0x58U 1859 typedef struct 1860 { 1861 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1862 uint8_t n_v : 1; 1863 uint8_t p_v : 1; 1864 uint8_t n_z : 1; 1865 uint8_t p_z : 1; 1866 uint8_t n_y : 1; 1867 uint8_t p_y : 1; 1868 uint8_t n_x : 1; 1869 uint8_t p_x : 1; 1870 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1871 uint8_t p_x : 1; 1872 uint8_t n_x : 1; 1873 uint8_t p_y : 1; 1874 uint8_t n_y : 1; 1875 uint8_t p_z : 1; 1876 uint8_t n_z : 1; 1877 uint8_t p_v : 1; 1878 uint8_t n_v : 1; 1879 #endif /* DRV_BYTE_ORDER */ 1880 } lsm6dsrx_fsm_outs13_t; 1881 1882 #define LSM6DSRX_FSM_OUTS14 0x59U 1883 typedef struct 1884 { 1885 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1886 uint8_t n_v : 1; 1887 uint8_t p_v : 1; 1888 uint8_t n_z : 1; 1889 uint8_t p_z : 1; 1890 uint8_t n_y : 1; 1891 uint8_t p_y : 1; 1892 uint8_t n_x : 1; 1893 uint8_t p_x : 1; 1894 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1895 uint8_t p_x : 1; 1896 uint8_t n_x : 1; 1897 uint8_t p_y : 1; 1898 uint8_t n_y : 1; 1899 uint8_t p_z : 1; 1900 uint8_t n_z : 1; 1901 uint8_t p_v : 1; 1902 uint8_t n_v : 1; 1903 #endif /* DRV_BYTE_ORDER */ 1904 } lsm6dsrx_fsm_outs14_t; 1905 1906 #define LSM6DSRX_FSM_OUTS15 0x5AU 1907 typedef struct 1908 { 1909 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1910 uint8_t n_v : 1; 1911 uint8_t p_v : 1; 1912 uint8_t n_z : 1; 1913 uint8_t p_z : 1; 1914 uint8_t n_y : 1; 1915 uint8_t p_y : 1; 1916 uint8_t n_x : 1; 1917 uint8_t p_x : 1; 1918 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1919 uint8_t p_x : 1; 1920 uint8_t n_x : 1; 1921 uint8_t p_y : 1; 1922 uint8_t n_y : 1; 1923 uint8_t p_z : 1; 1924 uint8_t n_z : 1; 1925 uint8_t p_v : 1; 1926 uint8_t n_v : 1; 1927 #endif /* DRV_BYTE_ORDER */ 1928 } lsm6dsrx_fsm_outs15_t; 1929 1930 #define LSM6DSRX_FSM_OUTS16 0x5BU 1931 typedef struct 1932 { 1933 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1934 uint8_t n_v : 1; 1935 uint8_t p_v : 1; 1936 uint8_t n_z : 1; 1937 uint8_t p_z : 1; 1938 uint8_t n_y : 1; 1939 uint8_t p_y : 1; 1940 uint8_t n_x : 1; 1941 uint8_t p_x : 1; 1942 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1943 uint8_t p_x : 1; 1944 uint8_t n_x : 1; 1945 uint8_t p_y : 1; 1946 uint8_t n_y : 1; 1947 uint8_t p_z : 1; 1948 uint8_t n_z : 1; 1949 uint8_t p_v : 1; 1950 uint8_t n_v : 1; 1951 #endif /* DRV_BYTE_ORDER */ 1952 } lsm6dsrx_fsm_outs16_t; 1953 1954 #define LSM6DSRX_EMB_FUNC_ODR_CFG_B 0x5FU 1955 typedef struct 1956 { 1957 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1958 uint8_t not_used_01 : 3; 1959 uint8_t fsm_odr : 2; 1960 uint8_t not_used_02 : 3; 1961 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1962 uint8_t not_used_02 : 3; 1963 uint8_t fsm_odr : 2; 1964 uint8_t not_used_01 : 3; 1965 #endif /* DRV_BYTE_ORDER */ 1966 } lsm6dsrx_emb_func_odr_cfg_b_t; 1967 1968 #define LSM6DSRX_EMB_FUNC_ODR_CFG_C 0x60U 1969 typedef struct 1970 { 1971 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1972 uint8_t not_used_01 : 4; 1973 uint8_t mlc_odr : 2; 1974 uint8_t not_used_02 : 2; 1975 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1976 uint8_t not_used_02 : 2; 1977 uint8_t mlc_odr : 2; 1978 uint8_t not_used_01 : 4; 1979 #endif /* DRV_BYTE_ORDER */ 1980 } lsm6dsrx_emb_func_odr_cfg_c_t; 1981 1982 #define LSM6DSRX_STEP_COUNTER_L 0x62U 1983 #define LSM6DSRX_STEP_COUNTER_H 0x63U 1984 #define LSM6DSRX_EMB_FUNC_SRC 0x64U 1985 typedef struct 1986 { 1987 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1988 uint8_t not_used_01 : 2; 1989 uint8_t stepcounter_bit_set : 1; 1990 uint8_t step_overflow : 1; 1991 uint8_t step_count_delta_ia : 1; 1992 uint8_t step_detected : 1; 1993 uint8_t not_used_02 : 1; 1994 uint8_t pedo_rst_step : 1; 1995 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1996 uint8_t pedo_rst_step : 1; 1997 uint8_t not_used_02 : 1; 1998 uint8_t step_detected : 1; 1999 uint8_t step_count_delta_ia : 1; 2000 uint8_t step_overflow : 1; 2001 uint8_t stepcounter_bit_set : 1; 2002 uint8_t not_used_01 : 2; 2003 #endif /* DRV_BYTE_ORDER */ 2004 } lsm6dsrx_emb_func_src_t; 2005 2006 #define LSM6DSRX_EMB_FUNC_INIT_A 0x66U 2007 typedef struct 2008 { 2009 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2010 uint8_t not_used_01 : 3; 2011 uint8_t step_det_init : 1; 2012 uint8_t tilt_init : 1; 2013 uint8_t sig_mot_init : 1; 2014 uint8_t not_used_02 : 2; 2015 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2016 uint8_t not_used_02 : 2; 2017 uint8_t sig_mot_init : 1; 2018 uint8_t tilt_init : 1; 2019 uint8_t step_det_init : 1; 2020 uint8_t not_used_01 : 3; 2021 #endif /* DRV_BYTE_ORDER */ 2022 } lsm6dsrx_emb_func_init_a_t; 2023 2024 #define LSM6DSRX_EMB_FUNC_INIT_B 0x67U 2025 typedef struct 2026 { 2027 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2028 uint8_t fsm_init : 1; 2029 uint8_t not_used_01 : 2; 2030 uint8_t fifo_compr_init : 1; 2031 uint8_t mlc_init : 1; 2032 uint8_t not_used_02 : 3; 2033 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2034 uint8_t not_used_02 : 3; 2035 uint8_t mlc_init : 1; 2036 uint8_t fifo_compr_init : 1; 2037 uint8_t not_used_01 : 2; 2038 uint8_t fsm_init : 1; 2039 #endif /* DRV_BYTE_ORDER */ 2040 } lsm6dsrx_emb_func_init_b_t; 2041 2042 #define LSM6DSRX_MLC0_SRC 0x70U 2043 #define LSM6DSRX_MLC1_SRC 0x71U 2044 #define LSM6DSRX_MLC2_SRC 0x72U 2045 #define LSM6DSRX_MLC3_SRC 0x73U 2046 #define LSM6DSRX_MLC4_SRC 0x74U 2047 #define LSM6DSRX_MLC5_SRC 0x75U 2048 #define LSM6DSRX_MLC6_SRC 0x76U 2049 #define LSM6DSRX_MLC7_SRC 0x77U 2050 2051 /** @defgroup bitfields page 0 and 1 2052 * @{ 2053 * 2054 */ 2055 #define LSM6DSRX_MAG_SENSITIVITY_L 0xBAU 2056 #define LSM6DSRX_MAG_SENSITIVITY_H 0xBBU 2057 #define LSM6DSRX_MAG_OFFX_L 0xC0U 2058 #define LSM6DSRX_MAG_OFFX_H 0xC1U 2059 #define LSM6DSRX_MAG_OFFY_L 0xC2U 2060 #define LSM6DSRX_MAG_OFFY_H 0xC3U 2061 #define LSM6DSRX_MAG_OFFZ_L 0xC4U 2062 #define LSM6DSRX_MAG_OFFZ_H 0xC5U 2063 #define LSM6DSRX_MAG_SI_XX_L 0xC6U 2064 #define LSM6DSRX_MAG_SI_XX_H 0xC7U 2065 #define LSM6DSRX_MAG_SI_XY_L 0xC8U 2066 #define LSM6DSRX_MAG_SI_XY_H 0xC9U 2067 #define LSM6DSRX_MAG_SI_XZ_L 0xCAU 2068 #define LSM6DSRX_MAG_SI_XZ_H 0xCBU 2069 #define LSM6DSRX_MAG_SI_YY_L 0xCCU 2070 #define LSM6DSRX_MAG_SI_YY_H 0xCDU 2071 #define LSM6DSRX_MAG_SI_YZ_L 0xCEU 2072 #define LSM6DSRX_MAG_SI_YZ_H 0xCFU 2073 #define LSM6DSRX_MAG_SI_ZZ_L 0xD0U 2074 #define LSM6DSRX_MAG_SI_ZZ_H 0xD1U 2075 #define LSM6DSRX_MAG_CFG_A 0xD4U 2076 typedef struct 2077 { 2078 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2079 uint8_t mag_z_axis : 3; 2080 uint8_t not_used_01 : 1; 2081 uint8_t mag_y_axis : 3; 2082 uint8_t not_used_02 : 1; 2083 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2084 uint8_t not_used_02 : 1; 2085 uint8_t mag_y_axis : 3; 2086 uint8_t not_used_01 : 1; 2087 uint8_t mag_z_axis : 3; 2088 #endif /* DRV_BYTE_ORDER */ 2089 } lsm6dsrx_mag_cfg_a_t; 2090 2091 #define LSM6DSRX_MAG_CFG_B 0xD5U 2092 typedef struct 2093 { 2094 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2095 uint8_t mag_x_axis : 3; 2096 uint8_t not_used_01 : 5; 2097 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2098 uint8_t not_used_01 : 5; 2099 uint8_t mag_x_axis : 3; 2100 #endif /* DRV_BYTE_ORDER */ 2101 } lsm6dsrx_mag_cfg_b_t; 2102 2103 #define LSM6DSRX_FSM_LC_TIMEOUT_L 0x17AU 2104 #define LSM6DSRX_FSM_LC_TIMEOUT_H 0x17BU 2105 #define LSM6DSRX_FSM_PROGRAMS 0x17CU 2106 #define LSM6DSRX_FSM_START_ADD_L 0x17EU 2107 #define LSM6DSRX_FSM_START_ADD_H 0x17FU 2108 #define LSM6DSRX_PEDO_CMD_REG 0x183U 2109 typedef struct 2110 { 2111 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2112 uint8_t not_used_01 : 3; 2113 uint8_t carry_count_en : 1; 2114 uint8_t not_used_02 : 4; 2115 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2116 uint8_t not_used_02 : 4; 2117 uint8_t carry_count_en : 1; 2118 uint8_t not_used_01 : 3; 2119 #endif /* DRV_BYTE_ORDER */ 2120 } lsm6dsrx_pedo_cmd_reg_t; 2121 2122 #define LSM6DSRX_PEDO_DEB_STEPS_CONF 0x184U 2123 #define LSM6DSRX_PEDO_SC_DELTAT_L 0x1D0U 2124 #define LSM6DSRX_PEDO_SC_DELTAT_H 0x1D1U 2125 #define LSM6DSRX_MLC_MAG_SENSITIVITY_L 0x1E8U 2126 #define LSM6DSRX_MLC_MAG_SENSITIVITY_H 0x1E9U 2127 2128 /** 2129 * @} 2130 * 2131 */ 2132 2133 /** @defgroup bitfields page sensor_hub 2134 * @{ 2135 * 2136 */ 2137 2138 #define LSM6DSRX_SENSOR_HUB_1 0x02U 2139 typedef struct 2140 { 2141 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2142 uint8_t bit0 : 1; 2143 uint8_t bit1 : 1; 2144 uint8_t bit2 : 1; 2145 uint8_t bit3 : 1; 2146 uint8_t bit4 : 1; 2147 uint8_t bit5 : 1; 2148 uint8_t bit6 : 1; 2149 uint8_t bit7 : 1; 2150 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2151 uint8_t bit7 : 1; 2152 uint8_t bit6 : 1; 2153 uint8_t bit5 : 1; 2154 uint8_t bit4 : 1; 2155 uint8_t bit3 : 1; 2156 uint8_t bit2 : 1; 2157 uint8_t bit1 : 1; 2158 uint8_t bit0 : 1; 2159 #endif /* DRV_BYTE_ORDER */ 2160 } lsm6dsrx_sensor_hub_1_t; 2161 2162 #define LSM6DSRX_SENSOR_HUB_2 0x03U 2163 typedef struct 2164 { 2165 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2166 uint8_t bit0 : 1; 2167 uint8_t bit1 : 1; 2168 uint8_t bit2 : 1; 2169 uint8_t bit3 : 1; 2170 uint8_t bit4 : 1; 2171 uint8_t bit5 : 1; 2172 uint8_t bit6 : 1; 2173 uint8_t bit7 : 1; 2174 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2175 uint8_t bit7 : 1; 2176 uint8_t bit6 : 1; 2177 uint8_t bit5 : 1; 2178 uint8_t bit4 : 1; 2179 uint8_t bit3 : 1; 2180 uint8_t bit2 : 1; 2181 uint8_t bit1 : 1; 2182 uint8_t bit0 : 1; 2183 #endif /* DRV_BYTE_ORDER */ 2184 } lsm6dsrx_sensor_hub_2_t; 2185 2186 #define LSM6DSRX_SENSOR_HUB_3 0x04U 2187 typedef struct 2188 { 2189 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2190 uint8_t bit0 : 1; 2191 uint8_t bit1 : 1; 2192 uint8_t bit2 : 1; 2193 uint8_t bit3 : 1; 2194 uint8_t bit4 : 1; 2195 uint8_t bit5 : 1; 2196 uint8_t bit6 : 1; 2197 uint8_t bit7 : 1; 2198 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2199 uint8_t bit7 : 1; 2200 uint8_t bit6 : 1; 2201 uint8_t bit5 : 1; 2202 uint8_t bit4 : 1; 2203 uint8_t bit3 : 1; 2204 uint8_t bit2 : 1; 2205 uint8_t bit1 : 1; 2206 uint8_t bit0 : 1; 2207 #endif /* DRV_BYTE_ORDER */ 2208 } lsm6dsrx_sensor_hub_3_t; 2209 2210 #define LSM6DSRX_SENSOR_HUB_4 0x05U 2211 typedef struct 2212 { 2213 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2214 uint8_t bit0 : 1; 2215 uint8_t bit1 : 1; 2216 uint8_t bit2 : 1; 2217 uint8_t bit3 : 1; 2218 uint8_t bit4 : 1; 2219 uint8_t bit5 : 1; 2220 uint8_t bit6 : 1; 2221 uint8_t bit7 : 1; 2222 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2223 uint8_t bit7 : 1; 2224 uint8_t bit6 : 1; 2225 uint8_t bit5 : 1; 2226 uint8_t bit4 : 1; 2227 uint8_t bit3 : 1; 2228 uint8_t bit2 : 1; 2229 uint8_t bit1 : 1; 2230 uint8_t bit0 : 1; 2231 #endif /* DRV_BYTE_ORDER */ 2232 } lsm6dsrx_sensor_hub_4_t; 2233 2234 #define LSM6DSRX_SENSOR_HUB_5 0x06U 2235 typedef struct 2236 { 2237 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2238 uint8_t bit0 : 1; 2239 uint8_t bit1 : 1; 2240 uint8_t bit2 : 1; 2241 uint8_t bit3 : 1; 2242 uint8_t bit4 : 1; 2243 uint8_t bit5 : 1; 2244 uint8_t bit6 : 1; 2245 uint8_t bit7 : 1; 2246 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2247 uint8_t bit7 : 1; 2248 uint8_t bit6 : 1; 2249 uint8_t bit5 : 1; 2250 uint8_t bit4 : 1; 2251 uint8_t bit3 : 1; 2252 uint8_t bit2 : 1; 2253 uint8_t bit1 : 1; 2254 uint8_t bit0 : 1; 2255 #endif /* DRV_BYTE_ORDER */ 2256 } lsm6dsrx_sensor_hub_5_t; 2257 2258 #define LSM6DSRX_SENSOR_HUB_6 0x07U 2259 typedef struct 2260 { 2261 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2262 uint8_t bit0 : 1; 2263 uint8_t bit1 : 1; 2264 uint8_t bit2 : 1; 2265 uint8_t bit3 : 1; 2266 uint8_t bit4 : 1; 2267 uint8_t bit5 : 1; 2268 uint8_t bit6 : 1; 2269 uint8_t bit7 : 1; 2270 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2271 uint8_t bit7 : 1; 2272 uint8_t bit6 : 1; 2273 uint8_t bit5 : 1; 2274 uint8_t bit4 : 1; 2275 uint8_t bit3 : 1; 2276 uint8_t bit2 : 1; 2277 uint8_t bit1 : 1; 2278 uint8_t bit0 : 1; 2279 #endif /* DRV_BYTE_ORDER */ 2280 } lsm6dsrx_sensor_hub_6_t; 2281 2282 #define LSM6DSRX_SENSOR_HUB_7 0x08U 2283 typedef struct 2284 { 2285 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2286 uint8_t bit0 : 1; 2287 uint8_t bit1 : 1; 2288 uint8_t bit2 : 1; 2289 uint8_t bit3 : 1; 2290 uint8_t bit4 : 1; 2291 uint8_t bit5 : 1; 2292 uint8_t bit6 : 1; 2293 uint8_t bit7 : 1; 2294 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2295 uint8_t bit7 : 1; 2296 uint8_t bit6 : 1; 2297 uint8_t bit5 : 1; 2298 uint8_t bit4 : 1; 2299 uint8_t bit3 : 1; 2300 uint8_t bit2 : 1; 2301 uint8_t bit1 : 1; 2302 uint8_t bit0 : 1; 2303 #endif /* DRV_BYTE_ORDER */ 2304 } lsm6dsrx_sensor_hub_7_t; 2305 2306 #define LSM6DSRX_SENSOR_HUB_8 0x09U 2307 typedef struct 2308 { 2309 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2310 uint8_t bit0 : 1; 2311 uint8_t bit1 : 1; 2312 uint8_t bit2 : 1; 2313 uint8_t bit3 : 1; 2314 uint8_t bit4 : 1; 2315 uint8_t bit5 : 1; 2316 uint8_t bit6 : 1; 2317 uint8_t bit7 : 1; 2318 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2319 uint8_t bit7 : 1; 2320 uint8_t bit6 : 1; 2321 uint8_t bit5 : 1; 2322 uint8_t bit4 : 1; 2323 uint8_t bit3 : 1; 2324 uint8_t bit2 : 1; 2325 uint8_t bit1 : 1; 2326 uint8_t bit0 : 1; 2327 #endif /* DRV_BYTE_ORDER */ 2328 } lsm6dsrx_sensor_hub_8_t; 2329 2330 #define LSM6DSRX_SENSOR_HUB_9 0x0AU 2331 typedef struct 2332 { 2333 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2334 uint8_t bit0 : 1; 2335 uint8_t bit1 : 1; 2336 uint8_t bit2 : 1; 2337 uint8_t bit3 : 1; 2338 uint8_t bit4 : 1; 2339 uint8_t bit5 : 1; 2340 uint8_t bit6 : 1; 2341 uint8_t bit7 : 1; 2342 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2343 uint8_t bit7 : 1; 2344 uint8_t bit6 : 1; 2345 uint8_t bit5 : 1; 2346 uint8_t bit4 : 1; 2347 uint8_t bit3 : 1; 2348 uint8_t bit2 : 1; 2349 uint8_t bit1 : 1; 2350 uint8_t bit0 : 1; 2351 #endif /* DRV_BYTE_ORDER */ 2352 } lsm6dsrx_sensor_hub_9_t; 2353 2354 #define LSM6DSRX_SENSOR_HUB_10 0x0BU 2355 typedef struct 2356 { 2357 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2358 uint8_t bit0 : 1; 2359 uint8_t bit1 : 1; 2360 uint8_t bit2 : 1; 2361 uint8_t bit3 : 1; 2362 uint8_t bit4 : 1; 2363 uint8_t bit5 : 1; 2364 uint8_t bit6 : 1; 2365 uint8_t bit7 : 1; 2366 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2367 uint8_t bit7 : 1; 2368 uint8_t bit6 : 1; 2369 uint8_t bit5 : 1; 2370 uint8_t bit4 : 1; 2371 uint8_t bit3 : 1; 2372 uint8_t bit2 : 1; 2373 uint8_t bit1 : 1; 2374 uint8_t bit0 : 1; 2375 #endif /* DRV_BYTE_ORDER */ 2376 } lsm6dsrx_sensor_hub_10_t; 2377 2378 #define LSM6DSRX_SENSOR_HUB_11 0x0CU 2379 typedef struct 2380 { 2381 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2382 uint8_t bit0 : 1; 2383 uint8_t bit1 : 1; 2384 uint8_t bit2 : 1; 2385 uint8_t bit3 : 1; 2386 uint8_t bit4 : 1; 2387 uint8_t bit5 : 1; 2388 uint8_t bit6 : 1; 2389 uint8_t bit7 : 1; 2390 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2391 uint8_t bit7 : 1; 2392 uint8_t bit6 : 1; 2393 uint8_t bit5 : 1; 2394 uint8_t bit4 : 1; 2395 uint8_t bit3 : 1; 2396 uint8_t bit2 : 1; 2397 uint8_t bit1 : 1; 2398 uint8_t bit0 : 1; 2399 #endif /* DRV_BYTE_ORDER */ 2400 } lsm6dsrx_sensor_hub_11_t; 2401 2402 #define LSM6DSRX_SENSOR_HUB_12 0x0DU 2403 typedef struct 2404 { 2405 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2406 uint8_t bit0 : 1; 2407 uint8_t bit1 : 1; 2408 uint8_t bit2 : 1; 2409 uint8_t bit3 : 1; 2410 uint8_t bit4 : 1; 2411 uint8_t bit5 : 1; 2412 uint8_t bit6 : 1; 2413 uint8_t bit7 : 1; 2414 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2415 uint8_t bit7 : 1; 2416 uint8_t bit6 : 1; 2417 uint8_t bit5 : 1; 2418 uint8_t bit4 : 1; 2419 uint8_t bit3 : 1; 2420 uint8_t bit2 : 1; 2421 uint8_t bit1 : 1; 2422 uint8_t bit0 : 1; 2423 #endif /* DRV_BYTE_ORDER */ 2424 } lsm6dsrx_sensor_hub_12_t; 2425 2426 #define LSM6DSRX_SENSOR_HUB_13 0x0EU 2427 typedef struct 2428 { 2429 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2430 uint8_t bit0 : 1; 2431 uint8_t bit1 : 1; 2432 uint8_t bit2 : 1; 2433 uint8_t bit3 : 1; 2434 uint8_t bit4 : 1; 2435 uint8_t bit5 : 1; 2436 uint8_t bit6 : 1; 2437 uint8_t bit7 : 1; 2438 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2439 uint8_t bit7 : 1; 2440 uint8_t bit6 : 1; 2441 uint8_t bit5 : 1; 2442 uint8_t bit4 : 1; 2443 uint8_t bit3 : 1; 2444 uint8_t bit2 : 1; 2445 uint8_t bit1 : 1; 2446 uint8_t bit0 : 1; 2447 #endif /* DRV_BYTE_ORDER */ 2448 } lsm6dsrx_sensor_hub_13_t; 2449 2450 #define LSM6DSRX_SENSOR_HUB_14 0x0FU 2451 typedef struct 2452 { 2453 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2454 uint8_t bit0 : 1; 2455 uint8_t bit1 : 1; 2456 uint8_t bit2 : 1; 2457 uint8_t bit3 : 1; 2458 uint8_t bit4 : 1; 2459 uint8_t bit5 : 1; 2460 uint8_t bit6 : 1; 2461 uint8_t bit7 : 1; 2462 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2463 uint8_t bit7 : 1; 2464 uint8_t bit6 : 1; 2465 uint8_t bit5 : 1; 2466 uint8_t bit4 : 1; 2467 uint8_t bit3 : 1; 2468 uint8_t bit2 : 1; 2469 uint8_t bit1 : 1; 2470 uint8_t bit0 : 1; 2471 #endif /* DRV_BYTE_ORDER */ 2472 } lsm6dsrx_sensor_hub_14_t; 2473 2474 #define LSM6DSRX_SENSOR_HUB_15 0x10U 2475 typedef struct 2476 { 2477 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2478 uint8_t bit0 : 1; 2479 uint8_t bit1 : 1; 2480 uint8_t bit2 : 1; 2481 uint8_t bit3 : 1; 2482 uint8_t bit4 : 1; 2483 uint8_t bit5 : 1; 2484 uint8_t bit6 : 1; 2485 uint8_t bit7 : 1; 2486 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2487 uint8_t bit7 : 1; 2488 uint8_t bit6 : 1; 2489 uint8_t bit5 : 1; 2490 uint8_t bit4 : 1; 2491 uint8_t bit3 : 1; 2492 uint8_t bit2 : 1; 2493 uint8_t bit1 : 1; 2494 uint8_t bit0 : 1; 2495 #endif /* DRV_BYTE_ORDER */ 2496 } lsm6dsrx_sensor_hub_15_t; 2497 2498 #define LSM6DSRX_SENSOR_HUB_16 0x11U 2499 typedef struct 2500 { 2501 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2502 uint8_t bit0 : 1; 2503 uint8_t bit1 : 1; 2504 uint8_t bit2 : 1; 2505 uint8_t bit3 : 1; 2506 uint8_t bit4 : 1; 2507 uint8_t bit5 : 1; 2508 uint8_t bit6 : 1; 2509 uint8_t bit7 : 1; 2510 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2511 uint8_t bit7 : 1; 2512 uint8_t bit6 : 1; 2513 uint8_t bit5 : 1; 2514 uint8_t bit4 : 1; 2515 uint8_t bit3 : 1; 2516 uint8_t bit2 : 1; 2517 uint8_t bit1 : 1; 2518 uint8_t bit0 : 1; 2519 #endif /* DRV_BYTE_ORDER */ 2520 } lsm6dsrx_sensor_hub_16_t; 2521 2522 #define LSM6DSRX_SENSOR_HUB_17 0x12U 2523 typedef struct 2524 { 2525 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2526 uint8_t bit0 : 1; 2527 uint8_t bit1 : 1; 2528 uint8_t bit2 : 1; 2529 uint8_t bit3 : 1; 2530 uint8_t bit4 : 1; 2531 uint8_t bit5 : 1; 2532 uint8_t bit6 : 1; 2533 uint8_t bit7 : 1; 2534 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2535 uint8_t bit7 : 1; 2536 uint8_t bit6 : 1; 2537 uint8_t bit5 : 1; 2538 uint8_t bit4 : 1; 2539 uint8_t bit3 : 1; 2540 uint8_t bit2 : 1; 2541 uint8_t bit1 : 1; 2542 uint8_t bit0 : 1; 2543 #endif /* DRV_BYTE_ORDER */ 2544 } lsm6dsrx_sensor_hub_17_t; 2545 2546 #define LSM6DSRX_SENSOR_HUB_18 0x13U 2547 typedef struct 2548 { 2549 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2550 uint8_t bit0 : 1; 2551 uint8_t bit1 : 1; 2552 uint8_t bit2 : 1; 2553 uint8_t bit3 : 1; 2554 uint8_t bit4 : 1; 2555 uint8_t bit5 : 1; 2556 uint8_t bit6 : 1; 2557 uint8_t bit7 : 1; 2558 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2559 uint8_t bit7 : 1; 2560 uint8_t bit6 : 1; 2561 uint8_t bit5 : 1; 2562 uint8_t bit4 : 1; 2563 uint8_t bit3 : 1; 2564 uint8_t bit2 : 1; 2565 uint8_t bit1 : 1; 2566 uint8_t bit0 : 1; 2567 #endif /* DRV_BYTE_ORDER */ 2568 } lsm6dsrx_sensor_hub_18_t; 2569 2570 #define LSM6DSRX_MASTER_CONFIG 0x14U 2571 typedef struct 2572 { 2573 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2574 uint8_t aux_sens_on : 2; 2575 uint8_t master_on : 1; 2576 uint8_t shub_pu_en : 1; 2577 uint8_t pass_through_mode : 1; 2578 uint8_t start_config : 1; 2579 uint8_t write_once : 1; 2580 uint8_t rst_master_regs : 1; 2581 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2582 uint8_t rst_master_regs : 1; 2583 uint8_t write_once : 1; 2584 uint8_t start_config : 1; 2585 uint8_t pass_through_mode : 1; 2586 uint8_t shub_pu_en : 1; 2587 uint8_t master_on : 1; 2588 uint8_t aux_sens_on : 2; 2589 #endif /* DRV_BYTE_ORDER */ 2590 } lsm6dsrx_master_config_t; 2591 2592 #define LSM6DSRX_SLV0_ADD 0x15U 2593 typedef struct 2594 { 2595 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2596 uint8_t rw_0 : 1; 2597 uint8_t slave0 : 7; 2598 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2599 uint8_t slave0 : 7; 2600 uint8_t rw_0 : 1; 2601 #endif /* DRV_BYTE_ORDER */ 2602 } lsm6dsrx_slv0_add_t; 2603 2604 #define LSM6DSRX_SLV0_SUBADD 0x16U 2605 typedef struct 2606 { 2607 uint8_t slave0_reg : 8; 2608 } lsm6dsrx_slv0_subadd_t; 2609 2610 #define LSM6DSRX_SLV0_CONFIG 0x17U 2611 typedef struct 2612 { 2613 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2614 uint8_t slave0_numop : 3; 2615 uint8_t batch_ext_sens_0_en : 1; 2616 uint8_t not_used_01 : 2; 2617 uint8_t shub_odr : 2; 2618 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2619 uint8_t shub_odr : 2; 2620 uint8_t not_used_01 : 2; 2621 uint8_t batch_ext_sens_0_en : 1; 2622 uint8_t slave0_numop : 3; 2623 #endif /* DRV_BYTE_ORDER */ 2624 } lsm6dsrx_slv0_config_t; 2625 2626 #define LSM6DSRX_SLV1_ADD 0x18U 2627 typedef struct 2628 { 2629 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2630 uint8_t r_1 : 1; 2631 uint8_t slave1_add : 7; 2632 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2633 uint8_t slave1_add : 7; 2634 uint8_t r_1 : 1; 2635 #endif /* DRV_BYTE_ORDER */ 2636 } lsm6dsrx_slv1_add_t; 2637 2638 #define LSM6DSRX_SLV1_SUBADD 0x19U 2639 typedef struct 2640 { 2641 uint8_t slave1_reg : 8; 2642 } lsm6dsrx_slv1_subadd_t; 2643 2644 #define LSM6DSRX_SLV1_CONFIG 0x1AU 2645 typedef struct 2646 { 2647 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2648 uint8_t slave1_numop : 3; 2649 uint8_t batch_ext_sens_1_en : 1; 2650 uint8_t not_used_01 : 4; 2651 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2652 uint8_t not_used_01 : 4; 2653 uint8_t batch_ext_sens_1_en : 1; 2654 uint8_t slave1_numop : 3; 2655 #endif /* DRV_BYTE_ORDER */ 2656 } lsm6dsrx_slv1_config_t; 2657 2658 #define LSM6DSRX_SLV2_ADD 0x1BU 2659 typedef struct 2660 { 2661 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2662 uint8_t r_2 : 1; 2663 uint8_t slave2_add : 7; 2664 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2665 uint8_t slave2_add : 7; 2666 uint8_t r_2 : 1; 2667 #endif /* DRV_BYTE_ORDER */ 2668 } lsm6dsrx_slv2_add_t; 2669 2670 #define LSM6DSRX_SLV2_SUBADD 0x1CU 2671 typedef struct 2672 { 2673 uint8_t slave2_reg : 8; 2674 } lsm6dsrx_slv2_subadd_t; 2675 2676 #define LSM6DSRX_SLV2_CONFIG 0x1DU 2677 typedef struct 2678 { 2679 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2680 uint8_t slave2_numop : 3; 2681 uint8_t batch_ext_sens_2_en : 1; 2682 uint8_t not_used_01 : 4; 2683 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2684 uint8_t not_used_01 : 4; 2685 uint8_t batch_ext_sens_2_en : 1; 2686 uint8_t slave2_numop : 3; 2687 #endif /* DRV_BYTE_ORDER */ 2688 } lsm6dsrx_slv2_config_t; 2689 2690 #define LSM6DSRX_SLV3_ADD 0x1EU 2691 typedef struct 2692 { 2693 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2694 uint8_t r_3 : 1; 2695 uint8_t slave3_add : 7; 2696 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2697 uint8_t slave3_add : 7; 2698 uint8_t r_3 : 1; 2699 #endif /* DRV_BYTE_ORDER */ 2700 } lsm6dsrx_slv3_add_t; 2701 2702 #define LSM6DSRX_SLV3_SUBADD 0x1FU 2703 typedef struct 2704 { 2705 uint8_t slave3_reg : 8; 2706 } lsm6dsrx_slv3_subadd_t; 2707 2708 #define LSM6DSRX_SLV3_CONFIG 0x20U 2709 typedef struct 2710 { 2711 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2712 uint8_t slave3_numop : 3; 2713 uint8_t batch_ext_sens_3_en : 1; 2714 uint8_t not_used_01 : 4; 2715 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2716 uint8_t not_used_01 : 4; 2717 uint8_t batch_ext_sens_3_en : 1; 2718 uint8_t slave3_numop : 3; 2719 #endif /* DRV_BYTE_ORDER */ 2720 } lsm6dsrx_slv3_config_t; 2721 2722 #define LSM6DSRX_DATAWRITE_SLV0 0x21U 2723 typedef struct 2724 { 2725 uint8_t slave0_dataw : 8; 2726 } lsm6dsrx_datawrite_slv0_t; 2727 2728 #define LSM6DSRX_STATUS_MASTER 0x22U 2729 typedef struct 2730 { 2731 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2732 uint8_t sens_hub_endop : 1; 2733 uint8_t not_used_01 : 2; 2734 uint8_t slave0_nack : 1; 2735 uint8_t slave1_nack : 1; 2736 uint8_t slave2_nack : 1; 2737 uint8_t slave3_nack : 1; 2738 uint8_t wr_once_done : 1; 2739 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2740 uint8_t wr_once_done : 1; 2741 uint8_t slave3_nack : 1; 2742 uint8_t slave2_nack : 1; 2743 uint8_t slave1_nack : 1; 2744 uint8_t slave0_nack : 1; 2745 uint8_t not_used_01 : 2; 2746 uint8_t sens_hub_endop : 1; 2747 #endif /* DRV_BYTE_ORDER */ 2748 } lsm6dsrx_status_master_t; 2749 2750 /** 2751 * @} 2752 * 2753 */ 2754 2755 /** 2756 * @defgroup LSM6DSRX_Register_Union 2757 * @brief This union group all the registers having a bit-field 2758 * description. 2759 * This union is useful but it's not needed by the driver. 2760 * 2761 * REMOVING this union you are compliant with: 2762 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2763 * 2764 * @{ 2765 * 2766 */ 2767 typedef union 2768 { 2769 lsm6dsrx_func_cfg_access_t func_cfg_access; 2770 lsm6dsrx_pin_ctrl_t pin_ctrl; 2771 lsm6dsrx_s4s_tph_l_t s4s_tph_l; 2772 lsm6dsrx_s4s_tph_h_t s4s_tph_h; 2773 lsm6dsrx_s4s_rr_t s4s_rr; 2774 lsm6dsrx_fifo_ctrl1_t fifo_ctrl1; 2775 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2; 2776 lsm6dsrx_fifo_ctrl3_t fifo_ctrl3; 2777 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4; 2778 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1; 2779 lsm6dsrx_counter_bdr_reg2_t counter_bdr_reg2; 2780 lsm6dsrx_int1_ctrl_t int1_ctrl; 2781 lsm6dsrx_int2_ctrl_t int2_ctrl; 2782 lsm6dsrx_ctrl1_xl_t ctrl1_xl; 2783 lsm6dsrx_ctrl2_g_t ctrl2_g; 2784 lsm6dsrx_ctrl3_c_t ctrl3_c; 2785 lsm6dsrx_ctrl4_c_t ctrl4_c; 2786 lsm6dsrx_ctrl5_c_t ctrl5_c; 2787 lsm6dsrx_ctrl6_c_t ctrl6_c; 2788 lsm6dsrx_ctrl7_g_t ctrl7_g; 2789 lsm6dsrx_ctrl8_xl_t ctrl8_xl; 2790 lsm6dsrx_ctrl9_xl_t ctrl9_xl; 2791 lsm6dsrx_ctrl10_c_t ctrl10_c; 2792 lsm6dsrx_all_int_src_t all_int_src; 2793 lsm6dsrx_wake_up_src_t wake_up_src; 2794 lsm6dsrx_tap_src_t tap_src; 2795 lsm6dsrx_d6d_src_t d6d_src; 2796 lsm6dsrx_status_reg_t status_reg; 2797 lsm6dsrx_status_spiaux_t status_spiaux; 2798 lsm6dsrx_fifo_status1_t fifo_status1; 2799 lsm6dsrx_fifo_status2_t fifo_status2; 2800 lsm6dsrx_tap_cfg0_t tap_cfg0; 2801 lsm6dsrx_tap_cfg1_t tap_cfg1; 2802 lsm6dsrx_tap_cfg2_t tap_cfg2; 2803 lsm6dsrx_tap_ths_6d_t tap_ths_6d; 2804 lsm6dsrx_int_dur2_t int_dur2; 2805 lsm6dsrx_wake_up_ths_t wake_up_ths; 2806 lsm6dsrx_wake_up_dur_t wake_up_dur; 2807 lsm6dsrx_free_fall_t free_fall; 2808 lsm6dsrx_md1_cfg_t md1_cfg; 2809 lsm6dsrx_md2_cfg_t md2_cfg; 2810 lsm6dsrx_s4s_st_cmd_code_t s4s_st_cmd_code; 2811 lsm6dsrx_s4s_dt_reg_t s4s_dt_reg; 2812 lsm6dsrx_i3c_bus_avb_t i3c_bus_avb; 2813 lsm6dsrx_internal_freq_fine_t internal_freq_fine; 2814 lsm6dsrx_int_ois_t int_ois; 2815 lsm6dsrx_ctrl1_ois_t ctrl1_ois; 2816 lsm6dsrx_ctrl2_ois_t ctrl2_ois; 2817 lsm6dsrx_ctrl3_ois_t ctrl3_ois; 2818 lsm6dsrx_fifo_data_out_tag_t fifo_data_out_tag; 2819 lsm6dsrx_page_sel_t page_sel; 2820 lsm6dsrx_emb_func_en_a_t emb_func_en_a; 2821 lsm6dsrx_emb_func_en_b_t emb_func_en_b; 2822 lsm6dsrx_page_address_t page_address; 2823 lsm6dsrx_page_value_t page_value; 2824 lsm6dsrx_emb_func_int1_t emb_func_int1; 2825 lsm6dsrx_fsm_int1_a_t fsm_int1_a; 2826 lsm6dsrx_fsm_int1_b_t fsm_int1_b; 2827 lsm6dsrx_mlc_int1_t mlc_int1; 2828 lsm6dsrx_emb_func_int2_t emb_func_int2; 2829 lsm6dsrx_fsm_int2_a_t fsm_int2_a; 2830 lsm6dsrx_fsm_int2_b_t fsm_int2_b; 2831 lsm6dsrx_mlc_int2_t mlc_int2; 2832 lsm6dsrx_emb_func_status_t emb_func_status; 2833 lsm6dsrx_fsm_status_a_t fsm_status_a; 2834 lsm6dsrx_fsm_status_b_t fsm_status_b; 2835 lsm6dsrx_mlc_status_mainpage_t mlc_status_mainpage; 2836 lsm6dsrx_page_rw_t page_rw; 2837 lsm6dsrx_emb_func_fifo_cfg_t emb_func_fifo_cfg; 2838 lsm6dsrx_fsm_enable_a_t fsm_enable_a; 2839 lsm6dsrx_fsm_enable_b_t fsm_enable_b; 2840 lsm6dsrx_fsm_long_counter_clear_t fsm_long_counter_clear; 2841 lsm6dsrx_fsm_outs1_t fsm_outs1; 2842 lsm6dsrx_fsm_outs2_t fsm_outs2; 2843 lsm6dsrx_fsm_outs3_t fsm_outs3; 2844 lsm6dsrx_fsm_outs4_t fsm_outs4; 2845 lsm6dsrx_fsm_outs5_t fsm_outs5; 2846 lsm6dsrx_fsm_outs6_t fsm_outs6; 2847 lsm6dsrx_fsm_outs7_t fsm_outs7; 2848 lsm6dsrx_fsm_outs8_t fsm_outs8; 2849 lsm6dsrx_fsm_outs9_t fsm_outs9; 2850 lsm6dsrx_fsm_outs10_t fsm_outs10; 2851 lsm6dsrx_fsm_outs11_t fsm_outs11; 2852 lsm6dsrx_fsm_outs12_t fsm_outs12; 2853 lsm6dsrx_fsm_outs13_t fsm_outs13; 2854 lsm6dsrx_fsm_outs14_t fsm_outs14; 2855 lsm6dsrx_fsm_outs15_t fsm_outs15; 2856 lsm6dsrx_fsm_outs16_t fsm_outs16; 2857 lsm6dsrx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 2858 lsm6dsrx_emb_func_odr_cfg_c_t emb_func_odr_cfg_c_t; 2859 lsm6dsrx_emb_func_src_t emb_func_src; 2860 lsm6dsrx_emb_func_init_a_t emb_func_init_a; 2861 lsm6dsrx_emb_func_init_b_t emb_func_init_b; 2862 lsm6dsrx_mag_cfg_a_t mag_cfg_a; 2863 lsm6dsrx_mag_cfg_b_t mag_cfg_b; 2864 lsm6dsrx_pedo_cmd_reg_t pedo_cmd_reg; 2865 lsm6dsrx_sensor_hub_1_t sensor_hub_1; 2866 lsm6dsrx_sensor_hub_2_t sensor_hub_2; 2867 lsm6dsrx_sensor_hub_3_t sensor_hub_3; 2868 lsm6dsrx_sensor_hub_4_t sensor_hub_4; 2869 lsm6dsrx_sensor_hub_5_t sensor_hub_5; 2870 lsm6dsrx_sensor_hub_6_t sensor_hub_6; 2871 lsm6dsrx_sensor_hub_7_t sensor_hub_7; 2872 lsm6dsrx_sensor_hub_8_t sensor_hub_8; 2873 lsm6dsrx_sensor_hub_9_t sensor_hub_9; 2874 lsm6dsrx_sensor_hub_10_t sensor_hub_10; 2875 lsm6dsrx_sensor_hub_11_t sensor_hub_11; 2876 lsm6dsrx_sensor_hub_12_t sensor_hub_12; 2877 lsm6dsrx_sensor_hub_13_t sensor_hub_13; 2878 lsm6dsrx_sensor_hub_14_t sensor_hub_14; 2879 lsm6dsrx_sensor_hub_15_t sensor_hub_15; 2880 lsm6dsrx_sensor_hub_16_t sensor_hub_16; 2881 lsm6dsrx_sensor_hub_17_t sensor_hub_17; 2882 lsm6dsrx_sensor_hub_18_t sensor_hub_18; 2883 lsm6dsrx_master_config_t master_config; 2884 lsm6dsrx_slv0_add_t slv0_add; 2885 lsm6dsrx_slv0_subadd_t slv0_subadd; 2886 lsm6dsrx_slv0_config_t slv0_config; 2887 lsm6dsrx_slv1_add_t slv1_add; 2888 lsm6dsrx_slv1_subadd_t slv1_subadd; 2889 lsm6dsrx_slv1_config_t slv1_config; 2890 lsm6dsrx_slv2_add_t slv2_add; 2891 lsm6dsrx_slv2_subadd_t slv2_subadd; 2892 lsm6dsrx_slv2_config_t slv2_config; 2893 lsm6dsrx_slv3_add_t slv3_add; 2894 lsm6dsrx_slv3_subadd_t slv3_subadd; 2895 lsm6dsrx_slv3_config_t slv3_config; 2896 lsm6dsrx_datawrite_slv0_t datawrite_slv0; 2897 lsm6dsrx_status_master_t status_master; 2898 bitwise_t bitwise; 2899 uint8_t byte; 2900 } lsm6dsrx_reg_t; 2901 2902 /** 2903 * @} 2904 * 2905 */ 2906 2907 #ifndef __weak 2908 #define __weak __attribute__((weak)) 2909 #endif /* __weak */ 2910 2911 /* 2912 * These are the basic platform dependent I/O routines to read 2913 * and write device registers connected on a standard bus. 2914 * The driver keeps offering a default implementation based on function 2915 * pointers to read/write routines for backward compatibility. 2916 * The __weak directive allows the final application to overwrite 2917 * them with a custom implementation. 2918 */ 2919 int32_t lsm6dsrx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2920 uint8_t *data, 2921 uint16_t len); 2922 int32_t lsm6dsrx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2923 uint8_t *data, 2924 uint16_t len); 2925 2926 float_t lsm6dsrx_from_fs2g_to_mg(int16_t lsb); 2927 float_t lsm6dsrx_from_fs4g_to_mg(int16_t lsb); 2928 float_t lsm6dsrx_from_fs8g_to_mg(int16_t lsb); 2929 float_t lsm6dsrx_from_fs16g_to_mg(int16_t lsb); 2930 2931 float_t lsm6dsrx_from_fs125dps_to_mdps(int16_t lsb); 2932 float_t lsm6dsrx_from_fs250dps_to_mdps(int16_t lsb); 2933 float_t lsm6dsrx_from_fs500dps_to_mdps(int16_t lsb); 2934 float_t lsm6dsrx_from_fs1000dps_to_mdps(int16_t lsb); 2935 float_t lsm6dsrx_from_fs2000dps_to_mdps(int16_t lsb); 2936 float_t lsm6dsrx_from_fs4000dps_to_mdps(int16_t lsb); 2937 2938 float_t lsm6dsrx_from_lsb_to_celsius(int16_t lsb); 2939 2940 uint64_t lsm6dsrx_from_lsb_to_nsec(uint32_t lsb); 2941 2942 typedef enum 2943 { 2944 LSM6DSRX_2g = 0, 2945 LSM6DSRX_16g = 1, /* if XL_FS_MODE = '1' -> LSM6DSRX_2g */ 2946 LSM6DSRX_4g = 2, 2947 LSM6DSRX_8g = 3, 2948 } lsm6dsrx_fs_xl_t; 2949 int32_t lsm6dsrx_xl_full_scale_set(const stmdev_ctx_t *ctx, 2950 lsm6dsrx_fs_xl_t val); 2951 int32_t lsm6dsrx_xl_full_scale_get(const stmdev_ctx_t *ctx, 2952 lsm6dsrx_fs_xl_t *val); 2953 2954 typedef enum 2955 { 2956 LSM6DSRX_XL_ODR_OFF = 0, 2957 LSM6DSRX_XL_ODR_12Hz5 = 1, 2958 LSM6DSRX_XL_ODR_26Hz = 2, 2959 LSM6DSRX_XL_ODR_52Hz = 3, 2960 LSM6DSRX_XL_ODR_104Hz = 4, 2961 LSM6DSRX_XL_ODR_208Hz = 5, 2962 LSM6DSRX_XL_ODR_416Hz = 6, 2963 LSM6DSRX_XL_ODR_833Hz = 7, 2964 LSM6DSRX_XL_ODR_1666Hz = 8, 2965 LSM6DSRX_XL_ODR_3332Hz = 9, 2966 LSM6DSRX_XL_ODR_6667Hz = 10, 2967 LSM6DSRX_XL_ODR_1Hz6 = 11, /* (low power only) */ 2968 } lsm6dsrx_odr_xl_t; 2969 int32_t lsm6dsrx_xl_data_rate_set(const stmdev_ctx_t *ctx, 2970 lsm6dsrx_odr_xl_t val); 2971 int32_t lsm6dsrx_xl_data_rate_get(const stmdev_ctx_t *ctx, 2972 lsm6dsrx_odr_xl_t *val); 2973 2974 typedef enum 2975 { 2976 LSM6DSRX_125dps = 2, 2977 LSM6DSRX_250dps = 0, 2978 LSM6DSRX_500dps = 4, 2979 LSM6DSRX_1000dps = 8, 2980 LSM6DSRX_2000dps = 12, 2981 LSM6DSRX_4000dps = 1, 2982 } lsm6dsrx_fs_g_t; 2983 int32_t lsm6dsrx_gy_full_scale_set(const stmdev_ctx_t *ctx, 2984 lsm6dsrx_fs_g_t val); 2985 int32_t lsm6dsrx_gy_full_scale_get(const stmdev_ctx_t *ctx, 2986 lsm6dsrx_fs_g_t *val); 2987 2988 typedef enum 2989 { 2990 LSM6DSRX_GY_ODR_OFF = 0, 2991 LSM6DSRX_GY_ODR_12Hz5 = 1, 2992 LSM6DSRX_GY_ODR_26Hz = 2, 2993 LSM6DSRX_GY_ODR_52Hz = 3, 2994 LSM6DSRX_GY_ODR_104Hz = 4, 2995 LSM6DSRX_GY_ODR_208Hz = 5, 2996 LSM6DSRX_GY_ODR_416Hz = 6, 2997 LSM6DSRX_GY_ODR_833Hz = 7, 2998 LSM6DSRX_GY_ODR_1666Hz = 8, 2999 LSM6DSRX_GY_ODR_3332Hz = 9, 3000 LSM6DSRX_GY_ODR_6667Hz = 10, 3001 } lsm6dsrx_odr_g_t; 3002 int32_t lsm6dsrx_gy_data_rate_set(const stmdev_ctx_t *ctx, 3003 lsm6dsrx_odr_g_t val); 3004 int32_t lsm6dsrx_gy_data_rate_get(const stmdev_ctx_t *ctx, 3005 lsm6dsrx_odr_g_t *val); 3006 3007 int32_t lsm6dsrx_block_data_update_set(const stmdev_ctx_t *ctx, 3008 uint8_t val); 3009 int32_t lsm6dsrx_block_data_update_get(const stmdev_ctx_t *ctx, 3010 uint8_t *val); 3011 3012 typedef enum 3013 { 3014 LSM6DSRX_LSb_1mg = 0, 3015 LSM6DSRX_LSb_16mg = 1, 3016 } lsm6dsrx_usr_off_w_t; 3017 int32_t lsm6dsrx_xl_offset_weight_set(const stmdev_ctx_t *ctx, 3018 lsm6dsrx_usr_off_w_t val); 3019 int32_t lsm6dsrx_xl_offset_weight_get(const stmdev_ctx_t *ctx, 3020 lsm6dsrx_usr_off_w_t *val); 3021 3022 typedef enum 3023 { 3024 LSM6DSRX_HIGH_PERFORMANCE_MD = 0, 3025 LSM6DSRX_LOW_NORMAL_POWER_MD = 1, 3026 } lsm6dsrx_xl_hm_mode_t; 3027 int32_t lsm6dsrx_xl_power_mode_set(const stmdev_ctx_t *ctx, 3028 lsm6dsrx_xl_hm_mode_t val); 3029 int32_t lsm6dsrx_xl_power_mode_get(const stmdev_ctx_t *ctx, 3030 lsm6dsrx_xl_hm_mode_t *val); 3031 3032 typedef enum 3033 { 3034 LSM6DSRX_GY_HIGH_PERFORMANCE = 0, 3035 LSM6DSRX_GY_NORMAL = 1, 3036 } lsm6dsrx_g_hm_mode_t; 3037 int32_t lsm6dsrx_gy_power_mode_set(const stmdev_ctx_t *ctx, 3038 lsm6dsrx_g_hm_mode_t val); 3039 int32_t lsm6dsrx_gy_power_mode_get(const stmdev_ctx_t *ctx, 3040 lsm6dsrx_g_hm_mode_t *val); 3041 3042 typedef struct 3043 { 3044 lsm6dsrx_all_int_src_t all_int_src; 3045 lsm6dsrx_wake_up_src_t wake_up_src; 3046 lsm6dsrx_tap_src_t tap_src; 3047 lsm6dsrx_d6d_src_t d6d_src; 3048 lsm6dsrx_status_reg_t status_reg; 3049 lsm6dsrx_emb_func_status_t emb_func_status; 3050 lsm6dsrx_fsm_status_a_t fsm_status_a; 3051 lsm6dsrx_fsm_status_b_t fsm_status_b; 3052 lsm6dsrx_mlc_status_mainpage_t mlc_status; 3053 } lsm6dsrx_all_sources_t; 3054 int32_t lsm6dsrx_all_sources_get(const stmdev_ctx_t *ctx, 3055 lsm6dsrx_all_sources_t *val); 3056 3057 int32_t lsm6dsrx_status_reg_get(const stmdev_ctx_t *ctx, 3058 lsm6dsrx_status_reg_t *val); 3059 3060 int32_t lsm6dsrx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 3061 uint8_t *val); 3062 3063 int32_t lsm6dsrx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 3064 uint8_t *val); 3065 3066 int32_t lsm6dsrx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 3067 uint8_t *val); 3068 3069 int32_t lsm6dsrx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, 3070 uint8_t *val); 3071 int32_t lsm6dsrx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, 3072 uint8_t *val); 3073 3074 int32_t lsm6dsrx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, 3075 uint8_t *val); 3076 int32_t lsm6dsrx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, 3077 uint8_t *val); 3078 3079 int32_t lsm6dsrx_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, 3080 uint8_t *val); 3081 int32_t lsm6dsrx_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, 3082 uint8_t *val); 3083 3084 int32_t lsm6dsrx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); 3085 int32_t lsm6dsrx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); 3086 3087 int32_t lsm6dsrx_timestamp_rst(const stmdev_ctx_t *ctx); 3088 3089 int32_t lsm6dsrx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 3090 int32_t lsm6dsrx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 3091 3092 int32_t lsm6dsrx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 3093 3094 typedef enum 3095 { 3096 LSM6DSRX_NO_ROUND = 0, 3097 LSM6DSRX_ROUND_XL = 1, 3098 LSM6DSRX_ROUND_GY = 2, 3099 LSM6DSRX_ROUND_GY_XL = 3, 3100 } lsm6dsrx_rounding_t; 3101 int32_t lsm6dsrx_rounding_mode_set(const stmdev_ctx_t *ctx, 3102 lsm6dsrx_rounding_t val); 3103 int32_t lsm6dsrx_rounding_mode_get(const stmdev_ctx_t *ctx, 3104 lsm6dsrx_rounding_t *val); 3105 3106 int32_t lsm6dsrx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 3107 3108 int32_t lsm6dsrx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 3109 3110 int32_t lsm6dsrx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 3111 3112 int32_t lsm6dsrx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); 3113 3114 int32_t lsm6dsrx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *val); 3115 3116 int32_t lsm6dsrx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); 3117 int32_t lsm6dsrx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); 3118 3119 int32_t lsm6dsrx_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); 3120 3121 int32_t lsm6dsrx_steps_reset(const stmdev_ctx_t *ctx); 3122 3123 typedef enum 3124 { 3125 LSM6DSRX_USER_BANK = 0, 3126 LSM6DSRX_SENSOR_HUB_BANK = 1, 3127 LSM6DSRX_EMBEDDED_FUNC_BANK = 2, 3128 } lsm6dsrx_reg_access_t; 3129 int32_t lsm6dsrx_mem_bank_set(const stmdev_ctx_t *ctx, 3130 lsm6dsrx_reg_access_t val); 3131 int32_t lsm6dsrx_mem_bank_get(const stmdev_ctx_t *ctx, 3132 lsm6dsrx_reg_access_t *val); 3133 3134 int32_t lsm6dsrx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, 3135 uint8_t *val); 3136 int32_t lsm6dsrx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, 3137 uint8_t *buf, uint8_t len); 3138 int32_t lsm6dsrx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, 3139 uint8_t *val); 3140 int32_t lsm6dsrx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, 3141 uint8_t *val); 3142 3143 typedef enum 3144 { 3145 LSM6DSRX_DRDY_LATCHED = 0, 3146 LSM6DSRX_DRDY_PULSED = 1, 3147 } lsm6dsrx_dataready_pulsed_t; 3148 int32_t lsm6dsrx_data_ready_mode_set(const stmdev_ctx_t *ctx, 3149 lsm6dsrx_dataready_pulsed_t val); 3150 int32_t lsm6dsrx_data_ready_mode_get(const stmdev_ctx_t *ctx, 3151 lsm6dsrx_dataready_pulsed_t *val); 3152 3153 int32_t lsm6dsrx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); 3154 3155 int32_t lsm6dsrx_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 3156 int32_t lsm6dsrx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 3157 3158 int32_t lsm6dsrx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 3159 int32_t lsm6dsrx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 3160 3161 int32_t lsm6dsrx_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 3162 int32_t lsm6dsrx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 3163 3164 typedef enum 3165 { 3166 LSM6DSRX_XL_ST_DISABLE = 0, 3167 LSM6DSRX_XL_ST_POSITIVE = 1, 3168 LSM6DSRX_XL_ST_NEGATIVE = 2, 3169 } lsm6dsrx_st_xl_t; 3170 int32_t lsm6dsrx_xl_self_test_set(const stmdev_ctx_t *ctx, 3171 lsm6dsrx_st_xl_t val); 3172 int32_t lsm6dsrx_xl_self_test_get(const stmdev_ctx_t *ctx, 3173 lsm6dsrx_st_xl_t *val); 3174 3175 typedef enum 3176 { 3177 LSM6DSRX_GY_ST_DISABLE = 0, 3178 LSM6DSRX_GY_ST_POSITIVE = 1, 3179 LSM6DSRX_GY_ST_NEGATIVE = 3, 3180 } lsm6dsrx_st_g_t; 3181 int32_t lsm6dsrx_gy_self_test_set(const stmdev_ctx_t *ctx, 3182 lsm6dsrx_st_g_t val); 3183 int32_t lsm6dsrx_gy_self_test_get(const stmdev_ctx_t *ctx, 3184 lsm6dsrx_st_g_t *val); 3185 3186 int32_t lsm6dsrx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); 3187 int32_t lsm6dsrx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); 3188 3189 int32_t lsm6dsrx_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); 3190 int32_t lsm6dsrx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); 3191 3192 int32_t lsm6dsrx_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); 3193 int32_t lsm6dsrx_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); 3194 3195 typedef enum 3196 { 3197 LSM6DSRX_ULTRA_LIGHT = 0, 3198 LSM6DSRX_VERY_LIGHT = 1, 3199 LSM6DSRX_LIGHT = 2, 3200 LSM6DSRX_MEDIUM = 3, 3201 LSM6DSRX_STRONG = 4, 3202 LSM6DSRX_VERY_STRONG = 5, 3203 LSM6DSRX_AGGRESSIVE = 6, 3204 LSM6DSRX_XTREME = 7, 3205 } lsm6dsrx_ftype_t; 3206 int32_t lsm6dsrx_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 3207 lsm6dsrx_ftype_t val); 3208 int32_t lsm6dsrx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 3209 lsm6dsrx_ftype_t *val); 3210 3211 int32_t lsm6dsrx_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); 3212 int32_t lsm6dsrx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); 3213 3214 typedef enum 3215 { 3216 LSM6DSRX_HP_PATH_DISABLE_ON_OUT = 0x00, 3217 LSM6DSRX_SLOPE_ODR_DIV_4 = 0x10, 3218 LSM6DSRX_HP_ODR_DIV_10 = 0x11, 3219 LSM6DSRX_HP_ODR_DIV_20 = 0x12, 3220 LSM6DSRX_HP_ODR_DIV_45 = 0x13, 3221 LSM6DSRX_HP_ODR_DIV_100 = 0x14, 3222 LSM6DSRX_HP_ODR_DIV_200 = 0x15, 3223 LSM6DSRX_HP_ODR_DIV_400 = 0x16, 3224 LSM6DSRX_HP_ODR_DIV_800 = 0x17, 3225 LSM6DSRX_HP_REF_MD_ODR_DIV_10 = 0x31, 3226 LSM6DSRX_HP_REF_MD_ODR_DIV_20 = 0x32, 3227 LSM6DSRX_HP_REF_MD_ODR_DIV_45 = 0x33, 3228 LSM6DSRX_HP_REF_MD_ODR_DIV_100 = 0x34, 3229 LSM6DSRX_HP_REF_MD_ODR_DIV_200 = 0x35, 3230 LSM6DSRX_HP_REF_MD_ODR_DIV_400 = 0x36, 3231 LSM6DSRX_HP_REF_MD_ODR_DIV_800 = 0x37, 3232 LSM6DSRX_LP_ODR_DIV_10 = 0x01, 3233 LSM6DSRX_LP_ODR_DIV_20 = 0x02, 3234 LSM6DSRX_LP_ODR_DIV_45 = 0x03, 3235 LSM6DSRX_LP_ODR_DIV_100 = 0x04, 3236 LSM6DSRX_LP_ODR_DIV_200 = 0x05, 3237 LSM6DSRX_LP_ODR_DIV_400 = 0x06, 3238 LSM6DSRX_LP_ODR_DIV_800 = 0x07, 3239 } lsm6dsrx_hp_slope_xl_en_t; 3240 int32_t lsm6dsrx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, 3241 lsm6dsrx_hp_slope_xl_en_t val); 3242 int32_t lsm6dsrx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, 3243 lsm6dsrx_hp_slope_xl_en_t *val); 3244 3245 int32_t lsm6dsrx_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); 3246 int32_t lsm6dsrx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); 3247 3248 typedef enum 3249 { 3250 LSM6DSRX_USE_SLOPE = 0, 3251 LSM6DSRX_USE_HPF = 1, 3252 } lsm6dsrx_slope_fds_t; 3253 int32_t lsm6dsrx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, 3254 lsm6dsrx_slope_fds_t val); 3255 int32_t lsm6dsrx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, 3256 lsm6dsrx_slope_fds_t *val); 3257 3258 typedef enum 3259 { 3260 LSM6DSRX_HP_FILTER_NONE = 0x00, 3261 LSM6DSRX_HP_FILTER_16mHz = 0x80, 3262 LSM6DSRX_HP_FILTER_65mHz = 0x81, 3263 LSM6DSRX_HP_FILTER_260mHz = 0x82, 3264 LSM6DSRX_HP_FILTER_1Hz04 = 0x83, 3265 } lsm6dsrx_hpm_g_t; 3266 int32_t lsm6dsrx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, 3267 lsm6dsrx_hpm_g_t val); 3268 int32_t lsm6dsrx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, 3269 lsm6dsrx_hpm_g_t *val); 3270 3271 typedef enum 3272 { 3273 LSM6DSRX_AUX_PULL_UP_DISC = 0, 3274 LSM6DSRX_AUX_PULL_UP_CONNECT = 1, 3275 } lsm6dsrx_ois_pu_dis_t; 3276 int32_t lsm6dsrx_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, 3277 lsm6dsrx_ois_pu_dis_t val); 3278 int32_t lsm6dsrx_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, 3279 lsm6dsrx_ois_pu_dis_t *val); 3280 3281 typedef enum 3282 { 3283 LSM6DSRX_AUX_ON = 1, 3284 LSM6DSRX_AUX_ON_BY_AUX_INTERFACE = 0, 3285 } lsm6dsrx_ois_on_t; 3286 int32_t lsm6dsrx_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, 3287 lsm6dsrx_ois_on_t val); 3288 int32_t lsm6dsrx_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, 3289 lsm6dsrx_ois_on_t *val); 3290 3291 int32_t lsm6dsrx_aux_status_reg_get(const stmdev_ctx_t *ctx, 3292 lsm6dsrx_status_spiaux_t *val); 3293 3294 int32_t lsm6dsrx_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 3295 uint8_t *val); 3296 3297 int32_t lsm6dsrx_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 3298 uint8_t *val); 3299 3300 int32_t lsm6dsrx_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, 3301 uint8_t *val); 3302 3303 typedef enum 3304 { 3305 LSM6DSRX_AUX_XL_DISABLE = 0, 3306 LSM6DSRX_AUX_XL_POS = 1, 3307 LSM6DSRX_AUX_XL_NEG = 2, 3308 } lsm6dsrx_st_xl_ois_t; 3309 int32_t lsm6dsrx_aux_xl_self_test_set(const stmdev_ctx_t *ctx, 3310 lsm6dsrx_st_xl_ois_t val); 3311 int32_t lsm6dsrx_aux_xl_self_test_get(const stmdev_ctx_t *ctx, 3312 lsm6dsrx_st_xl_ois_t *val); 3313 3314 typedef enum 3315 { 3316 LSM6DSRX_AUX_DEN_ACTIVE_LOW = 0, 3317 LSM6DSRX_AUX_DEN_ACTIVE_HIGH = 1, 3318 } lsm6dsrx_den_lh_ois_t; 3319 int32_t lsm6dsrx_aux_den_polarity_set(const stmdev_ctx_t *ctx, 3320 lsm6dsrx_den_lh_ois_t val); 3321 int32_t lsm6dsrx_aux_den_polarity_get(const stmdev_ctx_t *ctx, 3322 lsm6dsrx_den_lh_ois_t *val); 3323 3324 typedef enum 3325 { 3326 LSM6DSRX_AUX_DEN_DISABLE = 0, 3327 LSM6DSRX_AUX_DEN_LEVEL_LATCH = 3, 3328 LSM6DSRX_AUX_DEN_LEVEL_TRIG = 2, 3329 } lsm6dsrx_lvl2_ois_t; 3330 int32_t lsm6dsrx_aux_den_mode_set(const stmdev_ctx_t *ctx, 3331 lsm6dsrx_lvl2_ois_t val); 3332 int32_t lsm6dsrx_aux_den_mode_get(const stmdev_ctx_t *ctx, 3333 lsm6dsrx_lvl2_ois_t *val); 3334 3335 int32_t lsm6dsrx_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); 3336 int32_t lsm6dsrx_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); 3337 3338 typedef enum 3339 { 3340 LSM6DSRX_AUX_DISABLE = 0, 3341 LSM6DSRX_MODE_3_GY = 1, 3342 LSM6DSRX_MODE_4_GY_XL = 3, 3343 } lsm6dsrx_ois_en_spi2_t; 3344 int32_t lsm6dsrx_aux_mode_set(const stmdev_ctx_t *ctx, 3345 lsm6dsrx_ois_en_spi2_t val); 3346 int32_t lsm6dsrx_aux_mode_get(const stmdev_ctx_t *ctx, 3347 lsm6dsrx_ois_en_spi2_t *val); 3348 3349 typedef enum 3350 { 3351 LSM6DSRX_125dps_AUX = 0x04, 3352 LSM6DSRX_250dps_AUX = 0x00, 3353 LSM6DSRX_500dps_AUX = 0x01, 3354 LSM6DSRX_1000dps_AUX = 0x02, 3355 LSM6DSRX_2000dps_AUX = 0x03, 3356 } lsm6dsrx_fs_g_ois_t; 3357 int32_t lsm6dsrx_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, 3358 lsm6dsrx_fs_g_ois_t val); 3359 int32_t lsm6dsrx_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, 3360 lsm6dsrx_fs_g_ois_t *val); 3361 3362 typedef enum 3363 { 3364 LSM6DSRX_AUX_SPI_4_WIRE = 0, 3365 LSM6DSRX_AUX_SPI_3_WIRE = 1, 3366 } lsm6dsrx_sim_ois_t; 3367 int32_t lsm6dsrx_aux_spi_mode_set(const stmdev_ctx_t *ctx, 3368 lsm6dsrx_sim_ois_t val); 3369 int32_t lsm6dsrx_aux_spi_mode_get(const stmdev_ctx_t *ctx, 3370 lsm6dsrx_sim_ois_t *val); 3371 3372 typedef enum 3373 { 3374 LSM6DSRX_351Hz39 = 0, 3375 LSM6DSRX_236Hz63 = 1, 3376 LSM6DSRX_172Hz70 = 2, 3377 LSM6DSRX_937Hz91 = 3, 3378 } lsm6dsrx_ftype_ois_t; 3379 int32_t lsm6dsrx_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 3380 lsm6dsrx_ftype_ois_t val); 3381 int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 3382 lsm6dsrx_ftype_ois_t *val); 3383 3384 typedef enum 3385 { 3386 LSM6DSRX_AUX_HP_DISABLE = 0x00, 3387 LSM6DSRX_AUX_HP_Hz016 = 0x10, 3388 LSM6DSRX_AUX_HP_Hz065 = 0x11, 3389 LSM6DSRX_AUX_HP_Hz260 = 0x12, 3390 LSM6DSRX_AUX_HP_1Hz040 = 0x13, 3391 } lsm6dsrx_hpm_ois_t; 3392 int32_t lsm6dsrx_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, 3393 lsm6dsrx_hpm_ois_t val); 3394 int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, 3395 lsm6dsrx_hpm_ois_t *val); 3396 3397 typedef enum 3398 { 3399 LSM6DSRX_ENABLE_CLAMP = 0, 3400 LSM6DSRX_DISABLE_CLAMP = 1, 3401 } lsm6dsrx_st_ois_clampdis_t; 3402 int32_t lsm6dsrx_aux_gy_clamp_set(const stmdev_ctx_t *ctx, 3403 lsm6dsrx_st_ois_clampdis_t val); 3404 int32_t lsm6dsrx_aux_gy_clamp_get(const stmdev_ctx_t *ctx, 3405 lsm6dsrx_st_ois_clampdis_t *val); 3406 3407 typedef enum 3408 { 3409 LSM6DSRX_AUX_GY_DISABLE = 0, 3410 LSM6DSRX_AUX_GY_POS = 1, 3411 LSM6DSRX_AUX_GY_NEG = 3, 3412 } lsm6dsrx_st_ois_t; 3413 int32_t lsm6dsrx_aux_gy_self_test_set(const stmdev_ctx_t *ctx, 3414 lsm6dsrx_st_ois_t val); 3415 int32_t lsm6dsrx_aux_gy_self_test_get(const stmdev_ctx_t *ctx, 3416 lsm6dsrx_st_ois_t *val); 3417 3418 typedef enum 3419 { 3420 LSM6DSRX_631Hz = 0, 3421 LSM6DSRX_295Hz = 1, 3422 LSM6DSRX_140Hz = 2, 3423 LSM6DSRX_68Hz2 = 3, 3424 LSM6DSRX_33Hz6 = 4, 3425 LSM6DSRX_16Hz7 = 5, 3426 LSM6DSRX_8Hz3 = 6, 3427 LSM6DSRX_4Hz11 = 7, 3428 } lsm6dsrx_filter_xl_conf_ois_t; 3429 int32_t lsm6dsrx_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, 3430 lsm6dsrx_filter_xl_conf_ois_t val); 3431 int32_t lsm6dsrx_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, 3432 lsm6dsrx_filter_xl_conf_ois_t *val); 3433 3434 typedef enum 3435 { 3436 LSM6DSRX_AUX_2g = 0, 3437 LSM6DSRX_AUX_16g = 1, 3438 LSM6DSRX_AUX_4g = 2, 3439 LSM6DSRX_AUX_8g = 3, 3440 } lsm6dsrx_fs_xl_ois_t; 3441 int32_t lsm6dsrx_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, 3442 lsm6dsrx_fs_xl_ois_t val); 3443 int32_t lsm6dsrx_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, 3444 lsm6dsrx_fs_xl_ois_t *val); 3445 3446 typedef enum 3447 { 3448 LSM6DSRX_PULL_UP_DISC = 0, 3449 LSM6DSRX_PULL_UP_CONNECT = 1, 3450 } lsm6dsrx_sdo_pu_en_t; 3451 int32_t lsm6dsrx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 3452 lsm6dsrx_sdo_pu_en_t val); 3453 int32_t lsm6dsrx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 3454 lsm6dsrx_sdo_pu_en_t *val); 3455 3456 typedef enum 3457 { 3458 LSM6DSRX_PULL_DOWN_CONNECT = 0, 3459 LSM6DSRX_PULL_DOWN_DISC = 1, 3460 } lsm6dsrx_pd_dis_int1_t; 3461 int32_t lsm6dsrx_int1_mode_set(const stmdev_ctx_t *ctx, 3462 lsm6dsrx_pd_dis_int1_t val); 3463 int32_t lsm6dsrx_int1_mode_get(const stmdev_ctx_t *ctx, 3464 lsm6dsrx_pd_dis_int1_t *val); 3465 3466 typedef enum 3467 { 3468 LSM6DSRX_SPI_4_WIRE = 0, 3469 LSM6DSRX_SPI_3_WIRE = 1, 3470 } lsm6dsrx_sim_t; 3471 int32_t lsm6dsrx_spi_mode_set(const stmdev_ctx_t *ctx, 3472 lsm6dsrx_sim_t val); 3473 int32_t lsm6dsrx_spi_mode_get(const stmdev_ctx_t *ctx, 3474 lsm6dsrx_sim_t *val); 3475 3476 typedef enum 3477 { 3478 LSM6DSRX_I2C_ENABLE = 0, 3479 LSM6DSRX_I2C_DISABLE = 1, 3480 } lsm6dsrx_i2c_disable_t; 3481 int32_t lsm6dsrx_i2c_interface_set(const stmdev_ctx_t *ctx, 3482 lsm6dsrx_i2c_disable_t val); 3483 int32_t lsm6dsrx_i2c_interface_get(const stmdev_ctx_t *ctx, 3484 lsm6dsrx_i2c_disable_t *val); 3485 3486 typedef enum 3487 { 3488 LSM6DSRX_I3C_DISABLE = 0x80, 3489 LSM6DSRX_I3C_ENABLE_T_50us = 0x00, 3490 LSM6DSRX_I3C_ENABLE_T_2us = 0x01, 3491 LSM6DSRX_I3C_ENABLE_T_1ms = 0x02, 3492 LSM6DSRX_I3C_ENABLE_T_25ms = 0x03, 3493 } lsm6dsrx_i3c_disable_t; 3494 int32_t lsm6dsrx_i3c_disable_set(const stmdev_ctx_t *ctx, 3495 lsm6dsrx_i3c_disable_t val); 3496 int32_t lsm6dsrx_i3c_disable_get(const stmdev_ctx_t *ctx, 3497 lsm6dsrx_i3c_disable_t *val); 3498 3499 typedef struct 3500 { 3501 lsm6dsrx_int1_ctrl_t int1_ctrl; 3502 lsm6dsrx_md1_cfg_t md1_cfg; 3503 lsm6dsrx_emb_func_int1_t emb_func_int1; 3504 lsm6dsrx_fsm_int1_a_t fsm_int1_a; 3505 lsm6dsrx_fsm_int1_b_t fsm_int1_b; 3506 lsm6dsrx_mlc_int1_t mlc_int1; 3507 } lsm6dsrx_pin_int1_route_t; 3508 int32_t lsm6dsrx_pin_int1_route_set(const stmdev_ctx_t *ctx, 3509 lsm6dsrx_pin_int1_route_t *val); 3510 int32_t lsm6dsrx_pin_int1_route_get(const stmdev_ctx_t *ctx, 3511 lsm6dsrx_pin_int1_route_t *val); 3512 3513 typedef struct 3514 { 3515 lsm6dsrx_int2_ctrl_t int2_ctrl; 3516 lsm6dsrx_md2_cfg_t md2_cfg; 3517 lsm6dsrx_emb_func_int2_t emb_func_int2; 3518 lsm6dsrx_fsm_int2_a_t fsm_int2_a; 3519 lsm6dsrx_fsm_int2_b_t fsm_int2_b; 3520 lsm6dsrx_mlc_int2_t mlc_int2; 3521 } lsm6dsrx_pin_int2_route_t; 3522 int32_t lsm6dsrx_pin_int2_route_set(const stmdev_ctx_t *ctx, 3523 lsm6dsrx_pin_int2_route_t *val); 3524 int32_t lsm6dsrx_pin_int2_route_get(const stmdev_ctx_t *ctx, 3525 lsm6dsrx_pin_int2_route_t *val); 3526 3527 typedef enum 3528 { 3529 LSM6DSRX_PUSH_PULL = 0, 3530 LSM6DSRX_OPEN_DRAIN = 1, 3531 } lsm6dsrx_pp_od_t; 3532 int32_t lsm6dsrx_pin_mode_set(const stmdev_ctx_t *ctx, 3533 lsm6dsrx_pp_od_t val); 3534 int32_t lsm6dsrx_pin_mode_get(const stmdev_ctx_t *ctx, 3535 lsm6dsrx_pp_od_t *val); 3536 3537 typedef enum 3538 { 3539 LSM6DSRX_ACTIVE_HIGH = 0, 3540 LSM6DSRX_ACTIVE_LOW = 1, 3541 } lsm6dsrx_h_lactive_t; 3542 int32_t lsm6dsrx_pin_polarity_set(const stmdev_ctx_t *ctx, 3543 lsm6dsrx_h_lactive_t val); 3544 int32_t lsm6dsrx_pin_polarity_get(const stmdev_ctx_t *ctx, 3545 lsm6dsrx_h_lactive_t *val); 3546 3547 int32_t lsm6dsrx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 3548 int32_t lsm6dsrx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 3549 3550 typedef enum 3551 { 3552 LSM6DSRX_ALL_INT_PULSED = 0, 3553 LSM6DSRX_BASE_LATCHED_EMB_PULSED = 1, 3554 LSM6DSRX_BASE_PULSED_EMB_LATCHED = 2, 3555 LSM6DSRX_ALL_INT_LATCHED = 3, 3556 } lsm6dsrx_lir_t; 3557 int32_t lsm6dsrx_int_notification_set(const stmdev_ctx_t *ctx, 3558 lsm6dsrx_lir_t val); 3559 int32_t lsm6dsrx_int_notification_get(const stmdev_ctx_t *ctx, 3560 lsm6dsrx_lir_t *val); 3561 3562 typedef enum 3563 { 3564 LSM6DSRX_LSb_FS_DIV_64 = 0, 3565 LSM6DSRX_LSb_FS_DIV_256 = 1, 3566 } lsm6dsrx_wake_ths_w_t; 3567 int32_t lsm6dsrx_wkup_ths_weight_set(const stmdev_ctx_t *ctx, 3568 lsm6dsrx_wake_ths_w_t val); 3569 int32_t lsm6dsrx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, 3570 lsm6dsrx_wake_ths_w_t *val); 3571 3572 int32_t lsm6dsrx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 3573 int32_t lsm6dsrx_wkup_threshold_get(const stmdev_ctx_t *ctx, 3574 uint8_t *val); 3575 3576 int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, 3577 uint8_t val); 3578 int32_t lsm6dsrx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, 3579 uint8_t *val); 3580 3581 int32_t lsm6dsrx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3582 int32_t lsm6dsrx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3583 3584 int32_t lsm6dsrx_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3585 int32_t lsm6dsrx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3586 3587 typedef enum 3588 { 3589 LSM6DSRX_DRIVE_SLEEP_CHG_EVENT = 0, 3590 LSM6DSRX_DRIVE_SLEEP_STATUS = 1, 3591 } lsm6dsrx_sleep_status_on_int_t; 3592 int32_t lsm6dsrx_act_pin_notification_set(const stmdev_ctx_t *ctx, 3593 lsm6dsrx_sleep_status_on_int_t val); 3594 int32_t lsm6dsrx_act_pin_notification_get(const stmdev_ctx_t *ctx, 3595 lsm6dsrx_sleep_status_on_int_t *val); 3596 3597 typedef enum 3598 { 3599 LSM6DSRX_XL_AND_GY_NOT_AFFECTED = 0, 3600 LSM6DSRX_XL_12Hz5_GY_NOT_AFFECTED = 1, 3601 LSM6DSRX_XL_12Hz5_GY_SLEEP = 2, 3602 LSM6DSRX_XL_12Hz5_GY_PD = 3, 3603 } lsm6dsrx_inact_en_t; 3604 int32_t lsm6dsrx_act_mode_set(const stmdev_ctx_t *ctx, 3605 lsm6dsrx_inact_en_t val); 3606 int32_t lsm6dsrx_act_mode_get(const stmdev_ctx_t *ctx, 3607 lsm6dsrx_inact_en_t *val); 3608 3609 int32_t lsm6dsrx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3610 int32_t lsm6dsrx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3611 3612 int32_t lsm6dsrx_tap_detection_on_z_set(const stmdev_ctx_t *ctx, 3613 uint8_t val); 3614 int32_t lsm6dsrx_tap_detection_on_z_get(const stmdev_ctx_t *ctx, 3615 uint8_t *val); 3616 3617 int32_t lsm6dsrx_tap_detection_on_y_set(const stmdev_ctx_t *ctx, 3618 uint8_t val); 3619 int32_t lsm6dsrx_tap_detection_on_y_get(const stmdev_ctx_t *ctx, 3620 uint8_t *val); 3621 3622 int32_t lsm6dsrx_tap_detection_on_x_set(const stmdev_ctx_t *ctx, 3623 uint8_t val); 3624 int32_t lsm6dsrx_tap_detection_on_x_get(const stmdev_ctx_t *ctx, 3625 uint8_t *val); 3626 3627 int32_t lsm6dsrx_tap_threshold_x_set(const stmdev_ctx_t *ctx, 3628 uint8_t val); 3629 int32_t lsm6dsrx_tap_threshold_x_get(const stmdev_ctx_t *ctx, 3630 uint8_t *val); 3631 3632 typedef enum 3633 { 3634 LSM6DSRX_XYZ = 0, 3635 LSM6DSRX_YXZ = 1, 3636 LSM6DSRX_XZY = 2, 3637 LSM6DSRX_ZYX = 3, 3638 LSM6DSRX_YZX = 5, 3639 LSM6DSRX_ZXY = 6, 3640 } lsm6dsrx_tap_priority_t; 3641 int32_t lsm6dsrx_tap_axis_priority_set(const stmdev_ctx_t *ctx, 3642 lsm6dsrx_tap_priority_t val); 3643 int32_t lsm6dsrx_tap_axis_priority_get(const stmdev_ctx_t *ctx, 3644 lsm6dsrx_tap_priority_t *val); 3645 3646 int32_t lsm6dsrx_tap_threshold_y_set(const stmdev_ctx_t *ctx, 3647 uint8_t val); 3648 int32_t lsm6dsrx_tap_threshold_y_get(const stmdev_ctx_t *ctx, 3649 uint8_t *val); 3650 3651 int32_t lsm6dsrx_tap_threshold_z_set(const stmdev_ctx_t *ctx, 3652 uint8_t val); 3653 int32_t lsm6dsrx_tap_threshold_z_get(const stmdev_ctx_t *ctx, 3654 uint8_t *val); 3655 3656 int32_t lsm6dsrx_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); 3657 int32_t lsm6dsrx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); 3658 3659 int32_t lsm6dsrx_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); 3660 int32_t lsm6dsrx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); 3661 3662 int32_t lsm6dsrx_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3663 int32_t lsm6dsrx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3664 3665 typedef enum 3666 { 3667 LSM6DSRX_ONLY_SINGLE = 0, 3668 LSM6DSRX_BOTH_SINGLE_DOUBLE = 1, 3669 } lsm6dsrx_single_double_tap_t; 3670 int32_t lsm6dsrx_tap_mode_set(const stmdev_ctx_t *ctx, 3671 lsm6dsrx_single_double_tap_t val); 3672 int32_t lsm6dsrx_tap_mode_get(const stmdev_ctx_t *ctx, 3673 lsm6dsrx_single_double_tap_t *val); 3674 3675 typedef enum 3676 { 3677 LSM6DSRX_DEG_80 = 0, 3678 LSM6DSRX_DEG_70 = 1, 3679 LSM6DSRX_DEG_60 = 2, 3680 LSM6DSRX_DEG_50 = 3, 3681 } lsm6dsrx_sixd_ths_t; 3682 int32_t lsm6dsrx_6d_threshold_set(const stmdev_ctx_t *ctx, 3683 lsm6dsrx_sixd_ths_t val); 3684 int32_t lsm6dsrx_6d_threshold_get(const stmdev_ctx_t *ctx, 3685 lsm6dsrx_sixd_ths_t *val); 3686 3687 int32_t lsm6dsrx_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3688 int32_t lsm6dsrx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3689 3690 typedef enum 3691 { 3692 LSM6DSRX_FF_TSH_156mg = 0, 3693 LSM6DSRX_FF_TSH_219mg = 1, 3694 LSM6DSRX_FF_TSH_250mg = 2, 3695 LSM6DSRX_FF_TSH_312mg = 3, 3696 LSM6DSRX_FF_TSH_344mg = 4, 3697 LSM6DSRX_FF_TSH_406mg = 5, 3698 LSM6DSRX_FF_TSH_469mg = 6, 3699 LSM6DSRX_FF_TSH_500mg = 7, 3700 } lsm6dsrx_ff_ths_t; 3701 int32_t lsm6dsrx_ff_threshold_set(const stmdev_ctx_t *ctx, 3702 lsm6dsrx_ff_ths_t val); 3703 int32_t lsm6dsrx_ff_threshold_get(const stmdev_ctx_t *ctx, 3704 lsm6dsrx_ff_ths_t *val); 3705 3706 int32_t lsm6dsrx_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3707 int32_t lsm6dsrx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3708 3709 int32_t lsm6dsrx_fifo_watermark_set(const stmdev_ctx_t *ctx, 3710 uint16_t val); 3711 int32_t lsm6dsrx_fifo_watermark_get(const stmdev_ctx_t *ctx, 3712 uint16_t *val); 3713 3714 int32_t lsm6dsrx_compression_algo_init_set(const stmdev_ctx_t *ctx, 3715 uint8_t val); 3716 int32_t lsm6dsrx_compression_algo_init_get(const stmdev_ctx_t *ctx, 3717 uint8_t *val); 3718 3719 typedef enum 3720 { 3721 LSM6DSRX_CMP_DISABLE = 0x00, 3722 LSM6DSRX_CMP_ALWAYS = 0x04, 3723 LSM6DSRX_CMP_8_TO_1 = 0x05, 3724 LSM6DSRX_CMP_16_TO_1 = 0x06, 3725 LSM6DSRX_CMP_32_TO_1 = 0x07, 3726 } lsm6dsrx_uncoptr_rate_t; 3727 int32_t lsm6dsrx_compression_algo_set(const stmdev_ctx_t *ctx, 3728 lsm6dsrx_uncoptr_rate_t val); 3729 int32_t lsm6dsrx_compression_algo_get(const stmdev_ctx_t *ctx, 3730 lsm6dsrx_uncoptr_rate_t *val); 3731 3732 int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, 3733 uint8_t val); 3734 int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, 3735 uint8_t *val); 3736 3737 int32_t lsm6dsrx_compression_algo_real_time_set(const stmdev_ctx_t *ctx, 3738 uint8_t val); 3739 int32_t lsm6dsrx_compression_algo_real_time_get(const stmdev_ctx_t *ctx, 3740 uint8_t *val); 3741 3742 int32_t lsm6dsrx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, 3743 uint8_t val); 3744 int32_t lsm6dsrx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, 3745 uint8_t *val); 3746 3747 typedef enum 3748 { 3749 LSM6DSRX_XL_NOT_BATCHED = 0, 3750 LSM6DSRX_XL_BATCHED_AT_12Hz5 = 1, 3751 LSM6DSRX_XL_BATCHED_AT_26Hz = 2, 3752 LSM6DSRX_XL_BATCHED_AT_52Hz = 3, 3753 LSM6DSRX_XL_BATCHED_AT_104Hz = 4, 3754 LSM6DSRX_XL_BATCHED_AT_208Hz = 5, 3755 LSM6DSRX_XL_BATCHED_AT_417Hz = 6, 3756 LSM6DSRX_XL_BATCHED_AT_833Hz = 7, 3757 LSM6DSRX_XL_BATCHED_AT_1667Hz = 8, 3758 LSM6DSRX_XL_BATCHED_AT_3333Hz = 9, 3759 LSM6DSRX_XL_BATCHED_AT_6667Hz = 10, 3760 LSM6DSRX_XL_BATCHED_AT_6Hz5 = 11, 3761 } lsm6dsrx_bdr_xl_t; 3762 int32_t lsm6dsrx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 3763 lsm6dsrx_bdr_xl_t val); 3764 int32_t lsm6dsrx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 3765 lsm6dsrx_bdr_xl_t *val); 3766 3767 typedef enum 3768 { 3769 LSM6DSRX_GY_NOT_BATCHED = 0, 3770 LSM6DSRX_GY_BATCHED_AT_12Hz5 = 1, 3771 LSM6DSRX_GY_BATCHED_AT_26Hz = 2, 3772 LSM6DSRX_GY_BATCHED_AT_52Hz = 3, 3773 LSM6DSRX_GY_BATCHED_AT_104Hz = 4, 3774 LSM6DSRX_GY_BATCHED_AT_208Hz = 5, 3775 LSM6DSRX_GY_BATCHED_AT_417Hz = 6, 3776 LSM6DSRX_GY_BATCHED_AT_833Hz = 7, 3777 LSM6DSRX_GY_BATCHED_AT_1667Hz = 8, 3778 LSM6DSRX_GY_BATCHED_AT_3333Hz = 9, 3779 LSM6DSRX_GY_BATCHED_AT_6667Hz = 10, 3780 LSM6DSRX_GY_BATCHED_6Hz5 = 11, 3781 } lsm6dsrx_bdr_gy_t; 3782 int32_t lsm6dsrx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 3783 lsm6dsrx_bdr_gy_t val); 3784 int32_t lsm6dsrx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 3785 lsm6dsrx_bdr_gy_t *val); 3786 3787 typedef enum 3788 { 3789 LSM6DSRX_BYPASS_MODE = 0, 3790 LSM6DSRX_FIFO_MODE = 1, 3791 LSM6DSRX_STREAM_TO_FIFO_MODE = 3, 3792 LSM6DSRX_BYPASS_TO_STREAM_MODE = 4, 3793 LSM6DSRX_STREAM_MODE = 6, 3794 LSM6DSRX_BYPASS_TO_FIFO_MODE = 7, 3795 } lsm6dsrx_fifo_mode_t; 3796 int32_t lsm6dsrx_fifo_mode_set(const stmdev_ctx_t *ctx, 3797 lsm6dsrx_fifo_mode_t val); 3798 int32_t lsm6dsrx_fifo_mode_get(const stmdev_ctx_t *ctx, 3799 lsm6dsrx_fifo_mode_t *val); 3800 3801 typedef enum 3802 { 3803 LSM6DSRX_TEMP_NOT_BATCHED = 0, 3804 LSM6DSRX_TEMP_BATCHED_AT_52Hz = 1, 3805 LSM6DSRX_TEMP_BATCHED_AT_12Hz5 = 2, 3806 LSM6DSRX_TEMP_BATCHED_AT_1Hz6 = 3, 3807 } lsm6dsrx_odr_t_batch_t; 3808 int32_t lsm6dsrx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 3809 lsm6dsrx_odr_t_batch_t val); 3810 int32_t lsm6dsrx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 3811 lsm6dsrx_odr_t_batch_t *val); 3812 3813 typedef enum 3814 { 3815 LSM6DSRX_NO_DECIMATION = 0, 3816 LSM6DSRX_DEC_1 = 1, 3817 LSM6DSRX_DEC_8 = 2, 3818 LSM6DSRX_DEC_32 = 3, 3819 } lsm6dsrx_odr_ts_batch_t; 3820 int32_t lsm6dsrx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, 3821 lsm6dsrx_odr_ts_batch_t val); 3822 int32_t lsm6dsrx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, 3823 lsm6dsrx_odr_ts_batch_t *val); 3824 3825 typedef enum 3826 { 3827 LSM6DSRX_XL_BATCH_EVENT = 0, 3828 LSM6DSRX_GYRO_BATCH_EVENT = 1, 3829 } lsm6dsrx_trig_counter_bdr_t; 3830 int32_t lsm6dsrx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, 3831 lsm6dsrx_trig_counter_bdr_t val); 3832 int32_t lsm6dsrx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, 3833 lsm6dsrx_trig_counter_bdr_t *val); 3834 3835 int32_t lsm6dsrx_rst_batch_counter_set(const stmdev_ctx_t *ctx, 3836 uint8_t val); 3837 int32_t lsm6dsrx_rst_batch_counter_get(const stmdev_ctx_t *ctx, 3838 uint8_t *val); 3839 3840 int32_t lsm6dsrx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, 3841 uint16_t val); 3842 int32_t lsm6dsrx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, 3843 uint16_t *val); 3844 3845 int32_t lsm6dsrx_fifo_data_level_get(const stmdev_ctx_t *ctx, 3846 uint16_t *val); 3847 3848 int32_t lsm6dsrx_fifo_status_get(const stmdev_ctx_t *ctx, 3849 lsm6dsrx_fifo_status2_t *val); 3850 3851 int32_t lsm6dsrx_fifo_full_flag_get(const stmdev_ctx_t *ctx, 3852 uint8_t *val); 3853 3854 int32_t lsm6dsrx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3855 3856 int32_t lsm6dsrx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3857 3858 typedef enum 3859 { 3860 LSM6DSRX_GYRO_NC_TAG = 1, 3861 LSM6DSRX_XL_NC_TAG, 3862 LSM6DSRX_TEMPERATURE_TAG, 3863 LSM6DSRX_TIMESTAMP_TAG, 3864 LSM6DSRX_CFG_CHANGE_TAG, 3865 LSM6DSRX_XL_NC_T_2_TAG, 3866 LSM6DSRX_XL_NC_T_1_TAG, 3867 LSM6DSRX_XL_2XC_TAG, 3868 LSM6DSRX_XL_3XC_TAG, 3869 LSM6DSRX_GYRO_NC_T_2_TAG, 3870 LSM6DSRX_GYRO_NC_T_1_TAG, 3871 LSM6DSRX_GYRO_2XC_TAG, 3872 LSM6DSRX_GYRO_3XC_TAG, 3873 LSM6DSRX_SENSORHUB_SLAVE0_TAG, 3874 LSM6DSRX_SENSORHUB_SLAVE1_TAG, 3875 LSM6DSRX_SENSORHUB_SLAVE2_TAG, 3876 LSM6DSRX_SENSORHUB_SLAVE3_TAG, 3877 LSM6DSRX_STEP_CPUNTER_TAG, 3878 LSM6DSRX_GAME_ROTATION_TAG, 3879 LSM6DSRX_GEOMAG_ROTATION_TAG, 3880 LSM6DSRX_ROTATION_TAG, 3881 LSM6DSRX_SENSORHUB_NACK_TAG = 0x19, 3882 } lsm6dsrx_fifo_tag_t; 3883 int32_t lsm6dsrx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, 3884 lsm6dsrx_fifo_tag_t *val); 3885 3886 int32_t lsm6dsrx_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, 3887 uint8_t val); 3888 int32_t lsm6dsrx_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, 3889 uint8_t *val); 3890 3891 int32_t lsm6dsrx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, 3892 uint8_t val); 3893 int32_t lsm6dsrx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, 3894 uint8_t *val); 3895 3896 int32_t lsm6dsrx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, 3897 uint8_t val); 3898 int32_t lsm6dsrx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, 3899 uint8_t *val); 3900 3901 int32_t lsm6dsrx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, 3902 uint8_t val); 3903 int32_t lsm6dsrx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, 3904 uint8_t *val); 3905 3906 int32_t lsm6dsrx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, 3907 uint8_t val); 3908 int32_t lsm6dsrx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, 3909 uint8_t *val); 3910 3911 typedef enum 3912 { 3913 LSM6DSRX_DEN_DISABLE = 0, 3914 LSM6DSRX_LEVEL_FIFO = 6, 3915 LSM6DSRX_LEVEL_LETCHED = 3, 3916 LSM6DSRX_LEVEL_TRIGGER = 2, 3917 LSM6DSRX_EDGE_TRIGGER = 4, 3918 } lsm6dsrx_den_mode_t; 3919 int32_t lsm6dsrx_den_mode_set(const stmdev_ctx_t *ctx, 3920 lsm6dsrx_den_mode_t val); 3921 int32_t lsm6dsrx_den_mode_get(const stmdev_ctx_t *ctx, 3922 lsm6dsrx_den_mode_t *val); 3923 3924 typedef enum 3925 { 3926 LSM6DSRX_DEN_ACT_LOW = 0, 3927 LSM6DSRX_DEN_ACT_HIGH = 1, 3928 } lsm6dsrx_den_lh_t; 3929 int32_t lsm6dsrx_den_polarity_set(const stmdev_ctx_t *ctx, 3930 lsm6dsrx_den_lh_t val); 3931 int32_t lsm6dsrx_den_polarity_get(const stmdev_ctx_t *ctx, 3932 lsm6dsrx_den_lh_t *val); 3933 3934 typedef enum 3935 { 3936 LSM6DSRX_STAMP_IN_GY_DATA = 0, 3937 LSM6DSRX_STAMP_IN_XL_DATA = 1, 3938 LSM6DSRX_STAMP_IN_GY_XL_DATA = 2, 3939 } lsm6dsrx_den_xl_g_t; 3940 int32_t lsm6dsrx_den_enable_set(const stmdev_ctx_t *ctx, 3941 lsm6dsrx_den_xl_g_t val); 3942 int32_t lsm6dsrx_den_enable_get(const stmdev_ctx_t *ctx, 3943 lsm6dsrx_den_xl_g_t *val); 3944 3945 int32_t lsm6dsrx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, 3946 uint8_t val); 3947 int32_t lsm6dsrx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, 3948 uint8_t *val); 3949 3950 int32_t lsm6dsrx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, 3951 uint8_t val); 3952 int32_t lsm6dsrx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, 3953 uint8_t *val); 3954 3955 int32_t lsm6dsrx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, 3956 uint8_t val); 3957 int32_t lsm6dsrx_den_mark_axis_z_get(const stmdev_ctx_t *ctx, 3958 uint8_t *val); 3959 3960 int32_t lsm6dsrx_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 3961 int32_t lsm6dsrx_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 3962 3963 int32_t lsm6dsrx_pedo_step_detect_get(const stmdev_ctx_t *ctx, 3964 uint8_t *val); 3965 3966 int32_t lsm6dsrx_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, 3967 uint8_t *val); 3968 int32_t lsm6dsrx_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, 3969 uint8_t *val); 3970 3971 int32_t lsm6dsrx_pedo_steps_period_set(const stmdev_ctx_t *ctx, 3972 uint16_t val); 3973 int32_t lsm6dsrx_pedo_steps_period_get(const stmdev_ctx_t *ctx, 3974 uint16_t *val); 3975 3976 typedef enum 3977 { 3978 LSM6DSRX_EVERY_STEP = 0, 3979 LSM6DSRX_COUNT_OVERFLOW = 1, 3980 } lsm6dsrx_carry_count_en_t; 3981 int32_t lsm6dsrx_pedo_int_mode_set(const stmdev_ctx_t *ctx, 3982 lsm6dsrx_carry_count_en_t val); 3983 int32_t lsm6dsrx_pedo_int_mode_get(const stmdev_ctx_t *ctx, 3984 lsm6dsrx_carry_count_en_t *val); 3985 3986 int32_t lsm6dsrx_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 3987 int32_t lsm6dsrx_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 3988 3989 int32_t lsm6dsrx_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, 3990 uint8_t *val); 3991 3992 int32_t lsm6dsrx_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 3993 int32_t lsm6dsrx_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 3994 3995 int32_t lsm6dsrx_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, 3996 uint8_t *val); 3997 3998 int32_t lsm6dsrx_mag_sensitivity_set(const stmdev_ctx_t *ctx, 3999 uint16_t val); 4000 int32_t lsm6dsrx_mag_sensitivity_get(const stmdev_ctx_t *ctx, 4001 uint16_t *val); 4002 4003 int32_t lsm6dsrx_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 4004 int32_t lsm6dsrx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 4005 4006 int32_t lsm6dsrx_mag_soft_iron_set(const stmdev_ctx_t *ctx, 4007 uint16_t *val); 4008 int32_t lsm6dsrx_mag_soft_iron_get(const stmdev_ctx_t *ctx, 4009 uint16_t *val); 4010 4011 typedef enum 4012 { 4013 LSM6DSRX_Z_EQ_Y = 0, 4014 LSM6DSRX_Z_EQ_MIN_Y = 1, 4015 LSM6DSRX_Z_EQ_X = 2, 4016 LSM6DSRX_Z_EQ_MIN_X = 3, 4017 LSM6DSRX_Z_EQ_MIN_Z = 4, 4018 LSM6DSRX_Z_EQ_Z = 5, 4019 } lsm6dsrx_mag_z_axis_t; 4020 int32_t lsm6dsrx_mag_z_orient_set(const stmdev_ctx_t *ctx, 4021 lsm6dsrx_mag_z_axis_t val); 4022 int32_t lsm6dsrx_mag_z_orient_get(const stmdev_ctx_t *ctx, 4023 lsm6dsrx_mag_z_axis_t *val); 4024 4025 typedef enum 4026 { 4027 LSM6DSRX_Y_EQ_Y = 0, 4028 LSM6DSRX_Y_EQ_MIN_Y = 1, 4029 LSM6DSRX_Y_EQ_X = 2, 4030 LSM6DSRX_Y_EQ_MIN_X = 3, 4031 LSM6DSRX_Y_EQ_MIN_Z = 4, 4032 LSM6DSRX_Y_EQ_Z = 5, 4033 } lsm6dsrx_mag_y_axis_t; 4034 int32_t lsm6dsrx_mag_y_orient_set(const stmdev_ctx_t *ctx, 4035 lsm6dsrx_mag_y_axis_t val); 4036 int32_t lsm6dsrx_mag_y_orient_get(const stmdev_ctx_t *ctx, 4037 lsm6dsrx_mag_y_axis_t *val); 4038 4039 typedef enum 4040 { 4041 LSM6DSRX_X_EQ_Y = 0, 4042 LSM6DSRX_X_EQ_MIN_Y = 1, 4043 LSM6DSRX_X_EQ_X = 2, 4044 LSM6DSRX_X_EQ_MIN_X = 3, 4045 LSM6DSRX_X_EQ_MIN_Z = 4, 4046 LSM6DSRX_X_EQ_Z = 5, 4047 } lsm6dsrx_mag_x_axis_t; 4048 int32_t lsm6dsrx_mag_x_orient_set(const stmdev_ctx_t *ctx, 4049 lsm6dsrx_mag_x_axis_t val); 4050 int32_t lsm6dsrx_mag_x_orient_get(const stmdev_ctx_t *ctx, 4051 lsm6dsrx_mag_x_axis_t *val); 4052 4053 int32_t lsm6dsrx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, 4054 uint8_t *val); 4055 4056 int32_t lsm6dsrx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); 4057 int32_t lsm6dsrx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 4058 4059 typedef struct 4060 { 4061 lsm6dsrx_fsm_enable_a_t fsm_enable_a; 4062 lsm6dsrx_fsm_enable_b_t fsm_enable_b; 4063 } lsm6dsrx_emb_fsm_enable_t; 4064 int32_t lsm6dsrx_fsm_enable_set(const stmdev_ctx_t *ctx, 4065 lsm6dsrx_emb_fsm_enable_t *val); 4066 int32_t lsm6dsrx_fsm_enable_get(const stmdev_ctx_t *ctx, 4067 lsm6dsrx_emb_fsm_enable_t *val); 4068 4069 int32_t lsm6dsrx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 4070 int32_t lsm6dsrx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 4071 4072 typedef enum 4073 { 4074 LSM6DSRX_LC_NORMAL = 0, 4075 LSM6DSRX_LC_CLEAR = 1, 4076 LSM6DSRX_LC_CLEAR_DONE = 2, 4077 } lsm6dsrx_fsm_lc_clr_t; 4078 int32_t lsm6dsrx_long_clr_set(const stmdev_ctx_t *ctx, 4079 lsm6dsrx_fsm_lc_clr_t val); 4080 int32_t lsm6dsrx_long_clr_get(const stmdev_ctx_t *ctx, 4081 lsm6dsrx_fsm_lc_clr_t *val); 4082 4083 typedef struct 4084 { 4085 lsm6dsrx_fsm_outs1_t fsm_outs1; 4086 lsm6dsrx_fsm_outs2_t fsm_outs2; 4087 lsm6dsrx_fsm_outs3_t fsm_outs3; 4088 lsm6dsrx_fsm_outs4_t fsm_outs4; 4089 lsm6dsrx_fsm_outs5_t fsm_outs5; 4090 lsm6dsrx_fsm_outs6_t fsm_outs6; 4091 lsm6dsrx_fsm_outs7_t fsm_outs7; 4092 lsm6dsrx_fsm_outs8_t fsm_outs8; 4093 lsm6dsrx_fsm_outs9_t fsm_outs9; 4094 lsm6dsrx_fsm_outs10_t fsm_outs10; 4095 lsm6dsrx_fsm_outs11_t fsm_outs11; 4096 lsm6dsrx_fsm_outs12_t fsm_outs12; 4097 lsm6dsrx_fsm_outs13_t fsm_outs13; 4098 lsm6dsrx_fsm_outs14_t fsm_outs14; 4099 lsm6dsrx_fsm_outs15_t fsm_outs15; 4100 lsm6dsrx_fsm_outs16_t fsm_outs16; 4101 } lsm6dsrx_fsm_out_t; 4102 int32_t lsm6dsrx_fsm_out_get(const stmdev_ctx_t *ctx, 4103 lsm6dsrx_fsm_out_t *val); 4104 4105 typedef enum 4106 { 4107 LSM6DSRX_ODR_FSM_12Hz5 = 0, 4108 LSM6DSRX_ODR_FSM_26Hz = 1, 4109 LSM6DSRX_ODR_FSM_52Hz = 2, 4110 LSM6DSRX_ODR_FSM_104Hz = 3, 4111 } lsm6dsrx_fsm_odr_t; 4112 int32_t lsm6dsrx_fsm_data_rate_set(const stmdev_ctx_t *ctx, 4113 lsm6dsrx_fsm_odr_t val); 4114 int32_t lsm6dsrx_fsm_data_rate_get(const stmdev_ctx_t *ctx, 4115 lsm6dsrx_fsm_odr_t *val); 4116 4117 int32_t lsm6dsrx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); 4118 int32_t lsm6dsrx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); 4119 4120 int32_t lsm6dsrx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, 4121 uint16_t val); 4122 int32_t lsm6dsrx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, 4123 uint16_t *val); 4124 4125 int32_t lsm6dsrx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, 4126 uint8_t *val); 4127 int32_t lsm6dsrx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, 4128 uint8_t *val); 4129 4130 int32_t lsm6dsrx_fsm_start_address_set(const stmdev_ctx_t *ctx, 4131 uint16_t val); 4132 int32_t lsm6dsrx_fsm_start_address_get(const stmdev_ctx_t *ctx, 4133 uint16_t *val); 4134 4135 int32_t lsm6dsrx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val); 4136 int32_t lsm6dsrx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val); 4137 4138 int32_t lsm6dsrx_mlc_status_get(const stmdev_ctx_t *ctx, 4139 lsm6dsrx_mlc_status_mainpage_t *val); 4140 4141 typedef enum 4142 { 4143 LSM6DSRX_ODR_PRGS_12Hz5 = 0, 4144 LSM6DSRX_ODR_PRGS_26Hz = 1, 4145 LSM6DSRX_ODR_PRGS_52Hz = 2, 4146 LSM6DSRX_ODR_PRGS_104Hz = 3, 4147 } lsm6dsrx_mlc_odr_t; 4148 int32_t lsm6dsrx_mlc_data_rate_set(const stmdev_ctx_t *ctx, 4149 lsm6dsrx_mlc_odr_t val); 4150 int32_t lsm6dsrx_mlc_data_rate_get(const stmdev_ctx_t *ctx, 4151 lsm6dsrx_mlc_odr_t *val); 4152 4153 int32_t lsm6dsrx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); 4154 int32_t lsm6dsrx_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); 4155 int32_t lsm6dsrx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); 4156 4157 typedef struct 4158 { 4159 lsm6dsrx_sensor_hub_1_t sh_byte_1; 4160 lsm6dsrx_sensor_hub_2_t sh_byte_2; 4161 lsm6dsrx_sensor_hub_3_t sh_byte_3; 4162 lsm6dsrx_sensor_hub_4_t sh_byte_4; 4163 lsm6dsrx_sensor_hub_5_t sh_byte_5; 4164 lsm6dsrx_sensor_hub_6_t sh_byte_6; 4165 lsm6dsrx_sensor_hub_7_t sh_byte_7; 4166 lsm6dsrx_sensor_hub_8_t sh_byte_8; 4167 lsm6dsrx_sensor_hub_9_t sh_byte_9; 4168 lsm6dsrx_sensor_hub_10_t sh_byte_10; 4169 lsm6dsrx_sensor_hub_11_t sh_byte_11; 4170 lsm6dsrx_sensor_hub_12_t sh_byte_12; 4171 lsm6dsrx_sensor_hub_13_t sh_byte_13; 4172 lsm6dsrx_sensor_hub_14_t sh_byte_14; 4173 lsm6dsrx_sensor_hub_15_t sh_byte_15; 4174 lsm6dsrx_sensor_hub_16_t sh_byte_16; 4175 lsm6dsrx_sensor_hub_17_t sh_byte_17; 4176 lsm6dsrx_sensor_hub_18_t sh_byte_18; 4177 } lsm6dsrx_emb_sh_read_t; 4178 int32_t lsm6dsrx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, 4179 lsm6dsrx_emb_sh_read_t *val, 4180 uint8_t len); 4181 4182 typedef enum 4183 { 4184 LSM6DSRX_SLV_0 = 0, 4185 LSM6DSRX_SLV_0_1 = 1, 4186 LSM6DSRX_SLV_0_1_2 = 2, 4187 LSM6DSRX_SLV_0_1_2_3 = 3, 4188 } lsm6dsrx_aux_sens_on_t; 4189 int32_t lsm6dsrx_sh_slave_connected_set(const stmdev_ctx_t *ctx, 4190 lsm6dsrx_aux_sens_on_t val); 4191 int32_t lsm6dsrx_sh_slave_connected_get(const stmdev_ctx_t *ctx, 4192 lsm6dsrx_aux_sens_on_t *val); 4193 4194 int32_t lsm6dsrx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); 4195 int32_t lsm6dsrx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); 4196 4197 typedef enum 4198 { 4199 LSM6DSRX_EXT_PULL_UP = 0, 4200 LSM6DSRX_INTERNAL_PULL_UP = 1, 4201 } lsm6dsrx_shub_pu_en_t; 4202 int32_t lsm6dsrx_sh_pin_mode_set(const stmdev_ctx_t *ctx, 4203 lsm6dsrx_shub_pu_en_t val); 4204 int32_t lsm6dsrx_sh_pin_mode_get(const stmdev_ctx_t *ctx, 4205 lsm6dsrx_shub_pu_en_t *val); 4206 4207 int32_t lsm6dsrx_sh_pass_through_set(const stmdev_ctx_t *ctx, 4208 uint8_t val); 4209 int32_t lsm6dsrx_sh_pass_through_get(const stmdev_ctx_t *ctx, 4210 uint8_t *val); 4211 4212 typedef enum 4213 { 4214 LSM6DSRX_EXT_ON_INT2_PIN = 1, 4215 LSM6DSRX_XL_GY_DRDY = 0, 4216 } lsm6dsrx_start_config_t; 4217 int32_t lsm6dsrx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, 4218 lsm6dsrx_start_config_t val); 4219 int32_t lsm6dsrx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, 4220 lsm6dsrx_start_config_t *val); 4221 4222 typedef enum 4223 { 4224 LSM6DSRX_EACH_SH_CYCLE = 0, 4225 LSM6DSRX_ONLY_FIRST_CYCLE = 1, 4226 } lsm6dsrx_write_once_t; 4227 int32_t lsm6dsrx_sh_write_mode_set(const stmdev_ctx_t *ctx, 4228 lsm6dsrx_write_once_t val); 4229 int32_t lsm6dsrx_sh_write_mode_get(const stmdev_ctx_t *ctx, 4230 lsm6dsrx_write_once_t *val); 4231 4232 int32_t lsm6dsrx_sh_reset_set(const stmdev_ctx_t *ctx); 4233 int32_t lsm6dsrx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 4234 4235 typedef enum 4236 { 4237 LSM6DSRX_SH_ODR_104Hz = 0, 4238 LSM6DSRX_SH_ODR_52Hz = 1, 4239 LSM6DSRX_SH_ODR_26Hz = 2, 4240 LSM6DSRX_SH_ODR_13Hz = 3, 4241 } lsm6dsrx_shub_odr_t; 4242 int32_t lsm6dsrx_sh_data_rate_set(const stmdev_ctx_t *ctx, 4243 lsm6dsrx_shub_odr_t val); 4244 int32_t lsm6dsrx_sh_data_rate_get(const stmdev_ctx_t *ctx, 4245 lsm6dsrx_shub_odr_t *val); 4246 4247 typedef struct 4248 { 4249 uint8_t slv0_add; 4250 uint8_t slv0_subadd; 4251 uint8_t slv0_data; 4252 } lsm6dsrx_sh_cfg_write_t; 4253 int32_t lsm6dsrx_sh_cfg_write(const stmdev_ctx_t *ctx, 4254 lsm6dsrx_sh_cfg_write_t *val); 4255 4256 typedef struct 4257 { 4258 uint8_t slv_add; 4259 uint8_t slv_subadd; 4260 uint8_t slv_len; 4261 } lsm6dsrx_sh_cfg_read_t; 4262 int32_t lsm6dsrx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, 4263 lsm6dsrx_sh_cfg_read_t *val); 4264 int32_t lsm6dsrx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, 4265 lsm6dsrx_sh_cfg_read_t *val); 4266 int32_t lsm6dsrx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, 4267 lsm6dsrx_sh_cfg_read_t *val); 4268 int32_t lsm6dsrx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, 4269 lsm6dsrx_sh_cfg_read_t *val); 4270 4271 int32_t lsm6dsrx_sh_status_get(const stmdev_ctx_t *ctx, 4272 lsm6dsrx_status_master_t *val); 4273 4274 typedef enum 4275 { 4276 LSM6DSRX_S4S_TPH_7bit = 0, 4277 LSM6DSRX_S4S_TPH_15bit = 1, 4278 } lsm6dsrx_s4s_tph_res_t; 4279 int32_t lsm6dsrx_s4s_tph_res_set(const stmdev_ctx_t *ctx, 4280 lsm6dsrx_s4s_tph_res_t val); 4281 int32_t lsm6dsrx_s4s_tph_res_get(const stmdev_ctx_t *ctx, 4282 lsm6dsrx_s4s_tph_res_t *val); 4283 4284 int32_t lsm6dsrx_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val); 4285 int32_t lsm6dsrx_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val); 4286 4287 typedef enum 4288 { 4289 LSM6DSRX_S4S_DT_RES_11 = 0, 4290 LSM6DSRX_S4S_DT_RES_12 = 1, 4291 LSM6DSRX_S4S_DT_RES_13 = 2, 4292 LSM6DSRX_S4S_DT_RES_14 = 3, 4293 } lsm6dsrx_s4s_res_ratio_t; 4294 int32_t lsm6dsrx_s4s_res_ratio_set(const stmdev_ctx_t *ctx, 4295 lsm6dsrx_s4s_res_ratio_t val); 4296 int32_t lsm6dsrx_s4s_res_ratio_get(const stmdev_ctx_t *ctx, 4297 lsm6dsrx_s4s_res_ratio_t *val); 4298 4299 int32_t lsm6dsrx_s4s_command_set(const stmdev_ctx_t *ctx, uint8_t val); 4300 int32_t lsm6dsrx_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val); 4301 4302 int32_t lsm6dsrx_s4s_dt_set(const stmdev_ctx_t *ctx, uint8_t val); 4303 int32_t lsm6dsrx_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val); 4304 4305 /** 4306 *@} 4307 * 4308 */ 4309 4310 #ifdef __cplusplus 4311 } 4312 #endif 4313 4314 #endif /* LSM6DSRX_REGS_H */ 4315 4316 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4317
