1 /** 2 ****************************************************************************** 3 * @file hts221_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * hts221_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef HTS221_REGS_H 23 #define HTS221_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup HTS221 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 /* #define DRV_BYTE_ORDER DRV_BIG_ENDIAN */ 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup HTS221_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format **/ 172 #define HTS221_I2C_ADDRESS 0xBFU 173 174 /** Device Identification (Who am I) **/ 175 #define HTS221_ID 0xBCU 176 177 /** 178 * @} 179 * 180 */ 181 182 #define HTS221_WHO_AM_I 0x0FU 183 #define HTS221_AV_CONF 0x10U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t avgh : 3; 188 uint8_t avgt : 3; 189 uint8_t not_used_01 : 2; 190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 191 uint8_t not_used_01 : 2; 192 uint8_t avgt : 3; 193 uint8_t avgh : 3; 194 #endif /* DRV_BYTE_ORDER */ 195 } hts221_av_conf_t; 196 197 #define HTS221_CTRL_REG1 0x20U 198 typedef struct 199 { 200 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 201 uint8_t odr : 2; 202 uint8_t bdu : 1; 203 uint8_t not_used_01 : 4; 204 uint8_t pd : 1; 205 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 206 uint8_t pd : 1; 207 uint8_t not_used_01 : 4; 208 uint8_t bdu : 1; 209 uint8_t odr : 2; 210 #endif /* DRV_BYTE_ORDER */ 211 } hts221_ctrl_reg1_t; 212 213 #define HTS221_CTRL_REG2 0x21U 214 typedef struct 215 { 216 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 217 uint8_t one_shot : 1; 218 uint8_t heater : 1; 219 uint8_t not_used_01 : 5; 220 uint8_t boot : 1; 221 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 222 uint8_t boot : 1; 223 uint8_t not_used_01 : 5; 224 uint8_t heater : 1; 225 uint8_t one_shot : 1; 226 #endif /* DRV_BYTE_ORDER */ 227 } hts221_ctrl_reg2_t; 228 229 #define HTS221_CTRL_REG3 0x22U 230 typedef struct 231 { 232 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 233 uint8_t not_used_01 : 2; 234 uint8_t drdy : 1; 235 uint8_t not_used_02 : 3; 236 uint8_t pp_od : 1; 237 uint8_t drdy_h_l : 1; 238 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 239 uint8_t drdy_h_l : 1; 240 uint8_t pp_od : 1; 241 uint8_t not_used_02 : 3; 242 uint8_t drdy : 1; 243 uint8_t not_used_01 : 2; 244 #endif /* DRV_BYTE_ORDER */ 245 } hts221_ctrl_reg3_t; 246 247 #define HTS221_STATUS_REG 0x27U 248 typedef struct 249 { 250 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 251 uint8_t t_da : 1; 252 uint8_t h_da : 1; 253 uint8_t not_used_01 : 6; 254 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 255 uint8_t not_used_01 : 6; 256 uint8_t h_da : 1; 257 uint8_t t_da : 1; 258 #endif /* DRV_BYTE_ORDER */ 259 } hts221_status_reg_t; 260 261 #define HTS221_HUMIDITY_OUT_L 0x28U 262 #define HTS221_HUMIDITY_OUT_H 0x29U 263 #define HTS221_TEMP_OUT_L 0x2AU 264 #define HTS221_TEMP_OUT_H 0x2BU 265 #define HTS221_H0_RH_X2 0x30U 266 #define HTS221_H1_RH_X2 0x31U 267 #define HTS221_T0_DEGC_X8 0x32U 268 #define HTS221_T1_DEGC_X8 0x33U 269 #define HTS221_T1_T0_MSB 0x35U 270 typedef struct 271 { 272 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 273 uint8_t t0_msb : 2; 274 uint8_t t1_msb : 2; 275 uint8_t not_used_01 : 4; 276 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 277 uint8_t not_used_01 : 4; 278 uint8_t t1_msb : 2; 279 uint8_t t0_msb : 2; 280 #endif /* DRV_BYTE_ORDER */ 281 } hts221_t1_t0_msb_t; 282 283 #define HTS221_H0_T0_OUT_L 0x36U 284 #define HTS221_H0_T0_OUT_H 0x37U 285 #define HTS221_H1_T0_OUT_L 0x3AU 286 #define HTS221_H1_T0_OUT_H 0x3BU 287 #define HTS221_T0_OUT_L 0x3CU 288 #define HTS221_T0_OUT_H 0x3DU 289 #define HTS221_T1_OUT_L 0x3EU 290 #define HTS221_T1_OUT_H 0x3FU 291 292 /** 293 * @defgroup HTS221_Register_Union 294 * @brief This union group all the registers having a bit-field 295 * description. 296 * This union is useful but it's not needed by the driver. 297 * 298 * REMOVING this union you are compliant with: 299 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 300 * 301 * @{ 302 * 303 */ 304 typedef union 305 { 306 hts221_av_conf_t av_conf; 307 hts221_ctrl_reg1_t ctrl_reg1; 308 hts221_ctrl_reg2_t ctrl_reg2; 309 hts221_ctrl_reg3_t ctrl_reg3; 310 hts221_status_reg_t status_reg; 311 hts221_t1_t0_msb_t t1_t0_msb; 312 bitwise_t bitwise; 313 uint8_t byte; 314 } hts221_reg_t; 315 316 /** 317 * @} 318 * 319 */ 320 321 #ifndef __weak 322 #define __weak __attribute__((weak)) 323 #endif /* __weak */ 324 325 /* 326 * These are the basic platform dependent I/O routines to read 327 * and write device registers connected on a standard bus. 328 * The driver keeps offering a default implementation based on function 329 * pointers to read/write routines for backward compatibility. 330 * The __weak directive allows the final application to overwrite 331 * them with a custom implementation. 332 */ 333 int32_t hts221_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 334 uint8_t *data, 335 uint16_t len); 336 int32_t hts221_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 337 uint8_t *data, 338 uint16_t len); 339 340 typedef enum 341 { 342 HTS221_H_AVG_4 = 0, 343 HTS221_H_AVG_8 = 1, 344 HTS221_H_AVG_16 = 2, 345 HTS221_H_AVG_32 = 3, 346 HTS221_H_AVG_64 = 4, 347 HTS221_H_AVG_128 = 5, 348 HTS221_H_AVG_256 = 6, 349 HTS221_H_AVG_512 = 7, 350 HTS221_H_AVG_ND = 8, 351 } hts221_avgh_t; 352 int32_t hts221_humidity_avg_set(const stmdev_ctx_t *ctx, hts221_avgh_t val); 353 int32_t hts221_humidity_avg_get(const stmdev_ctx_t *ctx, 354 hts221_avgh_t *val); 355 356 typedef enum 357 { 358 HTS221_T_AVG_2 = 0, 359 HTS221_T_AVG_4 = 1, 360 HTS221_T_AVG_8 = 2, 361 HTS221_T_AVG_16 = 3, 362 HTS221_T_AVG_32 = 4, 363 HTS221_T_AVG_64 = 5, 364 HTS221_T_AVG_128 = 6, 365 HTS221_T_AVG_256 = 7, 366 HTS221_T_AVG_ND = 8, 367 } hts221_avgt_t; 368 int32_t hts221_temperature_avg_set(const stmdev_ctx_t *ctx, 369 hts221_avgt_t val); 370 int32_t hts221_temperature_avg_get(const stmdev_ctx_t *ctx, 371 hts221_avgt_t *val); 372 373 typedef enum 374 { 375 HTS221_ONE_SHOT = 0, 376 HTS221_ODR_1Hz = 1, 377 HTS221_ODR_7Hz = 2, 378 HTS221_ODR_12Hz5 = 3, 379 HTS221_ODR_ND = 4, 380 } hts221_odr_t; 381 int32_t hts221_data_rate_set(const stmdev_ctx_t *ctx, hts221_odr_t val); 382 int32_t hts221_data_rate_get(const stmdev_ctx_t *ctx, hts221_odr_t *val); 383 384 int32_t hts221_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 385 int32_t hts221_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); 386 387 int32_t hts221_one_shoot_trigger_set(const stmdev_ctx_t *ctx, uint8_t val); 388 int32_t hts221_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val); 389 390 int32_t hts221_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 391 392 int32_t hts221_hum_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 393 394 int32_t hts221_humidity_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 395 396 int32_t hts221_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 397 398 int32_t hts221_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 399 400 int32_t hts221_power_on_set(const stmdev_ctx_t *ctx, uint8_t val); 401 402 int32_t hts221_power_on_get(const stmdev_ctx_t *ctx, uint8_t *val); 403 404 int32_t hts221_heater_set(const stmdev_ctx_t *ctx, uint8_t val); 405 int32_t hts221_heater_get(const stmdev_ctx_t *ctx, uint8_t *val); 406 407 int32_t hts221_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 408 int32_t hts221_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 409 410 int32_t hts221_status_get(const stmdev_ctx_t *ctx, 411 hts221_status_reg_t *val); 412 413 int32_t hts221_drdy_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); 414 int32_t hts221_drdy_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); 415 416 typedef enum 417 { 418 HTS221_PUSH_PULL = 0, 419 HTS221_OPEN_DRAIN = 1, 420 HTS221_PIN_MODE_ND = 2, 421 } hts221_pp_od_t; 422 int32_t hts221_pin_mode_set(const stmdev_ctx_t *ctx, hts221_pp_od_t val); 423 int32_t hts221_pin_mode_get(const stmdev_ctx_t *ctx, hts221_pp_od_t *val); 424 425 typedef enum 426 { 427 HTS221_ACTIVE_HIGH = 0, 428 HTS221_ACTIVE_LOW = 1, 429 HTS221_ACTIVE_ND = 2, 430 } hts221_drdy_h_l_t; 431 int32_t hts221_int_polarity_set(const stmdev_ctx_t *ctx, 432 hts221_drdy_h_l_t val); 433 int32_t hts221_int_polarity_get(const stmdev_ctx_t *ctx, 434 hts221_drdy_h_l_t *val); 435 436 int32_t hts221_hum_rh_point_0_get(const stmdev_ctx_t *ctx, float_t *val); 437 int32_t hts221_hum_rh_point_1_get(const stmdev_ctx_t *ctx, float_t *val); 438 439 int32_t hts221_temp_deg_point_0_get(const stmdev_ctx_t *ctx, float_t *val); 440 int32_t hts221_temp_deg_point_1_get(const stmdev_ctx_t *ctx, float_t *val); 441 442 int32_t hts221_hum_adc_point_0_get(const stmdev_ctx_t *ctx, float_t *val); 443 int32_t hts221_hum_adc_point_1_get(const stmdev_ctx_t *ctx, float_t *val); 444 445 int32_t hts221_temp_adc_point_0_get(const stmdev_ctx_t *ctx, float_t *val); 446 int32_t hts221_temp_adc_point_1_get(const stmdev_ctx_t *ctx, float_t *val); 447 448 /** 449 * @} 450 * 451 */ 452 453 #ifdef __cplusplus 454 } 455 #endif 456 457 #endif /*HTS221_REGS_H */ 458 459 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 460
