1 /** 2 ****************************************************************************** 3 * @file sths34pf80_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * sths34pf80_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef STHS34PF80_REGS_H 23 #define STHS34PF80_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup STHS34PF80 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup STHS34PF80_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format **/ 172 #define STHS34PF80_I2C_ADD 0xB5U 173 174 /** Device Identification (Who am I) **/ 175 #define STHS34PF80_ID 0xD3U 176 177 /** 178 * @} 179 * 180 */ 181 182 /** @defgroup bitfields page main 183 * @{ 184 * 185 */ 186 187 #define STHS34PF80_LPF1 0x0CU 188 typedef struct 189 { 190 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 191 uint8_t lpf_m : 3; 192 uint8_t lpf_p_m : 3; 193 uint8_t not_used0 : 2; 194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 195 uint8_t not_used0 : 2; 196 uint8_t lpf_p_m : 3; 197 uint8_t lpf_m : 3; 198 #endif /* DRV_BYTE_ORDER */ 199 } sths34pf80_lpf1_t; 200 201 #define STHS34PF80_LPF2 0x0DU 202 typedef struct 203 { 204 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 205 uint8_t lpf_a_t : 3; 206 uint8_t lpf_p : 3; 207 uint8_t not_used0 : 2; 208 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 209 uint8_t not_used0 : 2; 210 uint8_t lpf_p : 3; 211 uint8_t lpf_a_t : 3; 212 #endif /* DRV_BYTE_ORDER */ 213 } sths34pf80_lpf2_t; 214 215 #define STHS34PF80_WHO_AM_I 0x0FU 216 typedef struct 217 { 218 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 219 uint8_t id : 8; 220 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 221 uint8_t id : 8; 222 #endif /* DRV_BYTE_ORDER */ 223 } sths34pf80_who_am_i_t; 224 225 #define STHS34PF80_AVG_TRIM 0x10U 226 typedef struct 227 { 228 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 229 uint8_t avg_tmos : 3; 230 uint8_t not_used0 : 1; 231 uint8_t avg_t : 2; 232 uint8_t not_used1 : 2; 233 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 234 uint8_t not_used1 : 2; 235 uint8_t avg_t : 2; 236 uint8_t not_used0 : 1; 237 uint8_t avg_tmos : 3; 238 #endif /* DRV_BYTE_ORDER */ 239 } sths34pf80_avg_trim_t; 240 241 #define STHS34PF80_CTRL0 0x17U 242 typedef struct 243 { 244 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 245 uint8_t not_used0 : 4; 246 uint8_t gain : 3; 247 uint8_t not_used1 : 1; 248 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 249 uint8_t not_used1 : 1; 250 uint8_t gain : 3; 251 uint8_t not_used0 : 4; 252 #endif /* DRV_BYTE_ORDER */ 253 } sths34pf80_ctrl0_t; 254 255 #define STHS34PF80_SENS_DATA 0x1DU 256 typedef struct 257 { 258 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 259 uint8_t sens : 8; 260 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 261 uint8_t sens : 8; 262 #endif /* DRV_BYTE_ORDER */ 263 } sths34pf80_sens_data_t; 264 265 #define STHS34PF80_CTRL1 0x20U 266 typedef struct 267 { 268 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 269 uint8_t odr : 4; 270 uint8_t bdu : 1; 271 uint8_t not_used0 : 3; 272 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 273 uint8_t not_used0 : 3; 274 uint8_t bdu : 1; 275 uint8_t odr : 4; 276 #endif /* DRV_BYTE_ORDER */ 277 } sths34pf80_ctrl1_t; 278 279 #define STHS34PF80_CTRL2 0x21U 280 typedef struct 281 { 282 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 283 uint8_t one_shot : 1; 284 uint8_t not_used0 : 3; 285 uint8_t func_cfg_access : 1; 286 uint8_t not_used1 : 2; 287 uint8_t boot : 1; 288 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 289 uint8_t boot : 1; 290 uint8_t not_used1 : 2; 291 uint8_t func_cfg_access : 1; 292 uint8_t not_used0 : 3; 293 uint8_t one_shot : 1; 294 #endif /* DRV_BYTE_ORDER */ 295 } sths34pf80_ctrl2_t; 296 297 #define STHS34PF80_CTRL3 0x22U 298 typedef struct 299 { 300 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 301 uint8_t ien : 2; 302 uint8_t int_latched : 1; 303 uint8_t int_msk : 3; 304 uint8_t pp_od : 1; 305 uint8_t int_h_l : 1; 306 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 307 uint8_t int_h_l : 1; 308 uint8_t pp_od : 1; 309 uint8_t int_msk : 3; 310 uint8_t int_latched : 1; 311 uint8_t ien : 2; 312 #endif /* DRV_BYTE_ORDER */ 313 } sths34pf80_ctrl3_t; 314 315 #define STHS34PF80_STATUS 0x23U 316 typedef struct 317 { 318 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 319 uint8_t not_used0 : 2; 320 uint8_t drdy : 1; 321 uint8_t not_used1 : 5; 322 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 323 uint8_t not_used1 : 5; 324 uint8_t drdy : 1; 325 uint8_t not_used0 : 2; 326 #endif /* DRV_BYTE_ORDER */ 327 } sths34pf80_status_t; 328 329 #define STHS34PF80_FUNC_STATUS 0x25U 330 typedef struct 331 { 332 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 333 uint8_t tamb_shock_flag : 1; 334 uint8_t mot_flag : 1; 335 uint8_t pres_flag : 1; 336 uint8_t not_used0 : 5; 337 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 338 uint8_t not_used0 : 5; 339 uint8_t pres_flag : 1; 340 uint8_t mot_flag : 1; 341 uint8_t tamb_shock_flag : 1; 342 #endif /* DRV_BYTE_ORDER */ 343 } sths34pf80_func_status_t; 344 345 #define STHS34PF80_TOBJECT_L 0x26U 346 typedef struct 347 { 348 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 349 uint8_t tobject : 8; 350 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 351 uint8_t tobject : 8; 352 #endif /* DRV_BYTE_ORDER */ 353 } sths34pf80_tobject_l_t; 354 355 #define STHS34PF80_TOBJECT_H 0x27U 356 typedef struct 357 { 358 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 359 uint8_t tobject : 8; 360 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 361 uint8_t tobject : 8; 362 #endif /* DRV_BYTE_ORDER */ 363 } sths34pf80_tobject_h_t; 364 365 #define STHS34PF80_TAMBIENT_L 0x28U 366 typedef struct 367 { 368 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 369 uint8_t tambient : 8; 370 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 371 uint8_t tambient : 8; 372 #endif /* DRV_BYTE_ORDER */ 373 } sths34pf80_tambient_l_t; 374 375 #define STHS34PF80_TAMBIENT_H 0x29U 376 typedef struct 377 { 378 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 379 uint8_t tambient : 8; 380 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 381 uint8_t tambient : 8; 382 #endif /* DRV_BYTE_ORDER */ 383 } sths34pf80_tambient_h_t; 384 385 #define STHS34PF80_TOBJ_COMP_L 0x38U 386 typedef struct 387 { 388 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 389 uint8_t tobj_comp : 8; 390 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 391 uint8_t tobj_comp : 8; 392 #endif /* DRV_BYTE_ORDER */ 393 } sths34pf80_tobj_comp_l_t; 394 395 #define STHS34PF80_TOBJ_COMP_H 0x39U 396 typedef struct 397 { 398 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 399 uint8_t tobj_comp : 8; 400 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 401 uint8_t tobj_comp : 8; 402 #endif /* DRV_BYTE_ORDER */ 403 } sths34pf80_tobj_comp_h_t; 404 405 #define STHS34PF80_TPRESENCE_L 0x3AU 406 typedef struct 407 { 408 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 409 uint8_t tpresence : 8; 410 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 411 uint8_t tpresence : 8; 412 #endif /* DRV_BYTE_ORDER */ 413 } sths34pf80_tpresence_l_t; 414 415 #define STHS34PF80_TPRESENCE_H 0x3BU 416 typedef struct 417 { 418 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 419 uint8_t tpresence : 8; 420 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 421 uint8_t tpresence : 8; 422 #endif /* DRV_BYTE_ORDER */ 423 } sths34pf80_tpresence_h_t; 424 425 #define STHS34PF80_TMOTION_L 0x3CU 426 typedef struct 427 { 428 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 429 uint8_t tmotion : 8; 430 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 431 uint8_t tmotion : 8; 432 #endif /* DRV_BYTE_ORDER */ 433 } sths34pf80_tmotion_l_t; 434 435 #define STHS34PF80_TMOTION_H 0x3DU 436 typedef struct 437 { 438 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 439 uint8_t tmotion : 8; 440 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 441 uint8_t tmotion : 8; 442 #endif /* DRV_BYTE_ORDER */ 443 } sths34pf80_tmotion_h_t; 444 445 #define STHS34PF80_TAMB_SHOCK_L 0x3EU 446 typedef struct 447 { 448 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 449 uint8_t tamb_shock : 8; 450 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 451 uint8_t tamb_shock : 8; 452 #endif /* DRV_BYTE_ORDER */ 453 } sths34pf80_tamb_shock_l_t; 454 455 #define STHS34PF80_TAMB_SHOCK_H 0x3FU 456 typedef struct 457 { 458 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 459 uint8_t tamb_shock : 8; 460 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 461 uint8_t tamb_shock : 8; 462 #endif /* DRV_BYTE_ORDER */ 463 } sths34pf80_tamb_shock_h_t; 464 465 /** 466 * @} 467 * 468 */ 469 470 /** @defgroup bitfields page embedded 471 * @{ 472 * 473 */ 474 475 #define STHS34PF80_FUNC_CFG_ADDR 0x08U 476 typedef struct 477 { 478 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 479 uint8_t func_cfg_addr : 8; 480 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 481 uint8_t func_cfg_addr : 8; 482 #endif /* DRV_BYTE_ORDER */ 483 } sths34pf80_func_cfg_addr_t; 484 485 #define STHS34PF80_FUNC_CFG_DATA 0x09U 486 typedef struct 487 { 488 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 489 uint8_t func_cfg_data : 8; 490 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 491 uint8_t func_cfg_data : 8; 492 #endif /* DRV_BYTE_ORDER */ 493 } sths34pf80_func_cfg_data_t; 494 495 #define STHS34PF80_PAGE_RW 0x11U 496 typedef struct 497 { 498 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 499 uint8_t not_used0 : 5; 500 uint8_t func_cfg_read : 1; 501 uint8_t func_cfg_write : 1; 502 uint8_t not_used1 : 1; 503 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 504 uint8_t not_used1 : 1; 505 uint8_t func_cfg_write : 1; 506 uint8_t func_cfg_read : 1; 507 uint8_t not_used0 : 5; 508 #endif /* DRV_BYTE_ORDER */ 509 } sths34pf80_page_rw_t; 510 511 #define STHS34PF80_PRESENCE_THS 0x20U 512 #define STHS34PF80_MOTION_THS 0x22U 513 #define STHS34PF80_TAMB_SHOCK_THS 0x24U 514 #define STHS34PF80_HYST_MOTION 0x26U 515 #define STHS34PF80_HYST_PRESENCE 0x27U 516 #define STHS34PF80_ALGO_CONFIG 0x28U 517 #define STHS34PF80_HYST_TAMB_SHOCK 0x29U 518 #define STHS34PF80_RESET_ALGO 0x2AU 519 520 /** 521 * @} 522 * 523 */ 524 525 typedef union 526 { 527 sths34pf80_lpf1_t lpf1; 528 sths34pf80_lpf2_t lpf2; 529 sths34pf80_who_am_i_t who_am_i; 530 sths34pf80_avg_trim_t avg_trim; 531 sths34pf80_ctrl1_t ctrl1; 532 sths34pf80_ctrl2_t ctrl2; 533 sths34pf80_ctrl3_t ctrl3; 534 sths34pf80_status_t status; 535 sths34pf80_func_status_t func_status; 536 sths34pf80_tobject_l_t tobject_l; 537 sths34pf80_tobject_h_t tobject_h; 538 sths34pf80_tambient_l_t tambient_l; 539 sths34pf80_tambient_h_t tambient_h; 540 sths34pf80_tpresence_l_t tpresence_l; 541 sths34pf80_tpresence_h_t tpresence_h; 542 sths34pf80_tmotion_l_t tmotion_l; 543 sths34pf80_tmotion_h_t tmotion_h; 544 sths34pf80_tamb_shock_l_t tamb_shock_l; 545 sths34pf80_tamb_shock_h_t tamb_shock_h; 546 bitwise_t bitwise; 547 uint8_t byte; 548 } prefix_lowmain_t; 549 550 typedef union 551 { 552 sths34pf80_func_cfg_addr_t func_cfg_addr; 553 sths34pf80_func_cfg_data_t func_cfg_data; 554 sths34pf80_page_rw_t page_rw; 555 bitwise_t bitwise; 556 uint8_t byte; 557 } prefix_lowembedded_t; 558 559 /** 560 * @} 561 * 562 */ 563 564 #ifndef __weak 565 #define __weak __attribute__((weak)) 566 #endif /* __weak */ 567 568 /* 569 * These are the basic platform dependent I/O routines to read 570 * and write device registers connected on a standard bus. 571 * The driver keeps offering a default implementation based on function 572 * pointers to read/write routines for backward compatibility. 573 * The default implementation is declared with a __weak directive to 574 * allow the final application to overwrite it with a custom implementation. 575 */ 576 int32_t sths34pf80_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 577 uint8_t *data, 578 uint16_t len); 579 int32_t sths34pf80_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 580 uint8_t *data, 581 uint16_t len); 582 583 int32_t sths34pf80_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); 584 585 typedef enum 586 { 587 STHS34PF80_AVG_TMOS_2 = 0x0, 588 STHS34PF80_AVG_TMOS_8 = 0x1, 589 STHS34PF80_AVG_TMOS_32 = 0x2, 590 STHS34PF80_AVG_TMOS_128 = 0x3, 591 STHS34PF80_AVG_TMOS_256 = 0x4, 592 STHS34PF80_AVG_TMOS_512 = 0x5, 593 STHS34PF80_AVG_TMOS_1024 = 0x6, 594 STHS34PF80_AVG_TMOS_2048 = 0x7, 595 } sths34pf80_avg_tobject_num_t; 596 int32_t sths34pf80_avg_tobject_num_set(stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t val); 597 int32_t sths34pf80_avg_tobject_num_get(stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t *val); 598 599 typedef enum 600 { 601 STHS34PF80_AVG_T_8 = 0x0, 602 STHS34PF80_AVG_T_4 = 0x1, 603 STHS34PF80_AVG_T_2 = 0x2, 604 STHS34PF80_AVG_T_1 = 0x3, 605 } sths34pf80_avg_tambient_num_t; 606 int32_t sths34pf80_avg_tambient_num_set(stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t val); 607 int32_t sths34pf80_avg_tambient_num_get(stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t *val); 608 609 typedef enum 610 { 611 STHS34PF80_GAIN_WIDE_MODE = 0x0, 612 STHS34PF80_GAIN_DEFAULT_MODE = 0x7, 613 } sths34pf80_gain_mode_t; 614 615 int32_t sths34pf80_gain_mode_set(stmdev_ctx_t *ctx, sths34pf80_gain_mode_t val); 616 int32_t sths34pf80_gain_mode_get(stmdev_ctx_t *ctx, sths34pf80_gain_mode_t *val); 617 618 int32_t sths34pf80_tmos_sensitivity_set(stmdev_ctx_t *ctx, uint16_t *val); 619 int32_t sths34pf80_tmos_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); 620 621 typedef enum 622 { 623 STHS34PF80_TMOS_ODR_OFF = 0x0, 624 STHS34PF80_TMOS_ODR_AT_0Hz25 = 0x1, 625 STHS34PF80_TMOS_ODR_AT_0Hz50 = 0x2, 626 STHS34PF80_TMOS_ODR_AT_1Hz = 0x3, 627 STHS34PF80_TMOS_ODR_AT_2Hz = 0x4, 628 STHS34PF80_TMOS_ODR_AT_4Hz = 0x5, 629 STHS34PF80_TMOS_ODR_AT_8Hz = 0x6, 630 STHS34PF80_TMOS_ODR_AT_15Hz = 0x7, 631 STHS34PF80_TMOS_ODR_AT_30Hz = 0x8, 632 } sths34pf80_tmos_odr_t; 633 int32_t sths34pf80_tmos_odr_set(stmdev_ctx_t *ctx, sths34pf80_tmos_odr_t val); 634 int32_t sths34pf80_tmos_odr_get(stmdev_ctx_t *ctx, sths34pf80_tmos_odr_t *val); 635 636 int32_t sths34pf80_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 637 int32_t sths34pf80_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); 638 639 typedef enum 640 { 641 STHS34PF80_TMOS_IDLE_MODE = 0x0, 642 STHS34PF80_TMOS_ONE_SHOT = 0x1, 643 } sths34pf80_tmos_one_shot_t; 644 int32_t sths34pf80_tmos_one_shot_set(stmdev_ctx_t *ctx, sths34pf80_tmos_one_shot_t val); 645 int32_t sths34pf80_tmos_one_shot_get(stmdev_ctx_t *ctx, sths34pf80_tmos_one_shot_t *val); 646 647 typedef enum 648 { 649 STHS34PF80_MAIN_MEM_BANK = 0x0, 650 STHS34PF80_EMBED_FUNC_MEM_BANK = 0x1, 651 } sths34pf80_mem_bank_t; 652 int32_t sths34pf80_mem_bank_set(stmdev_ctx_t *ctx, sths34pf80_mem_bank_t val); 653 int32_t sths34pf80_mem_bank_get(stmdev_ctx_t *ctx, sths34pf80_mem_bank_t *val); 654 655 int32_t sths34pf80_boot_set(stmdev_ctx_t *ctx, uint8_t val); 656 int32_t sths34pf80_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 657 658 typedef struct 659 { 660 uint8_t drdy : 1; 661 } sths34pf80_tmos_drdy_status_t; 662 int32_t sths34pf80_tmos_drdy_status_get(stmdev_ctx_t *ctx, sths34pf80_tmos_drdy_status_t *val); 663 664 typedef struct 665 { 666 uint8_t tamb_shock_flag : 1; 667 uint8_t mot_flag : 1; 668 uint8_t pres_flag : 1; 669 } sths34pf80_tmos_func_status_t; 670 int32_t sths34pf80_tmos_func_status_get(stmdev_ctx_t *ctx, sths34pf80_tmos_func_status_t *val); 671 672 int32_t sths34pf80_tobject_raw_get(stmdev_ctx_t *ctx, int16_t *val); 673 int32_t sths34pf80_tambient_raw_get(stmdev_ctx_t *ctx, int16_t *val); 674 int32_t sths34pf80_tobj_comp_raw_get(stmdev_ctx_t *ctx, int16_t *val); 675 int32_t sths34pf80_tpresence_raw_get(stmdev_ctx_t *ctx, int16_t *val); 676 int32_t sths34pf80_tmotion_raw_get(stmdev_ctx_t *ctx, int16_t *val); 677 int32_t sths34pf80_tamb_shock_raw_get(stmdev_ctx_t *ctx, int16_t *val); 678 679 typedef enum 680 { 681 STHS34PF80_LPF_ODR_DIV_9 = 0x0, 682 STHS34PF80_LPF_ODR_DIV_20 = 0x1, 683 STHS34PF80_LPF_ODR_DIV_50 = 0x2, 684 STHS34PF80_LPF_ODR_DIV_100 = 0x3, 685 STHS34PF80_LPF_ODR_DIV_200 = 0x4, 686 STHS34PF80_LPF_ODR_DIV_400 = 0x5, 687 STHS34PF80_LPF_ODR_DIV_800 = 0x6, 688 } sths34pf80_lpf_bandwidth_t; 689 int32_t sths34pf80_lpf_m_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val); 690 int32_t sths34pf80_lpf_m_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val); 691 int32_t sths34pf80_lpf_p_m_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val); 692 int32_t sths34pf80_lpf_p_m_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val); 693 int32_t sths34pf80_lpf_a_t_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val); 694 int32_t sths34pf80_lpf_a_t_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val); 695 int32_t sths34pf80_lpf_p_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val); 696 int32_t sths34pf80_lpf_p_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val); 697 698 typedef enum 699 { 700 STHS34PF80_TMOS_INT_HIZ = 0x0, 701 STHS34PF80_TMOS_INT_DRDY = 0x1, 702 STHS34PF80_TMOS_INT_OR = 0x2, 703 } sths34pf80_tmos_route_int_t; 704 int32_t sths34pf80_tmos_route_int_set(stmdev_ctx_t *ctx, sths34pf80_tmos_route_int_t val); 705 int32_t sths34pf80_tmos_route_int_get(stmdev_ctx_t *ctx, sths34pf80_tmos_route_int_t *val); 706 707 typedef enum 708 { 709 STHS34PF80_TMOS_INT_NONE = 0x0, 710 STHS34PF80_TMOS_INT_TSHOCK = 0x1, 711 STHS34PF80_TMOS_INT_MOTION = 0x2, 712 STHS34PF80_TMOS_INT_TSHOCK_MOTION = 0x3, 713 STHS34PF80_TMOS_INT_PRESENCE = 0x4, 714 STHS34PF80_TMOS_INT_TSHOCK_PRESENCE = 0x5, 715 STHS34PF80_TMOS_INT_MOTION_PRESENCE = 0x6, 716 STHS34PF80_TMOS_INT_ALL = 0x7, 717 } sths34pf80_tmos_int_or_t; 718 int32_t sths34pf80_tmos_int_or_set(stmdev_ctx_t *ctx, sths34pf80_tmos_int_or_t val); 719 int32_t sths34pf80_tmos_int_or_get(stmdev_ctx_t *ctx, sths34pf80_tmos_int_or_t *val); 720 721 typedef struct 722 { 723 enum { 724 STHS34PF80_PUSH_PULL = 0x0, 725 STHS34PF80_OPEN_DRAIN = 0x1, 726 } pin; 727 728 enum { 729 STHS34PF80_ACTIVE_HIGH = 0x0, 730 STHS34PF80_ACTIVE_LOW = 0x1, 731 } polarity; 732 } sths34pf80_int_mode_t; 733 int32_t sths34pf80_int_mode_set(stmdev_ctx_t *ctx, sths34pf80_int_mode_t val); 734 int32_t sths34pf80_int_mode_get(stmdev_ctx_t *ctx, sths34pf80_int_mode_t *val); 735 736 typedef enum { 737 STHS34PF80_DRDY_PULSED = 0x0, 738 STHS34PF80_DRDY_LATCHED = 0x1, 739 } sths34pf80_drdy_mode_t; 740 int32_t sths34pf80_drdy_mode_set(stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t val); 741 int32_t sths34pf80_drdy_mode_get(stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t *val); 742 743 int32_t sths34pf80_func_cfg_write(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, uint8_t len); 744 int32_t sths34pf80_func_cfg_read(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, uint8_t len); 745 746 int32_t sths34pf80_presence_threshold_set(stmdev_ctx_t *ctx, uint16_t val); 747 int32_t sths34pf80_presence_threshold_get(stmdev_ctx_t *ctx, uint16_t *val); 748 749 int32_t sths34pf80_motion_threshold_set(stmdev_ctx_t *ctx, uint16_t val); 750 int32_t sths34pf80_motion_threshold_get(stmdev_ctx_t *ctx, uint16_t *val); 751 752 int32_t sths34pf80_tambient_shock_threshold_set(stmdev_ctx_t *ctx, uint16_t val); 753 int32_t sths34pf80_tambient_shock_threshold_get(stmdev_ctx_t *ctx, uint16_t *val); 754 755 int32_t sths34pf80_motion_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val); 756 int32_t sths34pf80_motion_hysteresis_get(stmdev_ctx_t *ctx, uint8_t *val); 757 758 int32_t sths34pf80_presence_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val); 759 int32_t sths34pf80_presence_hysteresis_get(stmdev_ctx_t *ctx, uint8_t *val); 760 761 int32_t sths34pf80_tambient_shock_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val); 762 int32_t sths34pf80_tambient_shock_hysteresis_get(stmdev_ctx_t *ctx, uint8_t *val); 763 764 int32_t sths34pf80_int_or_pulsed_set(stmdev_ctx_t *ctx, uint8_t val); 765 int32_t sths34pf80_int_or_pulsed_get(stmdev_ctx_t *ctx, uint8_t *val); 766 int32_t sths34pf80_tobject_algo_compensation_set(stmdev_ctx_t *ctx, uint8_t val); 767 int32_t sths34pf80_tobject_algo_compensation_get(stmdev_ctx_t *ctx, uint8_t *val); 768 int32_t sths34pf80_presence_abs_value_set(stmdev_ctx_t *ctx, uint8_t val); 769 int32_t sths34pf80_presence_abs_value_get(stmdev_ctx_t *ctx, uint8_t *val); 770 771 int32_t sths34pf80_algo_reset(stmdev_ctx_t *ctx); 772 773 #ifdef __cplusplus 774 } 775 #endif 776 777 #endif /*STHS34PF80_DRIVER_H */ 778 779 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 780
