1 /* 2 ****************************************************************************** 3 * @file asm330lhb_reg.h 4 * @author Sensor Solutions Software Team 5 * @brief This file contains all the functions prototypes for the 6 * asm330lhb_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2023 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ASM330LHB_REGS_H 23 #define ASM330LHB_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <math.h> 32 33 /** @addtogroup ASM330LHB 34 * @{ 35 * 36 */ 37 38 /** @defgroup Endianness definitions 39 * @{ 40 * 41 */ 42 43 #ifndef DRV_BYTE_ORDER 44 #ifndef __BYTE_ORDER__ 45 46 #define DRV_LITTLE_ENDIAN 1234 47 #define DRV_BIG_ENDIAN 4321 48 49 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 50 * by uncommenting the define which fits your platform endianness 51 */ 52 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 53 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 54 55 #else /* defined __BYTE_ORDER__ */ 56 57 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 58 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 59 #define DRV_BYTE_ORDER __BYTE_ORDER__ 60 61 #endif /* __BYTE_ORDER__*/ 62 #endif /* DRV_BYTE_ORDER */ 63 64 /** 65 * @} 66 * 67 */ 68 69 /** @defgroup STMicroelectronics sensors common types 70 * @{ 71 * 72 */ 73 74 #ifndef MEMS_SHARED_TYPES 75 #define MEMS_SHARED_TYPES 76 77 typedef struct 78 { 79 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 80 uint8_t bit0 : 1; 81 uint8_t bit1 : 1; 82 uint8_t bit2 : 1; 83 uint8_t bit3 : 1; 84 uint8_t bit4 : 1; 85 uint8_t bit5 : 1; 86 uint8_t bit6 : 1; 87 uint8_t bit7 : 1; 88 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 89 uint8_t bit7 : 1; 90 uint8_t bit6 : 1; 91 uint8_t bit5 : 1; 92 uint8_t bit4 : 1; 93 uint8_t bit3 : 1; 94 uint8_t bit2 : 1; 95 uint8_t bit1 : 1; 96 uint8_t bit0 : 1; 97 #endif /* DRV_BYTE_ORDER */ 98 } bitwise_t; 99 100 #define PROPERTY_DISABLE (0U) 101 #define PROPERTY_ENABLE (1U) 102 103 /** @addtogroup Interfaces_Functions 104 * @brief This section provide a set of functions used to read and 105 * write a generic register of the device. 106 * MANDATORY: return 0 -> no Error. 107 * @{ 108 * 109 */ 110 111 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 112 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 113 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 114 115 typedef struct 116 { 117 /** Component mandatory fields **/ 118 stmdev_write_ptr write_reg; 119 stmdev_read_ptr read_reg; 120 /** Component optional fields **/ 121 stmdev_mdelay_ptr mdelay; 122 /** Customizable optional pointer **/ 123 void *handle; 124 } stmdev_ctx_t; 125 126 /** 127 * @} 128 * 129 */ 130 131 #endif /* MEMS_SHARED_TYPES */ 132 133 #ifndef MEMS_UCF_SHARED_TYPES 134 #define MEMS_UCF_SHARED_TYPES 135 136 /** @defgroup Generic address-data structure definition 137 * @brief This structure is useful to load a predefined configuration 138 * of a sensor. 139 * You can create a sensor configuration by your own or using 140 * Unico / Unicleo tools available on STMicroelectronics 141 * web site. 142 * 143 * @{ 144 * 145 */ 146 147 typedef struct 148 { 149 uint8_t address; 150 uint8_t data; 151 } ucf_line_t; 152 153 /** 154 * @} 155 * 156 */ 157 158 #endif /* MEMS_UCF_SHARED_TYPES */ 159 160 /** 161 * @} 162 * 163 */ 164 165 /** @defgroup ASM330LHB Infos 166 * @{ 167 * 168 */ 169 170 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 171 #define ASM330LHB_I2C_ADD_L 0xD5U 172 #define ASM330LHB_I2C_ADD_H 0xD7U 173 174 /** Device Identification (Who am I) **/ 175 #define ASM330LHB_ID 0x6BU 176 177 /** 178 * @} 179 * 180 */ 181 182 #define ASM330LHB_FUNC_CFG_ACCESS 0x01U 183 typedef struct 184 { 185 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 186 uint8_t not_used_01 : 7; 187 uint8_t reg_access : 1; /* func_cfg_access */ 188 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 189 uint8_t reg_access : 1; /* func_cfg_access */ 190 uint8_t not_used_01 : 7; 191 #endif /* DRV_BYTE_ORDER */ 192 } asm330lhb_func_cfg_access_t; 193 194 #define ASM330LHB_PIN_CTRL 0x02U 195 typedef struct 196 { 197 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 198 uint8_t not_used_01 : 6; 199 uint8_t sdo_pu_en : 1; 200 uint8_t not_used_02 : 1; 201 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 202 uint8_t not_used_02 : 1; 203 uint8_t sdo_pu_en : 1; 204 uint8_t not_used_01 : 6; 205 #endif /* DRV_BYTE_ORDER */ 206 } asm330lhb_pin_ctrl_t; 207 208 #define ASM330LHB_FIFO_CTRL1 0x07U 209 typedef struct 210 { 211 uint8_t wtm : 8; 212 } asm330lhb_fifo_ctrl1_t; 213 214 #define ASM330LHB_FIFO_CTRL2 0x08U 215 typedef struct 216 { 217 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 218 uint8_t wtm : 1; 219 uint8_t not_used_01 : 3; 220 uint8_t odrchg_en : 1; 221 uint8_t not_used_02 : 2; 222 uint8_t stop_on_wtm : 1; 223 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 224 uint8_t stop_on_wtm : 1; 225 uint8_t not_used_02 : 2; 226 uint8_t odrchg_en : 1; 227 uint8_t not_used_01 : 3; 228 uint8_t wtm : 1; 229 #endif /* DRV_BYTE_ORDER */ 230 } asm330lhb_fifo_ctrl2_t; 231 232 #define ASM330LHB_FIFO_CTRL3 0x09U 233 typedef struct 234 { 235 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 236 uint8_t bdr_xl : 4; 237 uint8_t bdr_gy : 4; 238 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 239 uint8_t bdr_gy : 4; 240 uint8_t bdr_xl : 4; 241 #endif /* DRV_BYTE_ORDER */ 242 } asm330lhb_fifo_ctrl3_t; 243 244 #define ASM330LHB_FIFO_CTRL4 0x0AU 245 typedef struct 246 { 247 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 248 uint8_t fifo_mode : 3; 249 uint8_t not_used_01 : 1; 250 uint8_t odr_t_batch : 2; 251 uint8_t dec_ts_batch : 2; 252 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 253 uint8_t dec_ts_batch : 2; 254 uint8_t odr_t_batch : 2; 255 uint8_t not_used_01 : 1; 256 uint8_t fifo_mode : 3; 257 #endif /* DRV_BYTE_ORDER */ 258 } asm330lhb_fifo_ctrl4_t; 259 260 #define ASM330LHB_COUNTER_BDR_REG1 0x0BU 261 typedef struct 262 { 263 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 264 uint8_t cnt_bdr_th : 3; 265 uint8_t not_used_01 : 2; 266 uint8_t trig_counter_bdr : 1; 267 uint8_t rst_counter_bdr : 1; 268 uint8_t dataready_pulsed : 1; 269 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 270 uint8_t dataready_pulsed : 1; 271 uint8_t rst_counter_bdr : 1; 272 uint8_t trig_counter_bdr : 1; 273 uint8_t not_used_01 : 2; 274 uint8_t cnt_bdr_th : 3; 275 #endif /* DRV_BYTE_ORDER */ 276 } asm330lhb_counter_bdr_reg1_t; 277 278 #define ASM330LHB_COUNTER_BDR_REG2 0x0CU 279 typedef struct 280 { 281 uint8_t cnt_bdr_th : 8; 282 } asm330lhb_counter_bdr_reg2_t; 283 284 #define ASM330LHB_INT1_CTRL 0x0DU 285 typedef struct 286 { 287 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 288 uint8_t int1_drdy_xl : 1; 289 uint8_t int1_drdy_g : 1; 290 uint8_t int1_boot : 1; 291 uint8_t int1_fifo_th : 1; 292 uint8_t int1_fifo_ovr : 1; 293 uint8_t int1_fifo_full : 1; 294 uint8_t int1_cnt_bdr : 1; 295 uint8_t den_drdy_flag : 1; 296 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 297 uint8_t den_drdy_flag : 1; 298 uint8_t int1_cnt_bdr : 1; 299 uint8_t int1_fifo_full : 1; 300 uint8_t int1_fifo_ovr : 1; 301 uint8_t int1_fifo_th : 1; 302 uint8_t int1_boot : 1; 303 uint8_t int1_drdy_g : 1; 304 uint8_t int1_drdy_xl : 1; 305 #endif /* DRV_BYTE_ORDER */ 306 } asm330lhb_int1_ctrl_t; 307 308 #define ASM330LHB_INT2_CTRL 0x0EU 309 typedef struct 310 { 311 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 312 uint8_t int2_drdy_xl : 1; 313 uint8_t int2_drdy_g : 1; 314 uint8_t int2_drdy_temp : 1; 315 uint8_t int2_fifo_th : 1; 316 uint8_t int2_fifo_ovr : 1; 317 uint8_t int2_fifo_full : 1; 318 uint8_t int2_cnt_bdr : 1; 319 uint8_t not_used_01 : 1; 320 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 321 uint8_t not_used_01 : 1; 322 uint8_t int2_cnt_bdr : 1; 323 uint8_t int2_fifo_full : 1; 324 uint8_t int2_fifo_ovr : 1; 325 uint8_t int2_fifo_th : 1; 326 uint8_t int2_drdy_temp : 1; 327 uint8_t int2_drdy_g : 1; 328 uint8_t int2_drdy_xl : 1; 329 #endif /* DRV_BYTE_ORDER */ 330 } asm330lhb_int2_ctrl_t; 331 332 #define ASM330LHB_WHO_AM_I 0x0FU 333 334 #define ASM330LHB_CTRL1_XL 0x10U 335 typedef struct 336 { 337 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 338 uint8_t not_used_01 : 1; 339 uint8_t lpf2_xl_en : 1; 340 uint8_t fs_xl : 2; 341 uint8_t odr_xl : 4; 342 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 343 uint8_t odr_xl : 4; 344 uint8_t fs_xl : 2; 345 uint8_t lpf2_xl_en : 1; 346 uint8_t not_used_01 : 1; 347 #endif /* DRV_BYTE_ORDER */ 348 } asm330lhb_ctrl1_xl_t; 349 350 #define ASM330LHB_CTRL2_G 0x11U 351 typedef struct 352 { 353 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 354 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 355 uint8_t odr_g : 4; 356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 357 uint8_t odr_g : 4; 358 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 359 #endif /* DRV_BYTE_ORDER */ 360 } asm330lhb_ctrl2_g_t; 361 362 #define ASM330LHB_CTRL3_C 0x12U 363 typedef struct 364 { 365 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 366 uint8_t sw_reset : 1; 367 uint8_t not_used_01 : 1; 368 uint8_t if_inc : 1; 369 uint8_t sim : 1; 370 uint8_t pp_od : 1; 371 uint8_t h_lactive : 1; 372 uint8_t bdu : 1; 373 uint8_t boot : 1; 374 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 375 uint8_t boot : 1; 376 uint8_t bdu : 1; 377 uint8_t h_lactive : 1; 378 uint8_t pp_od : 1; 379 uint8_t sim : 1; 380 uint8_t if_inc : 1; 381 uint8_t not_used_01 : 1; 382 uint8_t sw_reset : 1; 383 #endif /* DRV_BYTE_ORDER */ 384 } asm330lhb_ctrl3_c_t; 385 386 #define ASM330LHB_CTRL4_C 0x13U 387 typedef struct 388 { 389 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 390 uint8_t not_used_01 : 1; 391 uint8_t lpf1_sel_g : 1; 392 uint8_t i2c_disable : 1; 393 uint8_t drdy_mask : 1; 394 uint8_t not_used_02 : 1; 395 uint8_t int2_on_int1 : 1; 396 uint8_t sleep_g : 1; 397 uint8_t not_used_03 : 1; 398 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 399 uint8_t not_used_03 : 1; 400 uint8_t sleep_g : 1; 401 uint8_t int2_on_int1 : 1; 402 uint8_t not_used_02 : 1; 403 uint8_t drdy_mask : 1; 404 uint8_t i2c_disable : 1; 405 uint8_t lpf1_sel_g : 1; 406 uint8_t not_used_01 : 1; 407 #endif /* DRV_BYTE_ORDER */ 408 } asm330lhb_ctrl4_c_t; 409 410 #define ASM330LHB_CTRL5_C 0x14U 411 typedef struct 412 { 413 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 414 uint8_t st_xl : 2; 415 uint8_t st_g : 2; 416 uint8_t not_used_01 : 1; 417 uint8_t rounding : 2; 418 uint8_t not_used_02 : 1; 419 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 420 uint8_t not_used_02 : 1; 421 uint8_t rounding : 2; 422 uint8_t not_used_01 : 1; 423 uint8_t st_g : 2; 424 uint8_t st_xl : 2; 425 #endif /* DRV_BYTE_ORDER */ 426 } asm330lhb_ctrl5_c_t; 427 428 #define ASM330LHB_CTRL6_C 0x15U 429 typedef struct 430 { 431 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 432 uint8_t ftype : 3; 433 uint8_t usr_off_w : 1; 434 uint8_t xl_hm_mode : 1; 435 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 436 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 437 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 438 uint8_t xl_hm_mode : 1; 439 uint8_t usr_off_w : 1; 440 uint8_t ftype : 3; 441 #endif /* DRV_BYTE_ORDER */ 442 } asm330lhb_ctrl6_c_t; 443 444 #define ASM330LHB_CTRL7_G 0x16U 445 typedef struct 446 { 447 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 448 uint8_t not_used_00 : 1; 449 uint8_t usr_off_on_out : 1; 450 uint8_t not_used_01 : 2; 451 uint8_t hpm_g : 2; 452 uint8_t hp_en_g : 1; 453 uint8_t g_hm_mode : 1; 454 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 455 uint8_t g_hm_mode : 1; 456 uint8_t hp_en_g : 1; 457 uint8_t hpm_g : 2; 458 uint8_t not_used_01 : 2; 459 uint8_t usr_off_on_out : 1; 460 uint8_t not_used_00 : 1; 461 #endif /* DRV_BYTE_ORDER */ 462 } asm330lhb_ctrl7_g_t; 463 464 #define ASM330LHB_CTRL8_XL 0x17U 465 typedef struct 466 { 467 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 468 uint8_t low_pass_on_6d : 1; 469 uint8_t not_used_01 : 1; 470 uint8_t hp_slope_xl_en : 1; 471 uint8_t fastsettl_mode_xl : 1; 472 uint8_t hp_ref_mode_xl : 1; 473 uint8_t hpcf_xl : 3; 474 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 475 uint8_t hpcf_xl : 3; 476 uint8_t hp_ref_mode_xl : 1; 477 uint8_t fastsettl_mode_xl : 1; 478 uint8_t hp_slope_xl_en : 1; 479 uint8_t not_used_01 : 1; 480 uint8_t low_pass_on_6d : 1; 481 #endif /* DRV_BYTE_ORDER */ 482 } asm330lhb_ctrl8_xl_t; 483 484 #define ASM330LHB_CTRL9_XL 0x18U 485 typedef struct 486 { 487 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 488 uint8_t not_used_01 : 1; 489 uint8_t i3c_disable : 1; 490 uint8_t den_lh : 1; 491 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 492 uint8_t den_z : 1; 493 uint8_t den_y : 1; 494 uint8_t den_x : 1; 495 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 496 uint8_t den_x : 1; 497 uint8_t den_y : 1; 498 uint8_t den_z : 1; 499 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 500 uint8_t den_lh : 1; 501 uint8_t i3c_disable : 1; 502 uint8_t not_used_01 : 1; 503 #endif /* DRV_BYTE_ORDER */ 504 } asm330lhb_ctrl9_xl_t; 505 506 #define ASM330LHB_CTRL10_C 0x19U 507 typedef struct 508 { 509 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 510 uint8_t not_used_01 : 5; 511 uint8_t timestamp_en : 1; 512 uint8_t not_used_02 : 2; 513 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 514 uint8_t not_used_02 : 2; 515 uint8_t timestamp_en : 1; 516 uint8_t not_used_01 : 5; 517 #endif /* DRV_BYTE_ORDER */ 518 } asm330lhb_ctrl10_c_t; 519 520 #define ASM330LHB_ALL_INT_SRC 0x1AU 521 typedef struct 522 { 523 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 524 uint8_t ff_ia : 1; 525 uint8_t wu_ia : 1; 526 uint8_t not_used_00 : 2; 527 uint8_t d6d_ia : 1; 528 uint8_t sleep_change_ia : 1; 529 uint8_t not_used_01 : 1; 530 uint8_t timestamp_endcount : 1; 531 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 532 uint8_t timestamp_endcount : 1; 533 uint8_t not_used_01 : 1; 534 uint8_t sleep_change_ia : 1; 535 uint8_t d6d_ia : 1; 536 uint8_t not_used_00 : 2; 537 uint8_t wu_ia : 1; 538 uint8_t ff_ia : 1; 539 #endif /* DRV_BYTE_ORDER */ 540 } asm330lhb_all_int_src_t; 541 542 #define ASM330LHB_WAKE_UP_SRC 0x1BU 543 typedef struct 544 { 545 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 546 uint8_t z_wu : 1; 547 uint8_t y_wu : 1; 548 uint8_t x_wu : 1; 549 uint8_t wu_ia : 1; 550 uint8_t sleep_state : 1; 551 uint8_t ff_ia : 1; 552 uint8_t sleep_change_ia : 1; 553 uint8_t not_used_01 : 1; 554 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 555 uint8_t not_used_01 : 1; 556 uint8_t sleep_change_ia : 1; 557 uint8_t ff_ia : 1; 558 uint8_t sleep_state : 1; 559 uint8_t wu_ia : 1; 560 uint8_t x_wu : 1; 561 uint8_t y_wu : 1; 562 uint8_t z_wu : 1; 563 #endif /* DRV_BYTE_ORDER */ 564 } asm330lhb_wake_up_src_t; 565 566 #define ASM330LHB_D6D_SRC 0x1DU 567 typedef struct 568 { 569 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 570 uint8_t xl : 1; 571 uint8_t xh : 1; 572 uint8_t yl : 1; 573 uint8_t yh : 1; 574 uint8_t zl : 1; 575 uint8_t zh : 1; 576 uint8_t d6d_ia : 1; 577 uint8_t den_drdy : 1; 578 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 579 uint8_t den_drdy : 1; 580 uint8_t d6d_ia : 1; 581 uint8_t zh : 1; 582 uint8_t zl : 1; 583 uint8_t yh : 1; 584 uint8_t yl : 1; 585 uint8_t xh : 1; 586 uint8_t xl : 1; 587 #endif /* DRV_BYTE_ORDER */ 588 } asm330lhb_d6d_src_t; 589 590 #define ASM330LHB_STATUS_REG 0x1EU 591 typedef struct 592 { 593 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 594 uint8_t xlda : 1; 595 uint8_t gda : 1; 596 uint8_t tda : 1; 597 uint8_t boot_check_fail : 1; 598 uint8_t not_used_01 : 4; 599 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 600 uint8_t not_used_01 : 4; 601 uint8_t boot_check_fail : 1; 602 uint8_t tda : 1; 603 uint8_t gda : 1; 604 uint8_t xlda : 1; 605 #endif /* DRV_BYTE_ORDER */ 606 } asm330lhb_status_reg_t; 607 608 #define ASM330LHB_OUT_TEMP_L 0x20U 609 #define ASM330LHB_OUT_TEMP_H 0x21U 610 #define ASM330LHB_OUTX_L_G 0x22U 611 #define ASM330LHB_OUTX_H_G 0x23U 612 #define ASM330LHB_OUTY_L_G 0x24U 613 #define ASM330LHB_OUTY_H_G 0x25U 614 #define ASM330LHB_OUTZ_L_G 0x26U 615 #define ASM330LHB_OUTZ_H_G 0x27U 616 #define ASM330LHB_OUTX_L_A 0x28U 617 #define ASM330LHB_OUTX_H_A 0x29U 618 #define ASM330LHB_OUTY_L_A 0x2AU 619 #define ASM330LHB_OUTY_H_A 0x2BU 620 #define ASM330LHB_OUTZ_L_A 0x2CU 621 #define ASM330LHB_OUTZ_H_A 0x2DU 622 #define ASM330LHB_EMB_FUNC_STATUS_MAINPAGE 0x35U 623 typedef struct 624 { 625 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 626 uint8_t not_used_01 : 7; 627 uint8_t is_fsm_lc : 1; 628 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 629 uint8_t is_fsm_lc : 1; 630 uint8_t not_used_01 : 7; 631 #endif /* DRV_BYTE_ORDER */ 632 } asm330lhb_emb_func_status_mainpage_t; 633 634 #define ASM330LHB_FSM_STATUS_A_MAINPAGE 0x36U 635 typedef struct 636 { 637 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 638 uint8_t is_fsm1 : 1; 639 uint8_t is_fsm2 : 1; 640 uint8_t is_fsm3 : 1; 641 uint8_t is_fsm4 : 1; 642 uint8_t is_fsm5 : 1; 643 uint8_t is_fsm6 : 1; 644 uint8_t is_fsm7 : 1; 645 uint8_t is_fsm8 : 1; 646 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 647 uint8_t is_fsm8 : 1; 648 uint8_t is_fsm7 : 1; 649 uint8_t is_fsm6 : 1; 650 uint8_t is_fsm5 : 1; 651 uint8_t is_fsm4 : 1; 652 uint8_t is_fsm3 : 1; 653 uint8_t is_fsm2 : 1; 654 uint8_t is_fsm1 : 1; 655 #endif /* DRV_BYTE_ORDER */ 656 } asm330lhb_fsm_status_a_mainpage_t; 657 658 #define ASM330LHB_FSM_STATUS_B_MAINPAGE 0x37U 659 typedef struct 660 { 661 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 662 uint8_t is_fsm9 : 1; 663 uint8_t is_fsm10 : 1; 664 uint8_t is_fsm11 : 1; 665 uint8_t is_fsm12 : 1; 666 uint8_t is_fsm13 : 1; 667 uint8_t is_fsm14 : 1; 668 uint8_t is_fsm15 : 1; 669 uint8_t is_fsm16 : 1; 670 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 671 uint8_t is_fsm16 : 1; 672 uint8_t is_fsm15 : 1; 673 uint8_t is_fsm14 : 1; 674 uint8_t is_fsm13 : 1; 675 uint8_t is_fsm12 : 1; 676 uint8_t is_fsm11 : 1; 677 uint8_t is_fsm10 : 1; 678 uint8_t is_fsm9 : 1; 679 #endif /* DRV_BYTE_ORDER */ 680 } asm330lhb_fsm_status_b_mainpage_t; 681 682 #define ASM330LHB_MLC_STATUS_MAINPAGE 0x38U 683 typedef struct 684 { 685 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 686 uint8_t is_mlc1 : 1; 687 uint8_t is_mlc2 : 1; 688 uint8_t is_mlc3 : 1; 689 uint8_t is_mlc4 : 1; 690 uint8_t is_mlc5 : 1; 691 uint8_t is_mlc6 : 1; 692 uint8_t is_mlc7 : 1; 693 uint8_t is_mlc8 : 1; 694 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 695 uint8_t is_mlc8 : 1; 696 uint8_t is_mlc7 : 1; 697 uint8_t is_mlc6 : 1; 698 uint8_t is_mlc5 : 1; 699 uint8_t is_mlc4 : 1; 700 uint8_t is_mlc3 : 1; 701 uint8_t is_mlc2 : 1; 702 uint8_t is_mlc1 : 1; 703 #endif /* DRV_BYTE_ORDER */ 704 } asm330lhb_mlc_status_mainpage_t; 705 706 #define ASM330LHB_FIFO_STATUS1 0x3AU 707 typedef struct 708 { 709 uint8_t diff_fifo : 8; 710 } asm330lhb_fifo_status1_t; 711 712 #define ASM330LHB_FIFO_STATUS2 0x3BU 713 typedef struct 714 { 715 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 716 uint8_t diff_fifo : 2; 717 uint8_t not_used_01 : 1; 718 uint8_t over_run_latched : 1; 719 uint8_t counter_bdr_ia : 1; 720 uint8_t fifo_full_ia : 1; 721 uint8_t fifo_ovr_ia : 1; 722 uint8_t fifo_wtm_ia : 1; 723 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 724 uint8_t fifo_wtm_ia : 1; 725 uint8_t fifo_ovr_ia : 1; 726 uint8_t fifo_full_ia : 1; 727 uint8_t counter_bdr_ia : 1; 728 uint8_t over_run_latched : 1; 729 uint8_t not_used_01 : 1; 730 uint8_t diff_fifo : 2; 731 #endif /* DRV_BYTE_ORDER */ 732 } asm330lhb_fifo_status2_t; 733 734 #define ASM330LHB_TIMESTAMP0 0x40U 735 #define ASM330LHB_TIMESTAMP1 0x41U 736 #define ASM330LHB_TIMESTAMP2 0x42U 737 #define ASM330LHB_TIMESTAMP3 0x43U 738 #define ASM330LHB_INT_CFG0 0x56U 739 typedef struct 740 { 741 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 742 uint8_t lir : 1; 743 uint8_t not_used_01 : 3; 744 uint8_t slope_fds : 1; 745 uint8_t sleep_status_on_int : 1; 746 uint8_t int_clr_on_read : 1; 747 uint8_t not_used_02 : 1; 748 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 749 uint8_t not_used_02 : 1; 750 uint8_t int_clr_on_read : 1; 751 uint8_t sleep_status_on_int : 1; 752 uint8_t slope_fds : 1; 753 uint8_t not_used_01 : 3; 754 uint8_t lir : 1; 755 #endif /* DRV_BYTE_ORDER */ 756 } asm330lhb_int_cfg0_t; 757 758 #define ASM330LHB_INT_CFG1 0x58U 759 typedef struct 760 { 761 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 762 uint8_t not_used_01 : 5; 763 uint8_t inact_en : 2; 764 uint8_t interrupts_enable : 1; 765 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 766 uint8_t interrupts_enable : 1; 767 uint8_t inact_en : 2; 768 uint8_t not_used_01 : 5; 769 #endif /* DRV_BYTE_ORDER */ 770 } asm330lhb_int_cfg1_t; 771 772 #define ASM330LHB_THS_6D 0x59U 773 typedef struct 774 { 775 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 776 uint8_t not_used_01 : 5; 777 uint8_t sixd_ths : 2; 778 uint8_t d4d_en : 1; 779 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 780 uint8_t d4d_en : 1; 781 uint8_t sixd_ths : 2; 782 uint8_t not_used_01 : 5; 783 #endif /* DRV_BYTE_ORDER */ 784 } asm330lhb_ths_6d_t; 785 786 #define ASM330LHB_WAKE_UP_THS 0x5BU 787 typedef struct 788 { 789 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 790 uint8_t wk_ths : 6; 791 uint8_t usr_off_on_wu : 1; 792 uint8_t not_used_01 : 1; 793 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 794 uint8_t not_used_01 : 1; 795 uint8_t usr_off_on_wu : 1; 796 uint8_t wk_ths : 6; 797 #endif /* DRV_BYTE_ORDER */ 798 } asm330lhb_wake_up_ths_t; 799 800 #define ASM330LHB_WAKE_UP_DUR 0x5CU 801 typedef struct 802 { 803 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 804 uint8_t sleep_dur : 4; 805 uint8_t wake_ths_w : 1; 806 uint8_t wake_dur : 2; 807 uint8_t ff_dur : 1; 808 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 809 uint8_t ff_dur : 1; 810 uint8_t wake_dur : 2; 811 uint8_t wake_ths_w : 1; 812 uint8_t sleep_dur : 4; 813 #endif /* DRV_BYTE_ORDER */ 814 } asm330lhb_wake_up_dur_t; 815 816 #define ASM330LHB_FREE_FALL 0x5DU 817 typedef struct 818 { 819 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 820 uint8_t ff_ths : 3; 821 uint8_t ff_dur : 5; 822 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 823 uint8_t ff_dur : 5; 824 uint8_t ff_ths : 3; 825 #endif /* DRV_BYTE_ORDER */ 826 } asm330lhb_free_fall_t; 827 828 #define ASM330LHB_MD1_CFG 0x5EU 829 typedef struct 830 { 831 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 832 uint8_t not_used_00 : 1; 833 uint8_t int1_emb_func : 1; 834 uint8_t int1_6d : 1; 835 uint8_t not_used_01 : 1; 836 uint8_t int1_ff : 1; 837 uint8_t int1_wu : 1; 838 uint8_t not_used_02 : 1; 839 uint8_t int1_sleep_change : 1; 840 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 841 uint8_t int1_sleep_change : 1; 842 uint8_t not_used_02 : 1; 843 uint8_t int1_wu : 1; 844 uint8_t int1_ff : 1; 845 uint8_t not_used_01 : 1; 846 uint8_t int1_6d : 1; 847 uint8_t int1_emb_func : 1; 848 uint8_t not_used_00 : 1; 849 #endif /* DRV_BYTE_ORDER */ 850 } asm330lhb_md1_cfg_t; 851 852 #define ASM330LHB_MD2_CFG 0x5FU 853 typedef struct 854 { 855 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 856 uint8_t int2_timestamp : 1; 857 uint8_t int2_emb_func : 1; 858 uint8_t int2_6d : 1; 859 uint8_t not_used_01 : 1; 860 uint8_t int2_ff : 1; 861 uint8_t int2_wu : 1; 862 uint8_t not_used_02 : 1; 863 uint8_t int2_sleep_change : 1; 864 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 865 uint8_t int2_sleep_change : 1; 866 uint8_t not_used_02 : 1; 867 uint8_t int2_wu : 1; 868 uint8_t int2_ff : 1; 869 uint8_t not_used_01 : 1; 870 uint8_t int2_6d : 1; 871 uint8_t int2_emb_func : 1; 872 uint8_t int2_timestamp : 1; 873 #endif /* DRV_BYTE_ORDER */ 874 } asm330lhb_md2_cfg_t; 875 876 #define ASM330LHB_I3C_BUS_AVB 0x62U 877 typedef struct 878 { 879 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 880 uint8_t pd_dis_int1 : 1; 881 uint8_t not_used_01 : 2; 882 uint8_t i3c_bus_avb_sel : 2; 883 uint8_t not_used_02 : 3; 884 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 885 uint8_t not_used_02 : 3; 886 uint8_t i3c_bus_avb_sel : 2; 887 uint8_t not_used_01 : 2; 888 uint8_t pd_dis_int1 : 1; 889 #endif /* DRV_BYTE_ORDER */ 890 } asm330lhb_i3c_bus_avb_t; 891 892 #define ASM330LHB_INTERNAL_FREQ_FINE 0x63U 893 typedef struct 894 { 895 uint8_t freq_fine : 8; 896 } asm330lhb_internal_freq_fine_t; 897 898 #define ASM330LHB_X_OFS_USR 0x73U 899 #define ASM330LHB_Y_OFS_USR 0x74U 900 #define ASM330LHB_Z_OFS_USR 0x75U 901 #define ASM330LHB_FIFO_DATA_OUT_TAG 0x78U 902 typedef struct 903 { 904 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 905 uint8_t tag_parity : 1; 906 uint8_t tag_cnt : 2; 907 uint8_t tag_sensor : 5; 908 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 909 uint8_t tag_sensor : 5; 910 uint8_t tag_cnt : 2; 911 uint8_t tag_parity : 1; 912 #endif /* DRV_BYTE_ORDER */ 913 } asm330lhb_fifo_data_out_tag_t; 914 915 #define ASM330LHB_FIFO_DATA_OUT_X_L 0x79U 916 #define ASM330LHB_FIFO_DATA_OUT_X_H 0x7AU 917 #define ASM330LHB_FIFO_DATA_OUT_Y_L 0x7BU 918 #define ASM330LHB_FIFO_DATA_OUT_Y_H 0x7CU 919 #define ASM330LHB_FIFO_DATA_OUT_Z_L 0x7DU 920 #define ASM330LHB_FIFO_DATA_OUT_Z_H 0x7EU 921 922 #define ASM330LHB_PAGE_SEL 0x02U 923 typedef struct 924 { 925 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 926 uint8_t not_used_01 : 1; 927 uint8_t emb_func_clk_dis : 1; 928 uint8_t not_used_02 : 2; 929 uint8_t page_sel : 4; 930 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 931 uint8_t page_sel : 4; 932 uint8_t not_used_02 : 2; 933 uint8_t emb_func_clk_dis : 1; 934 uint8_t not_used_01 : 1; 935 #endif /* DRV_BYTE_ORDER */ 936 } asm330lhb_page_sel_t; 937 938 #define ASM330LHB_EMB_FUNC_EN_B 0x05U 939 typedef struct 940 { 941 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 942 uint8_t fsm_en : 1; 943 uint8_t not_used_01 : 3; 944 uint8_t mlc_en : 1; 945 uint8_t not_used_02 : 3; 946 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 947 uint8_t not_used_02 : 3; 948 uint8_t mlc_en : 1; 949 uint8_t not_used_01 : 3; 950 uint8_t fsm_en : 1; 951 #endif /* DRV_BYTE_ORDER */ 952 } asm330lhb_emb_func_en_b_t; 953 954 #define ASM330LHB_PAGE_ADDRESS 0x08U 955 typedef struct 956 { 957 uint8_t page_addr : 8; 958 } asm330lhb_page_address_t; 959 960 #define ASM330LHB_PAGE_VALUE 0x09U 961 typedef struct 962 { 963 uint8_t page_value : 8; 964 } asm330lhb_page_value_t; 965 966 #define ASM330LHB_EMB_FUNC_INT1 0x0AU 967 typedef struct 968 { 969 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 970 uint8_t not_used_01 : 7; 971 uint8_t int1_fsm_lc : 1; 972 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 973 uint8_t int1_fsm_lc : 1; 974 uint8_t not_used_01 : 7; 975 #endif /* DRV_BYTE_ORDER */ 976 } asm330lhb_emb_func_int1_t; 977 978 #define ASM330LHB_FSM_INT1_A 0x0BU 979 typedef struct 980 { 981 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 982 uint8_t int1_fsm1 : 1; 983 uint8_t int1_fsm2 : 1; 984 uint8_t int1_fsm3 : 1; 985 uint8_t int1_fsm4 : 1; 986 uint8_t int1_fsm5 : 1; 987 uint8_t int1_fsm6 : 1; 988 uint8_t int1_fsm7 : 1; 989 uint8_t int1_fsm8 : 1; 990 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 991 uint8_t int1_fsm8 : 1; 992 uint8_t int1_fsm7 : 1; 993 uint8_t int1_fsm6 : 1; 994 uint8_t int1_fsm5 : 1; 995 uint8_t int1_fsm4 : 1; 996 uint8_t int1_fsm3 : 1; 997 uint8_t int1_fsm2 : 1; 998 uint8_t int1_fsm1 : 1; 999 #endif /* DRV_BYTE_ORDER */ 1000 } asm330lhb_fsm_int1_a_t; 1001 1002 #define ASM330LHB_FSM_INT1_B 0x0CU 1003 typedef struct 1004 { 1005 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1006 uint8_t int1_fsm9 : 1; 1007 uint8_t int1_fsm10 : 1; 1008 uint8_t int1_fsm11 : 1; 1009 uint8_t int1_fsm12 : 1; 1010 uint8_t int1_fsm13 : 1; 1011 uint8_t int1_fsm14 : 1; 1012 uint8_t int1_fsm15 : 1; 1013 uint8_t int1_fsm16 : 1; 1014 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1015 uint8_t int1_fsm16 : 1; 1016 uint8_t int1_fsm15 : 1; 1017 uint8_t int1_fsm14 : 1; 1018 uint8_t int1_fsm13 : 1; 1019 uint8_t int1_fsm12 : 1; 1020 uint8_t int1_fsm11 : 1; 1021 uint8_t int1_fsm10 : 1; 1022 uint8_t int1_fsm9 : 1; 1023 #endif /* DRV_BYTE_ORDER */ 1024 } asm330lhb_fsm_int1_b_t; 1025 1026 #define ASM330LHB_MLC_INT1 0x0DU 1027 typedef struct 1028 { 1029 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1030 uint8_t int1_mlc1 : 1; 1031 uint8_t int1_mlc2 : 1; 1032 uint8_t int1_mlc3 : 1; 1033 uint8_t int1_mlc4 : 1; 1034 uint8_t int1_mlc5 : 1; 1035 uint8_t int1_mlc6 : 1; 1036 uint8_t int1_mlc7 : 1; 1037 uint8_t int1_mlc8 : 1; 1038 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1039 uint8_t int1_mlc8 : 1; 1040 uint8_t int1_mlc7 : 1; 1041 uint8_t int1_mlc6 : 1; 1042 uint8_t int1_mlc5 : 1; 1043 uint8_t int1_mlc4 : 1; 1044 uint8_t int1_mlc3 : 1; 1045 uint8_t int1_mlc2 : 1; 1046 uint8_t int1_mlc1 : 1; 1047 #endif /* DRV_BYTE_ORDER */ 1048 } asm330lhb_mlc_int1_t; 1049 1050 #define ASM330LHB_EMB_FUNC_INT2 0x0EU 1051 typedef struct 1052 { 1053 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1054 uint8_t not_used_01 : 7; 1055 uint8_t int2_fsm_lc : 1; 1056 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1057 uint8_t int2_fsm_lc : 1; 1058 uint8_t not_used_01 : 7; 1059 #endif /* DRV_BYTE_ORDER */ 1060 } asm330lhb_emb_func_int2_t; 1061 1062 #define ASM330LHB_FSM_INT2_A 0x0FU 1063 typedef struct 1064 { 1065 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1066 uint8_t int2_fsm1 : 1; 1067 uint8_t int2_fsm2 : 1; 1068 uint8_t int2_fsm3 : 1; 1069 uint8_t int2_fsm4 : 1; 1070 uint8_t int2_fsm5 : 1; 1071 uint8_t int2_fsm6 : 1; 1072 uint8_t int2_fsm7 : 1; 1073 uint8_t int2_fsm8 : 1; 1074 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1075 uint8_t int2_fsm8 : 1; 1076 uint8_t int2_fsm7 : 1; 1077 uint8_t int2_fsm6 : 1; 1078 uint8_t int2_fsm5 : 1; 1079 uint8_t int2_fsm4 : 1; 1080 uint8_t int2_fsm3 : 1; 1081 uint8_t int2_fsm2 : 1; 1082 uint8_t int2_fsm1 : 1; 1083 #endif /* DRV_BYTE_ORDER */ 1084 } asm330lhb_fsm_int2_a_t; 1085 1086 #define ASM330LHB_FSM_INT2_B 0x10U 1087 typedef struct 1088 { 1089 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1090 uint8_t int2_fsm9 : 1; 1091 uint8_t int2_fsm10 : 1; 1092 uint8_t int2_fsm11 : 1; 1093 uint8_t int2_fsm12 : 1; 1094 uint8_t int2_fsm13 : 1; 1095 uint8_t int2_fsm14 : 1; 1096 uint8_t int2_fsm15 : 1; 1097 uint8_t int2_fsm16 : 1; 1098 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1099 uint8_t int2_fsm16 : 1; 1100 uint8_t int2_fsm15 : 1; 1101 uint8_t int2_fsm14 : 1; 1102 uint8_t int2_fsm13 : 1; 1103 uint8_t int2_fsm12 : 1; 1104 uint8_t int2_fsm11 : 1; 1105 uint8_t int2_fsm10 : 1; 1106 uint8_t int2_fsm9 : 1; 1107 #endif /* DRV_BYTE_ORDER */ 1108 } asm330lhb_fsm_int2_b_t; 1109 1110 #define ASM330LHB_MLC_INT2 0x11U 1111 typedef struct 1112 { 1113 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1114 uint8_t int2_mlc1 : 1; 1115 uint8_t int2_mlc2 : 1; 1116 uint8_t int2_mlc3 : 1; 1117 uint8_t int2_mlc4 : 1; 1118 uint8_t int2_mlc5 : 1; 1119 uint8_t int2_mlc6 : 1; 1120 uint8_t int2_mlc7 : 1; 1121 uint8_t int2_mlc8 : 1; 1122 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1123 uint8_t int2_mlc8 : 1; 1124 uint8_t int2_mlc7 : 1; 1125 uint8_t int2_mlc6 : 1; 1126 uint8_t int2_mlc5 : 1; 1127 uint8_t int2_mlc4 : 1; 1128 uint8_t int2_mlc3 : 1; 1129 uint8_t int2_mlc2 : 1; 1130 uint8_t int2_mlc1 : 1; 1131 #endif /* DRV_BYTE_ORDER */ 1132 } asm330lhb_mlc_int2_t; 1133 1134 #define ASM330LHB_EMB_FUNC_STATUS 0x12U 1135 typedef struct 1136 { 1137 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1138 uint8_t not_used_01 : 7; 1139 uint8_t is_fsm_lc : 1; 1140 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1141 uint8_t is_fsm_lc : 1; 1142 uint8_t not_used_01 : 7; 1143 #endif /* DRV_BYTE_ORDER */ 1144 } asm330lhb_emb_func_status_t; 1145 1146 #define ASM330LHB_FSM_STATUS_A 0x13U 1147 typedef struct 1148 { 1149 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1150 uint8_t is_fsm1 : 1; 1151 uint8_t is_fsm2 : 1; 1152 uint8_t is_fsm3 : 1; 1153 uint8_t is_fsm4 : 1; 1154 uint8_t is_fsm5 : 1; 1155 uint8_t is_fsm6 : 1; 1156 uint8_t is_fsm7 : 1; 1157 uint8_t is_fsm8 : 1; 1158 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1159 uint8_t is_fsm8 : 1; 1160 uint8_t is_fsm7 : 1; 1161 uint8_t is_fsm6 : 1; 1162 uint8_t is_fsm5 : 1; 1163 uint8_t is_fsm4 : 1; 1164 uint8_t is_fsm3 : 1; 1165 uint8_t is_fsm2 : 1; 1166 uint8_t is_fsm1 : 1; 1167 #endif /* DRV_BYTE_ORDER */ 1168 } asm330lhb_fsm_status_a_t; 1169 1170 #define ASM330LHB_FSM_STATUS_B 0x14U 1171 typedef struct 1172 { 1173 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1174 uint8_t is_fsm9 : 1; 1175 uint8_t is_fsm10 : 1; 1176 uint8_t is_fsm11 : 1; 1177 uint8_t is_fsm12 : 1; 1178 uint8_t is_fsm13 : 1; 1179 uint8_t is_fsm14 : 1; 1180 uint8_t is_fsm15 : 1; 1181 uint8_t is_fsm16 : 1; 1182 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1183 uint8_t is_fsm16 : 1; 1184 uint8_t is_fsm15 : 1; 1185 uint8_t is_fsm14 : 1; 1186 uint8_t is_fsm13 : 1; 1187 uint8_t is_fsm12 : 1; 1188 uint8_t is_fsm11 : 1; 1189 uint8_t is_fsm10 : 1; 1190 uint8_t is_fsm9 : 1; 1191 #endif /* DRV_BYTE_ORDER */ 1192 } asm330lhb_fsm_status_b_t; 1193 1194 #define ASM330LHB_MLC_STATUS 0x15U 1195 typedef struct 1196 { 1197 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1198 uint8_t is_mlc1 : 1; 1199 uint8_t is_mlc2 : 1; 1200 uint8_t is_mlc3 : 1; 1201 uint8_t is_mlc4 : 1; 1202 uint8_t is_mlc5 : 1; 1203 uint8_t is_mlc6 : 1; 1204 uint8_t is_mlc7 : 1; 1205 uint8_t is_mlc8 : 1; 1206 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1207 uint8_t is_mlc8 : 1; 1208 uint8_t is_mlc7 : 1; 1209 uint8_t is_mlc6 : 1; 1210 uint8_t is_mlc5 : 1; 1211 uint8_t is_mlc4 : 1; 1212 uint8_t is_mlc3 : 1; 1213 uint8_t is_mlc2 : 1; 1214 uint8_t is_mlc1 : 1; 1215 #endif /* DRV_BYTE_ORDER */ 1216 } asm330lhb_mlc_status_t; 1217 1218 #define ASM330LHB_PAGE_RW 0x17U 1219 typedef struct 1220 { 1221 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1222 uint8_t not_used_01 : 5; 1223 uint8_t page_rw : 2; /* page_write + page_read */ 1224 uint8_t emb_func_lir : 1; 1225 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1226 uint8_t emb_func_lir : 1; 1227 uint8_t page_rw : 2; /* page_write + page_read */ 1228 uint8_t not_used_01 : 5; 1229 #endif /* DRV_BYTE_ORDER */ 1230 } asm330lhb_page_rw_t; 1231 1232 #define ASM330LHB_FSM_ENABLE_A 0x46U 1233 typedef struct 1234 { 1235 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1236 uint8_t fsm1_en : 1; 1237 uint8_t fsm2_en : 1; 1238 uint8_t fsm3_en : 1; 1239 uint8_t fsm4_en : 1; 1240 uint8_t fsm5_en : 1; 1241 uint8_t fsm6_en : 1; 1242 uint8_t fsm7_en : 1; 1243 uint8_t fsm8_en : 1; 1244 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1245 uint8_t fsm8_en : 1; 1246 uint8_t fsm7_en : 1; 1247 uint8_t fsm6_en : 1; 1248 uint8_t fsm5_en : 1; 1249 uint8_t fsm4_en : 1; 1250 uint8_t fsm3_en : 1; 1251 uint8_t fsm2_en : 1; 1252 uint8_t fsm1_en : 1; 1253 #endif /* DRV_BYTE_ORDER */ 1254 } asm330lhb_fsm_enable_a_t; 1255 1256 #define ASM330LHB_FSM_ENABLE_B 0x47U 1257 typedef struct 1258 { 1259 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1260 uint8_t fsm9_en : 1; 1261 uint8_t fsm10_en : 1; 1262 uint8_t fsm11_en : 1; 1263 uint8_t fsm12_en : 1; 1264 uint8_t fsm13_en : 1; 1265 uint8_t fsm14_en : 1; 1266 uint8_t fsm15_en : 1; 1267 uint8_t fsm16_en : 1; 1268 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1269 uint8_t fsm16_en : 1; 1270 uint8_t fsm15_en : 1; 1271 uint8_t fsm14_en : 1; 1272 uint8_t fsm13_en : 1; 1273 uint8_t fsm12_en : 1; 1274 uint8_t fsm11_en : 1; 1275 uint8_t fsm10_en : 1; 1276 uint8_t fsm9_en : 1; 1277 #endif /* DRV_BYTE_ORDER */ 1278 } asm330lhb_fsm_enable_b_t; 1279 1280 #define ASM330LHB_FSM_LONG_COUNTER_L 0x48U 1281 #define ASM330LHB_FSM_LONG_COUNTER_H 0x49U 1282 #define ASM330LHB_FSM_LONG_COUNTER_CLEAR 0x4AU 1283 typedef struct 1284 { 1285 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1286 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1287 uint8_t not_used_01 : 6; 1288 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1289 uint8_t not_used_01 : 6; 1290 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1291 #endif /* DRV_BYTE_ORDER */ 1292 } asm330lhb_fsm_long_counter_clear_t; 1293 1294 #define ASM330LHB_FSM_OUTS1 0x4CU 1295 typedef struct 1296 { 1297 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1298 uint8_t n_v : 1; 1299 uint8_t p_v : 1; 1300 uint8_t n_z : 1; 1301 uint8_t p_z : 1; 1302 uint8_t n_y : 1; 1303 uint8_t p_y : 1; 1304 uint8_t n_x : 1; 1305 uint8_t p_x : 1; 1306 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1307 uint8_t p_x : 1; 1308 uint8_t n_x : 1; 1309 uint8_t p_y : 1; 1310 uint8_t n_y : 1; 1311 uint8_t p_z : 1; 1312 uint8_t n_z : 1; 1313 uint8_t p_v : 1; 1314 uint8_t n_v : 1; 1315 #endif /* DRV_BYTE_ORDER */ 1316 } asm330lhb_fsm_outs1_t; 1317 1318 #define ASM330LHB_FSM_OUTS2 0x4DU 1319 typedef struct 1320 { 1321 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1322 uint8_t n_v : 1; 1323 uint8_t p_v : 1; 1324 uint8_t n_z : 1; 1325 uint8_t p_z : 1; 1326 uint8_t n_y : 1; 1327 uint8_t p_y : 1; 1328 uint8_t n_x : 1; 1329 uint8_t p_x : 1; 1330 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1331 uint8_t p_x : 1; 1332 uint8_t n_x : 1; 1333 uint8_t p_y : 1; 1334 uint8_t n_y : 1; 1335 uint8_t p_z : 1; 1336 uint8_t n_z : 1; 1337 uint8_t p_v : 1; 1338 uint8_t n_v : 1; 1339 #endif /* DRV_BYTE_ORDER */ 1340 } asm330lhb_fsm_outs2_t; 1341 1342 #define ASM330LHB_FSM_OUTS3 0x4EU 1343 typedef struct 1344 { 1345 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1346 uint8_t n_v : 1; 1347 uint8_t p_v : 1; 1348 uint8_t n_z : 1; 1349 uint8_t p_z : 1; 1350 uint8_t n_y : 1; 1351 uint8_t p_y : 1; 1352 uint8_t n_x : 1; 1353 uint8_t p_x : 1; 1354 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1355 uint8_t p_x : 1; 1356 uint8_t n_x : 1; 1357 uint8_t p_y : 1; 1358 uint8_t n_y : 1; 1359 uint8_t p_z : 1; 1360 uint8_t n_z : 1; 1361 uint8_t p_v : 1; 1362 uint8_t n_v : 1; 1363 #endif /* DRV_BYTE_ORDER */ 1364 } asm330lhb_fsm_outs3_t; 1365 1366 #define ASM330LHB_FSM_OUTS4 0x4FU 1367 typedef struct 1368 { 1369 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1370 uint8_t n_v : 1; 1371 uint8_t p_v : 1; 1372 uint8_t n_z : 1; 1373 uint8_t p_z : 1; 1374 uint8_t n_y : 1; 1375 uint8_t p_y : 1; 1376 uint8_t n_x : 1; 1377 uint8_t p_x : 1; 1378 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1379 uint8_t p_x : 1; 1380 uint8_t n_x : 1; 1381 uint8_t p_y : 1; 1382 uint8_t n_y : 1; 1383 uint8_t p_z : 1; 1384 uint8_t n_z : 1; 1385 uint8_t p_v : 1; 1386 uint8_t n_v : 1; 1387 #endif /* DRV_BYTE_ORDER */ 1388 } asm330lhb_fsm_outs4_t; 1389 1390 #define ASM330LHB_FSM_OUTS5 0x50U 1391 typedef struct 1392 { 1393 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1394 uint8_t n_v : 1; 1395 uint8_t p_v : 1; 1396 uint8_t n_z : 1; 1397 uint8_t p_z : 1; 1398 uint8_t n_y : 1; 1399 uint8_t p_y : 1; 1400 uint8_t n_x : 1; 1401 uint8_t p_x : 1; 1402 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1403 uint8_t p_x : 1; 1404 uint8_t n_x : 1; 1405 uint8_t p_y : 1; 1406 uint8_t n_y : 1; 1407 uint8_t p_z : 1; 1408 uint8_t n_z : 1; 1409 uint8_t p_v : 1; 1410 uint8_t n_v : 1; 1411 #endif /* DRV_BYTE_ORDER */ 1412 } asm330lhb_fsm_outs5_t; 1413 1414 #define ASM330LHB_FSM_OUTS6 0x51U 1415 typedef struct 1416 { 1417 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1418 uint8_t n_v : 1; 1419 uint8_t p_v : 1; 1420 uint8_t n_z : 1; 1421 uint8_t p_z : 1; 1422 uint8_t n_y : 1; 1423 uint8_t p_y : 1; 1424 uint8_t n_x : 1; 1425 uint8_t p_x : 1; 1426 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1427 uint8_t p_x : 1; 1428 uint8_t n_x : 1; 1429 uint8_t p_y : 1; 1430 uint8_t n_y : 1; 1431 uint8_t p_z : 1; 1432 uint8_t n_z : 1; 1433 uint8_t p_v : 1; 1434 uint8_t n_v : 1; 1435 #endif /* DRV_BYTE_ORDER */ 1436 } asm330lhb_fsm_outs6_t; 1437 1438 #define ASM330LHB_FSM_OUTS7 0x52U 1439 typedef struct 1440 { 1441 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1442 uint8_t n_v : 1; 1443 uint8_t p_v : 1; 1444 uint8_t n_z : 1; 1445 uint8_t p_z : 1; 1446 uint8_t n_y : 1; 1447 uint8_t p_y : 1; 1448 uint8_t n_x : 1; 1449 uint8_t p_x : 1; 1450 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1451 uint8_t p_x : 1; 1452 uint8_t n_x : 1; 1453 uint8_t p_y : 1; 1454 uint8_t n_y : 1; 1455 uint8_t p_z : 1; 1456 uint8_t n_z : 1; 1457 uint8_t p_v : 1; 1458 uint8_t n_v : 1; 1459 #endif /* DRV_BYTE_ORDER */ 1460 } asm330lhb_fsm_outs7_t; 1461 1462 #define ASM330LHB_FSM_OUTS8 0x53U 1463 typedef struct 1464 { 1465 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1466 uint8_t n_v : 1; 1467 uint8_t p_v : 1; 1468 uint8_t n_z : 1; 1469 uint8_t p_z : 1; 1470 uint8_t n_y : 1; 1471 uint8_t p_y : 1; 1472 uint8_t n_x : 1; 1473 uint8_t p_x : 1; 1474 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1475 uint8_t p_x : 1; 1476 uint8_t n_x : 1; 1477 uint8_t p_y : 1; 1478 uint8_t n_y : 1; 1479 uint8_t p_z : 1; 1480 uint8_t n_z : 1; 1481 uint8_t p_v : 1; 1482 uint8_t n_v : 1; 1483 #endif /* DRV_BYTE_ORDER */ 1484 } asm330lhb_fsm_outs8_t; 1485 1486 #define ASM330LHB_FSM_OUTS9 0x54U 1487 typedef struct 1488 { 1489 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1490 uint8_t n_v : 1; 1491 uint8_t p_v : 1; 1492 uint8_t n_z : 1; 1493 uint8_t p_z : 1; 1494 uint8_t n_y : 1; 1495 uint8_t p_y : 1; 1496 uint8_t n_x : 1; 1497 uint8_t p_x : 1; 1498 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1499 uint8_t p_x : 1; 1500 uint8_t n_x : 1; 1501 uint8_t p_y : 1; 1502 uint8_t n_y : 1; 1503 uint8_t p_z : 1; 1504 uint8_t n_z : 1; 1505 uint8_t p_v : 1; 1506 uint8_t n_v : 1; 1507 #endif /* DRV_BYTE_ORDER */ 1508 } asm330lhb_fsm_outs9_t; 1509 1510 #define ASM330LHB_FSM_OUTS10 0x55U 1511 typedef struct 1512 { 1513 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1514 uint8_t n_v : 1; 1515 uint8_t p_v : 1; 1516 uint8_t n_z : 1; 1517 uint8_t p_z : 1; 1518 uint8_t n_y : 1; 1519 uint8_t p_y : 1; 1520 uint8_t n_x : 1; 1521 uint8_t p_x : 1; 1522 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1523 uint8_t p_x : 1; 1524 uint8_t n_x : 1; 1525 uint8_t p_y : 1; 1526 uint8_t n_y : 1; 1527 uint8_t p_z : 1; 1528 uint8_t n_z : 1; 1529 uint8_t p_v : 1; 1530 uint8_t n_v : 1; 1531 #endif /* DRV_BYTE_ORDER */ 1532 } asm330lhb_fsm_outs10_t; 1533 1534 #define ASM330LHB_FSM_OUTS11 0x56U 1535 typedef struct 1536 { 1537 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1538 uint8_t n_v : 1; 1539 uint8_t p_v : 1; 1540 uint8_t n_z : 1; 1541 uint8_t p_z : 1; 1542 uint8_t n_y : 1; 1543 uint8_t p_y : 1; 1544 uint8_t n_x : 1; 1545 uint8_t p_x : 1; 1546 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1547 uint8_t p_x : 1; 1548 uint8_t n_x : 1; 1549 uint8_t p_y : 1; 1550 uint8_t n_y : 1; 1551 uint8_t p_z : 1; 1552 uint8_t n_z : 1; 1553 uint8_t p_v : 1; 1554 uint8_t n_v : 1; 1555 #endif /* DRV_BYTE_ORDER */ 1556 } asm330lhb_fsm_outs11_t; 1557 1558 #define ASM330LHB_FSM_OUTS12 0x57U 1559 typedef struct 1560 { 1561 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1562 uint8_t n_v : 1; 1563 uint8_t p_v : 1; 1564 uint8_t n_z : 1; 1565 uint8_t p_z : 1; 1566 uint8_t n_y : 1; 1567 uint8_t p_y : 1; 1568 uint8_t n_x : 1; 1569 uint8_t p_x : 1; 1570 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1571 uint8_t p_x : 1; 1572 uint8_t n_x : 1; 1573 uint8_t p_y : 1; 1574 uint8_t n_y : 1; 1575 uint8_t p_z : 1; 1576 uint8_t n_z : 1; 1577 uint8_t p_v : 1; 1578 uint8_t n_v : 1; 1579 #endif /* DRV_BYTE_ORDER */ 1580 } asm330lhb_fsm_outs12_t; 1581 1582 #define ASM330LHB_FSM_OUTS13 0x58U 1583 typedef struct 1584 { 1585 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1586 uint8_t n_v : 1; 1587 uint8_t p_v : 1; 1588 uint8_t n_z : 1; 1589 uint8_t p_z : 1; 1590 uint8_t n_y : 1; 1591 uint8_t p_y : 1; 1592 uint8_t n_x : 1; 1593 uint8_t p_x : 1; 1594 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1595 uint8_t p_x : 1; 1596 uint8_t n_x : 1; 1597 uint8_t p_y : 1; 1598 uint8_t n_y : 1; 1599 uint8_t p_z : 1; 1600 uint8_t n_z : 1; 1601 uint8_t p_v : 1; 1602 uint8_t n_v : 1; 1603 #endif /* DRV_BYTE_ORDER */ 1604 } asm330lhb_fsm_outs13_t; 1605 1606 #define ASM330LHB_FSM_OUTS14 0x59U 1607 typedef struct 1608 { 1609 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1610 uint8_t n_v : 1; 1611 uint8_t p_v : 1; 1612 uint8_t n_z : 1; 1613 uint8_t p_z : 1; 1614 uint8_t n_y : 1; 1615 uint8_t p_y : 1; 1616 uint8_t n_x : 1; 1617 uint8_t p_x : 1; 1618 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1619 uint8_t p_x : 1; 1620 uint8_t n_x : 1; 1621 uint8_t p_y : 1; 1622 uint8_t n_y : 1; 1623 uint8_t p_z : 1; 1624 uint8_t n_z : 1; 1625 uint8_t p_v : 1; 1626 uint8_t n_v : 1; 1627 #endif /* DRV_BYTE_ORDER */ 1628 } asm330lhb_fsm_outs14_t; 1629 1630 #define ASM330LHB_FSM_OUTS15 0x5AU 1631 typedef struct 1632 { 1633 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1634 uint8_t n_v : 1; 1635 uint8_t p_v : 1; 1636 uint8_t n_z : 1; 1637 uint8_t p_z : 1; 1638 uint8_t n_y : 1; 1639 uint8_t p_y : 1; 1640 uint8_t n_x : 1; 1641 uint8_t p_x : 1; 1642 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1643 uint8_t p_x : 1; 1644 uint8_t n_x : 1; 1645 uint8_t p_y : 1; 1646 uint8_t n_y : 1; 1647 uint8_t p_z : 1; 1648 uint8_t n_z : 1; 1649 uint8_t p_v : 1; 1650 uint8_t n_v : 1; 1651 #endif /* DRV_BYTE_ORDER */ 1652 } asm330lhb_fsm_outs15_t; 1653 1654 #define ASM330LHB_FSM_OUTS16 0x5BU 1655 typedef struct 1656 { 1657 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1658 uint8_t n_v : 1; 1659 uint8_t p_v : 1; 1660 uint8_t n_z : 1; 1661 uint8_t p_z : 1; 1662 uint8_t n_y : 1; 1663 uint8_t p_y : 1; 1664 uint8_t n_x : 1; 1665 uint8_t p_x : 1; 1666 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1667 uint8_t p_x : 1; 1668 uint8_t n_x : 1; 1669 uint8_t p_y : 1; 1670 uint8_t n_y : 1; 1671 uint8_t p_z : 1; 1672 uint8_t n_z : 1; 1673 uint8_t p_v : 1; 1674 uint8_t n_v : 1; 1675 #endif /* DRV_BYTE_ORDER */ 1676 } asm330lhb_fsm_outs16_t; 1677 1678 #define ASM330LHB_EMB_FUNC_ODR_CFG_B 0x5FU 1679 typedef struct 1680 { 1681 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1682 uint8_t not_used_01 : 3; 1683 uint8_t fsm_odr : 2; 1684 uint8_t not_used_02 : 3; 1685 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1686 uint8_t not_used_02 : 3; 1687 uint8_t fsm_odr : 2; 1688 uint8_t not_used_01 : 3; 1689 #endif /* DRV_BYTE_ORDER */ 1690 } asm330lhb_emb_func_odr_cfg_b_t; 1691 1692 #define ASM330LHB_EMB_FUNC_ODR_CFG_C 0x60U 1693 typedef struct 1694 { 1695 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1696 uint8_t not_used_01 : 4; 1697 uint8_t mlc_odr : 2; 1698 uint8_t not_used_02 : 2; 1699 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1700 uint8_t not_used_02 : 2; 1701 uint8_t mlc_odr : 2; 1702 uint8_t not_used_01 : 4; 1703 #endif /* DRV_BYTE_ORDER */ 1704 } asm330lhb_emb_func_odr_cfg_c_t; 1705 1706 #define ASM330LHB_EMB_FUNC_INIT_B 0x67U 1707 typedef struct 1708 { 1709 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1710 uint8_t fsm_init : 1; 1711 uint8_t not_used_01 : 3; 1712 uint8_t mlc_init : 1; 1713 uint8_t not_used_02 : 3; 1714 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1715 uint8_t not_used_02 : 3; 1716 uint8_t mlc_init : 1; 1717 uint8_t not_used_01 : 3; 1718 uint8_t fsm_init : 1; 1719 #endif /* DRV_BYTE_ORDER */ 1720 } asm330lhb_emb_func_init_b_t; 1721 1722 #define ASM330LHB_MLC0_SRC 0x70U 1723 #define ASM330LHB_MLC1_SRC 0x71U 1724 #define ASM330LHB_MLC2_SRC 0x72U 1725 #define ASM330LHB_MLC3_SRC 0x73U 1726 #define ASM330LHB_MLC4_SRC 0x74U 1727 #define ASM330LHB_MLC5_SRC 0x75U 1728 #define ASM330LHB_MLC6_SRC 0x76U 1729 #define ASM330LHB_MLC7_SRC 0x77U 1730 1731 #define ASM330LHB_FSM_LC_TIMEOUT_L 0x17AU 1732 #define ASM330LHB_FSM_LC_TIMEOUT_H 0x17BU 1733 #define ASM330LHB_FSM_PROGRAMS 0x17CU 1734 #define ASM330LHB_FSM_START_ADD_L 0x17EU 1735 #define ASM330LHB_FSM_START_ADD_H 0x17FU 1736 1737 /** 1738 * @defgroup ASM330LHB_Register_Union 1739 * @brief This union group all the registers that has a bit-field 1740 * description. 1741 * This union is useful but not need by the driver. 1742 * 1743 * REMOVING this union you are compliant with: 1744 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 1745 * 1746 * @{ 1747 * 1748 */ 1749 typedef union 1750 { 1751 asm330lhb_func_cfg_access_t func_cfg_access; 1752 asm330lhb_pin_ctrl_t pin_ctrl; 1753 asm330lhb_fifo_ctrl1_t fifo_ctrl1; 1754 asm330lhb_fifo_ctrl2_t fifo_ctrl2; 1755 asm330lhb_fifo_ctrl3_t fifo_ctrl3; 1756 asm330lhb_fifo_ctrl4_t fifo_ctrl4; 1757 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; 1758 asm330lhb_counter_bdr_reg2_t counter_bdr_reg2; 1759 asm330lhb_int1_ctrl_t int1_ctrl; 1760 asm330lhb_int2_ctrl_t int2_ctrl; 1761 asm330lhb_ctrl1_xl_t ctrl1_xl; 1762 asm330lhb_ctrl2_g_t ctrl2_g; 1763 asm330lhb_ctrl3_c_t ctrl3_c; 1764 asm330lhb_ctrl4_c_t ctrl4_c; 1765 asm330lhb_ctrl5_c_t ctrl5_c; 1766 asm330lhb_ctrl6_c_t ctrl6_c; 1767 asm330lhb_ctrl7_g_t ctrl7_g; 1768 asm330lhb_ctrl8_xl_t ctrl8_xl; 1769 asm330lhb_ctrl9_xl_t ctrl9_xl; 1770 asm330lhb_ctrl10_c_t ctrl10_c; 1771 asm330lhb_all_int_src_t all_int_src; 1772 asm330lhb_wake_up_src_t wake_up_src; 1773 asm330lhb_d6d_src_t d6d_src; 1774 asm330lhb_status_reg_t status_reg; 1775 asm330lhb_fifo_status1_t fifo_status1; 1776 asm330lhb_fifo_status2_t fifo_status2; 1777 asm330lhb_int_cfg0_t int_cfg0; 1778 asm330lhb_int_cfg1_t int_cfg1; 1779 asm330lhb_ths_6d_t ths_6d; 1780 asm330lhb_wake_up_ths_t wake_up_ths; 1781 asm330lhb_wake_up_dur_t wake_up_dur; 1782 asm330lhb_free_fall_t free_fall; 1783 asm330lhb_md1_cfg_t md1_cfg; 1784 asm330lhb_md2_cfg_t md2_cfg; 1785 asm330lhb_i3c_bus_avb_t i3c_bus_avb; 1786 asm330lhb_internal_freq_fine_t internal_freq_fine; 1787 asm330lhb_fifo_data_out_tag_t fifo_data_out_tag; 1788 asm330lhb_page_sel_t page_sel; 1789 asm330lhb_emb_func_en_b_t emb_func_en_b; 1790 asm330lhb_page_address_t page_address; 1791 asm330lhb_page_value_t page_value; 1792 asm330lhb_emb_func_int1_t emb_func_int1; 1793 asm330lhb_fsm_int1_a_t fsm_int1_a; 1794 asm330lhb_fsm_int1_b_t fsm_int1_b; 1795 asm330lhb_mlc_int1_t mlc_int1; 1796 asm330lhb_emb_func_int2_t emb_func_int2; 1797 asm330lhb_fsm_int2_a_t fsm_int2_a; 1798 asm330lhb_fsm_int2_b_t fsm_int2_b; 1799 asm330lhb_mlc_int2_t mlc_int2; 1800 asm330lhb_emb_func_status_t emb_func_status; 1801 asm330lhb_fsm_status_a_t fsm_status_a; 1802 asm330lhb_fsm_status_b_t fsm_status_b; 1803 asm330lhb_mlc_status_mainpage_t mlc_status_mainpage; 1804 asm330lhb_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; 1805 asm330lhb_page_rw_t page_rw; 1806 asm330lhb_fsm_enable_a_t fsm_enable_a; 1807 asm330lhb_fsm_enable_b_t fsm_enable_b; 1808 asm330lhb_fsm_long_counter_clear_t fsm_long_counter_clear; 1809 asm330lhb_fsm_outs1_t fsm_outs1; 1810 asm330lhb_fsm_outs2_t fsm_outs2; 1811 asm330lhb_fsm_outs3_t fsm_outs3; 1812 asm330lhb_fsm_outs4_t fsm_outs4; 1813 asm330lhb_fsm_outs5_t fsm_outs5; 1814 asm330lhb_fsm_outs6_t fsm_outs6; 1815 asm330lhb_fsm_outs7_t fsm_outs7; 1816 asm330lhb_fsm_outs8_t fsm_outs8; 1817 asm330lhb_fsm_outs9_t fsm_outs9; 1818 asm330lhb_fsm_outs10_t fsm_outs10; 1819 asm330lhb_fsm_outs11_t fsm_outs11; 1820 asm330lhb_fsm_outs12_t fsm_outs12; 1821 asm330lhb_fsm_outs13_t fsm_outs13; 1822 asm330lhb_fsm_outs14_t fsm_outs14; 1823 asm330lhb_fsm_outs15_t fsm_outs15; 1824 asm330lhb_fsm_outs16_t fsm_outs16; 1825 asm330lhb_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 1826 asm330lhb_emb_func_init_b_t emb_func_init_b; 1827 bitwise_t bitwise; 1828 uint8_t byte; 1829 } asm330lhb_reg_t; 1830 1831 /** 1832 * @} 1833 * 1834 */ 1835 1836 #ifndef __weak 1837 #define __weak __attribute__((weak)) 1838 #endif /* __weak */ 1839 1840 /* 1841 * These are the basic platform dependent I/O routines to read 1842 * and write device registers connected on a standard bus. 1843 * The driver keeps offering a default implementation based on function 1844 * pointers to read/write routines for backward compatibility. 1845 * The __weak directive allows the final application to overwrite 1846 * them with a custom implementation. 1847 */ 1848 1849 int32_t asm330lhb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 1850 uint16_t len); 1851 int32_t asm330lhb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 1852 uint16_t len); 1853 1854 float_t asm330lhb_from_fs2g_to_mg(int16_t lsb); 1855 float_t asm330lhb_from_fs4g_to_mg(int16_t lsb); 1856 float_t asm330lhb_from_fs8g_to_mg(int16_t lsb); 1857 float_t asm330lhb_from_fs16g_to_mg(int16_t lsb); 1858 float_t asm330lhb_from_fs125dps_to_mdps(int16_t lsb); 1859 float_t asm330lhb_from_fs250dps_to_mdps(int16_t lsb); 1860 float_t asm330lhb_from_fs500dps_to_mdps(int16_t lsb); 1861 float_t asm330lhb_from_fs1000dps_to_mdps(int16_t lsb); 1862 float_t asm330lhb_from_fs2000dps_to_mdps(int16_t lsb); 1863 float_t asm330lhb_from_fs4000dps_to_mdps(int16_t lsb); 1864 float_t asm330lhb_from_lsb_to_celsius(int16_t lsb); 1865 float_t asm330lhb_from_lsb_to_nsec(int32_t lsb); 1866 1867 typedef enum 1868 { 1869 ASM330LHB_2g = 0, 1870 ASM330LHB_16g = 1, /* if XL_FS_MODE = '1' -> ASM330LHB_2g */ 1871 ASM330LHB_4g = 2, 1872 ASM330LHB_8g = 3, 1873 } asm330lhb_fs_xl_t; 1874 int32_t asm330lhb_xl_full_scale_set(stmdev_ctx_t *ctx, asm330lhb_fs_xl_t val); 1875 int32_t asm330lhb_xl_full_scale_get(stmdev_ctx_t *ctx, 1876 asm330lhb_fs_xl_t *val); 1877 1878 typedef enum 1879 { 1880 ASM330LHB_XL_ODR_OFF = 0, 1881 ASM330LHB_XL_ODR_12Hz5 = 1, 1882 ASM330LHB_XL_ODR_26Hz = 2, 1883 ASM330LHB_XL_ODR_52Hz = 3, 1884 ASM330LHB_XL_ODR_104Hz = 4, 1885 ASM330LHB_XL_ODR_208Hz = 5, 1886 ASM330LHB_XL_ODR_417Hz = 6, 1887 ASM330LHB_XL_ODR_833Hz = 7, 1888 ASM330LHB_XL_ODR_1667Hz = 8, 1889 ASM330LHB_XL_ODR_1Hz6 = 11, /* (low power only) */ 1890 } asm330lhb_odr_xl_t; 1891 int32_t asm330lhb_xl_data_rate_set(stmdev_ctx_t *ctx, asm330lhb_odr_xl_t val); 1892 int32_t asm330lhb_xl_data_rate_get(stmdev_ctx_t *ctx, 1893 asm330lhb_odr_xl_t *val); 1894 1895 typedef enum 1896 { 1897 ASM330LHB_125dps = 2, 1898 ASM330LHB_250dps = 0, 1899 ASM330LHB_500dps = 4, 1900 ASM330LHB_1000dps = 8, 1901 ASM330LHB_2000dps = 12, 1902 ASM330LHB_4000dps = 1, 1903 } asm330lhb_fs_g_t; 1904 int32_t asm330lhb_gy_full_scale_set(stmdev_ctx_t *ctx, asm330lhb_fs_g_t val); 1905 int32_t asm330lhb_gy_full_scale_get(stmdev_ctx_t *ctx, asm330lhb_fs_g_t *val); 1906 1907 typedef enum 1908 { 1909 ASM330LHB_GY_ODR_OFF = 0, 1910 ASM330LHB_GY_ODR_12Hz5 = 1, 1911 ASM330LHB_GY_ODR_26Hz = 2, 1912 ASM330LHB_GY_ODR_52Hz = 3, 1913 ASM330LHB_GY_ODR_104Hz = 4, 1914 ASM330LHB_GY_ODR_208Hz = 5, 1915 ASM330LHB_GY_ODR_417Hz = 6, 1916 ASM330LHB_GY_ODR_833Hz = 7, 1917 ASM330LHB_GY_ODR_1667Hz = 8, 1918 } asm330lhb_odr_g_t; 1919 int32_t asm330lhb_gy_data_rate_set(stmdev_ctx_t *ctx, 1920 asm330lhb_odr_g_t val); 1921 int32_t asm330lhb_gy_data_rate_get(stmdev_ctx_t *ctx, 1922 asm330lhb_odr_g_t *val); 1923 1924 int32_t asm330lhb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 1925 int32_t asm330lhb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); 1926 1927 typedef enum 1928 { 1929 ASM330LHB_LSb_1mg = 0, 1930 ASM330LHB_LSb_16mg = 1, 1931 } asm330lhb_usr_off_w_t; 1932 int32_t asm330lhb_xl_offset_weight_set(stmdev_ctx_t *ctx, 1933 asm330lhb_usr_off_w_t val); 1934 int32_t asm330lhb_xl_offset_weight_get(stmdev_ctx_t *ctx, 1935 asm330lhb_usr_off_w_t *val); 1936 1937 typedef enum 1938 { 1939 ASM330LHB_HIGH_PERFORMANCE_MD = 0, 1940 ASM330LHB_LOW_NORMAL_POWER_MD = 1, 1941 } asm330lhb_xl_hm_mode_t; 1942 int32_t asm330lhb_xl_power_mode_set(stmdev_ctx_t *ctx, 1943 asm330lhb_xl_hm_mode_t val); 1944 int32_t asm330lhb_xl_power_mode_get(stmdev_ctx_t *ctx, 1945 asm330lhb_xl_hm_mode_t *val); 1946 1947 typedef enum 1948 { 1949 ASM330LHB_GY_HIGH_PERFORMANCE = 0, 1950 ASM330LHB_GY_NORMAL = 1, 1951 } asm330lhb_g_hm_mode_t; 1952 int32_t asm330lhb_gy_power_mode_set(stmdev_ctx_t *ctx, 1953 asm330lhb_g_hm_mode_t val); 1954 int32_t asm330lhb_gy_power_mode_get(stmdev_ctx_t *ctx, 1955 asm330lhb_g_hm_mode_t *val); 1956 1957 typedef struct 1958 { 1959 asm330lhb_all_int_src_t all_int_src; 1960 asm330lhb_wake_up_src_t wake_up_src; 1961 asm330lhb_d6d_src_t d6d_src; 1962 asm330lhb_status_reg_t status_reg; 1963 asm330lhb_emb_func_status_t emb_func_status; 1964 asm330lhb_fsm_status_a_t fsm_status_a; 1965 asm330lhb_fsm_status_b_t fsm_status_b; 1966 asm330lhb_mlc_status_mainpage_t mlc_status; 1967 } asm330lhb_all_sources_t; 1968 int32_t asm330lhb_all_sources_get(stmdev_ctx_t *ctx, 1969 asm330lhb_all_sources_t *val); 1970 1971 int32_t asm330lhb_status_reg_get(stmdev_ctx_t *ctx, 1972 asm330lhb_status_reg_t *val); 1973 1974 int32_t asm330lhb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 1975 1976 int32_t asm330lhb_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 1977 1978 int32_t asm330lhb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 1979 1980 int32_t asm330lhb_boot_device_status_get(stmdev_ctx_t *ctx, uint8_t *val); 1981 1982 int32_t asm330lhb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); 1983 int32_t asm330lhb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); 1984 1985 int32_t asm330lhb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); 1986 int32_t asm330lhb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); 1987 1988 int32_t asm330lhb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); 1989 int32_t asm330lhb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); 1990 1991 int32_t asm330lhb_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); 1992 int32_t asm330lhb_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); 1993 1994 int32_t asm330lhb_timestamp_rst(stmdev_ctx_t *ctx); 1995 1996 int32_t asm330lhb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); 1997 int32_t asm330lhb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); 1998 1999 int32_t asm330lhb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); 2000 2001 typedef enum 2002 { 2003 ASM330LHB_NO_ROUND = 0, 2004 ASM330LHB_ROUND_XL = 1, 2005 ASM330LHB_ROUND_GY = 2, 2006 ASM330LHB_ROUND_GY_XL = 3, 2007 } asm330lhb_rounding_t; 2008 int32_t asm330lhb_rounding_mode_set(stmdev_ctx_t *ctx, 2009 asm330lhb_rounding_t val); 2010 int32_t asm330lhb_rounding_mode_get(stmdev_ctx_t *ctx, 2011 asm330lhb_rounding_t *val); 2012 2013 int32_t asm330lhb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2014 2015 int32_t asm330lhb_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2016 2017 int32_t asm330lhb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2018 2019 int32_t asm330lhb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val); 2020 2021 int32_t asm330lhb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); 2022 int32_t asm330lhb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); 2023 2024 typedef enum 2025 { 2026 ASM330LHB_USER_BANK = 0, 2027 ASM330LHB_EMBEDDED_FUNC_BANK = 1, 2028 } asm330lhb_reg_access_t; 2029 int32_t asm330lhb_mem_bank_set(stmdev_ctx_t *ctx, asm330lhb_reg_access_t val); 2030 int32_t asm330lhb_mem_bank_get(stmdev_ctx_t *ctx, 2031 asm330lhb_reg_access_t *val); 2032 2033 int32_t asm330lhb_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, 2034 uint8_t *val); 2035 int32_t asm330lhb_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, 2036 uint8_t *buf, uint8_t len); 2037 int32_t asm330lhb_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, 2038 uint8_t *val); 2039 int32_t asm330lhb_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, 2040 uint8_t *val); 2041 2042 typedef enum 2043 { 2044 ASM330LHB_DRDY_LATCHED = 0, 2045 ASM330LHB_DRDY_PULSED = 1, 2046 } asm330lhb_dataready_pulsed_t; 2047 int32_t asm330lhb_data_ready_mode_set(stmdev_ctx_t *ctx, 2048 asm330lhb_dataready_pulsed_t val); 2049 int32_t asm330lhb_data_ready_mode_get(stmdev_ctx_t *ctx, 2050 asm330lhb_dataready_pulsed_t *val); 2051 2052 int32_t asm330lhb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 2053 2054 int32_t asm330lhb_reset_set(stmdev_ctx_t *ctx, uint8_t val); 2055 int32_t asm330lhb_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 2056 2057 int32_t asm330lhb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 2058 int32_t asm330lhb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); 2059 2060 int32_t asm330lhb_boot_set(stmdev_ctx_t *ctx, uint8_t val); 2061 int32_t asm330lhb_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 2062 2063 typedef enum 2064 { 2065 ASM330LHB_XL_ST_DISABLE = 0, 2066 ASM330LHB_XL_ST_POSITIVE = 1, 2067 ASM330LHB_XL_ST_NEGATIVE = 2, 2068 } asm330lhb_st_xl_t; 2069 int32_t asm330lhb_xl_self_test_set(stmdev_ctx_t *ctx, asm330lhb_st_xl_t val); 2070 int32_t asm330lhb_xl_self_test_get(stmdev_ctx_t *ctx, asm330lhb_st_xl_t *val); 2071 2072 typedef enum 2073 { 2074 ASM330LHB_GY_ST_DISABLE = 0, 2075 ASM330LHB_GY_ST_POSITIVE = 1, 2076 ASM330LHB_GY_ST_NEGATIVE = 3, 2077 } asm330lhb_st_g_t; 2078 int32_t asm330lhb_gy_self_test_set(stmdev_ctx_t *ctx, asm330lhb_st_g_t val); 2079 int32_t asm330lhb_gy_self_test_get(stmdev_ctx_t *ctx, asm330lhb_st_g_t *val); 2080 2081 int32_t asm330lhb_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); 2082 int32_t asm330lhb_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); 2083 2084 int32_t asm330lhb_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); 2085 int32_t asm330lhb_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); 2086 2087 int32_t asm330lhb_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val); 2088 int32_t asm330lhb_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val); 2089 2090 typedef enum 2091 { 2092 ASM330LHB_ULTRA_LIGHT = 0, 2093 ASM330LHB_VERY_LIGHT = 1, 2094 ASM330LHB_LIGHT = 2, 2095 ASM330LHB_MEDIUM = 3, 2096 ASM330LHB_STRONG = 4, 2097 ASM330LHB_VERY_STRONG = 5, 2098 ASM330LHB_AGGRESSIVE = 6, 2099 ASM330LHB_XTREME = 7, 2100 } asm330lhb_ftype_t; 2101 int32_t asm330lhb_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, 2102 asm330lhb_ftype_t val); 2103 int32_t asm330lhb_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, 2104 asm330lhb_ftype_t *val); 2105 2106 int32_t asm330lhb_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); 2107 int32_t asm330lhb_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); 2108 2109 typedef enum 2110 { 2111 ASM330LHB_HP_PATH_DISABLE_ON_OUT = 0x00, 2112 ASM330LHB_SLOPE_ODR_DIV_4 = 0x10, 2113 ASM330LHB_HP_ODR_DIV_10 = 0x11, 2114 ASM330LHB_HP_ODR_DIV_20 = 0x12, 2115 ASM330LHB_HP_ODR_DIV_45 = 0x13, 2116 ASM330LHB_HP_ODR_DIV_100 = 0x14, 2117 ASM330LHB_HP_ODR_DIV_200 = 0x15, 2118 ASM330LHB_HP_ODR_DIV_400 = 0x16, 2119 ASM330LHB_HP_ODR_DIV_800 = 0x17, 2120 ASM330LHB_HP_REF_MD_ODR_DIV_10 = 0x31, 2121 ASM330LHB_HP_REF_MD_ODR_DIV_20 = 0x32, 2122 ASM330LHB_HP_REF_MD_ODR_DIV_45 = 0x33, 2123 ASM330LHB_HP_REF_MD_ODR_DIV_100 = 0x34, 2124 ASM330LHB_HP_REF_MD_ODR_DIV_200 = 0x35, 2125 ASM330LHB_HP_REF_MD_ODR_DIV_400 = 0x36, 2126 ASM330LHB_HP_REF_MD_ODR_DIV_800 = 0x37, 2127 ASM330LHB_LP_ODR_DIV_10 = 0x01, 2128 ASM330LHB_LP_ODR_DIV_20 = 0x02, 2129 ASM330LHB_LP_ODR_DIV_45 = 0x03, 2130 ASM330LHB_LP_ODR_DIV_100 = 0x04, 2131 ASM330LHB_LP_ODR_DIV_200 = 0x05, 2132 ASM330LHB_LP_ODR_DIV_400 = 0x06, 2133 ASM330LHB_LP_ODR_DIV_800 = 0x07, 2134 } asm330lhb_hp_slope_xl_en_t; 2135 int32_t asm330lhb_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, 2136 asm330lhb_hp_slope_xl_en_t val); 2137 int32_t asm330lhb_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, 2138 asm330lhb_hp_slope_xl_en_t *val); 2139 2140 int32_t asm330lhb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); 2141 int32_t asm330lhb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); 2142 2143 typedef enum 2144 { 2145 ASM330LHB_USE_SLOPE = 0, 2146 ASM330LHB_USE_HPF = 1, 2147 } asm330lhb_slope_fds_t; 2148 int32_t asm330lhb_xl_hp_path_internal_set(stmdev_ctx_t *ctx, 2149 asm330lhb_slope_fds_t val); 2150 int32_t asm330lhb_xl_hp_path_internal_get(stmdev_ctx_t *ctx, 2151 asm330lhb_slope_fds_t *val); 2152 2153 typedef enum 2154 { 2155 ASM330LHB_HP_FILTER_NONE = 0x00, 2156 ASM330LHB_HP_FILTER_16mHz = 0x80, 2157 ASM330LHB_HP_FILTER_65mHz = 0x81, 2158 ASM330LHB_HP_FILTER_260mHz = 0x82, 2159 ASM330LHB_HP_FILTER_1Hz04 = 0x83, 2160 } asm330lhb_hpm_g_t; 2161 int32_t asm330lhb_gy_hp_path_internal_set(stmdev_ctx_t *ctx, 2162 asm330lhb_hpm_g_t val); 2163 int32_t asm330lhb_gy_hp_path_internal_get(stmdev_ctx_t *ctx, 2164 asm330lhb_hpm_g_t *val); 2165 2166 typedef enum 2167 { 2168 ASM330LHB_PULL_UP_DISC = 0, 2169 ASM330LHB_PULL_UP_CONNECT = 1, 2170 } asm330lhb_sdo_pu_en_t; 2171 int32_t asm330lhb_sdo_sa0_mode_set(stmdev_ctx_t *ctx, 2172 asm330lhb_sdo_pu_en_t val); 2173 int32_t asm330lhb_sdo_sa0_mode_get(stmdev_ctx_t *ctx, 2174 asm330lhb_sdo_pu_en_t *val); 2175 2176 typedef enum 2177 { 2178 ASM330LHB_PULL_DOWN_CONNECT = 0, 2179 ASM330LHB_PULL_DOWN_DISC = 1, 2180 } asm330lhb_pd_dis_int1_t; 2181 int32_t asm330lhb_int1_mode_set(stmdev_ctx_t *ctx, 2182 asm330lhb_pd_dis_int1_t val); 2183 int32_t asm330lhb_int1_mode_get(stmdev_ctx_t *ctx, 2184 asm330lhb_pd_dis_int1_t *val); 2185 2186 typedef enum 2187 { 2188 ASM330LHB_SPI_4_WIRE = 0, 2189 ASM330LHB_SPI_3_WIRE = 1, 2190 } asm330lhb_sim_t; 2191 int32_t asm330lhb_spi_mode_set(stmdev_ctx_t *ctx, asm330lhb_sim_t val); 2192 int32_t asm330lhb_spi_mode_get(stmdev_ctx_t *ctx, asm330lhb_sim_t *val); 2193 2194 typedef enum 2195 { 2196 ASM330LHB_I2C_ENABLE = 0, 2197 ASM330LHB_I2C_DISABLE = 1, 2198 } asm330lhb_i2c_disable_t; 2199 int32_t asm330lhb_i2c_interface_set(stmdev_ctx_t *ctx, 2200 asm330lhb_i2c_disable_t val); 2201 int32_t asm330lhb_i2c_interface_get(stmdev_ctx_t *ctx, 2202 asm330lhb_i2c_disable_t *val); 2203 2204 typedef enum 2205 { 2206 ASM330LHB_I3C_DISABLE = 0x80, 2207 ASM330LHB_I3C_ENABLE_T_50us = 0x00, 2208 ASM330LHB_I3C_ENABLE_T_2us = 0x01, 2209 ASM330LHB_I3C_ENABLE_T_1ms = 0x02, 2210 ASM330LHB_I3C_ENABLE_T_25ms = 0x03, 2211 } asm330lhb_i3c_disable_t; 2212 int32_t asm330lhb_i3c_disable_set(stmdev_ctx_t *ctx, 2213 asm330lhb_i3c_disable_t val); 2214 int32_t asm330lhb_i3c_disable_get(stmdev_ctx_t *ctx, 2215 asm330lhb_i3c_disable_t *val); 2216 2217 typedef struct 2218 { 2219 asm330lhb_int1_ctrl_t int1_ctrl; 2220 asm330lhb_md1_cfg_t md1_cfg; 2221 asm330lhb_emb_func_int1_t emb_func_int1; 2222 asm330lhb_fsm_int1_a_t fsm_int1_a; 2223 asm330lhb_fsm_int1_b_t fsm_int1_b; 2224 asm330lhb_mlc_int1_t mlc_int1; 2225 } asm330lhb_pin_int1_route_t; 2226 int32_t asm330lhb_pin_int1_route_set(stmdev_ctx_t *ctx, 2227 asm330lhb_pin_int1_route_t *val); 2228 int32_t asm330lhb_pin_int1_route_get(stmdev_ctx_t *ctx, 2229 asm330lhb_pin_int1_route_t *val); 2230 2231 typedef struct 2232 { 2233 asm330lhb_int2_ctrl_t int2_ctrl; 2234 asm330lhb_md2_cfg_t md2_cfg; 2235 asm330lhb_emb_func_int2_t emb_func_int2; 2236 asm330lhb_fsm_int2_a_t fsm_int2_a; 2237 asm330lhb_fsm_int2_b_t fsm_int2_b; 2238 asm330lhb_mlc_int2_t mlc_int2; 2239 } asm330lhb_pin_int2_route_t; 2240 int32_t asm330lhb_pin_int2_route_set(stmdev_ctx_t *ctx, 2241 asm330lhb_pin_int2_route_t *val); 2242 int32_t asm330lhb_pin_int2_route_get(stmdev_ctx_t *ctx, 2243 asm330lhb_pin_int2_route_t *val); 2244 2245 typedef enum 2246 { 2247 ASM330LHB_PUSH_PULL = 0, 2248 ASM330LHB_OPEN_DRAIN = 1, 2249 } asm330lhb_pp_od_t; 2250 int32_t asm330lhb_pin_mode_set(stmdev_ctx_t *ctx, asm330lhb_pp_od_t val); 2251 int32_t asm330lhb_pin_mode_get(stmdev_ctx_t *ctx, asm330lhb_pp_od_t *val); 2252 2253 typedef enum 2254 { 2255 ASM330LHB_ACTIVE_HIGH = 0, 2256 ASM330LHB_ACTIVE_LOW = 1, 2257 } asm330lhb_h_lactive_t; 2258 int32_t asm330lhb_pin_polarity_set(stmdev_ctx_t *ctx, 2259 asm330lhb_h_lactive_t val); 2260 int32_t asm330lhb_pin_polarity_get(stmdev_ctx_t *ctx, 2261 asm330lhb_h_lactive_t *val); 2262 2263 int32_t asm330lhb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); 2264 int32_t asm330lhb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); 2265 2266 typedef enum 2267 { 2268 ASM330LHB_ALL_INT_PULSED = 0, 2269 ASM330LHB_BASE_LATCHED_EMB_PULSED = 1, 2270 ASM330LHB_BASE_PULSED_EMB_LATCHED = 2, 2271 ASM330LHB_ALL_INT_LATCHED = 3, 2272 } asm330lhb_lir_t; 2273 int32_t asm330lhb_int_notification_set(stmdev_ctx_t *ctx, 2274 asm330lhb_lir_t val); 2275 int32_t asm330lhb_int_notification_get(stmdev_ctx_t *ctx, 2276 asm330lhb_lir_t *val); 2277 2278 typedef enum 2279 { 2280 ASM330LHB_LSb_FS_DIV_64 = 0, 2281 ASM330LHB_LSb_FS_DIV_256 = 1, 2282 } asm330lhb_wake_ths_w_t; 2283 int32_t asm330lhb_wkup_ths_weight_set(stmdev_ctx_t *ctx, 2284 asm330lhb_wake_ths_w_t val); 2285 int32_t asm330lhb_wkup_ths_weight_get(stmdev_ctx_t *ctx, 2286 asm330lhb_wake_ths_w_t *val); 2287 2288 int32_t asm330lhb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 2289 int32_t asm330lhb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 2290 2291 int32_t asm330lhb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, 2292 uint8_t val); 2293 int32_t asm330lhb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, 2294 uint8_t *val); 2295 2296 int32_t asm330lhb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2297 int32_t asm330lhb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2298 2299 int32_t asm330lhb_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); 2300 int32_t asm330lhb_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 2301 2302 typedef enum 2303 { 2304 ASM330LHB_DRIVE_SLEEP_CHG_EVENT = 0, 2305 ASM330LHB_DRIVE_SLEEP_STATUS = 1, 2306 } asm330lhb_sleep_status_on_int_t; 2307 int32_t asm330lhb_act_pin_notification_set(stmdev_ctx_t *ctx, 2308 asm330lhb_sleep_status_on_int_t val); 2309 int32_t asm330lhb_act_pin_notification_get(stmdev_ctx_t *ctx, 2310 asm330lhb_sleep_status_on_int_t *val); 2311 2312 typedef enum 2313 { 2314 ASM330LHB_XL_AND_GY_NOT_AFFECTED = 0, 2315 ASM330LHB_XL_12Hz5_GY_NOT_AFFECTED = 1, 2316 ASM330LHB_XL_12Hz5_GY_SLEEP = 2, 2317 ASM330LHB_XL_12Hz5_GY_PD = 3, 2318 } asm330lhb_inact_en_t; 2319 int32_t asm330lhb_act_mode_set(stmdev_ctx_t *ctx, 2320 asm330lhb_inact_en_t val); 2321 int32_t asm330lhb_act_mode_get(stmdev_ctx_t *ctx, 2322 asm330lhb_inact_en_t *val); 2323 2324 int32_t asm330lhb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2325 int32_t asm330lhb_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2326 2327 typedef enum 2328 { 2329 ASM330LHB_DEG_80 = 0, 2330 ASM330LHB_DEG_70 = 1, 2331 ASM330LHB_DEG_60 = 2, 2332 ASM330LHB_DEG_50 = 3, 2333 } asm330lhb_sixd_ths_t; 2334 int32_t asm330lhb_6d_threshold_set(stmdev_ctx_t *ctx, 2335 asm330lhb_sixd_ths_t val); 2336 int32_t asm330lhb_6d_threshold_get(stmdev_ctx_t *ctx, 2337 asm330lhb_sixd_ths_t *val); 2338 2339 int32_t asm330lhb_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); 2340 int32_t asm330lhb_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 2341 2342 typedef enum 2343 { 2344 ASM330LHB_FF_TSH_156mg = 0, 2345 ASM330LHB_FF_TSH_219mg = 1, 2346 ASM330LHB_FF_TSH_250mg = 2, 2347 ASM330LHB_FF_TSH_312mg = 3, 2348 ASM330LHB_FF_TSH_344mg = 4, 2349 ASM330LHB_FF_TSH_406mg = 5, 2350 ASM330LHB_FF_TSH_469mg = 6, 2351 ASM330LHB_FF_TSH_500mg = 7, 2352 } asm330lhb_ff_ths_t; 2353 int32_t asm330lhb_ff_threshold_set(stmdev_ctx_t *ctx, 2354 asm330lhb_ff_ths_t val); 2355 int32_t asm330lhb_ff_threshold_get(stmdev_ctx_t *ctx, 2356 asm330lhb_ff_ths_t *val); 2357 2358 int32_t asm330lhb_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2359 int32_t asm330lhb_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2360 2361 int32_t asm330lhb_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); 2362 int32_t asm330lhb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); 2363 2364 int32_t asm330lhb_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, 2365 uint8_t val); 2366 int32_t asm330lhb_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, 2367 uint8_t *val); 2368 2369 int32_t asm330lhb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); 2370 int32_t asm330lhb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); 2371 2372 typedef enum 2373 { 2374 ASM330LHB_XL_NOT_BATCHED = 0, 2375 ASM330LHB_XL_BATCHED_AT_12Hz5 = 1, 2376 ASM330LHB_XL_BATCHED_AT_26Hz = 2, 2377 ASM330LHB_XL_BATCHED_AT_52Hz = 3, 2378 ASM330LHB_XL_BATCHED_AT_104Hz = 4, 2379 ASM330LHB_XL_BATCHED_AT_208Hz = 5, 2380 ASM330LHB_XL_BATCHED_AT_417Hz = 6, 2381 ASM330LHB_XL_BATCHED_AT_833Hz = 7, 2382 ASM330LHB_XL_BATCHED_AT_1667Hz = 8, 2383 ASM330LHB_XL_BATCHED_AT_1Hz6 = 11, 2384 } asm330lhb_bdr_xl_t; 2385 int32_t asm330lhb_fifo_xl_batch_set(stmdev_ctx_t *ctx, 2386 asm330lhb_bdr_xl_t val); 2387 int32_t asm330lhb_fifo_xl_batch_get(stmdev_ctx_t *ctx, 2388 asm330lhb_bdr_xl_t *val); 2389 2390 typedef enum 2391 { 2392 ASM330LHB_GY_NOT_BATCHED = 0, 2393 ASM330LHB_GY_BATCHED_AT_12Hz5 = 1, 2394 ASM330LHB_GY_BATCHED_AT_26Hz = 2, 2395 ASM330LHB_GY_BATCHED_AT_52Hz = 3, 2396 ASM330LHB_GY_BATCHED_AT_104Hz = 4, 2397 ASM330LHB_GY_BATCHED_AT_208Hz = 5, 2398 ASM330LHB_GY_BATCHED_AT_417Hz = 6, 2399 ASM330LHB_GY_BATCHED_AT_833Hz = 7, 2400 ASM330LHB_GY_BATCHED_AT_1667Hz = 8, 2401 ASM330LHB_GY_BATCHED_AT_6Hz5 = 11, 2402 } asm330lhb_bdr_gy_t; 2403 int32_t asm330lhb_fifo_gy_batch_set(stmdev_ctx_t *ctx, 2404 asm330lhb_bdr_gy_t val); 2405 int32_t asm330lhb_fifo_gy_batch_get(stmdev_ctx_t *ctx, 2406 asm330lhb_bdr_gy_t *val); 2407 2408 typedef enum 2409 { 2410 ASM330LHB_BYPASS_MODE = 0, 2411 ASM330LHB_FIFO_MODE = 1, 2412 ASM330LHB_STREAM_TO_FIFO_MODE = 3, 2413 ASM330LHB_BYPASS_TO_STREAM_MODE = 4, 2414 ASM330LHB_STREAM_MODE = 6, 2415 ASM330LHB_BYPASS_TO_FIFO_MODE = 7, 2416 } asm330lhb_fifo_mode_t; 2417 int32_t asm330lhb_fifo_mode_set(stmdev_ctx_t *ctx, asm330lhb_fifo_mode_t val); 2418 int32_t asm330lhb_fifo_mode_get(stmdev_ctx_t *ctx, 2419 asm330lhb_fifo_mode_t *val); 2420 2421 typedef enum 2422 { 2423 ASM330LHB_TEMP_NOT_BATCHED = 0, 2424 ASM330LHB_TEMP_BATCHED_AT_52Hz = 1, 2425 ASM330LHB_TEMP_BATCHED_AT_12Hz5 = 2, 2426 ASM330LHB_TEMP_BATCHED_AT_1Hz6 = 3, 2427 } asm330lhb_odr_t_batch_t; 2428 int32_t asm330lhb_fifo_temp_batch_set(stmdev_ctx_t *ctx, 2429 asm330lhb_odr_t_batch_t val); 2430 int32_t asm330lhb_fifo_temp_batch_get(stmdev_ctx_t *ctx, 2431 asm330lhb_odr_t_batch_t *val); 2432 2433 typedef enum 2434 { 2435 ASM330LHB_NO_DECIMATION = 0, 2436 ASM330LHB_DEC_1 = 1, 2437 ASM330LHB_DEC_8 = 2, 2438 ASM330LHB_DEC_32 = 3, 2439 } asm330lhb_dec_ts_batch_t; 2440 int32_t asm330lhb_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, 2441 asm330lhb_dec_ts_batch_t val); 2442 int32_t asm330lhb_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, 2443 asm330lhb_dec_ts_batch_t *val); 2444 2445 typedef enum 2446 { 2447 ASM330LHB_XL_BATCH_EVENT = 0, 2448 ASM330LHB_GYRO_BATCH_EVENT = 1, 2449 } asm330lhb_trig_counter_bdr_t; 2450 int32_t asm330lhb_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, 2451 asm330lhb_trig_counter_bdr_t val); 2452 int32_t asm330lhb_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, 2453 asm330lhb_trig_counter_bdr_t *val); 2454 2455 int32_t asm330lhb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val); 2456 int32_t asm330lhb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val); 2457 2458 int32_t asm330lhb_batch_counter_threshold_set(stmdev_ctx_t *ctx, 2459 uint16_t val); 2460 int32_t asm330lhb_batch_counter_threshold_get(stmdev_ctx_t *ctx, 2461 uint16_t *val); 2462 2463 int32_t asm330lhb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); 2464 2465 int32_t asm330lhb_fifo_status_get(stmdev_ctx_t *ctx, 2466 asm330lhb_fifo_status2_t *val); 2467 2468 int32_t asm330lhb_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 2469 2470 int32_t asm330lhb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 2471 2472 int32_t asm330lhb_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 2473 2474 typedef enum 2475 { 2476 ASM330LHB_GYRO_NC_TAG = 0x01, 2477 ASM330LHB_XL_NC_TAG = 0x02, 2478 ASM330LHB_TEMPERATURE_TAG = 0x03, 2479 ASM330LHB_TIMESTAMP_TAG = 0x04, 2480 ASM330LHB_CFG_CHANGE_TAG = 0x05, 2481 } asm330lhb_fifo_tag_t; 2482 int32_t asm330lhb_fifo_sensor_tag_get(stmdev_ctx_t *ctx, 2483 asm330lhb_fifo_tag_t *val); 2484 2485 typedef enum 2486 { 2487 ASM330LHB_DEN_DISABLE = 0, 2488 ASM330LHB_LEVEL_FIFO = 6, 2489 ASM330LHB_LEVEL_LETCHED = 3, 2490 ASM330LHB_LEVEL_TRIGGER = 2, 2491 ASM330LHB_EDGE_TRIGGER = 4, 2492 } asm330lhb_den_mode_t; 2493 int32_t asm330lhb_den_mode_set(stmdev_ctx_t *ctx, 2494 asm330lhb_den_mode_t val); 2495 int32_t asm330lhb_den_mode_get(stmdev_ctx_t *ctx, 2496 asm330lhb_den_mode_t *val); 2497 2498 typedef enum 2499 { 2500 ASM330LHB_DEN_ACT_LOW = 0, 2501 ASM330LHB_DEN_ACT_HIGH = 1, 2502 } asm330lhb_den_lh_t; 2503 int32_t asm330lhb_den_polarity_set(stmdev_ctx_t *ctx, 2504 asm330lhb_den_lh_t val); 2505 int32_t asm330lhb_den_polarity_get(stmdev_ctx_t *ctx, 2506 asm330lhb_den_lh_t *val); 2507 2508 typedef enum 2509 { 2510 ASM330LHB_STAMP_IN_GY_DATA = 0, 2511 ASM330LHB_STAMP_IN_XL_DATA = 1, 2512 ASM330LHB_STAMP_IN_GY_XL_DATA = 2, 2513 } asm330lhb_den_xl_g_t; 2514 int32_t asm330lhb_den_enable_set(stmdev_ctx_t *ctx, 2515 asm330lhb_den_xl_g_t val); 2516 int32_t asm330lhb_den_enable_get(stmdev_ctx_t *ctx, 2517 asm330lhb_den_xl_g_t *val); 2518 2519 int32_t asm330lhb_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); 2520 int32_t asm330lhb_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); 2521 2522 int32_t asm330lhb_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); 2523 int32_t asm330lhb_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); 2524 2525 int32_t asm330lhb_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); 2526 int32_t asm330lhb_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); 2527 2528 int32_t asm330lhb_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); 2529 int32_t asm330lhb_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); 2530 2531 int32_t asm330lhb_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); 2532 int32_t asm330lhb_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); 2533 2534 int32_t asm330lhb_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val); 2535 int32_t asm330lhb_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val); 2536 2537 typedef enum 2538 { 2539 ASM330LHB_Z_EQ_Y = 0, 2540 ASM330LHB_Z_EQ_MIN_Y = 1, 2541 ASM330LHB_Z_EQ_X = 2, 2542 ASM330LHB_Z_EQ_MIN_X = 3, 2543 ASM330LHB_Z_EQ_MIN_Z = 4, 2544 ASM330LHB_Z_EQ_Z = 5, 2545 } asm330lhb_mag_z_axis_t; 2546 int32_t asm330lhb_mag_z_orient_set(stmdev_ctx_t *ctx, 2547 asm330lhb_mag_z_axis_t val); 2548 int32_t asm330lhb_mag_z_orient_get(stmdev_ctx_t *ctx, 2549 asm330lhb_mag_z_axis_t *val); 2550 2551 typedef enum 2552 { 2553 ASM330LHB_Y_EQ_Y = 0, 2554 ASM330LHB_Y_EQ_MIN_Y = 1, 2555 ASM330LHB_Y_EQ_X = 2, 2556 ASM330LHB_Y_EQ_MIN_X = 3, 2557 ASM330LHB_Y_EQ_MIN_Z = 4, 2558 ASM330LHB_Y_EQ_Z = 5, 2559 } asm330lhb_mag_y_axis_t; 2560 int32_t asm330lhb_mag_y_orient_set(stmdev_ctx_t *ctx, 2561 asm330lhb_mag_y_axis_t val); 2562 int32_t asm330lhb_mag_y_orient_get(stmdev_ctx_t *ctx, 2563 asm330lhb_mag_y_axis_t *val); 2564 2565 typedef enum 2566 { 2567 ASM330LHB_X_EQ_Y = 0, 2568 ASM330LHB_X_EQ_MIN_Y = 1, 2569 ASM330LHB_X_EQ_X = 2, 2570 ASM330LHB_X_EQ_MIN_X = 3, 2571 ASM330LHB_X_EQ_MIN_Z = 4, 2572 ASM330LHB_X_EQ_Z = 5, 2573 } asm330lhb_mag_x_axis_t; 2574 int32_t asm330lhb_mag_x_orient_set(stmdev_ctx_t *ctx, 2575 asm330lhb_mag_x_axis_t val); 2576 int32_t asm330lhb_mag_x_orient_get(stmdev_ctx_t *ctx, 2577 asm330lhb_mag_x_axis_t *val); 2578 2579 typedef struct 2580 { 2581 uint16_t fsm1 : 1; 2582 uint16_t fsm2 : 1; 2583 uint16_t fsm3 : 1; 2584 uint16_t fsm4 : 1; 2585 uint16_t fsm5 : 1; 2586 uint16_t fsm6 : 1; 2587 uint16_t fsm7 : 1; 2588 uint16_t fsm8 : 1; 2589 uint16_t fsm9 : 1; 2590 uint16_t fsm10 : 1; 2591 uint16_t fsm11 : 1; 2592 uint16_t fsm12 : 1; 2593 uint16_t fsm13 : 1; 2594 uint16_t fsm14 : 1; 2595 uint16_t fsm15 : 1; 2596 uint16_t fsm16 : 1; 2597 } asm330lhb_fsm_status_t; 2598 int32_t asm330lhb_fsm_status_get(stmdev_ctx_t *ctx, 2599 asm330lhb_fsm_status_t *val); 2600 int32_t asm330lhb_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *buff); 2601 2602 int32_t asm330lhb_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, 2603 uint8_t *val); 2604 2605 int32_t asm330lhb_emb_func_clk_dis_set(stmdev_ctx_t *ctx, uint8_t val); 2606 int32_t asm330lhb_emb_func_clk_dis_get(stmdev_ctx_t *ctx, uint8_t *val); 2607 2608 int32_t asm330lhb_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); 2609 int32_t asm330lhb_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); 2610 2611 typedef struct 2612 { 2613 asm330lhb_fsm_enable_a_t fsm_enable_a; 2614 asm330lhb_fsm_enable_b_t fsm_enable_b; 2615 } asm330lhb_emb_fsm_enable_t; 2616 int32_t asm330lhb_fsm_enable_set(stmdev_ctx_t *ctx, 2617 asm330lhb_emb_fsm_enable_t *val); 2618 int32_t asm330lhb_fsm_enable_get(stmdev_ctx_t *ctx, 2619 asm330lhb_emb_fsm_enable_t *val); 2620 2621 int32_t asm330lhb_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); 2622 int32_t asm330lhb_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); 2623 2624 typedef enum 2625 { 2626 ASM330LHB_LC_NORMAL = 0, 2627 ASM330LHB_LC_CLEAR = 1, 2628 ASM330LHB_LC_CLEAR_DONE = 2, 2629 } asm330lhb_fsm_lc_clr_t; 2630 int32_t asm330lhb_long_clr_set(stmdev_ctx_t *ctx, 2631 asm330lhb_fsm_lc_clr_t val); 2632 int32_t asm330lhb_long_clr_get(stmdev_ctx_t *ctx, 2633 asm330lhb_fsm_lc_clr_t *val); 2634 2635 typedef enum 2636 { 2637 ASM330LHB_ODR_FSM_12Hz5 = 0, 2638 ASM330LHB_ODR_FSM_26Hz = 1, 2639 ASM330LHB_ODR_FSM_52Hz = 2, 2640 ASM330LHB_ODR_FSM_104Hz = 3, 2641 } asm330lhb_fsm_odr_t; 2642 int32_t asm330lhb_fsm_data_rate_set(stmdev_ctx_t *ctx, 2643 asm330lhb_fsm_odr_t val); 2644 int32_t asm330lhb_fsm_data_rate_get(stmdev_ctx_t *ctx, 2645 asm330lhb_fsm_odr_t *val); 2646 2647 int32_t asm330lhb_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); 2648 int32_t asm330lhb_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); 2649 2650 int32_t asm330lhb_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val); 2651 int32_t asm330lhb_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val); 2652 2653 int32_t asm330lhb_fsm_number_of_programs_set(stmdev_ctx_t *ctx, 2654 uint8_t *buff); 2655 int32_t asm330lhb_fsm_number_of_programs_get(stmdev_ctx_t *ctx, 2656 uint8_t *buff); 2657 2658 int32_t asm330lhb_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val); 2659 int32_t asm330lhb_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val); 2660 2661 int32_t asm330lhb_mlc_set(stmdev_ctx_t *ctx, uint8_t val); 2662 int32_t asm330lhb_mlc_get(stmdev_ctx_t *ctx, uint8_t *val); 2663 2664 int32_t asm330lhb_mlc_status_get(stmdev_ctx_t *ctx, 2665 asm330lhb_mlc_status_mainpage_t *val); 2666 2667 typedef enum 2668 { 2669 ASM330LHB_ODR_PRGS_12Hz5 = 0, 2670 ASM330LHB_ODR_PRGS_26Hz = 1, 2671 ASM330LHB_ODR_PRGS_52Hz = 2, 2672 ASM330LHB_ODR_PRGS_104Hz = 3, 2673 } asm330lhb_mlc_odr_t; 2674 int32_t asm330lhb_mlc_data_rate_set(stmdev_ctx_t *ctx, 2675 asm330lhb_mlc_odr_t val); 2676 int32_t asm330lhb_mlc_data_rate_get(stmdev_ctx_t *ctx, 2677 asm330lhb_mlc_odr_t *val); 2678 2679 int32_t asm330lhb_mlc_init_set(stmdev_ctx_t *ctx, uint8_t val); 2680 int32_t asm330lhb_mlc_init_get(stmdev_ctx_t *ctx, uint8_t *val); 2681 2682 int32_t asm330lhb_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); 2683 2684 int32_t asm330lhb_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); 2685 int32_t asm330lhb_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); 2686 2687 /** 2688 *@} 2689 * 2690 */ 2691 2692 #ifdef __cplusplus 2693 } 2694 #endif 2695 2696 #endif /* ASM330LHB_REGS_H */ 2697 2698 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2699
