1 /** 2 ****************************************************************************** 3 * @file lsm6dsv16bx_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dsv16bx_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSV16BX_REGS_H 23 #define LSM6DSV16BX_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSV16BX 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DSV16BX_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DSV16BX_I2C_ADD_L 0xD5U 173 #define LSM6DSV16BX_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DSV16BX_ID 0x71U 177 178 /** 179 * @} 180 * 181 */ 182 183 /** @defgroup bitfields page main 184 * @{ 185 * 186 */ 187 188 #define LSM6DSV16BX_FUNC_CFG_ACCESS 0x1U 189 typedef struct 190 { 191 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 192 uint8_t not_used0 : 2; 193 uint8_t sw_por : 1; 194 uint8_t fsm_wr_ctrl_en : 1; 195 uint8_t not_used1 : 3; 196 uint8_t emb_func_reg_access : 1; 197 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 198 uint8_t emb_func_reg_access : 1; 199 uint8_t not_used1 : 3; 200 uint8_t fsm_wr_ctrl_en : 1; 201 uint8_t sw_por : 1; 202 uint8_t not_used0 : 2; 203 #endif /* DRV_BYTE_ORDER */ 204 } lsm6dsv16bx_func_cfg_access_t; 205 206 #define LSM6DSV16BX_PIN_CTRL 0x2U 207 typedef struct 208 { 209 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 210 uint8_t not_used0 : 5; 211 uint8_t ibhr_por_en : 1; 212 uint8_t sdo_pu_en : 1; 213 uint8_t tdm_wclk_pu_dis : 1; 214 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 215 uint8_t tdm_wclk_pu_dis : 1; 216 uint8_t sdo_pu_en : 1; 217 uint8_t ibhr_por_en : 1; 218 uint8_t not_used0 : 5; 219 #endif /* DRV_BYTE_ORDER */ 220 } lsm6dsv16bx_pin_ctrl_t; 221 222 #define LSM6DSV16BX_IF_CFG 0x3U 223 typedef struct 224 { 225 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 226 uint8_t i2c_i3c_disable : 1; 227 uint8_t not_used0 : 1; 228 uint8_t sim : 1; 229 uint8_t pp_od : 1; 230 uint8_t h_lactive : 1; 231 uint8_t asf_ctrl : 1; 232 uint8_t tdm_out_pu_en : 1; 233 uint8_t sda_pu_en : 1; 234 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 235 uint8_t sda_pu_en : 1; 236 uint8_t tdm_out_pu_en : 1; 237 uint8_t asf_ctrl : 1; 238 uint8_t h_lactive : 1; 239 uint8_t pp_od : 1; 240 uint8_t sim : 1; 241 uint8_t not_used0 : 1; 242 uint8_t i2c_i3c_disable : 1; 243 #endif /* DRV_BYTE_ORDER */ 244 } lsm6dsv16bx_if_cfg_t; 245 246 #define LSM6DSV16BX_FIFO_CTRL1 0x7U 247 typedef struct 248 { 249 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 250 uint8_t wtm : 8; 251 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 252 uint8_t wtm : 8; 253 #endif /* DRV_BYTE_ORDER */ 254 } lsm6dsv16bx_fifo_ctrl1_t; 255 256 #define LSM6DSV16BX_FIFO_CTRL2 0x8U 257 typedef struct 258 { 259 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 260 uint8_t xl_dualc_batch_from_fsm : 1; 261 uint8_t uncompr_rate : 2; 262 uint8_t not_used0 : 1; 263 uint8_t odr_chg_en : 1; 264 uint8_t not_used1 : 1; 265 uint8_t fifo_compr_rt_en : 1; 266 uint8_t stop_on_wtm : 1; 267 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 268 uint8_t stop_on_wtm : 1; 269 uint8_t fifo_compr_rt_en : 1; 270 uint8_t not_used1 : 1; 271 uint8_t odr_chg_en : 1; 272 uint8_t not_used0 : 1; 273 uint8_t uncompr_rate : 2; 274 uint8_t xl_dualc_batch_from_fsm : 1; 275 #endif /* DRV_BYTE_ORDER */ 276 } lsm6dsv16bx_fifo_ctrl2_t; 277 278 #define LSM6DSV16BX_FIFO_CTRL3 0x9U 279 typedef struct 280 { 281 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 282 uint8_t bdr_xl : 4; 283 uint8_t bdr_gy : 4; 284 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 285 uint8_t bdr_gy : 4; 286 uint8_t bdr_xl : 4; 287 #endif /* DRV_BYTE_ORDER */ 288 } lsm6dsv16bx_fifo_ctrl3_t; 289 290 #define LSM6DSV16BX_FIFO_CTRL4 0x0AU 291 typedef struct 292 { 293 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 294 uint8_t fifo_mode : 3; 295 uint8_t not_used0 : 1; 296 uint8_t odr_t_batch : 2; 297 uint8_t dec_ts_batch : 2; 298 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 299 uint8_t dec_ts_batch : 2; 300 uint8_t odr_t_batch : 2; 301 uint8_t not_used0 : 1; 302 uint8_t fifo_mode : 3; 303 #endif /* DRV_BYTE_ORDER */ 304 } lsm6dsv16bx_fifo_ctrl4_t; 305 306 #define LSM6DSV16BX_COUNTER_BDR_REG1 0x0BU 307 typedef struct 308 { 309 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 310 uint8_t cnt_bdr_th : 2; 311 uint8_t ah_qvar_batch_en : 1; 312 uint8_t not_used0 : 2; 313 uint8_t trig_counter_bdr : 2; 314 uint8_t not_used1 : 1; 315 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 316 uint8_t not_used1 : 1; 317 uint8_t trig_counter_bdr : 2; 318 uint8_t not_used0 : 2; 319 uint8_t ah_qvar_batch_en : 1; 320 uint8_t cnt_bdr_th : 2; 321 #endif /* DRV_BYTE_ORDER */ 322 } lsm6dsv16bx_counter_bdr_reg1_t; 323 324 #define LSM6DSV16BX_COUNTER_BDR_REG2 0x0CU 325 typedef struct 326 { 327 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 328 uint8_t cnt_bdr_th : 8; 329 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 330 uint8_t cnt_bdr_th : 8; 331 #endif /* DRV_BYTE_ORDER */ 332 } lsm6dsv16bx_counter_bdr_reg2_t; 333 334 #define LSM6DSV16BX_INT1_CTRL 0x0DU 335 typedef struct 336 { 337 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 338 uint8_t int1_drdy_xl : 1; 339 uint8_t int1_drdy_g : 1; 340 uint8_t not_used0 : 1; 341 uint8_t int1_fifo_th : 1; 342 uint8_t int1_fifo_ovr : 1; 343 uint8_t int1_fifo_full : 1; 344 uint8_t int1_cnt_bdr : 1; 345 uint8_t not_used1 : 1; 346 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 347 uint8_t not_used1 : 1; 348 uint8_t int1_cnt_bdr : 1; 349 uint8_t int1_fifo_full : 1; 350 uint8_t int1_fifo_ovr : 1; 351 uint8_t int1_fifo_th : 1; 352 uint8_t not_used0 : 1; 353 uint8_t int1_drdy_g : 1; 354 uint8_t int1_drdy_xl : 1; 355 #endif /* DRV_BYTE_ORDER */ 356 } lsm6dsv16bx_int1_ctrl_t; 357 358 #define LSM6DSV16BX_INT2_CTRL 0x0EU 359 typedef struct 360 { 361 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 362 uint8_t int2_drdy_xl : 1; 363 uint8_t int2_drdy_g : 1; 364 uint8_t not_used0 : 1; 365 uint8_t int2_fifo_th : 1; 366 uint8_t int2_fifo_ovr : 1; 367 uint8_t int2_fifo_full : 1; 368 uint8_t int2_cnt_bdr : 1; 369 uint8_t int2_emb_func_endop : 1; 370 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 371 uint8_t int2_emb_func_endop : 1; 372 uint8_t int2_cnt_bdr : 1; 373 uint8_t int2_fifo_full : 1; 374 uint8_t int2_fifo_ovr : 1; 375 uint8_t int2_fifo_th : 1; 376 uint8_t not_used0 : 1; 377 uint8_t int2_drdy_g : 1; 378 uint8_t int2_drdy_xl : 1; 379 #endif /* DRV_BYTE_ORDER */ 380 } lsm6dsv16bx_int2_ctrl_t; 381 382 #define LSM6DSV16BX_WHO_AM_I 0x0FU 383 typedef struct 384 { 385 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 386 uint8_t id : 8; 387 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 388 uint8_t id : 8; 389 #endif /* DRV_BYTE_ORDER */ 390 } lsm6dsv16bx_who_am_i_t; 391 392 #define LSM6DSV16BX_CTRL1 0x10U 393 typedef struct 394 { 395 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 396 uint8_t odr_xl : 4; 397 uint8_t op_mode_xl : 3; 398 uint8_t not_used0 : 1; 399 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 400 uint8_t not_used0 : 1; 401 uint8_t op_mode_xl : 3; 402 uint8_t odr_xl : 4; 403 #endif /* DRV_BYTE_ORDER */ 404 } lsm6dsv16bx_ctrl1_t; 405 406 #define LSM6DSV16BX_CTRL2 0x11U 407 typedef struct 408 { 409 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 410 uint8_t odr_g : 4; 411 uint8_t op_mode_g : 3; 412 uint8_t not_used0 : 1; 413 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 414 uint8_t not_used0 : 1; 415 uint8_t op_mode_g : 3; 416 uint8_t odr_g : 4; 417 #endif /* DRV_BYTE_ORDER */ 418 } lsm6dsv16bx_ctrl2_t; 419 420 #define LSM6DSV16BX_CTRL3 0x12U 421 typedef struct 422 { 423 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 424 uint8_t sw_reset : 1; 425 uint8_t not_used0 : 1; 426 uint8_t if_inc : 1; 427 uint8_t not_used1 : 3; 428 uint8_t bdu : 1; 429 uint8_t boot : 1; 430 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 431 uint8_t boot : 1; 432 uint8_t bdu : 1; 433 uint8_t not_used1 : 3; 434 uint8_t if_inc : 1; 435 uint8_t not_used0 : 1; 436 uint8_t sw_reset : 1; 437 #endif /* DRV_BYTE_ORDER */ 438 } lsm6dsv16bx_ctrl3_t; 439 440 #define LSM6DSV16BX_CTRL4 0x13U 441 typedef struct 442 { 443 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 444 uint8_t not_used1 : 1; 445 uint8_t drdy_pulsed : 1; 446 uint8_t int2_drdy_temp : 1; 447 uint8_t drdy_mask : 1; 448 uint8_t int2_on_int1 : 1; 449 uint8_t not_used0 : 3; 450 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 451 uint8_t not_used0 : 3; 452 uint8_t int2_on_int1 : 1; 453 uint8_t drdy_mask : 1; 454 uint8_t int2_drdy_temp : 1; 455 uint8_t drdy_pulsed : 1; 456 uint8_t not_used1 : 1; 457 #endif /* DRV_BYTE_ORDER */ 458 } lsm6dsv16bx_ctrl4_t; 459 460 #define LSM6DSV16BX_CTRL5 0x14U 461 typedef struct 462 { 463 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 464 uint8_t int_en_i3c : 1; 465 uint8_t bus_act_sel : 2; 466 uint8_t not_used0 : 5; 467 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 468 uint8_t not_used0 : 5; 469 uint8_t bus_act_sel : 2; 470 uint8_t int_en_i3c : 1; 471 #endif /* DRV_BYTE_ORDER */ 472 } lsm6dsv16bx_ctrl5_t; 473 474 #define LSM6DSV16BX_CTRL6 0x15U 475 typedef struct 476 { 477 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 478 uint8_t fs_g : 4; 479 uint8_t lpf1_g_bw : 3; 480 uint8_t not_used0 : 1; 481 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 482 uint8_t not_used0 : 1; 483 uint8_t lpf1_g_bw : 3; 484 uint8_t fs_g : 4; 485 #endif /* DRV_BYTE_ORDER */ 486 } lsm6dsv16bx_ctrl6_t; 487 488 #define LSM6DSV16BX_CTRL7 0x16U 489 typedef struct 490 { 491 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 492 uint8_t lpf1_g_en : 1; 493 uint8_t not_used0 : 1; 494 uint8_t ah_qvar2_en : 1; 495 uint8_t ah_qvar1_en : 1; 496 uint8_t ah_qvar_c_zin : 2; 497 uint8_t int2_drdy_ah_qvar : 1; 498 uint8_t ah_qvar_en : 1; 499 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 500 uint8_t ah_qvar_en : 1; 501 uint8_t int2_drdy_ah_qvar : 1; 502 uint8_t ah_qvar_c_zin : 2; 503 uint8_t ah_qvar1_en : 1; 504 uint8_t ah_qvar2_en : 1; 505 uint8_t not_used0 : 1; 506 uint8_t lpf1_g_en : 1; 507 #endif /* DRV_BYTE_ORDER */ 508 } lsm6dsv16bx_ctrl7_t; 509 510 #define LSM6DSV16BX_CTRL8 0x17U 511 typedef struct 512 { 513 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 514 uint8_t fs_xl : 2; 515 uint8_t not_used0 : 1; 516 uint8_t xl_dualc_en : 1; 517 uint8_t ah_qvar_hpf : 1; 518 uint8_t hp_lpf2_xl_bw : 3; 519 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 520 uint8_t hp_lpf2_xl_bw : 3; 521 uint8_t ah_qvar_hpf : 1; 522 uint8_t xl_dualc_en : 1; 523 uint8_t not_used0 : 1; 524 uint8_t fs_xl : 2; 525 #endif /* DRV_BYTE_ORDER */ 526 } lsm6dsv16bx_ctrl8_t; 527 528 #define LSM6DSV16BX_CTRL9 0x18U 529 typedef struct 530 { 531 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 532 uint8_t usr_off_on_out : 1; 533 uint8_t usr_off_w : 1; 534 uint8_t not_used0 : 1; 535 uint8_t lpf2_xl_en : 1; 536 uint8_t hp_slope_xl_en : 1; 537 uint8_t xl_fastsettl_mode : 1; 538 uint8_t hp_ref_mode_xl : 1; 539 uint8_t ah_qvar_lpf : 1; 540 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 541 uint8_t ah_qvar_lpf : 1; 542 uint8_t hp_ref_mode_xl : 1; 543 uint8_t xl_fastsettl_mode : 1; 544 uint8_t hp_slope_xl_en : 1; 545 uint8_t lpf2_xl_en : 1; 546 uint8_t not_used0 : 1; 547 uint8_t usr_off_w : 1; 548 uint8_t usr_off_on_out : 1; 549 #endif /* DRV_BYTE_ORDER */ 550 } lsm6dsv16bx_ctrl9_t; 551 552 #define LSM6DSV16BX_CTRL10 0x19U 553 typedef struct 554 { 555 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 556 uint8_t st_xl : 2; 557 uint8_t st_g : 2; 558 uint8_t xl_st_offset : 1; 559 uint8_t ah_qvar_sw : 1; 560 uint8_t emb_func_debug : 1; 561 uint8_t not_used0 : 1; 562 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 563 uint8_t not_used0 : 1; 564 uint8_t emb_func_debug : 1; 565 uint8_t ah_qvar_sw : 1; 566 uint8_t xl_st_offset : 1; 567 uint8_t st_g : 2; 568 uint8_t st_xl : 2; 569 #endif /* DRV_BYTE_ORDER */ 570 } lsm6dsv16bx_ctrl10_t; 571 572 #define LSM6DSV16BX_CTRL_STATUS 0x1AU 573 typedef struct 574 { 575 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 576 uint8_t not_used0 : 2; 577 uint8_t fsm_wr_ctrl_status : 1; 578 uint8_t not_used1 : 5; 579 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 580 uint8_t not_used1 : 5; 581 uint8_t fsm_wr_ctrl_status : 1; 582 uint8_t not_used0 : 2; 583 #endif /* DRV_BYTE_ORDER */ 584 } lsm6dsv16bx_ctrl_status_t; 585 586 #define LSM6DSV16BX_FIFO_STATUS1 0x1BU 587 typedef struct 588 { 589 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 590 uint8_t diff_fifo : 8; 591 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 592 uint8_t diff_fifo : 8; 593 #endif /* DRV_BYTE_ORDER */ 594 } lsm6dsv16bx_fifo_status1_t; 595 596 #define LSM6DSV16BX_FIFO_STATUS2 0x1CU 597 typedef struct 598 { 599 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 600 uint8_t diff_fifo : 1; 601 uint8_t not_used0 : 2; 602 uint8_t fifo_ovr_latched : 1; 603 uint8_t counter_bdr_ia : 1; 604 uint8_t fifo_full_ia : 1; 605 uint8_t fifo_ovr_ia : 1; 606 uint8_t fifo_wtm_ia : 1; 607 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 608 uint8_t fifo_wtm_ia : 1; 609 uint8_t fifo_ovr_ia : 1; 610 uint8_t fifo_full_ia : 1; 611 uint8_t counter_bdr_ia : 1; 612 uint8_t fifo_ovr_latched : 1; 613 uint8_t not_used0 : 2; 614 uint8_t diff_fifo : 1; 615 #endif /* DRV_BYTE_ORDER */ 616 } lsm6dsv16bx_fifo_status2_t; 617 618 #define LSM6DSV16BX_ALL_INT_SRC 0x1DU 619 typedef struct 620 { 621 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 622 uint8_t ff_ia : 1; 623 uint8_t wu_ia : 1; 624 uint8_t tap_ia : 1; 625 uint8_t not_used0 : 1; 626 uint8_t d6d_ia : 1; 627 uint8_t sleep_change_ia : 1; 628 uint8_t not_used1 : 1; 629 uint8_t emb_func_ia : 1; 630 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 631 uint8_t emb_func_ia : 1; 632 uint8_t not_used1 : 1; 633 uint8_t sleep_change_ia : 1; 634 uint8_t d6d_ia : 1; 635 uint8_t not_used0 : 1; 636 uint8_t tap_ia : 1; 637 uint8_t wu_ia : 1; 638 uint8_t ff_ia : 1; 639 #endif /* DRV_BYTE_ORDER */ 640 } lsm6dsv16bx_all_int_src_t; 641 642 #define LSM6DSV16BX_STATUS_REG 0x1EU 643 typedef struct 644 { 645 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 646 uint8_t xlda : 1; 647 uint8_t gda : 1; 648 uint8_t tda : 1; 649 uint8_t ah_qvarda : 1; 650 uint8_t not_used0 : 3; 651 uint8_t timestamp_endcount : 1; 652 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 653 uint8_t timestamp_endcount : 1; 654 uint8_t not_used0 : 3; 655 uint8_t ah_qvarda : 1; 656 uint8_t tda : 1; 657 uint8_t gda : 1; 658 uint8_t xlda : 1; 659 #endif /* DRV_BYTE_ORDER */ 660 } lsm6dsv16bx_status_reg_t; 661 662 #define LSM6DSV16BX_OUT_TEMP_L 0x20U 663 typedef struct 664 { 665 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 666 uint8_t temp : 8; 667 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 668 uint8_t temp : 8; 669 #endif /* DRV_BYTE_ORDER */ 670 } lsm6dsv16bx_out_temp_l_t; 671 672 #define LSM6DSV16BX_OUT_TEMP_H 0x21U 673 typedef struct 674 { 675 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 676 uint8_t temp : 8; 677 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 678 uint8_t temp : 8; 679 #endif /* DRV_BYTE_ORDER */ 680 } lsm6dsv16bx_out_temp_h_t; 681 682 #define LSM6DSV16BX_OUTX_L_G 0x22U 683 typedef struct 684 { 685 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 686 uint8_t outx_g : 8; 687 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 688 uint8_t outx_g : 8; 689 #endif /* DRV_BYTE_ORDER */ 690 } lsm6dsv16bx_outx_l_g_t; 691 692 #define LSM6DSV16BX_OUTX_H_G 0x23U 693 typedef struct 694 { 695 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 696 uint8_t outx_g : 8; 697 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 698 uint8_t outx_g : 8; 699 #endif /* DRV_BYTE_ORDER */ 700 } lsm6dsv16bx_outx_h_g_t; 701 702 #define LSM6DSV16BX_OUTY_L_G 0x24U 703 typedef struct 704 { 705 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 706 uint8_t outy_g : 8; 707 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 708 uint8_t outy_g : 8; 709 #endif /* DRV_BYTE_ORDER */ 710 } lsm6dsv16bx_outy_l_g_t; 711 712 #define LSM6DSV16BX_OUTY_H_G 0x25U 713 typedef struct 714 { 715 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 716 uint8_t outy_g : 8; 717 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 718 uint8_t outy_g : 8; 719 #endif /* DRV_BYTE_ORDER */ 720 } lsm6dsv16bx_outy_h_g_t; 721 722 #define LSM6DSV16BX_OUTZ_L_G 0x26U 723 typedef struct 724 { 725 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 726 uint8_t outz_g : 8; 727 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 728 uint8_t outz_g : 8; 729 #endif /* DRV_BYTE_ORDER */ 730 } lsm6dsv16bx_outz_l_g_t; 731 732 #define LSM6DSV16BX_OUTZ_H_G 0x27U 733 typedef struct 734 { 735 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 736 uint8_t outz_g : 8; 737 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 738 uint8_t outz_g : 8; 739 #endif /* DRV_BYTE_ORDER */ 740 } lsm6dsv16bx_outz_h_g_t; 741 742 #define LSM6DSV16BX_OUTZ_L_A 0x28U 743 typedef struct 744 { 745 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 746 uint8_t outz_a : 8; 747 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 748 uint8_t outz_a : 8; 749 #endif /* DRV_BYTE_ORDER */ 750 } lsm6dsv16bx_outz_l_a_t; 751 752 #define LSM6DSV16BX_OUTZ_H_A 0x29U 753 typedef struct 754 { 755 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 756 uint8_t outz_a : 8; 757 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 758 uint8_t outz_a : 8; 759 #endif /* DRV_BYTE_ORDER */ 760 } lsm6dsv16bx_outz_h_a_t; 761 762 #define LSM6DSV16BX_OUTY_L_A 0x2AU 763 typedef struct 764 { 765 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 766 uint8_t outy_a : 8; 767 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 768 uint8_t outy_a : 8; 769 #endif /* DRV_BYTE_ORDER */ 770 } lsm6dsv16bx_outy_l_a_t; 771 772 #define LSM6DSV16BX_OUTY_H_A 0x2BU 773 typedef struct 774 { 775 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 776 uint8_t outy_a : 8; 777 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 778 uint8_t outy_a : 8; 779 #endif /* DRV_BYTE_ORDER */ 780 } lsm6dsv16bx_outy_h_a_t; 781 782 #define LSM6DSV16BX_OUTX_L_A 0x2CU 783 typedef struct 784 { 785 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 786 uint8_t outx_a : 8; 787 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 788 uint8_t outx_a : 8; 789 #endif /* DRV_BYTE_ORDER */ 790 } lsm6dsv16bx_outx_l_a_t; 791 792 #define LSM6DSV16BX_OUTX_H_A 0x2DU 793 typedef struct 794 { 795 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 796 uint8_t outx_a : 8; 797 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 798 uint8_t outx_a : 8; 799 #endif /* DRV_BYTE_ORDER */ 800 } lsm6dsv16bx_outx_h_a_t; 801 802 #define LSM6DSV16BX_UI_OUTZ_L_A_OIS_DUALC 0x34U 803 typedef struct 804 { 805 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 806 uint8_t ui_outz_a_ois_dualc : 8; 807 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 808 uint8_t ui_outz_a_ois_dualc : 8; 809 #endif /* DRV_BYTE_ORDER */ 810 } lsm6dsv16bx_ui_outz_l_a_ois_dualc_t; 811 812 #define LSM6DSV16BX_UI_OUTZ_H_A_OIS_DUALC 0x35U 813 typedef struct 814 { 815 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 816 uint8_t ui_outz_a_ois_dualc : 8; 817 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 818 uint8_t ui_outz_a_ois_dualc : 8; 819 #endif /* DRV_BYTE_ORDER */ 820 } lsm6dsv16bx_ui_outz_h_a_ois_dualc_t; 821 822 #define LSM6DSV16BX_UI_OUTY_L_A_OIS_DUALC 0x36U 823 typedef struct 824 { 825 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 826 uint8_t ui_outy_a_ois_dualc : 8; 827 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 828 uint8_t ui_outy_a_ois_dualc : 8; 829 #endif /* DRV_BYTE_ORDER */ 830 } lsm6dsv16bx_ui_outy_l_a_ois_dualc_t; 831 832 #define LSM6DSV16BX_UI_OUTY_H_A_OIS_DUALC 0x37U 833 typedef struct 834 { 835 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 836 uint8_t ui_outy_a_ois_dualc : 8; 837 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 838 uint8_t ui_outy_a_ois_dualc : 8; 839 #endif /* DRV_BYTE_ORDER */ 840 } lsm6dsv16bx_ui_outy_h_a_ois_dualc_t; 841 842 #define LSM6DSV16BX_UI_OUTX_L_A_OIS_DUALC 0x38U 843 typedef struct 844 { 845 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 846 uint8_t ui_outx_a_ois_dualc : 8; 847 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 848 uint8_t ui_outx_a_ois_dualc : 8; 849 #endif /* DRV_BYTE_ORDER */ 850 } lsm6dsv16bx_ui_outx_l_a_ois_dualc_t; 851 852 #define LSM6DSV16BX_UI_OUTX_H_A_OIS_DUALC 0x39U 853 typedef struct 854 { 855 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 856 uint8_t ui_outx_a_ois_dualc : 8; 857 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 858 uint8_t ui_outx_a_ois_dualc : 8; 859 #endif /* DRV_BYTE_ORDER */ 860 } lsm6dsv16bx_ui_outx_h_a_ois_dualc_t; 861 862 #define LSM6DSV16BX_AH_QVAR_OUT_L 0x3AU 863 typedef struct 864 { 865 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 866 uint8_t ah_qvar : 8; 867 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 868 uint8_t ah_qvar : 8; 869 #endif /* DRV_BYTE_ORDER */ 870 } lsm6dsv16bx_ah_qvar_out_l_t; 871 872 #define LSM6DSV16BX_AH_QVAR_OUT_H 0x3BU 873 typedef struct 874 { 875 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 876 uint8_t ah_qvar : 8; 877 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 878 uint8_t ah_qvar : 8; 879 #endif /* DRV_BYTE_ORDER */ 880 } lsm6dsv16bx_ah_qvar_out_h_t; 881 882 #define LSM6DSV16BX_TIMESTAMP0 0x40U 883 typedef struct 884 { 885 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 886 uint8_t timestamp : 8; 887 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 888 uint8_t timestamp : 8; 889 #endif /* DRV_BYTE_ORDER */ 890 } lsm6dsv16bx_timestamp0_t; 891 892 #define LSM6DSV16BX_TIMESTAMP1 0x41U 893 typedef struct 894 { 895 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 896 uint8_t timestamp : 8; 897 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 898 uint8_t timestamp : 8; 899 #endif /* DRV_BYTE_ORDER */ 900 } lsm6dsv16bx_timestamp1_t; 901 902 #define LSM6DSV16BX_TIMESTAMP2 0x42U 903 typedef struct 904 { 905 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 906 uint8_t timestamp : 8; 907 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 908 uint8_t timestamp : 8; 909 #endif /* DRV_BYTE_ORDER */ 910 } lsm6dsv16bx_timestamp2_t; 911 912 #define LSM6DSV16BX_TIMESTAMP3 0x43U 913 typedef struct 914 { 915 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 916 uint8_t timestamp : 8; 917 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 918 uint8_t timestamp : 8; 919 #endif /* DRV_BYTE_ORDER */ 920 } lsm6dsv16bx_timestamp3_t; 921 922 #define LSM6DSV16BX_WAKE_UP_SRC 0x45U 923 typedef struct 924 { 925 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 926 uint8_t x_wu : 1; 927 uint8_t y_wu : 1; 928 uint8_t z_wu : 1; 929 uint8_t wu_ia : 1; 930 uint8_t sleep_state : 1; 931 uint8_t ff_ia : 1; 932 uint8_t sleep_change_ia : 1; 933 uint8_t not_used0 : 1; 934 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 935 uint8_t not_used0 : 1; 936 uint8_t sleep_change_ia : 1; 937 uint8_t ff_ia : 1; 938 uint8_t sleep_state : 1; 939 uint8_t wu_ia : 1; 940 uint8_t z_wu : 1; 941 uint8_t y_wu : 1; 942 uint8_t x_wu : 1; 943 #endif /* DRV_BYTE_ORDER */ 944 } lsm6dsv16bx_wake_up_src_t; 945 946 #define LSM6DSV16BX_TAP_SRC 0x46U 947 typedef struct 948 { 949 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 950 uint8_t x_tap : 1; 951 uint8_t y_tap : 1; 952 uint8_t z_tap : 1; 953 uint8_t tap_sign : 1; 954 uint8_t not_used0 : 1; 955 uint8_t double_tap : 1; 956 uint8_t single_tap : 1; 957 uint8_t tap_ia : 1; 958 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 959 uint8_t tap_ia : 1; 960 uint8_t single_tap : 1; 961 uint8_t double_tap : 1; 962 uint8_t not_used0 : 1; 963 uint8_t tap_sign : 1; 964 uint8_t z_tap : 1; 965 uint8_t y_tap : 1; 966 uint8_t x_tap : 1; 967 #endif /* DRV_BYTE_ORDER */ 968 } lsm6dsv16bx_tap_src_t; 969 970 #define LSM6DSV16BX_D6D_SRC 0x47U 971 typedef struct 972 { 973 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 974 uint8_t zl : 1; 975 uint8_t zh : 1; 976 uint8_t yl : 1; 977 uint8_t yh : 1; 978 uint8_t xl : 1; 979 uint8_t xh : 1; 980 uint8_t d6d_ia : 1; 981 uint8_t not_used0 : 1; 982 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 983 uint8_t not_used0 : 1; 984 uint8_t d6d_ia : 1; 985 uint8_t xh : 1; 986 uint8_t xl : 1; 987 uint8_t yh : 1; 988 uint8_t yl : 1; 989 uint8_t zh : 1; 990 uint8_t zl : 1; 991 #endif /* DRV_BYTE_ORDER */ 992 } lsm6dsv16bx_d6d_src_t; 993 994 #define LSM6DSV16BX_EMB_FUNC_STATUS_MAINPAGE 0x49U 995 typedef struct 996 { 997 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 998 uint8_t not_used0 : 3; 999 uint8_t is_step_det : 1; 1000 uint8_t is_tilt : 1; 1001 uint8_t is_sigmot : 1; 1002 uint8_t not_used1 : 1; 1003 uint8_t is_fsm_lc : 1; 1004 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1005 uint8_t is_fsm_lc : 1; 1006 uint8_t not_used1 : 1; 1007 uint8_t is_sigmot : 1; 1008 uint8_t is_tilt : 1; 1009 uint8_t is_step_det : 1; 1010 uint8_t not_used0 : 3; 1011 #endif /* DRV_BYTE_ORDER */ 1012 } lsm6dsv16bx_emb_func_status_mainpage_t; 1013 1014 #define LSM6DSV16BX_FSM_STATUS_MAINPAGE 0x4AU 1015 typedef struct 1016 { 1017 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1018 uint8_t is_fsm1 : 1; 1019 uint8_t is_fsm2 : 1; 1020 uint8_t is_fsm3 : 1; 1021 uint8_t is_fsm4 : 1; 1022 uint8_t is_fsm5 : 1; 1023 uint8_t is_fsm6 : 1; 1024 uint8_t is_fsm7 : 1; 1025 uint8_t is_fsm8 : 1; 1026 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1027 uint8_t is_fsm8 : 1; 1028 uint8_t is_fsm7 : 1; 1029 uint8_t is_fsm6 : 1; 1030 uint8_t is_fsm5 : 1; 1031 uint8_t is_fsm4 : 1; 1032 uint8_t is_fsm3 : 1; 1033 uint8_t is_fsm2 : 1; 1034 uint8_t is_fsm1 : 1; 1035 #endif /* DRV_BYTE_ORDER */ 1036 } lsm6dsv16bx_fsm_status_mainpage_t; 1037 1038 #define LSM6DSV16BX_MLC_STATUS_MAINPAGE 0x4BU 1039 typedef struct 1040 { 1041 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1042 uint8_t is_mlc1 : 1; 1043 uint8_t is_mlc2 : 1; 1044 uint8_t is_mlc3 : 1; 1045 uint8_t is_mlc4 : 1; 1046 uint8_t not_used0 : 4; 1047 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1048 uint8_t not_used0 : 4; 1049 uint8_t is_mlc4 : 1; 1050 uint8_t is_mlc3 : 1; 1051 uint8_t is_mlc2 : 1; 1052 uint8_t is_mlc1 : 1; 1053 #endif /* DRV_BYTE_ORDER */ 1054 } lsm6dsv16bx_mlc_status_mainpage_t; 1055 1056 #define LSM6DSV16BX_INTERNAL_FREQ 0x4FU 1057 typedef struct 1058 { 1059 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1060 uint8_t freq_fine : 8; 1061 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1062 uint8_t freq_fine : 8; 1063 #endif /* DRV_BYTE_ORDER */ 1064 } lsm6dsv16bx_internal_freq_t; 1065 1066 #define LSM6DSV16BX_FUNCTIONS_ENABLE 0x50U 1067 typedef struct 1068 { 1069 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1070 uint8_t inact_en : 2; 1071 uint8_t not_used0 : 1; 1072 uint8_t dis_rst_lir_all_int : 1; 1073 uint8_t not_used1 : 2; 1074 uint8_t timestamp_en : 1; 1075 uint8_t interrupts_enable : 1; 1076 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1077 uint8_t interrupts_enable : 1; 1078 uint8_t timestamp_en : 1; 1079 uint8_t not_used1 : 2; 1080 uint8_t dis_rst_lir_all_int : 1; 1081 uint8_t not_used0 : 1; 1082 uint8_t inact_en : 2; 1083 #endif /* DRV_BYTE_ORDER */ 1084 } lsm6dsv16bx_functions_enable_t; 1085 1086 #define LSM6DSV16BX_INACTIVITY_DUR 0x54U 1087 typedef struct 1088 { 1089 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1090 uint8_t inact_dur : 2; 1091 uint8_t xl_inact_odr : 2; 1092 uint8_t wu_inact_ths_w : 3; 1093 uint8_t sleep_status_on_int : 1; 1094 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1095 uint8_t sleep_status_on_int : 1; 1096 uint8_t wu_inact_ths_w : 3; 1097 uint8_t xl_inact_odr : 2; 1098 uint8_t inact_dur : 2; 1099 #endif /* DRV_BYTE_ORDER */ 1100 } lsm6dsv16bx_inactivity_dur_t; 1101 1102 #define LSM6DSV16BX_INACTIVITY_THS 0x55U 1103 typedef struct 1104 { 1105 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1106 uint8_t inact_ths : 6; 1107 uint8_t not_used0 : 2; 1108 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1109 uint8_t not_used0 : 2; 1110 uint8_t inact_ths : 6; 1111 #endif /* DRV_BYTE_ORDER */ 1112 } lsm6dsv16bx_inactivity_ths_t; 1113 1114 #define LSM6DSV16BX_TAP_CFG0 0x56U 1115 typedef struct 1116 { 1117 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1118 uint8_t lir : 1; 1119 uint8_t tap_x_en : 1; 1120 uint8_t tap_y_en : 1; 1121 uint8_t tap_z_en : 1; 1122 uint8_t slope_fds : 1; 1123 uint8_t hw_func_mask_xl_settl : 1; 1124 uint8_t low_pass_on_6d : 1; 1125 uint8_t not_used1 : 1; 1126 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1127 uint8_t not_used1 : 1; 1128 uint8_t low_pass_on_6d : 1; 1129 uint8_t hw_func_mask_xl_settl : 1; 1130 uint8_t slope_fds : 1; 1131 uint8_t tap_z_en : 1; 1132 uint8_t tap_y_en : 1; 1133 uint8_t tap_x_en : 1; 1134 uint8_t lir : 1; 1135 #endif /* DRV_BYTE_ORDER */ 1136 } lsm6dsv16bx_tap_cfg0_t; 1137 1138 #define LSM6DSV16BX_TAP_CFG1 0x57U 1139 typedef struct 1140 { 1141 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1142 uint8_t tap_ths_z : 5; 1143 uint8_t tap_priority : 3; 1144 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1145 uint8_t tap_priority : 3; 1146 uint8_t tap_ths_z : 5; 1147 #endif /* DRV_BYTE_ORDER */ 1148 } lsm6dsv16bx_tap_cfg1_t; 1149 1150 #define LSM6DSV16BX_TAP_CFG2 0x58U 1151 typedef struct 1152 { 1153 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1154 uint8_t tap_ths_y : 5; 1155 uint8_t not_used0 : 3; 1156 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1157 uint8_t not_used0 : 3; 1158 uint8_t tap_ths_y : 5; 1159 #endif /* DRV_BYTE_ORDER */ 1160 } lsm6dsv16bx_tap_cfg2_t; 1161 1162 #define LSM6DSV16BX_TAP_THS_6D 0x59U 1163 typedef struct 1164 { 1165 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1166 uint8_t tap_ths_x : 5; 1167 uint8_t sixd_ths : 2; 1168 uint8_t not_used0 : 1; 1169 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1170 uint8_t not_used0 : 1; 1171 uint8_t sixd_ths : 2; 1172 uint8_t tap_ths_x : 5; 1173 #endif /* DRV_BYTE_ORDER */ 1174 } lsm6dsv16bx_tap_ths_6d_t; 1175 1176 #define LSM6DSV16BX_TAP_DUR 0x5AU 1177 typedef struct 1178 { 1179 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1180 uint8_t shock : 2; 1181 uint8_t quiet : 2; 1182 uint8_t dur : 4; 1183 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1184 uint8_t dur : 4; 1185 uint8_t quiet : 2; 1186 uint8_t shock : 2; 1187 #endif /* DRV_BYTE_ORDER */ 1188 } lsm6dsv16bx_tap_dur_t; 1189 1190 #define LSM6DSV16BX_WAKE_UP_THS 0x5BU 1191 typedef struct 1192 { 1193 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1194 uint8_t wk_ths : 6; 1195 uint8_t usr_off_on_wu : 1; 1196 uint8_t single_double_tap : 1; 1197 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1198 uint8_t single_double_tap : 1; 1199 uint8_t usr_off_on_wu : 1; 1200 uint8_t wk_ths : 6; 1201 #endif /* DRV_BYTE_ORDER */ 1202 } lsm6dsv16bx_wake_up_ths_t; 1203 1204 #define LSM6DSV16BX_WAKE_UP_DUR 0x5CU 1205 typedef struct 1206 { 1207 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1208 uint8_t sleep_dur : 4; 1209 uint8_t not_used0 : 1; 1210 uint8_t wake_dur : 2; 1211 uint8_t ff_dur : 1; 1212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1213 uint8_t ff_dur : 1; 1214 uint8_t wake_dur : 2; 1215 uint8_t not_used0 : 1; 1216 uint8_t sleep_dur : 4; 1217 #endif /* DRV_BYTE_ORDER */ 1218 } lsm6dsv16bx_wake_up_dur_t; 1219 1220 #define LSM6DSV16BX_FREE_FALL 0x5DU 1221 typedef struct 1222 { 1223 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1224 uint8_t ff_ths : 3; 1225 uint8_t ff_dur : 5; 1226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1227 uint8_t ff_dur : 5; 1228 uint8_t ff_ths : 3; 1229 #endif /* DRV_BYTE_ORDER */ 1230 } lsm6dsv16bx_free_fall_t; 1231 1232 #define LSM6DSV16BX_MD1_CFG 0x5EU 1233 typedef struct 1234 { 1235 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1236 uint8_t not_used0 : 1; 1237 uint8_t int1_emb_func : 1; 1238 uint8_t int1_6d : 1; 1239 uint8_t int1_double_tap : 1; 1240 uint8_t int1_ff : 1; 1241 uint8_t int1_wu : 1; 1242 uint8_t int1_single_tap : 1; 1243 uint8_t int1_sleep_change : 1; 1244 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1245 uint8_t int1_sleep_change : 1; 1246 uint8_t int1_single_tap : 1; 1247 uint8_t int1_wu : 1; 1248 uint8_t int1_ff : 1; 1249 uint8_t int1_double_tap : 1; 1250 uint8_t int1_6d : 1; 1251 uint8_t int1_emb_func : 1; 1252 uint8_t not_used0 : 1; 1253 #endif /* DRV_BYTE_ORDER */ 1254 } lsm6dsv16bx_md1_cfg_t; 1255 1256 #define LSM6DSV16BX_MD2_CFG 0x5FU 1257 typedef struct 1258 { 1259 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1260 uint8_t int2_timestamp : 1; 1261 uint8_t int2_emb_func : 1; 1262 uint8_t int2_6d : 1; 1263 uint8_t int2_double_tap : 1; 1264 uint8_t int2_ff : 1; 1265 uint8_t int2_wu : 1; 1266 uint8_t int2_single_tap : 1; 1267 uint8_t int2_sleep_change : 1; 1268 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1269 uint8_t int2_sleep_change : 1; 1270 uint8_t int2_single_tap : 1; 1271 uint8_t int2_wu : 1; 1272 uint8_t int2_ff : 1; 1273 uint8_t int2_double_tap : 1; 1274 uint8_t int2_6d : 1; 1275 uint8_t int2_emb_func : 1; 1276 uint8_t int2_timestamp : 1; 1277 #endif /* DRV_BYTE_ORDER */ 1278 } lsm6dsv16bx_md2_cfg_t; 1279 1280 #define LSM6DSV16BX_EMB_FUNC_CFG 0x63U 1281 typedef struct 1282 { 1283 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1284 uint8_t not_used0 : 3; 1285 uint8_t emb_func_disable : 1; 1286 uint8_t emb_func_irq_mask_xl_settl : 1; 1287 uint8_t emb_func_irq_mask_g_settl : 1; 1288 uint8_t not_used1 : 2; 1289 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1290 uint8_t not_used1 : 2; 1291 uint8_t emb_func_irq_mask_g_settl : 1; 1292 uint8_t emb_func_irq_mask_xl_settl : 1; 1293 uint8_t emb_func_disable : 1; 1294 uint8_t not_used0 : 3; 1295 #endif /* DRV_BYTE_ORDER */ 1296 } lsm6dsv16bx_emb_func_cfg_t; 1297 1298 #define LSM6DSV16BX_TDM_CFG0 0x6CU 1299 typedef struct 1300 { 1301 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1302 uint8_t tdm_wclk_bclk_sel : 1; 1303 uint8_t tdm_wclk : 2; 1304 uint8_t not_used0 : 1; 1305 uint8_t tdm_slot_sel : 1; 1306 uint8_t tdm_bclk_edge_sel : 1; 1307 uint8_t tdm_delayed_cfg : 1; 1308 uint8_t not_used1 : 1; 1309 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1310 uint8_t not_used1 : 1; 1311 uint8_t tdm_delayed_cfg : 1; 1312 uint8_t tdm_bclk_edge_sel : 1; 1313 uint8_t tdm_slot_sel : 1; 1314 uint8_t not_used0 : 1; 1315 uint8_t tdm_wclk : 2; 1316 uint8_t tdm_wclk_bclk_sel : 1; 1317 #endif /* DRV_BYTE_ORDER */ 1318 } lsm6dsv16bx_tdm_cfg0_t; 1319 1320 #define LSM6DSV16BX_TDM_CFG1 0x6DU 1321 typedef struct 1322 { 1323 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1324 uint8_t not_used0 : 3; 1325 uint8_t tdm_axes_ord_sel : 2; 1326 uint8_t tdm_xl_z_en : 1; 1327 uint8_t tdm_xl_y_en : 1; 1328 uint8_t tdm_xl_x_en : 1; 1329 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1330 uint8_t tdm_xl_x_en : 1; 1331 uint8_t tdm_xl_y_en : 1; 1332 uint8_t tdm_xl_z_en : 1; 1333 uint8_t tdm_axes_ord_sel : 2; 1334 uint8_t not_used0 : 3; 1335 #endif /* DRV_BYTE_ORDER */ 1336 } lsm6dsv16bx_tdm_cfg1_t; 1337 1338 #define LSM6DSV16BX_TDM_CFG2 0x6EU 1339 typedef struct 1340 { 1341 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1342 uint8_t tdm_fs_xl : 2; 1343 uint8_t not_used0 : 1; 1344 uint8_t tdm_data_mask : 1; 1345 uint8_t not_used1 : 4; 1346 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1347 uint8_t not_used1 : 4; 1348 uint8_t tdm_data_mask : 1; 1349 uint8_t not_used0 : 1; 1350 uint8_t tdm_fs_xl : 2; 1351 #endif /* DRV_BYTE_ORDER */ 1352 } lsm6dsv16bx_tdm_cfg2_t; 1353 1354 #define LSM6DSV16BX_UI_INT_OIS 0x6FU 1355 typedef struct 1356 { 1357 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1358 uint8_t not_used0 : 4; 1359 uint8_t st_ois_clampdis : 1; 1360 uint8_t not_used1 : 1; 1361 uint8_t drdy_mask_ois : 1; 1362 uint8_t int2_drdy_ois : 1; 1363 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1364 uint8_t int2_drdy_ois : 1; 1365 uint8_t drdy_mask_ois : 1; 1366 uint8_t not_used1 : 1; 1367 uint8_t st_ois_clampdis : 1; 1368 uint8_t not_used0 : 4; 1369 #endif /* DRV_BYTE_ORDER */ 1370 } lsm6dsv16bx_ui_int_ois_t; 1371 1372 #define LSM6DSV16BX_Z_OFS_USR 0x73U 1373 typedef struct 1374 { 1375 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1376 uint8_t z_ofs_usr : 8; 1377 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1378 uint8_t z_ofs_usr : 8; 1379 #endif /* DRV_BYTE_ORDER */ 1380 } lsm6dsv16bx_z_ofs_usr_t; 1381 1382 #define LSM6DSV16BX_Y_OFS_USR 0x74U 1383 typedef struct 1384 { 1385 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1386 uint8_t y_ofs_usr : 8; 1387 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1388 uint8_t y_ofs_usr : 8; 1389 #endif /* DRV_BYTE_ORDER */ 1390 } lsm6dsv16bx_y_ofs_usr_t; 1391 1392 #define LSM6DSV16BX_X_OFS_USR 0x75U 1393 typedef struct 1394 { 1395 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1396 uint8_t x_ofs_usr : 8; 1397 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1398 uint8_t x_ofs_usr : 8; 1399 #endif /* DRV_BYTE_ORDER */ 1400 } lsm6dsv16bx_x_ofs_usr_t; 1401 1402 #define LSM6DSV16BX_FIFO_DATA_OUT_TAG 0x78U 1403 typedef struct 1404 { 1405 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1406 uint8_t not_used0 : 1; 1407 uint8_t tag_cnt : 2; 1408 uint8_t tag_sensor : 5; 1409 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1410 uint8_t tag_sensor : 5; 1411 uint8_t tag_cnt : 2; 1412 uint8_t not_used0 : 1; 1413 #endif /* DRV_BYTE_ORDER */ 1414 } lsm6dsv16bx_fifo_data_out_tag_t; 1415 1416 #define LSM6DSV16BX_FIFO_DATA_OUT_BYTE_0 0x79U 1417 typedef struct 1418 { 1419 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1420 uint8_t fifo_data_out : 8; 1421 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1422 uint8_t fifo_data_out : 8; 1423 #endif /* DRV_BYTE_ORDER */ 1424 } lsm6dsv16bx_fifo_data_out_byte_0_t; 1425 1426 #define LSM6DSV16BX_FIFO_DATA_OUT_BYTE_1 0x7AU 1427 typedef struct 1428 { 1429 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1430 uint8_t fifo_data_out : 8; 1431 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1432 uint8_t fifo_data_out : 8; 1433 #endif /* DRV_BYTE_ORDER */ 1434 } lsm6dsv16bx_fifo_data_out_byte_1_t; 1435 1436 #define LSM6DSV16BX_FIFO_DATA_OUT_BYTE_2 0x7BU 1437 typedef struct 1438 { 1439 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1440 uint8_t fifo_data_out : 8; 1441 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1442 uint8_t fifo_data_out : 8; 1443 #endif /* DRV_BYTE_ORDER */ 1444 } lsm6dsv16bx_fifo_data_out_byte_2_t; 1445 1446 #define LSM6DSV16BX_FIFO_DATA_OUT_BYTE_3 0x7CU 1447 typedef struct 1448 { 1449 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1450 uint8_t fifo_data_out : 8; 1451 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1452 uint8_t fifo_data_out : 8; 1453 #endif /* DRV_BYTE_ORDER */ 1454 } lsm6dsv16bx_fifo_data_out_byte_3_t; 1455 1456 #define LSM6DSV16BX_FIFO_DATA_OUT_BYTE_4 0x7DU 1457 typedef struct 1458 { 1459 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1460 uint8_t fifo_data_out : 8; 1461 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1462 uint8_t fifo_data_out : 8; 1463 #endif /* DRV_BYTE_ORDER */ 1464 } lsm6dsv16bx_fifo_data_out_byte_4_t; 1465 1466 #define LSM6DSV16BX_FIFO_DATA_OUT_BYTE_5 0x7EU 1467 typedef struct 1468 { 1469 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1470 uint8_t fifo_data_out : 8; 1471 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1472 uint8_t fifo_data_out : 8; 1473 #endif /* DRV_BYTE_ORDER */ 1474 } lsm6dsv16bx_fifo_data_out_byte_5_t; 1475 1476 /** 1477 * @} 1478 * 1479 */ 1480 1481 /** @defgroup bitfields page embedded 1482 * @{ 1483 * 1484 */ 1485 1486 #define LSM6DSV16BX_PAGE_SEL 0x2U 1487 typedef struct 1488 { 1489 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1490 uint8_t not_used0 : 4; 1491 uint8_t page_sel : 4; 1492 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1493 uint8_t page_sel : 4; 1494 uint8_t not_used0 : 4; 1495 #endif /* DRV_BYTE_ORDER */ 1496 } lsm6dsv16bx_page_sel_t; 1497 1498 #define LSM6DSV16BX_EMB_FUNC_EN_A 0x4U 1499 typedef struct 1500 { 1501 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1502 uint8_t not_used2 : 1; 1503 uint8_t sflp_game_en : 1; 1504 uint8_t not_used0 : 1; 1505 uint8_t pedo_en : 1; 1506 uint8_t tilt_en : 1; 1507 uint8_t sign_motion_en : 1; 1508 uint8_t not_used1 : 1; 1509 uint8_t mlc_before_fsm_en : 1; 1510 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1511 uint8_t mlc_before_fsm_en : 1; 1512 uint8_t not_used1 : 1; 1513 uint8_t sign_motion_en : 1; 1514 uint8_t tilt_en : 1; 1515 uint8_t pedo_en : 1; 1516 uint8_t not_used0 : 1; 1517 uint8_t sflp_game_en : 1; 1518 uint8_t not_used2 : 1; 1519 #endif /* DRV_BYTE_ORDER */ 1520 } lsm6dsv16bx_emb_func_en_a_t; 1521 1522 #define LSM6DSV16BX_EMB_FUNC_EN_B 0x5U 1523 typedef struct 1524 { 1525 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1526 uint8_t fsm_en : 1; 1527 uint8_t not_used0 : 2; 1528 uint8_t fifo_compr_en : 1; 1529 uint8_t mlc_en : 1; 1530 uint8_t not_used1 : 3; 1531 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1532 uint8_t not_used1 : 3; 1533 uint8_t mlc_en : 1; 1534 uint8_t fifo_compr_en : 1; 1535 uint8_t not_used0 : 2; 1536 uint8_t fsm_en : 1; 1537 #endif /* DRV_BYTE_ORDER */ 1538 } lsm6dsv16bx_emb_func_en_b_t; 1539 1540 #define LSM6DSV16BX_EMB_FUNC_EXEC_STATUS 0x7U 1541 typedef struct 1542 { 1543 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1544 uint8_t emb_func_endop : 1; 1545 uint8_t emb_func_exec_ovr : 1; 1546 uint8_t not_used0 : 6; 1547 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1548 uint8_t not_used0 : 6; 1549 uint8_t emb_func_exec_ovr : 1; 1550 uint8_t emb_func_endop : 1; 1551 #endif /* DRV_BYTE_ORDER */ 1552 } lsm6dsv16bx_emb_func_exec_status_t; 1553 1554 #define LSM6DSV16BX_PAGE_ADDRESS 0x8U 1555 typedef struct 1556 { 1557 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1558 uint8_t page_addr : 8; 1559 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1560 uint8_t page_addr : 8; 1561 #endif /* DRV_BYTE_ORDER */ 1562 } lsm6dsv16bx_page_address_t; 1563 1564 #define LSM6DSV16BX_PAGE_VALUE 0x9U 1565 typedef struct 1566 { 1567 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1568 uint8_t page_value : 8; 1569 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1570 uint8_t page_value : 8; 1571 #endif /* DRV_BYTE_ORDER */ 1572 } lsm6dsv16bx_page_value_t; 1573 1574 #define LSM6DSV16BX_EMB_FUNC_INT1 0x0AU 1575 typedef struct 1576 { 1577 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1578 uint8_t not_used0 : 3; 1579 uint8_t int1_step_detector : 1; 1580 uint8_t int1_tilt : 1; 1581 uint8_t int1_sig_mot : 1; 1582 uint8_t not_used1 : 1; 1583 uint8_t int1_fsm_lc : 1; 1584 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1585 uint8_t int1_fsm_lc : 1; 1586 uint8_t not_used1 : 1; 1587 uint8_t int1_sig_mot : 1; 1588 uint8_t int1_tilt : 1; 1589 uint8_t int1_step_detector : 1; 1590 uint8_t not_used0 : 3; 1591 #endif /* DRV_BYTE_ORDER */ 1592 } lsm6dsv16bx_emb_func_int1_t; 1593 1594 #define LSM6DSV16BX_FSM_INT1 0x0BU 1595 typedef struct 1596 { 1597 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1598 uint8_t int1_fsm1 : 1; 1599 uint8_t int1_fsm2 : 1; 1600 uint8_t int1_fsm3 : 1; 1601 uint8_t int1_fsm4 : 1; 1602 uint8_t int1_fsm5 : 1; 1603 uint8_t int1_fsm6 : 1; 1604 uint8_t int1_fsm7 : 1; 1605 uint8_t int1_fsm8 : 1; 1606 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1607 uint8_t int1_fsm8 : 1; 1608 uint8_t int1_fsm7 : 1; 1609 uint8_t int1_fsm6 : 1; 1610 uint8_t int1_fsm5 : 1; 1611 uint8_t int1_fsm4 : 1; 1612 uint8_t int1_fsm3 : 1; 1613 uint8_t int1_fsm2 : 1; 1614 uint8_t int1_fsm1 : 1; 1615 #endif /* DRV_BYTE_ORDER */ 1616 } lsm6dsv16bx_fsm_int1_t; 1617 1618 #define LSM6DSV16BX_MLC_INT1 0x0DU 1619 typedef struct 1620 { 1621 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1622 uint8_t int1_mlc1 : 1; 1623 uint8_t int1_mlc2 : 1; 1624 uint8_t int1_mlc3 : 1; 1625 uint8_t int1_mlc4 : 1; 1626 uint8_t not_used0 : 4; 1627 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1628 uint8_t not_used0 : 4; 1629 uint8_t int1_mlc4 : 1; 1630 uint8_t int1_mlc3 : 1; 1631 uint8_t int1_mlc2 : 1; 1632 uint8_t int1_mlc1 : 1; 1633 #endif /* DRV_BYTE_ORDER */ 1634 } lsm6dsv16bx_mlc_int1_t; 1635 1636 #define LSM6DSV16BX_EMB_FUNC_INT2 0x0EU 1637 typedef struct 1638 { 1639 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1640 uint8_t not_used0 : 3; 1641 uint8_t int2_step_detector : 1; 1642 uint8_t int2_tilt : 1; 1643 uint8_t int2_sig_mot : 1; 1644 uint8_t not_used1 : 1; 1645 uint8_t int2_fsm_lc : 1; 1646 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1647 uint8_t int2_fsm_lc : 1; 1648 uint8_t not_used1 : 1; 1649 uint8_t int2_sig_mot : 1; 1650 uint8_t int2_tilt : 1; 1651 uint8_t int2_step_detector : 1; 1652 uint8_t not_used0 : 3; 1653 #endif /* DRV_BYTE_ORDER */ 1654 } lsm6dsv16bx_emb_func_int2_t; 1655 1656 #define LSM6DSV16BX_FSM_INT2 0x0FU 1657 typedef struct 1658 { 1659 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1660 uint8_t int2_fsm1 : 1; 1661 uint8_t int2_fsm2 : 1; 1662 uint8_t int2_fsm3 : 1; 1663 uint8_t int2_fsm4 : 1; 1664 uint8_t int2_fsm5 : 1; 1665 uint8_t int2_fsm6 : 1; 1666 uint8_t int2_fsm7 : 1; 1667 uint8_t int2_fsm8 : 1; 1668 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1669 uint8_t int2_fsm8 : 1; 1670 uint8_t int2_fsm7 : 1; 1671 uint8_t int2_fsm6 : 1; 1672 uint8_t int2_fsm5 : 1; 1673 uint8_t int2_fsm4 : 1; 1674 uint8_t int2_fsm3 : 1; 1675 uint8_t int2_fsm2 : 1; 1676 uint8_t int2_fsm1 : 1; 1677 #endif /* DRV_BYTE_ORDER */ 1678 } lsm6dsv16bx_fsm_int2_t; 1679 1680 #define LSM6DSV16BX_MLC_INT2 0x11U 1681 typedef struct 1682 { 1683 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1684 uint8_t int2_mlc1 : 1; 1685 uint8_t int2_mlc2 : 1; 1686 uint8_t int2_mlc3 : 1; 1687 uint8_t int2_mlc4 : 1; 1688 uint8_t not_used0 : 4; 1689 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1690 uint8_t not_used0 : 4; 1691 uint8_t int2_mlc4 : 1; 1692 uint8_t int2_mlc3 : 1; 1693 uint8_t int2_mlc2 : 1; 1694 uint8_t int2_mlc1 : 1; 1695 #endif /* DRV_BYTE_ORDER */ 1696 } lsm6dsv16bx_mlc_int2_t; 1697 1698 #define LSM6DSV16BX_EMB_FUNC_STATUS 0x12U 1699 typedef struct 1700 { 1701 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1702 uint8_t not_used0 : 3; 1703 uint8_t is_step_det : 1; 1704 uint8_t is_tilt : 1; 1705 uint8_t is_sigmot : 1; 1706 uint8_t not_used1 : 1; 1707 uint8_t is_fsm_lc : 1; 1708 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1709 uint8_t is_fsm_lc : 1; 1710 uint8_t not_used1 : 1; 1711 uint8_t is_sigmot : 1; 1712 uint8_t is_tilt : 1; 1713 uint8_t is_step_det : 1; 1714 uint8_t not_used0 : 3; 1715 #endif /* DRV_BYTE_ORDER */ 1716 } lsm6dsv16bx_emb_func_status_t; 1717 1718 #define LSM6DSV16BX_FSM_STATUS 0x13U 1719 typedef struct 1720 { 1721 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1722 uint8_t is_fsm1 : 1; 1723 uint8_t is_fsm2 : 1; 1724 uint8_t is_fsm3 : 1; 1725 uint8_t is_fsm4 : 1; 1726 uint8_t is_fsm5 : 1; 1727 uint8_t is_fsm6 : 1; 1728 uint8_t is_fsm7 : 1; 1729 uint8_t is_fsm8 : 1; 1730 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1731 uint8_t is_fsm8 : 1; 1732 uint8_t is_fsm7 : 1; 1733 uint8_t is_fsm6 : 1; 1734 uint8_t is_fsm5 : 1; 1735 uint8_t is_fsm4 : 1; 1736 uint8_t is_fsm3 : 1; 1737 uint8_t is_fsm2 : 1; 1738 uint8_t is_fsm1 : 1; 1739 #endif /* DRV_BYTE_ORDER */ 1740 } lsm6dsv16bx_fsm_status_t; 1741 1742 #define LSM6DSV16BX_MLC_STATUS 0x15U 1743 typedef struct 1744 { 1745 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1746 uint8_t is_mlc1 : 1; 1747 uint8_t is_mlc2 : 1; 1748 uint8_t is_mlc3 : 1; 1749 uint8_t is_mlc4 : 1; 1750 uint8_t not_used0 : 4; 1751 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1752 uint8_t not_used0 : 4; 1753 uint8_t is_mlc4 : 1; 1754 uint8_t is_mlc3 : 1; 1755 uint8_t is_mlc2 : 1; 1756 uint8_t is_mlc1 : 1; 1757 #endif /* DRV_BYTE_ORDER */ 1758 } lsm6dsv16bx_mlc_status_t; 1759 1760 #define LSM6DSV16BX_PAGE_RW 0x17U 1761 typedef struct 1762 { 1763 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1764 uint8_t not_used0 : 5; 1765 uint8_t page_read : 1; 1766 uint8_t page_write : 1; 1767 uint8_t emb_func_lir : 1; 1768 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1769 uint8_t emb_func_lir : 1; 1770 uint8_t page_write : 1; 1771 uint8_t page_read : 1; 1772 uint8_t not_used0 : 5; 1773 #endif /* DRV_BYTE_ORDER */ 1774 } lsm6dsv16bx_page_rw_t; 1775 1776 #define LSM6DSV16BX_EMB_FUNC_FIFO_EN_A 0x44U 1777 typedef struct 1778 { 1779 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1780 uint8_t not_used0 : 1; 1781 uint8_t sflp_game_fifo_en : 1; 1782 uint8_t not_used1 : 2; 1783 uint8_t sflp_gravity_fifo_en : 1; 1784 uint8_t sflp_gbias_fifo_en : 1; 1785 uint8_t step_counter_fifo_en : 1; 1786 uint8_t mlc_fifo_en : 1; 1787 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1788 uint8_t mlc_fifo_en : 1; 1789 uint8_t step_counter_fifo_en : 1; 1790 uint8_t sflp_gbias_fifo_en : 1; 1791 uint8_t sflp_gravity_fifo_en : 1; 1792 uint8_t not_used1 : 2; 1793 uint8_t sflp_game_fifo_en : 1; 1794 uint8_t not_used0 : 1; 1795 #endif /* DRV_BYTE_ORDER */ 1796 } lsm6dsv16bx_emb_func_fifo_en_a_t; 1797 1798 #define LSM6DSV16BX_EMB_FUNC_FIFO_EN_B 0x45U 1799 typedef struct 1800 { 1801 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1802 uint8_t not_used0 : 1; 1803 uint8_t mlc_filter_feature_fifo_en : 1; 1804 uint8_t not_used1 : 6; 1805 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1806 uint8_t not_used1 : 6; 1807 uint8_t mlc_filter_feature_fifo_en : 1; 1808 uint8_t not_used0 : 1; 1809 #endif /* DRV_BYTE_ORDER */ 1810 } lsm6dsv16bx_emb_func_fifo_en_b_t; 1811 1812 #define LSM6DSV16BX_FSM_ENABLE 0x46U 1813 typedef struct 1814 { 1815 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1816 uint8_t fsm1_en : 1; 1817 uint8_t fsm2_en : 1; 1818 uint8_t fsm3_en : 1; 1819 uint8_t fsm4_en : 1; 1820 uint8_t fsm5_en : 1; 1821 uint8_t fsm6_en : 1; 1822 uint8_t fsm7_en : 1; 1823 uint8_t fsm8_en : 1; 1824 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1825 uint8_t fsm8_en : 1; 1826 uint8_t fsm7_en : 1; 1827 uint8_t fsm6_en : 1; 1828 uint8_t fsm5_en : 1; 1829 uint8_t fsm4_en : 1; 1830 uint8_t fsm3_en : 1; 1831 uint8_t fsm2_en : 1; 1832 uint8_t fsm1_en : 1; 1833 #endif /* DRV_BYTE_ORDER */ 1834 } lsm6dsv16bx_fsm_enable_t; 1835 1836 #define LSM6DSV16BX_FSM_LONG_COUNTER_L 0x48U 1837 typedef struct 1838 { 1839 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1840 uint8_t fsm_lc : 8; 1841 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1842 uint8_t fsm_lc : 8; 1843 #endif /* DRV_BYTE_ORDER */ 1844 } lsm6dsv16bx_fsm_long_counter_l_t; 1845 1846 #define LSM6DSV16BX_FSM_LONG_COUNTER_H 0x49U 1847 typedef struct 1848 { 1849 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1850 uint8_t fsm_lc : 8; 1851 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1852 uint8_t fsm_lc : 8; 1853 #endif /* DRV_BYTE_ORDER */ 1854 } lsm6dsv16bx_fsm_long_counter_h_t; 1855 1856 #define LSM6DSV16BX_INT_ACK_MASK 0x4BU 1857 typedef struct 1858 { 1859 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1860 uint8_t iack_mask : 8; 1861 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1862 uint8_t iack_mask : 8; 1863 #endif /* DRV_BYTE_ORDER */ 1864 } lsm6dsv16bx_int_ack_mask_t; 1865 1866 #define LSM6DSV16BX_FSM_OUTS1 0x4CU 1867 typedef struct 1868 { 1869 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1870 uint8_t fsm1_n_v : 1; 1871 uint8_t fsm1_p_v : 1; 1872 uint8_t fsm1_n_3 : 1; 1873 uint8_t fsm1_p_3 : 1; 1874 uint8_t fsm1_n_2 : 1; 1875 uint8_t fsm1_p_2 : 1; 1876 uint8_t fsm1_n_1 : 1; 1877 uint8_t fsm1_p_1 : 1; 1878 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1879 uint8_t fsm1_p_1 : 1; 1880 uint8_t fsm1_n_1 : 1; 1881 uint8_t fsm1_p_2 : 1; 1882 uint8_t fsm1_n_2 : 1; 1883 uint8_t fsm1_p_3 : 1; 1884 uint8_t fsm1_n_3 : 1; 1885 uint8_t fsm1_p_v : 1; 1886 uint8_t fsm1_n_v : 1; 1887 #endif /* DRV_BYTE_ORDER */ 1888 } lsm6dsv16bx_fsm_outs1_t; 1889 1890 #define LSM6DSV16BX_FSM_OUTS2 0x4DU 1891 typedef struct 1892 { 1893 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1894 uint8_t fsm2_n_v : 1; 1895 uint8_t fsm2_p_v : 1; 1896 uint8_t fsm2_n_3 : 1; 1897 uint8_t fsm2_p_3 : 1; 1898 uint8_t fsm2_n_2 : 1; 1899 uint8_t fsm2_p_2 : 1; 1900 uint8_t fsm2_n_1 : 1; 1901 uint8_t fsm2_p_1 : 1; 1902 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1903 uint8_t fsm2_p_1 : 1; 1904 uint8_t fsm2_n_1 : 1; 1905 uint8_t fsm2_p_2 : 1; 1906 uint8_t fsm2_n_2 : 1; 1907 uint8_t fsm2_p_3 : 1; 1908 uint8_t fsm2_n_3 : 1; 1909 uint8_t fsm2_p_v : 1; 1910 uint8_t fsm2_n_v : 1; 1911 #endif /* DRV_BYTE_ORDER */ 1912 } lsm6dsv16bx_fsm_outs2_t; 1913 1914 #define LSM6DSV16BX_FSM_OUTS3 0x4EU 1915 typedef struct 1916 { 1917 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1918 uint8_t fsm3_n_v : 1; 1919 uint8_t fsm3_p_v : 1; 1920 uint8_t fsm3_n_3 : 1; 1921 uint8_t fsm3_p_3 : 1; 1922 uint8_t fsm3_n_2 : 1; 1923 uint8_t fsm3_p_2 : 1; 1924 uint8_t fsm3_n_1 : 1; 1925 uint8_t fsm3_p_1 : 1; 1926 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1927 uint8_t fsm3_p_1 : 1; 1928 uint8_t fsm3_n_1 : 1; 1929 uint8_t fsm3_p_2 : 1; 1930 uint8_t fsm3_n_2 : 1; 1931 uint8_t fsm3_p_3 : 1; 1932 uint8_t fsm3_n_3 : 1; 1933 uint8_t fsm3_p_v : 1; 1934 uint8_t fsm3_n_v : 1; 1935 #endif /* DRV_BYTE_ORDER */ 1936 } lsm6dsv16bx_fsm_outs3_t; 1937 1938 #define LSM6DSV16BX_FSM_OUTS4 0x4FU 1939 typedef struct 1940 { 1941 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1942 uint8_t fsm4_n_v : 1; 1943 uint8_t fsm4_p_v : 1; 1944 uint8_t fsm4_n_3 : 1; 1945 uint8_t fsm4_p_3 : 1; 1946 uint8_t fsm4_n_2 : 1; 1947 uint8_t fsm4_p_2 : 1; 1948 uint8_t fsm4_n_1 : 1; 1949 uint8_t fsm4_p_1 : 1; 1950 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1951 uint8_t fsm4_p_1 : 1; 1952 uint8_t fsm4_n_1 : 1; 1953 uint8_t fsm4_p_2 : 1; 1954 uint8_t fsm4_n_2 : 1; 1955 uint8_t fsm4_p_3 : 1; 1956 uint8_t fsm4_n_3 : 1; 1957 uint8_t fsm4_p_v : 1; 1958 uint8_t fsm4_n_v : 1; 1959 #endif /* DRV_BYTE_ORDER */ 1960 } lsm6dsv16bx_fsm_outs4_t; 1961 1962 #define LSM6DSV16BX_FSM_OUTS5 0x50U 1963 typedef struct 1964 { 1965 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1966 uint8_t fsm5_n_v : 1; 1967 uint8_t fsm5_p_v : 1; 1968 uint8_t fsm5_n_3 : 1; 1969 uint8_t fsm5_p_3 : 1; 1970 uint8_t fsm5_n_2 : 1; 1971 uint8_t fsm5_p_2 : 1; 1972 uint8_t fsm5_n_1 : 1; 1973 uint8_t fsm5_p_1 : 1; 1974 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1975 uint8_t fsm5_p_1 : 1; 1976 uint8_t fsm5_n_1 : 1; 1977 uint8_t fsm5_p_2 : 1; 1978 uint8_t fsm5_n_2 : 1; 1979 uint8_t fsm5_p_3 : 1; 1980 uint8_t fsm5_n_3 : 1; 1981 uint8_t fsm5_p_v : 1; 1982 uint8_t fsm5_n_v : 1; 1983 #endif /* DRV_BYTE_ORDER */ 1984 } lsm6dsv16bx_fsm_outs5_t; 1985 1986 #define LSM6DSV16BX_FSM_OUTS6 0x51U 1987 typedef struct 1988 { 1989 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1990 uint8_t fsm6_n_v : 1; 1991 uint8_t fsm6_p_v : 1; 1992 uint8_t fsm6_n_3 : 1; 1993 uint8_t fsm6_p_3 : 1; 1994 uint8_t fsm6_n_2 : 1; 1995 uint8_t fsm6_p_2 : 1; 1996 uint8_t fsm6_n_1 : 1; 1997 uint8_t fsm6_p_1 : 1; 1998 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1999 uint8_t fsm6_p_1 : 1; 2000 uint8_t fsm6_n_1 : 1; 2001 uint8_t fsm6_p_2 : 1; 2002 uint8_t fsm6_n_2 : 1; 2003 uint8_t fsm6_p_3 : 1; 2004 uint8_t fsm6_n_3 : 1; 2005 uint8_t fsm6_p_v : 1; 2006 uint8_t fsm6_n_v : 1; 2007 #endif /* DRV_BYTE_ORDER */ 2008 } lsm6dsv16bx_fsm_outs6_t; 2009 2010 #define LSM6DSV16BX_FSM_OUTS7 0x52U 2011 typedef struct 2012 { 2013 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2014 uint8_t fsm7_n_v : 1; 2015 uint8_t fsm7_p_v : 1; 2016 uint8_t fsm7_n_3 : 1; 2017 uint8_t fsm7_p_3 : 1; 2018 uint8_t fsm7_n_2 : 1; 2019 uint8_t fsm7_p_2 : 1; 2020 uint8_t fsm7_n_1 : 1; 2021 uint8_t fsm7_p_1 : 1; 2022 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2023 uint8_t fsm7_p_1 : 1; 2024 uint8_t fsm7_n_1 : 1; 2025 uint8_t fsm7_p_2 : 1; 2026 uint8_t fsm7_n_2 : 1; 2027 uint8_t fsm7_p_3 : 1; 2028 uint8_t fsm7_n_3 : 1; 2029 uint8_t fsm7_p_v : 1; 2030 uint8_t fsm7_n_v : 1; 2031 #endif /* DRV_BYTE_ORDER */ 2032 } lsm6dsv16bx_fsm_outs7_t; 2033 2034 #define LSM6DSV16BX_FSM_OUTS8 0x53U 2035 typedef struct 2036 { 2037 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2038 uint8_t fsm8_n_v : 1; 2039 uint8_t fsm8_p_v : 1; 2040 uint8_t fsm8_n_3 : 1; 2041 uint8_t fsm8_p_3 : 1; 2042 uint8_t fsm8_n_2 : 1; 2043 uint8_t fsm8_p_2 : 1; 2044 uint8_t fsm8_n_1 : 1; 2045 uint8_t fsm8_p_1 : 1; 2046 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2047 uint8_t fsm8_p_1 : 1; 2048 uint8_t fsm8_n_1 : 1; 2049 uint8_t fsm8_p_2 : 1; 2050 uint8_t fsm8_n_2 : 1; 2051 uint8_t fsm8_p_3 : 1; 2052 uint8_t fsm8_n_3 : 1; 2053 uint8_t fsm8_p_v : 1; 2054 uint8_t fsm8_n_v : 1; 2055 #endif /* DRV_BYTE_ORDER */ 2056 } lsm6dsv16bx_fsm_outs8_t; 2057 2058 #define LSM6DSV16BX_SFLP_ODR 0x5EU 2059 typedef struct 2060 { 2061 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2062 uint8_t not_used0 : 3; 2063 uint8_t sflp_game_odr : 3; 2064 uint8_t not_used1 : 2; 2065 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2066 uint8_t not_used1 : 2; 2067 uint8_t sflp_game_odr : 3; 2068 uint8_t not_used0 : 3; 2069 #endif /* DRV_BYTE_ORDER */ 2070 } lsm6dsv16bx_sflp_odr_t; 2071 2072 #define LSM6DSV16BX_FSM_ODR 0x5FU 2073 typedef struct 2074 { 2075 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2076 uint8_t not_used0 : 3; 2077 uint8_t fsm_odr : 3; 2078 uint8_t not_used1 : 2; 2079 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2080 uint8_t not_used1 : 2; 2081 uint8_t fsm_odr : 3; 2082 uint8_t not_used0 : 3; 2083 #endif /* DRV_BYTE_ORDER */ 2084 } lsm6dsv16bx_fsm_odr_t; 2085 2086 #define LSM6DSV16BX_MLC_ODR 0x60U 2087 typedef struct 2088 { 2089 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2090 uint8_t not_used0 : 4; 2091 uint8_t mlc_odr : 3; 2092 uint8_t not_used1 : 1; 2093 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2094 uint8_t not_used1 : 1; 2095 uint8_t mlc_odr : 3; 2096 uint8_t not_used0 : 4; 2097 #endif /* DRV_BYTE_ORDER */ 2098 } lsm6dsv16bx_mlc_odr_t; 2099 2100 #define LSM6DSV16BX_STEP_COUNTER_L 0x62U 2101 typedef struct 2102 { 2103 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2104 uint8_t step : 8; 2105 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2106 uint8_t step : 8; 2107 #endif /* DRV_BYTE_ORDER */ 2108 } lsm6dsv16bx_step_counter_l_t; 2109 2110 #define LSM6DSV16BX_STEP_COUNTER_H 0x63U 2111 typedef struct 2112 { 2113 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2114 uint8_t step : 8; 2115 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2116 uint8_t step : 8; 2117 #endif /* DRV_BYTE_ORDER */ 2118 } lsm6dsv16bx_step_counter_h_t; 2119 2120 #define LSM6DSV16BX_EMB_FUNC_SRC 0x64U 2121 typedef struct 2122 { 2123 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2124 uint8_t not_used0 : 2; 2125 uint8_t stepcounter_bit_set : 1; 2126 uint8_t step_overflow : 1; 2127 uint8_t step_count_delta_ia : 1; 2128 uint8_t step_detected : 1; 2129 uint8_t not_used1 : 1; 2130 uint8_t pedo_rst_step : 1; 2131 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2132 uint8_t pedo_rst_step : 1; 2133 uint8_t not_used1 : 1; 2134 uint8_t step_detected : 1; 2135 uint8_t step_count_delta_ia : 1; 2136 uint8_t step_overflow : 1; 2137 uint8_t stepcounter_bit_set : 1; 2138 uint8_t not_used0 : 2; 2139 #endif /* DRV_BYTE_ORDER */ 2140 } lsm6dsv16bx_emb_func_src_t; 2141 2142 #define LSM6DSV16BX_EMB_FUNC_INIT_A 0x66U 2143 typedef struct 2144 { 2145 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2146 uint8_t not_used0 : 1; 2147 uint8_t sflp_game_init : 1; 2148 uint8_t not_used2 : 1; 2149 uint8_t step_det_init : 1; 2150 uint8_t tilt_init : 1; 2151 uint8_t sig_mot_init : 1; 2152 uint8_t not_used1 : 1; 2153 uint8_t mlc_before_fsm_init : 1; 2154 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2155 uint8_t mlc_before_fsm_init : 1; 2156 uint8_t not_used1 : 1; 2157 uint8_t sig_mot_init : 1; 2158 uint8_t tilt_init : 1; 2159 uint8_t step_det_init : 1; 2160 uint8_t not_used2 : 1; 2161 uint8_t sflp_game_init : 1; 2162 uint8_t not_used0 : 1; 2163 #endif /* DRV_BYTE_ORDER */ 2164 } lsm6dsv16bx_emb_func_init_a_t; 2165 2166 #define LSM6DSV16BX_EMB_FUNC_INIT_B 0x67U 2167 typedef struct 2168 { 2169 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2170 uint8_t fsm_init : 1; 2171 uint8_t not_used0 : 2; 2172 uint8_t fifo_compr_init : 1; 2173 uint8_t mlc_init : 1; 2174 uint8_t not_used1 : 3; 2175 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2176 uint8_t not_used1 : 3; 2177 uint8_t mlc_init : 1; 2178 uint8_t fifo_compr_init : 1; 2179 uint8_t not_used0 : 2; 2180 uint8_t fsm_init : 1; 2181 #endif /* DRV_BYTE_ORDER */ 2182 } lsm6dsv16bx_emb_func_init_b_t; 2183 2184 #define LSM6DSV16BX_MLC1_SRC 0x70U 2185 typedef struct 2186 { 2187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2188 uint8_t mlc1_src : 8; 2189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2190 uint8_t mlc1_src : 8; 2191 #endif /* DRV_BYTE_ORDER */ 2192 } lsm6dsv16bx_mlc1_src_t; 2193 2194 #define LSM6DSV16BX_MLC2_SRC 0x71U 2195 typedef struct 2196 { 2197 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2198 uint8_t mlc2_src : 8; 2199 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2200 uint8_t mlc2_src : 8; 2201 #endif /* DRV_BYTE_ORDER */ 2202 } lsm6dsv16bx_mlc2_src_t; 2203 2204 #define LSM6DSV16BX_MLC3_SRC 0x72U 2205 typedef struct 2206 { 2207 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2208 uint8_t mlc3_src : 8; 2209 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2210 uint8_t mlc3_src : 8; 2211 #endif /* DRV_BYTE_ORDER */ 2212 } lsm6dsv16bx_mlc3_src_t; 2213 2214 #define LSM6DSV16BX_MLC4_SRC 0x73U 2215 typedef struct 2216 { 2217 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2218 uint8_t mlc4_src : 8; 2219 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2220 uint8_t mlc4_src : 8; 2221 #endif /* DRV_BYTE_ORDER */ 2222 } lsm6dsv16bx_mlc4_src_t; 2223 2224 /** 2225 * @} 2226 * 2227 */ 2228 2229 /** @defgroup bitfields page pg0_emb_adv 2230 * @{ 2231 * 2232 */ 2233 #define LSM6DSV16BX_EMB_ADV_PG_0 0x000 2234 2235 #define LSM6DSV16BX_SFLP_GAME_GBIASX_L 0x6EU 2236 typedef struct 2237 { 2238 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2239 uint8_t gbiasx : 8; 2240 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2241 uint8_t gbiasx : 8; 2242 #endif /* DRV_BYTE_ORDER */ 2243 } lsm6dsv16bx_sflp_game_gbiasx_l_t; 2244 2245 #define LSM6DSV16BX_SFLP_GAME_GBIASX_H 0x6FU 2246 typedef struct 2247 { 2248 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2249 uint8_t gbiasx : 8; 2250 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2251 uint8_t gbiasx : 8; 2252 #endif /* DRV_BYTE_ORDER */ 2253 } lsm6dsv16bx_sflp_game_gbiasx_h_t; 2254 2255 #define LSM6DSV16BX_SFLP_GAME_GBIASY_L 0x70U 2256 typedef struct 2257 { 2258 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2259 uint8_t gbiasy : 8; 2260 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2261 uint8_t gbiasy : 8; 2262 #endif /* DRV_BYTE_ORDER */ 2263 } lsm6dsv16bx_sflp_game_gbiasy_l_t; 2264 2265 #define LSM6DSV16BX_SFLP_GAME_GBIASY_H 0x71U 2266 typedef struct 2267 { 2268 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2269 uint8_t gbiasy : 8; 2270 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2271 uint8_t gbiasy : 8; 2272 #endif /* DRV_BYTE_ORDER */ 2273 } lsm6dsv16bx_sflp_game_gbiasy_h_t; 2274 2275 #define LSM6DSV16BX_SFLP_GAME_GBIASZ_L 0x72U 2276 typedef struct 2277 { 2278 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2279 uint8_t gbiasz : 8; 2280 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2281 uint8_t gbiasz : 8; 2282 #endif /* DRV_BYTE_ORDER */ 2283 } lsm6dsv16bx_sflp_game_gbiasz_l_t; 2284 2285 #define LSM6DSV16BX_SFLP_GAME_GBIASZ_H 0x73U 2286 typedef struct 2287 { 2288 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2289 uint8_t gbiasz : 8; 2290 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2291 uint8_t gbiasz : 8; 2292 #endif /* DRV_BYTE_ORDER */ 2293 } lsm6dsv16bx_sflp_game_gbiasz_h_t; 2294 2295 #define LSM6DSV16BX_FSM_QVAR_SENSITIVITY_L 0xBAU 2296 typedef struct 2297 { 2298 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2299 uint8_t fsm_qvar_s : 8; 2300 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2301 uint8_t fsm_qvar_s : 8; 2302 #endif /* DRV_BYTE_ORDER */ 2303 } lsm6dsv16bx_fsm_qvar_sensitivity_l_t; 2304 2305 #define LSM6DSV16BX_FSM_QVAR_SENSITIVITY_H 0xBBU 2306 typedef struct 2307 { 2308 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2309 uint8_t fsm_qvar_s : 8; 2310 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2311 uint8_t fsm_qvar_s : 8; 2312 #endif /* DRV_BYTE_ORDER */ 2313 } lsm6dsv16bx_fsm_qvar_sensitivity_h_t; 2314 2315 /** 2316 * @} 2317 * 2318 */ 2319 2320 /** @defgroup bitfields page pg1_emb_adv 2321 * @{ 2322 * 2323 */ 2324 2325 #define LSM6DSV16BX_EMB_ADV_PG_1 0x001 2326 2327 #define LSM6DSV16BX_FSM_LC_TIMEOUT_L 0x17AU 2328 typedef struct 2329 { 2330 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2331 uint8_t fsm_lc_timeout : 8; 2332 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2333 uint8_t fsm_lc_timeout : 8; 2334 #endif /* DRV_BYTE_ORDER */ 2335 } lsm6dsv16bx_fsm_lc_timeout_l_t; 2336 2337 #define LSM6DSV16BX_FSM_LC_TIMEOUT_H 0x17BU 2338 typedef struct 2339 { 2340 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2341 uint8_t fsm_lc_timeout : 8; 2342 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2343 uint8_t fsm_lc_timeout : 8; 2344 #endif /* DRV_BYTE_ORDER */ 2345 } lsm6dsv16bx_fsm_lc_timeout_h_t; 2346 2347 #define LSM6DSV16BX_FSM_PROGRAMS 0x17CU 2348 typedef struct 2349 { 2350 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2351 uint8_t fsm_n_prog : 8; 2352 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2353 uint8_t fsm_n_prog : 8; 2354 #endif /* DRV_BYTE_ORDER */ 2355 } lsm6dsv16bx_fsm_programs_t; 2356 2357 #define LSM6DSV16BX_FSM_START_ADD_L 0x17EU 2358 typedef struct 2359 { 2360 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2361 uint8_t fsm_start : 8; 2362 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2363 uint8_t fsm_start : 8; 2364 #endif /* DRV_BYTE_ORDER */ 2365 } lsm6dsv16bx_fsm_start_add_l_t; 2366 2367 #define LSM6DSV16BX_FSM_START_ADD_H 0x17FU 2368 typedef struct 2369 { 2370 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2371 uint8_t fsm_start : 8; 2372 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2373 uint8_t fsm_start : 8; 2374 #endif /* DRV_BYTE_ORDER */ 2375 } lsm6dsv16bx_fsm_start_add_h_t; 2376 2377 #define LSM6DSV16BX_PEDO_CMD_REG 0x183U 2378 typedef struct 2379 { 2380 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2381 uint8_t not_used0 : 2; 2382 uint8_t fp_rejection_en : 1; 2383 uint8_t carry_count_en : 1; 2384 uint8_t not_used1 : 4; 2385 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2386 uint8_t not_used1 : 4; 2387 uint8_t carry_count_en : 1; 2388 uint8_t fp_rejection_en : 1; 2389 uint8_t not_used0 : 2; 2390 #endif /* DRV_BYTE_ORDER */ 2391 } lsm6dsv16bx_pedo_cmd_reg_t; 2392 2393 #define LSM6DSV16BX_PEDO_DEB_STEPS_CONF 0x184U 2394 typedef struct 2395 { 2396 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2397 uint8_t deb_step : 8; 2398 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2399 uint8_t deb_step : 8; 2400 #endif /* DRV_BYTE_ORDER */ 2401 } lsm6dsv16bx_pedo_deb_steps_conf_t; 2402 2403 #define LSM6DSV16BX_PEDO_SC_DELTAT_L 0x1D0U 2404 typedef struct 2405 { 2406 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2407 uint8_t pd_sc : 8; 2408 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2409 uint8_t pd_sc : 8; 2410 #endif /* DRV_BYTE_ORDER */ 2411 } lsm6dsv16bx_pedo_sc_deltat_l_t; 2412 2413 #define LSM6DSV16BX_PEDO_SC_DELTAT_H 0x1D1U 2414 typedef struct 2415 { 2416 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2417 uint8_t pd_sc : 8; 2418 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2419 uint8_t pd_sc : 8; 2420 #endif /* DRV_BYTE_ORDER */ 2421 } lsm6dsv16bx_pedo_sc_deltat_h_t; 2422 2423 #define LSM6DSV16BX_MLC_QVAR_SENSITIVITY_L 0x1E8U 2424 typedef struct 2425 { 2426 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2427 uint8_t mlc_qvar_s : 8; 2428 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2429 uint8_t mlc_qvar_s : 8; 2430 #endif /* DRV_BYTE_ORDER */ 2431 } lsm6dsv16bx_mlc_qvar_sensitivity_l_t; 2432 2433 #define LSM6DSV16BX_MLC_QVAR_SENSITIVITY_H 0x1E9U 2434 typedef struct 2435 { 2436 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2437 uint8_t mlc_qvar_s : 8; 2438 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2439 uint8_t mlc_qvar_s : 8; 2440 #endif /* DRV_BYTE_ORDER */ 2441 } lsm6dsv16bx_mlc_qvar_sensitivity_h_t; 2442 2443 /** 2444 * @} 2445 * 2446 */ 2447 2448 #define LSM6DSV16BX_START_FSM_ADD 0x035CU 2449 2450 /** 2451 * @defgroup LSM6DSV16BX_Register_Union 2452 * @brief These unions group all the registers having a bit-field 2453 * description. 2454 * These unions are useful but it's not needed by the driver. 2455 * 2456 * REMOVING this unions you are compliant with: 2457 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2458 * 2459 * @{ 2460 * 2461 */ 2462 typedef union 2463 { 2464 lsm6dsv16bx_func_cfg_access_t func_cfg_access; 2465 lsm6dsv16bx_pin_ctrl_t pin_ctrl; 2466 lsm6dsv16bx_if_cfg_t if_cfg; 2467 lsm6dsv16bx_fifo_ctrl1_t fifo_ctrl1; 2468 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; 2469 lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3; 2470 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; 2471 lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1; 2472 lsm6dsv16bx_counter_bdr_reg2_t counter_bdr_reg2; 2473 lsm6dsv16bx_int1_ctrl_t int1_ctrl; 2474 lsm6dsv16bx_int2_ctrl_t int2_ctrl; 2475 lsm6dsv16bx_who_am_i_t who_am_i; 2476 lsm6dsv16bx_ctrl1_t ctrl1; 2477 lsm6dsv16bx_ctrl2_t ctrl2; 2478 lsm6dsv16bx_ctrl3_t ctrl3; 2479 lsm6dsv16bx_ctrl4_t ctrl4; 2480 lsm6dsv16bx_ctrl5_t ctrl5; 2481 lsm6dsv16bx_ctrl6_t ctrl6; 2482 lsm6dsv16bx_ctrl7_t ctrl7; 2483 lsm6dsv16bx_ctrl8_t ctrl8; 2484 lsm6dsv16bx_ctrl9_t ctrl9; 2485 lsm6dsv16bx_ctrl10_t ctrl10; 2486 lsm6dsv16bx_fifo_status1_t fifo_status1; 2487 lsm6dsv16bx_fifo_status2_t fifo_status2; 2488 lsm6dsv16bx_all_int_src_t all_int_src; 2489 lsm6dsv16bx_status_reg_t status_reg; 2490 lsm6dsv16bx_out_temp_l_t out_temp_l; 2491 lsm6dsv16bx_out_temp_h_t out_temp_h; 2492 lsm6dsv16bx_outx_l_g_t outx_l_g; 2493 lsm6dsv16bx_outx_h_g_t outx_h_g; 2494 lsm6dsv16bx_outy_l_g_t outy_l_g; 2495 lsm6dsv16bx_outy_h_g_t outy_h_g; 2496 lsm6dsv16bx_outz_l_g_t outz_l_g; 2497 lsm6dsv16bx_outz_h_g_t outz_h_g; 2498 lsm6dsv16bx_outz_l_a_t outz_l_a; 2499 lsm6dsv16bx_outz_h_a_t outz_h_a; 2500 lsm6dsv16bx_outy_l_a_t outy_l_a; 2501 lsm6dsv16bx_outy_h_a_t outy_h_a; 2502 lsm6dsv16bx_outx_l_a_t outx_l_a; 2503 lsm6dsv16bx_outx_h_a_t outx_h_a; 2504 lsm6dsv16bx_ui_outz_l_a_ois_dualc_t ui_outz_l_a_ois_dualc; 2505 lsm6dsv16bx_ui_outz_h_a_ois_dualc_t ui_outz_h_a_ois_dualc; 2506 lsm6dsv16bx_ui_outy_l_a_ois_dualc_t ui_outy_l_a_ois_dualc; 2507 lsm6dsv16bx_ui_outy_h_a_ois_dualc_t ui_outy_h_a_ois_dualc; 2508 lsm6dsv16bx_ui_outx_l_a_ois_dualc_t ui_outx_l_a_ois_dualc; 2509 lsm6dsv16bx_ui_outx_h_a_ois_dualc_t ui_outx_h_a_ois_dualc; 2510 lsm6dsv16bx_ah_qvar_out_l_t ah_qvar_out_l; 2511 lsm6dsv16bx_ah_qvar_out_h_t ah_qvar_out_h; 2512 lsm6dsv16bx_timestamp0_t timestamp0; 2513 lsm6dsv16bx_timestamp1_t timestamp1; 2514 lsm6dsv16bx_timestamp2_t timestamp2; 2515 lsm6dsv16bx_timestamp3_t timestamp3; 2516 lsm6dsv16bx_wake_up_src_t wake_up_src; 2517 lsm6dsv16bx_tap_src_t tap_src; 2518 lsm6dsv16bx_d6d_src_t d6d_src; 2519 lsm6dsv16bx_emb_func_status_mainpage_t emb_func_status_mainpage; 2520 lsm6dsv16bx_fsm_status_mainpage_t fsm_status_mainpage; 2521 lsm6dsv16bx_mlc_status_mainpage_t mlc_status_mainpage; 2522 lsm6dsv16bx_internal_freq_t internal_freq; 2523 lsm6dsv16bx_functions_enable_t functions_enable; 2524 lsm6dsv16bx_inactivity_dur_t inactivity_dur; 2525 lsm6dsv16bx_inactivity_ths_t inactivity_ths; 2526 lsm6dsv16bx_tap_cfg0_t tap_cfg0; 2527 lsm6dsv16bx_tap_cfg1_t tap_cfg1; 2528 lsm6dsv16bx_tap_cfg2_t tap_cfg2; 2529 lsm6dsv16bx_tap_ths_6d_t tap_ths_6d; 2530 lsm6dsv16bx_tap_dur_t int_dur2; 2531 lsm6dsv16bx_wake_up_ths_t wake_up_ths; 2532 lsm6dsv16bx_wake_up_dur_t wake_up_dur; 2533 lsm6dsv16bx_free_fall_t free_fall; 2534 lsm6dsv16bx_md1_cfg_t md1_cfg; 2535 lsm6dsv16bx_md2_cfg_t md2_cfg; 2536 lsm6dsv16bx_emb_func_cfg_t emb_func_cfg; 2537 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; 2538 lsm6dsv16bx_tdm_cfg1_t tdm_cfg1; 2539 lsm6dsv16bx_tdm_cfg2_t tdm_cfg2; 2540 lsm6dsv16bx_ui_int_ois_t ui_int_ois; 2541 lsm6dsv16bx_z_ofs_usr_t z_ofs_usr; 2542 lsm6dsv16bx_y_ofs_usr_t y_ofs_usr; 2543 lsm6dsv16bx_x_ofs_usr_t x_ofs_usr; 2544 lsm6dsv16bx_fifo_data_out_tag_t fifo_data_out_tag; 2545 lsm6dsv16bx_fifo_data_out_byte_0_t fifo_data_out_byte_0; 2546 lsm6dsv16bx_fifo_data_out_byte_1_t fifo_data_out_byte_1; 2547 lsm6dsv16bx_fifo_data_out_byte_2_t fifo_data_out_byte_2; 2548 lsm6dsv16bx_fifo_data_out_byte_3_t fifo_data_out_byte_3; 2549 lsm6dsv16bx_fifo_data_out_byte_4_t fifo_data_out_byte_4; 2550 lsm6dsv16bx_fifo_data_out_byte_5_t fifo_data_out_byte_5; 2551 lsm6dsv16bx_page_sel_t page_sel; 2552 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; 2553 lsm6dsv16bx_emb_func_en_b_t emb_func_en_b; 2554 lsm6dsv16bx_emb_func_exec_status_t emb_func_exec_status; 2555 lsm6dsv16bx_page_address_t page_address; 2556 lsm6dsv16bx_page_value_t page_value; 2557 lsm6dsv16bx_emb_func_int1_t emb_func_int1; 2558 lsm6dsv16bx_fsm_int1_t fsm_int1; 2559 lsm6dsv16bx_mlc_int1_t mlc_int1; 2560 lsm6dsv16bx_emb_func_int2_t emb_func_int2; 2561 lsm6dsv16bx_fsm_int2_t fsm_int2; 2562 lsm6dsv16bx_mlc_int2_t mlc_int2; 2563 lsm6dsv16bx_emb_func_status_t emb_func_status; 2564 lsm6dsv16bx_fsm_status_t fsm_status; 2565 lsm6dsv16bx_mlc_status_t mlc_status; 2566 lsm6dsv16bx_page_rw_t page_rw; 2567 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; 2568 lsm6dsv16bx_emb_func_fifo_en_b_t emb_func_fifo_en_b; 2569 lsm6dsv16bx_fsm_enable_t fsm_enable; 2570 lsm6dsv16bx_fsm_long_counter_l_t fsm_long_counter_l; 2571 lsm6dsv16bx_fsm_long_counter_h_t fsm_long_counter_h; 2572 lsm6dsv16bx_fsm_outs1_t fsm_outs1; 2573 lsm6dsv16bx_fsm_outs2_t fsm_outs2; 2574 lsm6dsv16bx_fsm_outs3_t fsm_outs3; 2575 lsm6dsv16bx_fsm_outs4_t fsm_outs4; 2576 lsm6dsv16bx_fsm_outs5_t fsm_outs5; 2577 lsm6dsv16bx_fsm_outs6_t fsm_outs6; 2578 lsm6dsv16bx_fsm_outs7_t fsm_outs7; 2579 lsm6dsv16bx_fsm_outs8_t fsm_outs8; 2580 lsm6dsv16bx_fsm_odr_t fsm_odr; 2581 lsm6dsv16bx_mlc_odr_t mlc_odr; 2582 lsm6dsv16bx_step_counter_l_t step_counter_l; 2583 lsm6dsv16bx_step_counter_h_t step_counter_h; 2584 lsm6dsv16bx_emb_func_src_t emb_func_src; 2585 lsm6dsv16bx_emb_func_init_a_t emb_func_init_a; 2586 lsm6dsv16bx_emb_func_init_b_t emb_func_init_b; 2587 lsm6dsv16bx_mlc1_src_t mlc1_src; 2588 lsm6dsv16bx_mlc2_src_t mlc2_src; 2589 lsm6dsv16bx_mlc3_src_t mlc3_src; 2590 lsm6dsv16bx_mlc4_src_t mlc4_src; 2591 lsm6dsv16bx_fsm_qvar_sensitivity_l_t fsm_qvar_sensitivity_l; 2592 lsm6dsv16bx_fsm_qvar_sensitivity_h_t fsm_qvar_sensitivity_h; 2593 lsm6dsv16bx_fsm_lc_timeout_l_t fsm_lc_timeout_l; 2594 lsm6dsv16bx_fsm_lc_timeout_h_t fsm_lc_timeout_h; 2595 lsm6dsv16bx_fsm_programs_t fsm_programs; 2596 lsm6dsv16bx_fsm_start_add_l_t fsm_start_add_l; 2597 lsm6dsv16bx_fsm_start_add_h_t fsm_start_add_h; 2598 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg; 2599 lsm6dsv16bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; 2600 lsm6dsv16bx_pedo_sc_deltat_l_t pedo_sc_deltat_l; 2601 lsm6dsv16bx_pedo_sc_deltat_h_t pedo_sc_deltat_h; 2602 lsm6dsv16bx_mlc_qvar_sensitivity_l_t mlc_qvar_sensitivity_l; 2603 lsm6dsv16bx_mlc_qvar_sensitivity_h_t mlc_qvar_sensitivity_h; 2604 bitwise_t bitwise; 2605 uint8_t byte; 2606 } lsm6dsv16bx_reg_t; 2607 2608 2609 /** 2610 * @} 2611 * 2612 */ 2613 2614 #ifndef __weak 2615 #define __weak __attribute__((weak)) 2616 #endif /* __weak */ 2617 2618 /* 2619 * These are the basic platform dependent I/O routines to read 2620 * and write device registers connected on a standard bus. 2621 * The driver keeps offering a default implementation based on function 2622 * pointers to read/write routines for backward compatibility. 2623 * The __weak directive allows the final application to overwrite 2624 * them with a custom implementation. 2625 */ 2626 2627 int32_t lsm6dsv16bx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 2628 uint8_t *data, 2629 uint16_t len); 2630 int32_t lsm6dsv16bx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 2631 uint8_t *data, 2632 uint16_t len); 2633 2634 float_t lsm6dsv16bx_from_sflp_to_mg(int16_t lsb); 2635 float_t lsm6dsv16bx_from_fs2_to_mg(int16_t lsb); 2636 float_t lsm6dsv16bx_from_fs4_to_mg(int16_t lsb); 2637 float_t lsm6dsv16bx_from_fs8_to_mg(int16_t lsb); 2638 float_t lsm6dsv16bx_from_fs16_to_mg(int16_t lsb); 2639 2640 float_t lsm6dsv16bx_from_fs125_to_mdps(int16_t lsb); 2641 float_t lsm6dsv16bx_from_fs500_to_mdps(int16_t lsb); 2642 float_t lsm6dsv16bx_from_fs250_to_mdps(int16_t lsb); 2643 float_t lsm6dsv16bx_from_fs1000_to_mdps(int16_t lsb); 2644 float_t lsm6dsv16bx_from_fs2000_to_mdps(int16_t lsb); 2645 float_t lsm6dsv16bx_from_fs4000_to_mdps(int16_t lsb); 2646 2647 float_t lsm6dsv16bx_from_lsb_to_celsius(int16_t lsb); 2648 2649 uint64_t lsm6dsv16bx_from_lsb_to_nsec(uint32_t lsb); 2650 2651 typedef enum 2652 { 2653 LSM6DSV16BX_READY = 0x0, 2654 LSM6DSV16BX_GLOBAL_RST = 0x1, 2655 LSM6DSV16BX_RESTORE_CAL_PARAM = 0x2, 2656 LSM6DSV16BX_RESTORE_CTRL_REGS = 0x4, 2657 } lsm6dsv16bx_reset_t; 2658 int32_t lsm6dsv16bx_reset_set(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t val); 2659 int32_t lsm6dsv16bx_reset_get(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t *val); 2660 2661 typedef enum 2662 { 2663 LSM6DSV16BX_MAIN_MEM_BANK = 0x0, 2664 LSM6DSV16BX_EMBED_FUNC_MEM_BANK = 0x1, 2665 } lsm6dsv16bx_mem_bank_t; 2666 int32_t lsm6dsv16bx_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t val); 2667 int32_t lsm6dsv16bx_mem_bank_get(stmdev_ctx_t *ctx, 2668 lsm6dsv16bx_mem_bank_t *val); 2669 2670 int32_t lsm6dsv16bx_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); 2671 2672 typedef enum 2673 { 2674 LSM6DSV16BX_XL_ODR_OFF = 0x0, 2675 LSM6DSV16BX_XL_ODR_AT_1Hz875 = 0x1, 2676 LSM6DSV16BX_XL_ODR_AT_7Hz5 = 0x2, 2677 LSM6DSV16BX_XL_ODR_AT_15Hz = 0x3, 2678 LSM6DSV16BX_XL_ODR_AT_30Hz = 0x4, 2679 LSM6DSV16BX_XL_ODR_AT_60Hz = 0x5, 2680 LSM6DSV16BX_XL_ODR_AT_120Hz = 0x6, 2681 LSM6DSV16BX_XL_ODR_AT_240Hz = 0x7, 2682 LSM6DSV16BX_XL_ODR_AT_480Hz = 0x8, 2683 LSM6DSV16BX_XL_ODR_AT_960Hz = 0x9, 2684 LSM6DSV16BX_XL_ODR_AT_1920Hz = 0xA, 2685 LSM6DSV16BX_XL_ODR_AT_3840Hz = 0xB, 2686 LSM6DSV16BX_XL_ODR_AT_7680Hz = 0xC, 2687 } lsm6dsv16bx_xl_data_rate_t; 2688 int32_t lsm6dsv16bx_xl_data_rate_set(stmdev_ctx_t *ctx, 2689 lsm6dsv16bx_xl_data_rate_t val); 2690 int32_t lsm6dsv16bx_xl_data_rate_get(stmdev_ctx_t *ctx, 2691 lsm6dsv16bx_xl_data_rate_t *val); 2692 2693 typedef enum 2694 { 2695 LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD = 0x0, 2696 LSM6DSV16BX_XL_HIGH_ACCURANCY_ODR_MD = 0x1, 2697 LSM6DSV16BX_XL_LOW_POWER_2_AVG_MD = 0x4, 2698 LSM6DSV16BX_XL_LOW_POWER_4_AVG_MD = 0x5, 2699 LSM6DSV16BX_XL_LOW_POWER_8_AVG_MD = 0x6, 2700 LSM6DSV16BX_XL_NORMAL_MD = 0x7, 2701 } lsm6dsv16bx_xl_mode_t; 2702 int32_t lsm6dsv16bx_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t val); 2703 int32_t lsm6dsv16bx_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t *val); 2704 2705 typedef enum 2706 { 2707 LSM6DSV16BX_GY_ODR_OFF = 0x0, 2708 LSM6DSV16BX_GY_ODR_AT_7Hz5 = 0x2, 2709 LSM6DSV16BX_GY_ODR_AT_15Hz = 0x3, 2710 LSM6DSV16BX_GY_ODR_AT_30Hz = 0x4, 2711 LSM6DSV16BX_GY_ODR_AT_60Hz = 0x5, 2712 LSM6DSV16BX_GY_ODR_AT_120Hz = 0x6, 2713 LSM6DSV16BX_GY_ODR_AT_240Hz = 0x7, 2714 LSM6DSV16BX_GY_ODR_AT_480Hz = 0x8, 2715 LSM6DSV16BX_GY_ODR_AT_960Hz = 0x9, 2716 LSM6DSV16BX_GY_ODR_AT_1920Hz = 0xa, 2717 LSM6DSV16BX_GY_ODR_AT_3840Hz = 0xb, 2718 LSM6DSV16BX_GY_ODR_AT_7680Hz = 0xc, 2719 } lsm6dsv16bx_gy_data_rate_t; 2720 int32_t lsm6dsv16bx_gy_data_rate_set(stmdev_ctx_t *ctx, 2721 lsm6dsv16bx_gy_data_rate_t val); 2722 int32_t lsm6dsv16bx_gy_data_rate_get(stmdev_ctx_t *ctx, 2723 lsm6dsv16bx_gy_data_rate_t *val); 2724 2725 typedef enum 2726 { 2727 LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD = 0x0, 2728 LSM6DSV16BX_GY_HIGH_ACCURANCY_ODR_MD = 0x1, 2729 LSM6DSV16BX_GY_SLEEP_MD = 0x4, 2730 LSM6DSV16BX_GY_LOW_POWER_MD = 0x5, 2731 } lsm6dsv16bx_gy_mode_t; 2732 int32_t lsm6dsv16bx_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t val); 2733 int32_t lsm6dsv16bx_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t *val); 2734 2735 int32_t lsm6dsv16bx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 2736 int32_t lsm6dsv16bx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); 2737 2738 int32_t lsm6dsv16bx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 2739 int32_t lsm6dsv16bx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); 2740 2741 typedef enum 2742 { 2743 LSM6DSV16BX_DRDY_LATCHED = 0x0, 2744 LSM6DSV16BX_DRDY_PULSED = 0x1, 2745 } lsm6dsv16bx_data_ready_mode_t; 2746 int32_t lsm6dsv16bx_data_ready_mode_set(stmdev_ctx_t *ctx, 2747 lsm6dsv16bx_data_ready_mode_t val); 2748 int32_t lsm6dsv16bx_data_ready_mode_get(stmdev_ctx_t *ctx, 2749 lsm6dsv16bx_data_ready_mode_t *val); 2750 2751 typedef enum 2752 { 2753 LSM6DSV16BX_125dps = 0x0, 2754 LSM6DSV16BX_250dps = 0x1, 2755 LSM6DSV16BX_500dps = 0x2, 2756 LSM6DSV16BX_1000dps = 0x3, 2757 LSM6DSV16BX_2000dps = 0x4, 2758 LSM6DSV16BX_4000dps = 0x5, 2759 } lsm6dsv16bx_gy_full_scale_t; 2760 int32_t lsm6dsv16bx_gy_full_scale_set(stmdev_ctx_t *ctx, 2761 lsm6dsv16bx_gy_full_scale_t val); 2762 int32_t lsm6dsv16bx_gy_full_scale_get(stmdev_ctx_t *ctx, 2763 lsm6dsv16bx_gy_full_scale_t *val); 2764 2765 typedef enum 2766 { 2767 LSM6DSV16BX_2g = 0x0, 2768 LSM6DSV16BX_4g = 0x1, 2769 LSM6DSV16BX_8g = 0x2, 2770 LSM6DSV16BX_16g = 0x3, 2771 } lsm6dsv16bx_xl_full_scale_t; 2772 int32_t lsm6dsv16bx_xl_full_scale_set(stmdev_ctx_t *ctx, 2773 lsm6dsv16bx_xl_full_scale_t val); 2774 int32_t lsm6dsv16bx_xl_full_scale_get(stmdev_ctx_t *ctx, 2775 lsm6dsv16bx_xl_full_scale_t *val); 2776 2777 int32_t lsm6dsv16bx_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val); 2778 int32_t lsm6dsv16bx_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val); 2779 2780 typedef enum 2781 { 2782 LSM6DSV16BX_XL_ST_DISABLE = 0x0, 2783 LSM6DSV16BX_XL_ST_POSITIVE = 0x1, 2784 LSM6DSV16BX_XL_ST_NEGATIVE = 0x2, 2785 LSM6DSV16BX_XL_ST_OFFSET_POS = 0x5, 2786 LSM6DSV16BX_XL_ST_OFFSET_NEG = 0x6, 2787 } lsm6dsv16bx_xl_self_test_t; 2788 int32_t lsm6dsv16bx_xl_self_test_set(stmdev_ctx_t *ctx, 2789 lsm6dsv16bx_xl_self_test_t val); 2790 int32_t lsm6dsv16bx_xl_self_test_get(stmdev_ctx_t *ctx, 2791 lsm6dsv16bx_xl_self_test_t *val); 2792 2793 typedef enum 2794 { 2795 LSM6DSV16BX_GY_ST_DISABLE = 0x0, 2796 LSM6DSV16BX_GY_ST_POSITIVE = 0x1, 2797 LSM6DSV16BX_GY_ST_NEGATIVE = 0x2, 2798 } lsm6dsv16bx_gy_self_test_t; 2799 int32_t lsm6dsv16bx_gy_self_test_set(stmdev_ctx_t *ctx, 2800 lsm6dsv16bx_gy_self_test_t val); 2801 int32_t lsm6dsv16bx_gy_self_test_get(stmdev_ctx_t *ctx, 2802 lsm6dsv16bx_gy_self_test_t *val); 2803 2804 typedef struct 2805 { 2806 uint8_t drdy_xl : 1; 2807 uint8_t drdy_gy : 1; 2808 uint8_t drdy_temp : 1; 2809 uint8_t drdy_ah_qvar : 1; 2810 uint8_t gy_settling : 1; 2811 uint8_t den_flag : 1; 2812 uint8_t timestamp : 1; 2813 uint8_t free_fall : 1; 2814 uint8_t wake_up : 1; 2815 uint8_t wake_up_z : 1; 2816 uint8_t wake_up_y : 1; 2817 uint8_t wake_up_x : 1; 2818 uint8_t single_tap : 1; 2819 uint8_t double_tap : 1; 2820 uint8_t tap_z : 1; 2821 uint8_t tap_y : 1; 2822 uint8_t tap_x : 1; 2823 uint8_t tap_sign : 1; 2824 uint8_t six_d : 1; 2825 uint8_t six_d_xl : 1; 2826 uint8_t six_d_xh : 1; 2827 uint8_t six_d_yl : 1; 2828 uint8_t six_d_yh : 1; 2829 uint8_t six_d_zl : 1; 2830 uint8_t six_d_zh : 1; 2831 uint8_t sleep_change : 1; 2832 uint8_t sleep_state : 1; 2833 uint8_t step_detector : 1; 2834 uint8_t step_count_inc : 1; 2835 uint8_t step_count_overflow : 1; 2836 uint8_t step_on_delta_time : 1; 2837 uint8_t emb_func_stand_by : 1; 2838 uint8_t emb_func_time_exceed: 1; 2839 uint8_t tilt : 1; 2840 uint8_t sig_mot : 1; 2841 uint8_t fsm_lc : 1; 2842 uint8_t fsm1 : 1; 2843 uint8_t fsm2 : 1; 2844 uint8_t fsm3 : 1; 2845 uint8_t fsm4 : 1; 2846 uint8_t fsm5 : 1; 2847 uint8_t fsm6 : 1; 2848 uint8_t fsm7 : 1; 2849 uint8_t fsm8 : 1; 2850 uint8_t mlc1 : 1; 2851 uint8_t mlc2 : 1; 2852 uint8_t mlc3 : 1; 2853 uint8_t mlc4 : 1; 2854 uint8_t fifo_bdr : 1; 2855 uint8_t fifo_full : 1; 2856 uint8_t fifo_ovr : 1; 2857 uint8_t fifo_th : 1; 2858 } lsm6dsv16bx_all_sources_t; 2859 int32_t lsm6dsv16bx_all_sources_get(stmdev_ctx_t *ctx, 2860 lsm6dsv16bx_all_sources_t *val); 2861 2862 typedef struct 2863 { 2864 uint8_t drdy_xl : 1; 2865 uint8_t drdy_gy : 1; 2866 uint8_t drdy_temp : 1; 2867 } lsm6dsv16bx_data_ready_t; 2868 int32_t lsm6dsv16bx_flag_data_ready_get(stmdev_ctx_t *ctx, 2869 lsm6dsv16bx_data_ready_t *val); 2870 2871 int32_t lsm6dsv16bx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2872 2873 int32_t lsm6dsv16bx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2874 2875 int32_t lsm6dsv16bx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2876 2877 int32_t lsm6dsv16bx_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2878 2879 int32_t lsm6dsv16bx_ois_dual_acceleration_raw_get(stmdev_ctx_t *ctx, 2880 int16_t *val); 2881 2882 int32_t lsm6dsv16bx_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2883 2884 int32_t lsm6dsv16bx_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val); 2885 2886 typedef struct 2887 { 2888 uint8_t x : 1; 2889 uint8_t y : 1; 2890 uint8_t z : 1; 2891 } lsm6dsv16bx_xl_axis_t; 2892 int32_t lsm6dsv16bx_xl_axis_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t val); 2893 int32_t lsm6dsv16bx_xl_axis_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t *val); 2894 2895 int32_t lsm6dsv16bx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, 2896 uint8_t *buf, uint8_t len); 2897 int32_t lsm6dsv16bx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, 2898 uint8_t *buf, uint8_t len); 2899 2900 int32_t lsm6dsv16bx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); 2901 int32_t lsm6dsv16bx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); 2902 2903 int32_t lsm6dsv16bx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); 2904 2905 typedef enum 2906 { 2907 LSM6DSV16BX_AUTO = 0x0, 2908 LSM6DSV16BX_ALWAYS_ACTIVE = 0x1, 2909 } lsm6dsv16bx_filt_anti_spike_t; 2910 int32_t lsm6dsv16bx_filt_anti_spike_set(stmdev_ctx_t *ctx, 2911 lsm6dsv16bx_filt_anti_spike_t val); 2912 int32_t lsm6dsv16bx_filt_anti_spike_get(stmdev_ctx_t *ctx, 2913 lsm6dsv16bx_filt_anti_spike_t *val); 2914 2915 typedef struct 2916 { 2917 uint8_t drdy : 1; 2918 uint8_t irq_xl : 1; 2919 uint8_t irq_g : 1; 2920 uint8_t tdm_excep_code : 1; 2921 } lsm6dsv16bx_filt_settling_mask_t; 2922 int32_t lsm6dsv16bx_filt_settling_mask_set(stmdev_ctx_t *ctx, 2923 lsm6dsv16bx_filt_settling_mask_t val); 2924 int32_t lsm6dsv16bx_filt_settling_mask_get(stmdev_ctx_t *ctx, 2925 lsm6dsv16bx_filt_settling_mask_t *val); 2926 2927 typedef enum 2928 { 2929 LSM6DSV16BX_GY_ULTRA_LIGHT = 0x0, 2930 LSM6DSV16BX_GY_VERY_LIGHT = 0x1, 2931 LSM6DSV16BX_GY_LIGHT = 0x2, 2932 LSM6DSV16BX_GY_MEDIUM = 0x3, 2933 LSM6DSV16BX_GY_STRONG = 0x4, 2934 LSM6DSV16BX_GY_VERY_STRONG = 0x5, 2935 LSM6DSV16BX_GY_AGGRESSIVE = 0x6, 2936 LSM6DSV16BX_GY_XTREME = 0x7, 2937 } lsm6dsv16bx_filt_gy_lp1_bandwidth_t; 2938 int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, 2939 lsm6dsv16bx_filt_gy_lp1_bandwidth_t val); 2940 int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, 2941 lsm6dsv16bx_filt_gy_lp1_bandwidth_t *val); 2942 2943 int32_t lsm6dsv16bx_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val); 2944 int32_t lsm6dsv16bx_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); 2945 2946 typedef struct 2947 { 2948 uint8_t hpf : 1; 2949 uint8_t lpf : 1; 2950 } lsm6dsv16bx_filt_ah_qvar_conf_t; 2951 int32_t lsm6dsv16bx_filt_ah_qvar_conf_set(stmdev_ctx_t *ctx, 2952 lsm6dsv16bx_filt_ah_qvar_conf_t val); 2953 int32_t lsm6dsv16bx_filt_ah_qvar_conf_get(stmdev_ctx_t *ctx, 2954 lsm6dsv16bx_filt_ah_qvar_conf_t *val); 2955 2956 typedef enum 2957 { 2958 LSM6DSV16BX_XL_ULTRA_LIGHT = 0x0, 2959 LSM6DSV16BX_XL_VERY_LIGHT = 0x1, 2960 LSM6DSV16BX_XL_LIGHT = 0x2, 2961 LSM6DSV16BX_XL_MEDIUM = 0x3, 2962 LSM6DSV16BX_XL_STRONG = 0x4, 2963 LSM6DSV16BX_XL_VERY_STRONG = 0x5, 2964 LSM6DSV16BX_XL_AGGRESSIVE = 0x6, 2965 LSM6DSV16BX_XL_XTREME = 0x7, 2966 } lsm6dsv16bx_filt_xl_lp2_bandwidth_t; 2967 int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, 2968 lsm6dsv16bx_filt_xl_lp2_bandwidth_t val); 2969 int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, 2970 lsm6dsv16bx_filt_xl_lp2_bandwidth_t *val); 2971 2972 int32_t lsm6dsv16bx_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val); 2973 int32_t lsm6dsv16bx_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); 2974 2975 int32_t lsm6dsv16bx_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val); 2976 int32_t lsm6dsv16bx_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val); 2977 2978 int32_t lsm6dsv16bx_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); 2979 int32_t lsm6dsv16bx_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); 2980 2981 typedef enum 2982 { 2983 LSM6DSV16BX_HP_MD_NORMAL = 0x0, 2984 LSM6DSV16BX_HP_MD_REFERENCE = 0x1, 2985 } lsm6dsv16bx_filt_xl_hp_mode_t; 2986 int32_t lsm6dsv16bx_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, 2987 lsm6dsv16bx_filt_xl_hp_mode_t val); 2988 int32_t lsm6dsv16bx_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, 2989 lsm6dsv16bx_filt_xl_hp_mode_t *val); 2990 2991 typedef enum 2992 { 2993 LSM6DSV16BX_WK_FEED_SLOPE = 0x0, 2994 LSM6DSV16BX_WK_FEED_HIGH_PASS = 0x1, 2995 LSM6DSV16BX_WK_FEED_LP_WITH_OFFSET = 0x2, 2996 } lsm6dsv16bx_filt_wkup_act_feed_t; 2997 int32_t lsm6dsv16bx_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, 2998 lsm6dsv16bx_filt_wkup_act_feed_t val); 2999 int32_t lsm6dsv16bx_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, 3000 lsm6dsv16bx_filt_wkup_act_feed_t *val); 3001 3002 int32_t lsm6dsv16bx_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val); 3003 int32_t lsm6dsv16bx_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val); 3004 3005 typedef enum 3006 { 3007 LSM6DSV16BX_SIXD_FEED_ODR_DIV_2 = 0x0, 3008 LSM6DSV16BX_SIXD_FEED_LOW_PASS = 0x1, 3009 } lsm6dsv16bx_filt_sixd_feed_t; 3010 int32_t lsm6dsv16bx_filt_sixd_feed_set(stmdev_ctx_t *ctx, 3011 lsm6dsv16bx_filt_sixd_feed_t val); 3012 int32_t lsm6dsv16bx_filt_sixd_feed_get(stmdev_ctx_t *ctx, 3013 lsm6dsv16bx_filt_sixd_feed_t *val); 3014 3015 int32_t lsm6dsv16bx_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); 3016 int32_t lsm6dsv16bx_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); 3017 3018 typedef enum 3019 { 3020 LSM6DSV16BX_I2C_I3C_ENABLE = 0x0, 3021 LSM6DSV16BX_I2C_I3C_DISABLE = 0x1, 3022 } lsm6dsv16bx_ui_i2c_i3c_mode_t; 3023 int32_t lsm6dsv16bx_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, 3024 lsm6dsv16bx_ui_i2c_i3c_mode_t val); 3025 int32_t lsm6dsv16bx_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, 3026 lsm6dsv16bx_ui_i2c_i3c_mode_t *val); 3027 3028 typedef enum 3029 { 3030 LSM6DSV16BX_SPI_4_WIRE = 0x0, 3031 LSM6DSV16BX_SPI_3_WIRE = 0x1, 3032 } lsm6dsv16bx_spi_mode_t; 3033 int32_t lsm6dsv16bx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t val); 3034 int32_t lsm6dsv16bx_spi_mode_get(stmdev_ctx_t *ctx, 3035 lsm6dsv16bx_spi_mode_t *val); 3036 3037 int32_t lsm6dsv16bx_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); 3038 int32_t lsm6dsv16bx_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); 3039 3040 typedef enum 3041 { 3042 LSM6DSV16BX_IBI_2us = 0x0, 3043 LSM6DSV16BX_IBI_50us = 0x1, 3044 LSM6DSV16BX_IBI_1ms = 0x2, 3045 LSM6DSV16BX_IBI_25ms = 0x3, 3046 } lsm6dsv16bx_i3c_ibi_time_t; 3047 int32_t lsm6dsv16bx_i3c_ibi_time_set(stmdev_ctx_t *ctx, 3048 lsm6dsv16bx_i3c_ibi_time_t val); 3049 int32_t lsm6dsv16bx_i3c_ibi_time_get(stmdev_ctx_t *ctx, 3050 lsm6dsv16bx_i3c_ibi_time_t *val); 3051 3052 typedef enum 3053 { 3054 LSM6DSV16BX_PUSH_PULL = 0x0, 3055 LSM6DSV16BX_OPEN_DRAIN = 0x1, 3056 } lsm6dsv16bx_int_pin_mode_t; 3057 int32_t lsm6dsv16bx_int_pin_mode_set(stmdev_ctx_t *ctx, 3058 lsm6dsv16bx_int_pin_mode_t val); 3059 int32_t lsm6dsv16bx_int_pin_mode_get(stmdev_ctx_t *ctx, 3060 lsm6dsv16bx_int_pin_mode_t *val); 3061 3062 typedef enum 3063 { 3064 LSM6DSV16BX_ACTIVE_HIGH = 0x0, 3065 LSM6DSV16BX_ACTIVE_LOW = 0x1, 3066 } lsm6dsv16bx_pin_polarity_t; 3067 int32_t lsm6dsv16bx_pin_polarity_set(stmdev_ctx_t *ctx, 3068 lsm6dsv16bx_pin_polarity_t val); 3069 int32_t lsm6dsv16bx_pin_polarity_get(stmdev_ctx_t *ctx, 3070 lsm6dsv16bx_pin_polarity_t *val); 3071 3072 typedef struct 3073 { 3074 uint8_t boot : 1; 3075 uint8_t drdy_ois : 1; 3076 uint8_t drdy_xl : 1; 3077 uint8_t drdy_gy : 1; 3078 uint8_t drdy_temp : 1; 3079 uint8_t fifo_th : 1; 3080 uint8_t fifo_ovr : 1; 3081 uint8_t fifo_full : 1; 3082 uint8_t fifo_bdr : 1; 3083 uint8_t den_flag : 1; 3084 uint8_t timestamp : 1; // impact on int2 signals 3085 uint8_t six_d : 1; 3086 uint8_t double_tap : 1; 3087 uint8_t free_fall : 1; 3088 uint8_t wake_up : 1; 3089 uint8_t single_tap : 1; 3090 uint8_t sleep_change : 1; 3091 uint8_t sleep_status : 1; 3092 uint8_t step_detector : 1; 3093 uint8_t step_count_overflow : 1; 3094 uint8_t tilt : 1; 3095 uint8_t sig_mot : 1; 3096 uint8_t emb_func_stand_by : 1; // impact on int2 signals 3097 uint8_t fsm_lc : 1; 3098 uint8_t fsm1 : 1; 3099 uint8_t fsm2 : 1; 3100 uint8_t fsm3 : 1; 3101 uint8_t fsm4 : 1; 3102 uint8_t fsm5 : 1; 3103 uint8_t fsm6 : 1; 3104 uint8_t fsm7 : 1; 3105 uint8_t fsm8 : 1; 3106 uint8_t mlc1 : 1; 3107 uint8_t mlc2 : 1; 3108 uint8_t mlc3 : 1; 3109 uint8_t mlc4 : 1; 3110 } lsm6dsv16bx_pin_int1_route_t; 3111 int32_t lsm6dsv16bx_pin_int1_route_set(stmdev_ctx_t *ctx, 3112 lsm6dsv16bx_pin_int1_route_t val); 3113 int32_t lsm6dsv16bx_pin_int1_route_get(stmdev_ctx_t *ctx, 3114 lsm6dsv16bx_pin_int1_route_t *val); 3115 3116 typedef struct 3117 { 3118 uint8_t boot : 1; 3119 uint8_t drdy_ois : 1; 3120 uint8_t drdy_xl : 1; 3121 uint8_t drdy_gy : 1; 3122 uint8_t drdy_temp : 1; 3123 uint8_t fifo_th : 1; 3124 uint8_t fifo_ovr : 1; 3125 uint8_t fifo_full : 1; 3126 uint8_t fifo_bdr : 1; 3127 uint8_t den_flag : 1; 3128 uint8_t timestamp : 1; // impact on int2 signals 3129 uint8_t six_d : 1; 3130 uint8_t double_tap : 1; 3131 uint8_t free_fall : 1; 3132 uint8_t wake_up : 1; 3133 uint8_t single_tap : 1; 3134 uint8_t sleep_change : 1; 3135 uint8_t sleep_status : 1; 3136 uint8_t step_detector : 1; 3137 uint8_t step_count_overflow : 1; 3138 uint8_t tilt : 1; 3139 uint8_t sig_mot : 1; 3140 uint8_t emb_func_stand_by : 1; // impact on int2 signals 3141 uint8_t fsm_lc : 1; 3142 uint8_t fsm1 : 1; 3143 uint8_t fsm2 : 1; 3144 uint8_t fsm3 : 1; 3145 uint8_t fsm4 : 1; 3146 uint8_t fsm5 : 1; 3147 uint8_t fsm6 : 1; 3148 uint8_t fsm7 : 1; 3149 uint8_t fsm8 : 1; 3150 uint8_t mlc1 : 1; 3151 uint8_t mlc2 : 1; 3152 uint8_t mlc3 : 1; 3153 uint8_t mlc4 : 1; 3154 } lsm6dsv16bx_pin_int2_route_t; 3155 int32_t lsm6dsv16bx_pin_int2_route_set(stmdev_ctx_t *ctx, 3156 lsm6dsv16bx_pin_int2_route_t val); 3157 int32_t lsm6dsv16bx_pin_int2_route_get(stmdev_ctx_t *ctx, 3158 lsm6dsv16bx_pin_int2_route_t *val); 3159 3160 int32_t lsm6dsv16bx_pin_int_en_when_i2c_set(stmdev_ctx_t *ctx, uint8_t val); 3161 int32_t lsm6dsv16bx_pin_int_en_when_i2c_get(stmdev_ctx_t *ctx, uint8_t *val); 3162 3163 typedef enum 3164 { 3165 LSM6DSV16BX_ALL_INT_PULSED = 0x0, 3166 LSM6DSV16BX_BASE_LATCHED_EMB_PULSED = 0x1, 3167 LSM6DSV16BX_BASE_PULSED_EMB_LATCHED = 0x2, 3168 LSM6DSV16BX_ALL_INT_LATCHED = 0x3, 3169 } lsm6dsv16bx_int_notification_t; 3170 int32_t lsm6dsv16bx_int_notification_set(stmdev_ctx_t *ctx, 3171 lsm6dsv16bx_int_notification_t val); 3172 int32_t lsm6dsv16bx_int_notification_get(stmdev_ctx_t *ctx, 3173 lsm6dsv16bx_int_notification_t *val); 3174 3175 typedef enum 3176 { 3177 LSM6DSV16BX_XL_AND_GY_NOT_AFFECTED = 0x0, 3178 LSM6DSV16BX_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, 3179 LSM6DSV16BX_XL_LOW_POWER_GY_SLEEP = 0x2, 3180 LSM6DSV16BX_XL_LOW_POWER_GY_POWER_DOWN = 0x3, 3181 } lsm6dsv16bx_act_mode_t; 3182 int32_t lsm6dsv16bx_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t val); 3183 int32_t lsm6dsv16bx_act_mode_get(stmdev_ctx_t *ctx, 3184 lsm6dsv16bx_act_mode_t *val); 3185 3186 typedef enum 3187 { 3188 LSM6DSV16BX_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, 3189 LSM6DSV16BX_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, 3190 LSM6DSV16BX_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, 3191 LSM6DSV16BX_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, 3192 } lsm6dsv16bx_act_from_sleep_to_act_dur_t; 3193 int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, 3194 lsm6dsv16bx_act_from_sleep_to_act_dur_t val); 3195 int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, 3196 lsm6dsv16bx_act_from_sleep_to_act_dur_t *val); 3197 3198 typedef enum 3199 { 3200 LSM6DSV16BX_1Hz875 = 0x0, 3201 LSM6DSV16BX_15Hz = 0x1, 3202 LSM6DSV16BX_30Hz = 0x2, 3203 LSM6DSV16BX_60Hz = 0x3, 3204 } lsm6dsv16bx_act_sleep_xl_odr_t; 3205 int32_t lsm6dsv16bx_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, 3206 lsm6dsv16bx_act_sleep_xl_odr_t val); 3207 int32_t lsm6dsv16bx_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, 3208 lsm6dsv16bx_act_sleep_xl_odr_t *val); 3209 3210 typedef struct 3211 { 3212 uint32_t wk_ths_mg; 3213 uint32_t inact_ths_mg; 3214 } lsm6dsv16bx_act_thresholds_t; 3215 int32_t lsm6dsv16bx_act_thresholds_set(stmdev_ctx_t *ctx, 3216 lsm6dsv16bx_act_thresholds_t val); 3217 int32_t lsm6dsv16bx_act_thresholds_get(stmdev_ctx_t *ctx, 3218 lsm6dsv16bx_act_thresholds_t *val); 3219 3220 typedef struct 3221 { 3222 uint8_t shock : 2; 3223 uint8_t quiet : 4; 3224 } lsm6dsv16bx_act_wkup_time_windows_t; 3225 int32_t lsm6dsv16bx_act_wkup_time_windows_set(stmdev_ctx_t *ctx, 3226 lsm6dsv16bx_act_wkup_time_windows_t val); 3227 int32_t lsm6dsv16bx_act_wkup_time_windows_get(stmdev_ctx_t *ctx, 3228 lsm6dsv16bx_act_wkup_time_windows_t *val); 3229 3230 typedef struct 3231 { 3232 uint8_t tap_x_en : 1; 3233 uint8_t tap_y_en : 1; 3234 uint8_t tap_z_en : 1; 3235 } lsm6dsv16bx_tap_detection_t; 3236 int32_t lsm6dsv16bx_tap_detection_set(stmdev_ctx_t *ctx, 3237 lsm6dsv16bx_tap_detection_t val); 3238 int32_t lsm6dsv16bx_tap_detection_get(stmdev_ctx_t *ctx, 3239 lsm6dsv16bx_tap_detection_t *val); 3240 3241 typedef struct 3242 { 3243 uint8_t x : 1; 3244 uint8_t y : 1; 3245 uint8_t z : 1; 3246 } lsm6dsv16bx_tap_thresholds_t; 3247 int32_t lsm6dsv16bx_tap_thresholds_set(stmdev_ctx_t *ctx, 3248 lsm6dsv16bx_tap_thresholds_t val); 3249 int32_t lsm6dsv16bx_tap_thresholds_get(stmdev_ctx_t *ctx, 3250 lsm6dsv16bx_tap_thresholds_t *val); 3251 3252 3253 typedef enum 3254 { 3255 LSM6DSV16BX_XYZ = 0x3, 3256 LSM6DSV16BX_YXZ = 0x5, 3257 LSM6DSV16BX_XZY = 0x6, 3258 LSM6DSV16BX_ZYX = 0x0, 3259 LSM6DSV16BX_YZX = 0x1, 3260 LSM6DSV16BX_ZXY = 0x2, 3261 } lsm6dsv16bx_tap_axis_priority_t; 3262 int32_t lsm6dsv16bx_tap_axis_priority_set(stmdev_ctx_t *ctx, 3263 lsm6dsv16bx_tap_axis_priority_t val); 3264 int32_t lsm6dsv16bx_tap_axis_priority_get(stmdev_ctx_t *ctx, 3265 lsm6dsv16bx_tap_axis_priority_t *val); 3266 3267 typedef struct 3268 { 3269 uint8_t shock : 1; 3270 uint8_t quiet : 1; 3271 uint8_t tap_gap : 1; 3272 } lsm6dsv16bx_tap_time_windows_t; 3273 int32_t lsm6dsv16bx_tap_time_windows_set(stmdev_ctx_t *ctx, 3274 lsm6dsv16bx_tap_time_windows_t val); 3275 int32_t lsm6dsv16bx_tap_time_windows_get(stmdev_ctx_t *ctx, 3276 lsm6dsv16bx_tap_time_windows_t *val); 3277 3278 typedef enum 3279 { 3280 LSM6DSV16BX_ONLY_SINGLE = 0x0, 3281 LSM6DSV16BX_BOTH_SINGLE_DOUBLE = 0x1, 3282 } lsm6dsv16bx_tap_mode_t; 3283 int32_t lsm6dsv16bx_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t val); 3284 int32_t lsm6dsv16bx_tap_mode_get(stmdev_ctx_t *ctx, 3285 lsm6dsv16bx_tap_mode_t *val); 3286 3287 typedef enum 3288 { 3289 LSM6DSV16BX_DEG_80 = 0x0, 3290 LSM6DSV16BX_DEG_70 = 0x1, 3291 LSM6DSV16BX_DEG_60 = 0x2, 3292 LSM6DSV16BX_DEG_50 = 0x3, 3293 } lsm6dsv16bx_6d_threshold_t; 3294 int32_t lsm6dsv16bx_6d_threshold_set(stmdev_ctx_t *ctx, 3295 lsm6dsv16bx_6d_threshold_t val); 3296 int32_t lsm6dsv16bx_6d_threshold_get(stmdev_ctx_t *ctx, 3297 lsm6dsv16bx_6d_threshold_t *val); 3298 3299 int32_t lsm6dsv16bx_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val); 3300 int32_t lsm6dsv16bx_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val); 3301 3302 typedef enum 3303 { 3304 LSM6DSV16BX_156_mg = 0x0, 3305 LSM6DSV16BX_219_mg = 0x1, 3306 LSM6DSV16BX_250_mg = 0x2, 3307 LSM6DSV16BX_312_mg = 0x3, 3308 LSM6DSV16BX_344_mg = 0x4, 3309 LSM6DSV16BX_406_mg = 0x5, 3310 LSM6DSV16BX_469_mg = 0x6, 3311 LSM6DSV16BX_500_mg = 0x7, 3312 } lsm6dsv16bx_ff_thresholds_t; 3313 int32_t lsm6dsv16bx_ff_thresholds_set(stmdev_ctx_t *ctx, 3314 lsm6dsv16bx_ff_thresholds_t val); 3315 int32_t lsm6dsv16bx_ff_thresholds_get(stmdev_ctx_t *ctx, 3316 lsm6dsv16bx_ff_thresholds_t *val); 3317 3318 int32_t lsm6dsv16bx_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); 3319 int32_t lsm6dsv16bx_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); 3320 3321 int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val); 3322 int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 3323 3324 typedef enum 3325 { 3326 LSM6DSV16BX_CMP_DISABLE = 0x0, 3327 LSM6DSV16BX_CMP_8_TO_1 = 0x1, 3328 LSM6DSV16BX_CMP_16_TO_1 = 0x2, 3329 LSM6DSV16BX_CMP_32_TO_1 = 0x3, 3330 } lsm6dsv16bx_fifo_compress_algo_t; 3331 int32_t lsm6dsv16bx_fifo_compress_algo_set(stmdev_ctx_t *ctx, 3332 lsm6dsv16bx_fifo_compress_algo_t val); 3333 int32_t lsm6dsv16bx_fifo_compress_algo_get(stmdev_ctx_t *ctx, 3334 lsm6dsv16bx_fifo_compress_algo_t *val); 3335 3336 int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, 3337 uint8_t val); 3338 int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, 3339 uint8_t *val); 3340 3341 int32_t lsm6dsv16bx_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, 3342 uint8_t val); 3343 int32_t lsm6dsv16bx_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, 3344 uint8_t *val); 3345 3346 int32_t lsm6dsv16bx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); 3347 int32_t lsm6dsv16bx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); 3348 3349 typedef enum 3350 { 3351 LSM6DSV16BX_XL_NOT_BATCHED = 0x0, 3352 LSM6DSV16BX_XL_BATCHED_AT_1Hz875 = 0x1, 3353 LSM6DSV16BX_XL_BATCHED_AT_7Hz5 = 0x2, 3354 LSM6DSV16BX_XL_BATCHED_AT_15Hz = 0x3, 3355 LSM6DSV16BX_XL_BATCHED_AT_30Hz = 0x4, 3356 LSM6DSV16BX_XL_BATCHED_AT_60Hz = 0x5, 3357 LSM6DSV16BX_XL_BATCHED_AT_120Hz = 0x6, 3358 LSM6DSV16BX_XL_BATCHED_AT_240Hz = 0x7, 3359 LSM6DSV16BX_XL_BATCHED_AT_480Hz = 0x8, 3360 LSM6DSV16BX_XL_BATCHED_AT_960Hz = 0x9, 3361 LSM6DSV16BX_XL_BATCHED_AT_1920Hz = 0xA, 3362 LSM6DSV16BX_XL_BATCHED_AT_3840Hz = 0xB, 3363 LSM6DSV16BX_XL_BATCHED_AT_7680Hz = 0xC, 3364 } lsm6dsv16bx_fifo_xl_batch_t; 3365 int32_t lsm6dsv16bx_fifo_xl_batch_set(stmdev_ctx_t *ctx, 3366 lsm6dsv16bx_fifo_xl_batch_t val); 3367 int32_t lsm6dsv16bx_fifo_xl_batch_get(stmdev_ctx_t *ctx, 3368 lsm6dsv16bx_fifo_xl_batch_t *val); 3369 3370 typedef enum 3371 { 3372 LSM6DSV16BX_GY_NOT_BATCHED = 0x0, 3373 LSM6DSV16BX_GY_BATCHED_AT_1Hz875 = 0x1, 3374 LSM6DSV16BX_GY_BATCHED_AT_7Hz5 = 0x2, 3375 LSM6DSV16BX_GY_BATCHED_AT_15Hz = 0x3, 3376 LSM6DSV16BX_GY_BATCHED_AT_30Hz = 0x4, 3377 LSM6DSV16BX_GY_BATCHED_AT_60Hz = 0x5, 3378 LSM6DSV16BX_GY_BATCHED_AT_120Hz = 0x6, 3379 LSM6DSV16BX_GY_BATCHED_AT_240Hz = 0x7, 3380 LSM6DSV16BX_GY_BATCHED_AT_480Hz = 0x8, 3381 LSM6DSV16BX_GY_BATCHED_AT_960Hz = 0x9, 3382 LSM6DSV16BX_GY_BATCHED_AT_1920Hz = 0xa, 3383 LSM6DSV16BX_GY_BATCHED_AT_3840Hz = 0xb, 3384 LSM6DSV16BX_GY_BATCHED_AT_7680Hz = 0xc, 3385 } lsm6dsv16bx_fifo_gy_batch_t; 3386 int32_t lsm6dsv16bx_fifo_gy_batch_set(stmdev_ctx_t *ctx, 3387 lsm6dsv16bx_fifo_gy_batch_t val); 3388 int32_t lsm6dsv16bx_fifo_gy_batch_get(stmdev_ctx_t *ctx, 3389 lsm6dsv16bx_fifo_gy_batch_t *val); 3390 3391 typedef enum 3392 { 3393 LSM6DSV16BX_BYPASS_MODE = 0x0, 3394 LSM6DSV16BX_FIFO_MODE = 0x1, 3395 LSM6DSV16BX_STREAM_WTM_TO_FULL_MODE = 0x2, 3396 LSM6DSV16BX_STREAM_TO_FIFO_MODE = 0x3, 3397 LSM6DSV16BX_BYPASS_TO_STREAM_MODE = 0x4, 3398 LSM6DSV16BX_STREAM_MODE = 0x6, 3399 LSM6DSV16BX_BYPASS_TO_FIFO_MODE = 0x7, 3400 } lsm6dsv16bx_fifo_mode_t; 3401 int32_t lsm6dsv16bx_fifo_mode_set(stmdev_ctx_t *ctx, 3402 lsm6dsv16bx_fifo_mode_t val); 3403 int32_t lsm6dsv16bx_fifo_mode_get(stmdev_ctx_t *ctx, 3404 lsm6dsv16bx_fifo_mode_t *val); 3405 3406 typedef enum 3407 { 3408 LSM6DSV16BX_TEMP_NOT_BATCHED = 0x0, 3409 LSM6DSV16BX_TEMP_BATCHED_AT_1Hz875 = 0x1, 3410 LSM6DSV16BX_TEMP_BATCHED_AT_15Hz = 0x2, 3411 LSM6DSV16BX_TEMP_BATCHED_AT_60Hz = 0x3, 3412 } lsm6dsv16bx_fifo_temp_batch_t; 3413 int32_t lsm6dsv16bx_fifo_temp_batch_set(stmdev_ctx_t *ctx, 3414 lsm6dsv16bx_fifo_temp_batch_t val); 3415 int32_t lsm6dsv16bx_fifo_temp_batch_get(stmdev_ctx_t *ctx, 3416 lsm6dsv16bx_fifo_temp_batch_t *val); 3417 3418 typedef enum 3419 { 3420 LSM6DSV16BX_TMSTMP_NOT_BATCHED = 0x0, 3421 LSM6DSV16BX_TMSTMP_DEC_1 = 0x1, 3422 LSM6DSV16BX_TMSTMP_DEC_8 = 0x2, 3423 LSM6DSV16BX_TMSTMP_DEC_32 = 0x3, 3424 } lsm6dsv16bx_fifo_timestamp_batch_t; 3425 int32_t lsm6dsv16bx_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, 3426 lsm6dsv16bx_fifo_timestamp_batch_t val); 3427 int32_t lsm6dsv16bx_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, 3428 lsm6dsv16bx_fifo_timestamp_batch_t *val); 3429 3430 int32_t lsm6dsv16bx_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, 3431 uint16_t val); 3432 int32_t lsm6dsv16bx_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, 3433 uint16_t *val); 3434 3435 int32_t lsm6dsv16bx_fifo_batch_ah_qvar_set(stmdev_ctx_t *ctx, uint8_t val); 3436 int32_t lsm6dsv16bx_fifo_batch_ah_qvar_get(stmdev_ctx_t *ctx, uint8_t *val); 3437 3438 typedef enum 3439 { 3440 LSM6DSV16BX_XL_BATCH_EVENT = 0x0, 3441 LSM6DSV16BX_GY_BATCH_EVENT = 0x1, 3442 LSM6DSV16BX_GY_EIS_BATCH_EVENT = 0x2, 3443 } lsm6dsv16bx_fifo_batch_cnt_event_t; 3444 int32_t lsm6dsv16bx_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, 3445 lsm6dsv16bx_fifo_batch_cnt_event_t val); 3446 int32_t lsm6dsv16bx_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, 3447 lsm6dsv16bx_fifo_batch_cnt_event_t *val); 3448 3449 typedef struct 3450 { 3451 uint8_t game_rotation : 1; 3452 uint8_t gravity : 1; 3453 uint8_t gbias : 1; 3454 } lsm6dsv16bx_fifo_sflp_raw_t; 3455 int32_t lsm6dsv16bx_fifo_sflp_batch_set(stmdev_ctx_t *ctx, 3456 lsm6dsv16bx_fifo_sflp_raw_t val); 3457 int32_t lsm6dsv16bx_fifo_sflp_batch_get(stmdev_ctx_t *ctx, 3458 lsm6dsv16bx_fifo_sflp_raw_t *val); 3459 3460 typedef struct 3461 { 3462 uint16_t fifo_level : 9; 3463 uint8_t fifo_bdr : 1; 3464 uint8_t fifo_full : 1; 3465 uint8_t fifo_ovr : 1; 3466 uint8_t fifo_th : 1; 3467 } lsm6dsv16bx_fifo_status_t; 3468 3469 int32_t lsm6dsv16bx_fifo_status_get(stmdev_ctx_t *ctx, 3470 lsm6dsv16bx_fifo_status_t *val); 3471 3472 typedef struct 3473 { 3474 enum 3475 { 3476 LSM6DSV16BX_FIFO_EMPTY = 0x0, 3477 LSM6DSV16BX_GY_NC_TAG = 0x1, 3478 LSM6DSV16BX_XL_NC_TAG = 0x2, 3479 LSM6DSV16BX_TEMPERATURE_TAG = 0x3, 3480 LSM6DSV16BX_TIMESTAMP_TAG = 0x4, 3481 LSM6DSV16BX_CFG_CHANGE_TAG = 0x5, 3482 LSM6DSV16BX_XL_NC_T_2_TAG = 0x6, 3483 LSM6DSV16BX_XL_NC_T_1_TAG = 0x7, 3484 LSM6DSV16BX_XL_2XC_TAG = 0x8, 3485 LSM6DSV16BX_XL_3XC_TAG = 0x9, 3486 LSM6DSV16BX_GY_NC_T_2_TAG = 0xA, 3487 LSM6DSV16BX_GY_NC_T_1_TAG = 0xB, 3488 LSM6DSV16BX_GY_2XC_TAG = 0xC, 3489 LSM6DSV16BX_GY_3XC_TAG = 0xD, 3490 LSM6DSV16BX_STEP_COUNTER_TAG = 0x12, 3491 LSM6DSV16BX_SFLP_GAME_ROTATION_VECTOR_TAG = 0x13, 3492 LSM6DSV16BX_SFLP_GYROSCOPE_BIAS_TAG = 0x16, 3493 LSM6DSV16BX_SFLP_GRAVITY_VECTOR_TAG = 0x17, 3494 LSM6DSV16BX_MLC_RESULT_TAG = 0x1A, 3495 LSM6DSV16BX_MLC_FILTER = 0x1B, 3496 LSM6DSV16BX_MLC_FEATURE = 0x1C, 3497 LSM6DSV16BX_XL_DUAL_CORE = 0x1D, 3498 LSM6DSV16BX_AH_QVAR = 0x1F, 3499 } tag; 3500 uint8_t cnt; 3501 uint8_t data[6]; 3502 } lsm6dsv16bx_fifo_out_raw_t; 3503 int32_t lsm6dsv16bx_fifo_out_raw_get(stmdev_ctx_t *ctx, 3504 lsm6dsv16bx_fifo_out_raw_t *val); 3505 3506 int32_t lsm6dsv16bx_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val); 3507 int32_t lsm6dsv16bx_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 3508 3509 int32_t lsm6dsv16bx_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val); 3510 int32_t lsm6dsv16bx_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 3511 3512 int32_t lsm6dsv16bx_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val); 3513 int32_t lsm6dsv16bx_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 3514 3515 typedef struct 3516 { 3517 uint8_t step_counter_enable : 1; 3518 uint8_t false_step_rej : 1; 3519 } lsm6dsv16bx_stpcnt_mode_t; 3520 int32_t lsm6dsv16bx_stpcnt_mode_set(stmdev_ctx_t *ctx, 3521 lsm6dsv16bx_stpcnt_mode_t val); 3522 int32_t lsm6dsv16bx_stpcnt_mode_get(stmdev_ctx_t *ctx, 3523 lsm6dsv16bx_stpcnt_mode_t *val); 3524 3525 int32_t lsm6dsv16bx_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val); 3526 3527 int32_t lsm6dsv16bx_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val); 3528 int32_t lsm6dsv16bx_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val); 3529 3530 int32_t lsm6dsv16bx_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val); 3531 int32_t lsm6dsv16bx_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val); 3532 3533 int32_t lsm6dsv16bx_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val); 3534 int32_t lsm6dsv16bx_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val); 3535 3536 int32_t lsm6dsv16bx_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val); 3537 int32_t lsm6dsv16bx_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 3538 3539 int32_t lsm6dsv16bx_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val); 3540 int32_t lsm6dsv16bx_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 3541 3542 int32_t lsm6dsv16bx_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint16_t val); 3543 int32_t lsm6dsv16bx_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint16_t *val); 3544 3545 typedef struct 3546 { 3547 float_t gbias_x; /* dps */ 3548 float_t gbias_y; /* dps */ 3549 float_t gbias_z; /* dps */ 3550 } lsm6dsv16bx_sflp_gbias_t; 3551 int32_t lsm6dsv16bx_sflp_game_gbias_set(stmdev_ctx_t *ctx, 3552 lsm6dsv16bx_sflp_gbias_t *val); 3553 3554 int32_t lsm6dsv16bx_sflp_configure(stmdev_ctx_t *ctx); 3555 3556 typedef enum 3557 { 3558 LSM6DSV16BX_SFLP_15Hz = 0x0, 3559 LSM6DSV16BX_SFLP_30Hz = 0x1, 3560 LSM6DSV16BX_SFLP_60Hz = 0x2, 3561 LSM6DSV16BX_SFLP_120Hz = 0x3, 3562 LSM6DSV16BX_SFLP_240Hz = 0x4, 3563 LSM6DSV16BX_SFLP_480Hz = 0x5, 3564 } lsm6dsv16bx_sflp_data_rate_t; 3565 int32_t lsm6dsv16bx_sflp_data_rate_set(stmdev_ctx_t *ctx, 3566 lsm6dsv16bx_sflp_data_rate_t val); 3567 int32_t lsm6dsv16bx_sflp_data_rate_get(stmdev_ctx_t *ctx, 3568 lsm6dsv16bx_sflp_data_rate_t *val); 3569 3570 typedef enum 3571 { 3572 LSM6DSV16BX_PROTECT_CTRL_REGS = 0x0, 3573 LSM6DSV16BX_WRITE_CTRL_REG = 0x1, 3574 } lsm6dsv16bx_fsm_permission_t; 3575 int32_t lsm6dsv16bx_fsm_permission_set(stmdev_ctx_t *ctx, 3576 lsm6dsv16bx_fsm_permission_t val); 3577 int32_t lsm6dsv16bx_fsm_permission_get(stmdev_ctx_t *ctx, 3578 lsm6dsv16bx_fsm_permission_t *val); 3579 int32_t lsm6dsv16bx_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val); 3580 3581 typedef enum 3582 { 3583 LSM6DSV16BX_STD_IF_CONTROL = 0x0, 3584 LSM6DSV16BX_FSM_CONTROL = 0x1, 3585 } lsm6dsv16bx_fsm_permission_status_t; 3586 int32_t lsm6dsv16bx_fsm_permission_status_get(stmdev_ctx_t *ctx, 3587 lsm6dsv16bx_fsm_permission_status_t *val); 3588 3589 typedef struct 3590 { 3591 uint8_t fsm1_en : 1; 3592 uint8_t fsm2_en : 1; 3593 uint8_t fsm3_en : 1; 3594 uint8_t fsm4_en : 1; 3595 uint8_t fsm5_en : 1; 3596 uint8_t fsm6_en : 1; 3597 uint8_t fsm7_en : 1; 3598 uint8_t fsm8_en : 1; 3599 } lsm6dsv16bx_fsm_mode_t; 3600 int32_t lsm6dsv16bx_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t val); 3601 int32_t lsm6dsv16bx_fsm_mode_get(stmdev_ctx_t *ctx, 3602 lsm6dsv16bx_fsm_mode_t *val); 3603 3604 int32_t lsm6dsv16bx_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); 3605 int32_t lsm6dsv16bx_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); 3606 3607 typedef struct 3608 { 3609 uint8_t fsm_outs1; 3610 uint8_t fsm_outs2; 3611 uint8_t fsm_outs3; 3612 uint8_t fsm_outs4; 3613 uint8_t fsm_outs5; 3614 uint8_t fsm_outs6; 3615 uint8_t fsm_outs7; 3616 uint8_t fsm_outs8; 3617 } lsm6dsv16bx_fsm_out_t; 3618 int32_t lsm6dsv16bx_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_out_t *val); 3619 3620 typedef enum 3621 { 3622 LSM6DSV16BX_FSM_15Hz = 0x0, 3623 LSM6DSV16BX_FSM_30Hz = 0x1, 3624 LSM6DSV16BX_FSM_60Hz = 0x2, 3625 LSM6DSV16BX_FSM_120Hz = 0x3, 3626 LSM6DSV16BX_FSM_240Hz = 0x4, 3627 LSM6DSV16BX_FSM_480Hz = 0x5, 3628 LSM6DSV16BX_FSM_960Hz = 0x6, 3629 } lsm6dsv16bx_fsm_data_rate_t; 3630 int32_t lsm6dsv16bx_fsm_data_rate_set(stmdev_ctx_t *ctx, 3631 lsm6dsv16bx_fsm_data_rate_t val); 3632 int32_t lsm6dsv16bx_fsm_data_rate_get(stmdev_ctx_t *ctx, 3633 lsm6dsv16bx_fsm_data_rate_t *val); 3634 3635 int32_t lsm6dsv16bx_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val); 3636 int32_t lsm6dsv16bx_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val); 3637 3638 int32_t lsm6dsv16bx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val); 3639 int32_t lsm6dsv16bx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val); 3640 3641 int32_t lsm6dsv16bx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val); 3642 int32_t lsm6dsv16bx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val); 3643 3644 typedef enum 3645 { 3646 LSM6DSV16BX_MLC_OFF = 0x0, 3647 LSM6DSV16BX_MLC_ON = 0x1, 3648 LSM6DSV16BX_MLC_ON_BEFORE_FSM = 0x2, 3649 } lsm6dsv16bx_mlc_mode_t; 3650 int32_t lsm6dsv16bx_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t val); 3651 int32_t lsm6dsv16bx_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t *val); 3652 3653 typedef enum 3654 { 3655 LSM6DSV16BX_MLC_15Hz = 0x0, 3656 LSM6DSV16BX_MLC_30Hz = 0x1, 3657 LSM6DSV16BX_MLC_60Hz = 0x2, 3658 LSM6DSV16BX_MLC_120Hz = 0x3, 3659 LSM6DSV16BX_MLC_240Hz = 0x4, 3660 LSM6DSV16BX_MLC_480Hz = 0x5, 3661 LSM6DSV16BX_MLC_960Hz = 0x6, 3662 } lsm6dsv16bx_mlc_data_rate_t; 3663 int32_t lsm6dsv16bx_mlc_data_rate_set(stmdev_ctx_t *ctx, 3664 lsm6dsv16bx_mlc_data_rate_t val); 3665 int32_t lsm6dsv16bx_mlc_data_rate_get(stmdev_ctx_t *ctx, 3666 lsm6dsv16bx_mlc_data_rate_t *val); 3667 3668 typedef struct 3669 { 3670 uint8_t mlc1_src; 3671 uint8_t mlc2_src; 3672 uint8_t mlc3_src; 3673 uint8_t mlc4_src; 3674 } lsm6dsv16bx_mlc_out_t; 3675 int32_t lsm6dsv16bx_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_out_t *val); 3676 3677 int32_t lsm6dsv16bx_mlc_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); 3678 int32_t lsm6dsv16bx_mlc_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); 3679 3680 int32_t lsm6dsv16bx_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val); 3681 int32_t lsm6dsv16bx_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val); 3682 3683 typedef struct 3684 { 3685 float_t z_mg; 3686 float_t y_mg; 3687 float_t x_mg; 3688 } lsm6dsv16bxxl_offset_mg_t; 3689 int32_t lsm6dsv16bx_xl_offset_mg_set(stmdev_ctx_t *ctx, 3690 lsm6dsv16bxxl_offset_mg_t val); 3691 int32_t lsm6dsv16bx_xl_offset_mg_get(stmdev_ctx_t *ctx, 3692 lsm6dsv16bxxl_offset_mg_t *val); 3693 3694 typedef struct 3695 { 3696 uint8_t ah_qvar1_en : 1; 3697 uint8_t ah_qvar2_en : 1; 3698 uint8_t swaps : 1; 3699 } lsm6dsv16bx_ah_qvar_mode_t; 3700 int32_t lsm6dsv16bx_ah_qvar_mode_set(stmdev_ctx_t *ctx, 3701 lsm6dsv16bx_ah_qvar_mode_t val); 3702 int32_t lsm6dsv16bx_ah_qvar_mode_get(stmdev_ctx_t *ctx, 3703 lsm6dsv16bx_ah_qvar_mode_t *val); 3704 3705 typedef enum 3706 { 3707 LSM6DSV16BX_2400MOhm = 0x0, 3708 LSM6DSV16BX_730MOhm = 0x1, 3709 LSM6DSV16BX_300MOhm = 0x2, 3710 LSM6DSV16BX_255MOhm = 0x3, 3711 } lsm6dsv16bx_ah_qvar_zin_t; 3712 int32_t lsm6dsv16bx_ah_qvar_zin_set(stmdev_ctx_t *ctx, 3713 lsm6dsv16bx_ah_qvar_zin_t val); 3714 int32_t lsm6dsv16bx_ah_qvar_zin_get(stmdev_ctx_t *ctx, 3715 lsm6dsv16bx_ah_qvar_zin_t *val); 3716 3717 int32_t lsm6dsv16bx_fsm_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); 3718 int32_t lsm6dsv16bx_fsm_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); 3719 3720 typedef enum 3721 { 3722 LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST = 0x0, 3723 LSM6DSV16BX_I3C_GLOBAL_RST = 0x1, 3724 } lsm6dsv16bx_i3c_reset_mode_t; 3725 int32_t lsm6dsv16bx_i3c_reset_mode_set(stmdev_ctx_t *ctx, 3726 lsm6dsv16bx_i3c_reset_mode_t val); 3727 int32_t lsm6dsv16bx_i3c_reset_mode_get(stmdev_ctx_t *ctx, 3728 lsm6dsv16bx_i3c_reset_mode_t *val); 3729 3730 int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); 3731 int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); 3732 3733 int32_t lsm6dsv16bx_tdm_tdmout_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); 3734 int32_t lsm6dsv16bx_tdm_tdmout_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); 3735 3736 typedef enum 3737 { 3738 LSM6DSV16BX_WCLK_16kHZ_BCLK_2048kHz = 0x1, 3739 LSM6DSV16BX_WCLK_8kHZ_BCLK_2048kHz = 0x4, 3740 } lsm6dsv16bx_tdm_wclk_bclk_t; 3741 int32_t lsm6dsv16bx_tdm_wclk_bclk_set(stmdev_ctx_t *ctx, 3742 lsm6dsv16bx_tdm_wclk_bclk_t val); 3743 int32_t lsm6dsv16bx_tdm_wclk_bclk_get(stmdev_ctx_t *ctx, 3744 lsm6dsv16bx_tdm_wclk_bclk_t *val); 3745 3746 typedef enum 3747 { 3748 LSM6DSV16BX_SLOT_012 = 0x0, 3749 LSM6DSV16BX_SLOT_456 = 0x1, 3750 } lsm6dsv16bx_tdm_slot_t; 3751 int32_t lsm6dsv16bx_tdm_slot_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t val); 3752 int32_t lsm6dsv16bx_tdm_slot_get(stmdev_ctx_t *ctx, 3753 lsm6dsv16bx_tdm_slot_t *val); 3754 3755 typedef enum 3756 { 3757 LSM6DSV16BX_BCLK_RISING = 0x0, 3758 LSM6DSV16BX_BCLK_FALLING = 0x1, 3759 } lsm6dsv16bx_tdm_bclk_edge_t; 3760 int32_t lsm6dsv16bx_tdm_bclk_edge_set(stmdev_ctx_t *ctx, 3761 lsm6dsv16bx_tdm_bclk_edge_t val); 3762 int32_t lsm6dsv16bx_tdm_bclk_edge_get(stmdev_ctx_t *ctx, 3763 lsm6dsv16bx_tdm_bclk_edge_t *val); 3764 3765 int32_t lsm6dsv16bx_tdm_delayed_conf_set(stmdev_ctx_t *ctx, uint8_t val); 3766 int32_t lsm6dsv16bx_tdm_delayed_conf_get(stmdev_ctx_t *ctx, uint8_t *val); 3767 3768 typedef enum 3769 { 3770 LSM6DSV16BX_TDM_ORDER_ZYX = 0x0, 3771 LSM6DSV16BX_TDM_ORDER_XZY = 0x1, 3772 LSM6DSV16BX_TDM_ORDER_XYZ = 0x2, 3773 } lsm6dsv16bx_tdm_axis_order_t; 3774 int32_t lsm6dsv16bx_tdm_axis_order_set(stmdev_ctx_t *ctx, 3775 lsm6dsv16bx_tdm_axis_order_t val); 3776 int32_t lsm6dsv16bx_tdm_axis_order_get(stmdev_ctx_t *ctx, 3777 lsm6dsv16bx_tdm_axis_order_t *val); 3778 3779 typedef enum 3780 { 3781 LSM6DSV16BX_TDM_2g = 0x0, 3782 LSM6DSV16BX_TDM_4g = 0x1, 3783 LSM6DSV16BX_TDM_8g = 0x2, 3784 } lsm6dsv16bx_tdm_xl_full_scale_t; 3785 int32_t lsm6dsv16bx_tdm_xl_full_scale_set(stmdev_ctx_t *ctx, 3786 lsm6dsv16bx_tdm_xl_full_scale_t val); 3787 int32_t lsm6dsv16bx_tdm_xl_full_scale_get(stmdev_ctx_t *ctx, 3788 lsm6dsv16bx_tdm_xl_full_scale_t *val); 3789 3790 /** 3791 * @} 3792 * 3793 */ 3794 3795 #ifdef __cplusplus 3796 } 3797 #endif 3798 3799 #endif /*LSM6DSV16BX_DRIVER_H */ 3800 3801 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3802
