1 /***************************************************************************/ /** 2 * @file rsi_egpio.h 3 ******************************************************************************* 4 * # License 5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b> 6 ******************************************************************************* 7 * 8 * SPDX-License-Identifier: Zlib 9 * 10 * The licensor of this software is Silicon Laboratories Inc. 11 * 12 * This software is provided 'as-is', without any express or implied 13 * warranty. In no event will the authors be held liable for any damages 14 * arising from the use of this software. 15 * 16 * Permission is granted to anyone to use this software for any purpose, 17 * including commercial applications, and to alter it and redistribute it 18 * freely, subject to the following restrictions: 19 * 20 * 1. The origin of this software must not be misrepresented; you must not 21 * claim that you wrote the original software. If you use this software 22 * in a product, an acknowledgment in the product documentation would be 23 * appreciated but is not required. 24 * 2. Altered source versions must be plainly marked as such, and must not be 25 * misrepresented as being the original software. 26 * 3. This notice may not be removed or altered from any source distribution. 27 * 28 ******************************************************************************/ 29 30 // Includes Files 31 32 #include "rsi_ccp_common.h" 33 #include "base_types.h" 34 35 #ifndef RSI_EGPIO_H 36 #define RSI_EGPIO_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 // EGPIO numbers 43 #define GPIO0 0 // EGPIO number 0 44 #define GPIO1 1 // EGPIO number 1 45 #define GPIO2 2 // EGPIO number 2 46 #define GPIO3 3 // EGPIO number 3 47 #define GPIO4 4 // EGPIO number 4 48 #define GPIO5 5 // EGPIO number 5 49 #define GPIO6 6 // EGPIO number 6 50 #define GPIO7 7 // EGPIO number 7 51 #define GPIO8 8 // EGPIO number 8 52 #define GPIO9 9 // EGPIO number 9 53 #define GPIO10 10 // EGPIO number 10 54 #define GPIO11 11 // EGPIO number 11 55 #define GPIO12 12 // EGPIO number 12 56 #define GPIO13 13 // EGPIO number 13 57 #define GPIO14 14 // EGPIO number 14 58 #define GPIO15 15 // EGPIO number 14 59 60 // EGPIO Ports(NOTE : Each ports consists of 16 GPIO pins numbered from (0 - 15)) 61 #define EGPIO_PORT0 0 // EGPIO port number 0 62 #define EGPIO_PORT1 1 // EGPIO port number 1 63 #define EGPIO_PORT2 2 // EGPIO port number 2 64 65 // EGPIO PIN INTERRUPTS 66 // NOTE : Total 8 pin interrupts are supported , these interrupts can be mapped to any of the GPIO ports 67 #define EGPIO_PIN_INTERRUPT0 0 // Select interrupt channel 0 68 #define EGPIO_PIN_INTERRUPT1 1 // Select interrupt channel 1 69 #define EGPIO_PIN_INTERRUPT2 2 // Select interrupt channel 2 70 #define EGPIO_PIN_INTERRUPT3 3 // Select interrupt channel 3 71 #define EGPIO_PIN_INTERRUPT4 4 // Select interrupt channel 4 72 #define EGPIO_PIN_INTERRUPT5 5 // Select interrupt channel 5 73 #define EGPIO_PIN_INTERRUPT6 6 // Select interrupt channel 6 74 #define EGPIO_PIN_INTERRUPT7 7 // Select interrupt channel 7 75 76 // EGPIO GROUP INTERUPTS 77 // NOTE : Total 2 group interrupts are supported 78 #define EGPIO_GROUP_INTERRUPT0 0 // Select EGPIO Group interrupt channel 0 79 #define EGPIO_GROUP_INTERRUPT1 1 // Select EGPIO Group interrupt channel 1 80 81 // Pin multiplexing 82 // NOTE : Each GPIO supports up to 8 multiplexing functions those can be selected by passing following macros into the pin mux function 83 #define EGPIO_PIN_MUX_MODE0 0U // Select pin mode 0 84 #define EGPIO_PIN_MUX_MODE1 1U // Select pin mode 1 85 #define EGPIO_PIN_MUX_MODE2 2U // Select pin mode 2 86 #define EGPIO_PIN_MUX_MODE3 3U // Select pin mode 3 87 #define EGPIO_PIN_MUX_MODE4 4U // Select pin mode 4 88 #define EGPIO_PIN_MUX_MODE5 5U // Select pin mode 5 89 #define EGPIO_PIN_MUX_MODE6 6U // Select pin mode 6 90 #define EGPIO_PIN_MUX_MODE7 7U // Select pin mode 7 91 #define EGPIO_PIN_MUX_MODE8 8U // Select pin mode 8 92 #define EGPIO_PIN_MUX_MODE9 9U // Select pin mode 9 93 #define EGPIO_PIN_MUX_MODE10 10U // Select pin mode 10 94 #define EGPIO_PIN_MUX_MODE11 11U // Select pin mode 11 95 #define EGPIO_PIN_MUX_MODE12 12U // Select pin function 12 96 #define EGPIO_PIN_MUX_MODE13 13U // Select pin function 13 97 #define EGPIO_PIN_MUX_MODE14 14U // Select pin function 14 98 #define EGPIO_PIN_MUX_MODE15 15U // Select pin function 15 99 100 // interrupt clear flags 101 #define EGPIO_PIN_INT_CLR_FALLING BIT(2) // Falling edge interrupt clear 102 #define EGPIO_PIN_INT_CLR_RISING BIT(1) // Raising edge interrupt clear 103 #define INTERRUPT_STATUS_CLR BIT(0) // interrupts are cleared 104 #define WAKEUP_INTERRUPT BIT(1) 105 106 // GPIO directions 107 #define EGPIO_CONFIG_DIR_INPUT 1U // Configure EGPIO as input mode 108 #define EGPIO_CONFIG_DIR_OUTPUT 0U // Configure EGPIO as output mode 109 #define NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR (0x41300000 + 0x004) 110 111 // MISC host 112 #define MISC_HOST (*(volatile uint32_t *)(0x46008000 + 0x0C)) 113 114 // m4 PAD configuration defines 115 116 #define PAD_CONFIG_REG(x) (*(volatile uint32_t *)(0x46004000 + 4 * x)) // REN enable bit(this should be enable) 117 #define PADSELECTION \ 118 (*(volatile uint32_t *)(0x41300000 + 0x610)) // PAD selection (0 t0 21) A value of 1 on this gives control to M4SS 119 120 #if defined(SLI_SI917) || defined(SLI_SI915) 121 #define PADSELECTION_1 \ 122 (*(volatile uint32_t *)(0x41300000 + 0x618)) // PAD selection (22 to 33) A value of 1 on this gives control to M4SS 123 #endif 124 #define SDIO_CNTD_TO_TASS \ 125 (*(volatile uint32_t *)NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR) // sdio connected to tass (0 for M4SS and 1 for TASS) 126 127 // Ulp pad configuration defines 128 #define ULP_PAD_CONFIG_REG_0 (*(volatile uint32_t *)(0x2404A000 + 0x0)) 129 #define ULP_PAD_CONFIG_REG_1 (*(volatile uint32_t *)(0x2404A000 + 0x4)) 130 #define ULP_PAD_CONFIG_REG_2 (*(volatile uint32_t *)(0x2404A000 + 0x8)) 131 132 // ulp_socgpio_n_mode 133 #define ULP_SOC_GPIO_MODE(x) (*(volatile uint32_t *)(0x24041400 + 4 * x)) // x= 0 to 15 134 135 // MISC host 136 137 #define HOST_PADS_GPIO_MODE (*(volatile uint32_t *)(0x46008000 + 0x44)) 138 139 // Ulp Ren enable 140 #define CLOCK_ENABLE (*(uint32_t *)(0x24041400 + 0x00)) 141 142 typedef enum en_driver_state { 143 HiZ = 0, // 0 for HiZ (P1=0,P2=0) 144 Pullup = 1, // 1 for Pullup (P1=0,P2=1) 145 Pulldown = 2, // 2 for Pulldown (P1=1,P2=0) 146 Repeater = 3 // 3 for Repeater (P1=1,P2=1) 147 } en_driver_state_t; 148 typedef enum en_driver_strength_select { 149 two_milli_amps = 0, // 0 for two_milli_amps (E1=0,E2=0) 150 four_milli_amps = 1, // 1 for four_milli_amps (E1=0,E2=1) 151 eight_milli_amps = 2, // 2 for eight_milli_amps (E1=1,E2=0) 152 twelve_milli_amps = 3 // 3 for twelve_milli_amps(E1=1,E2=1) 153 } en_driver_strength_select_t; 154 155 #define DDS_MASK 0xC0 // driver disabled state 156 #define DSS_MASK 0x3 // driver strength select 157 #define POS_MASK 0x4 // power on start 158 #define ST_MASK 0x8 // active high schmitt trigger 159 #define RE_MASK 0x10 // receiver enable 160 #define SR_MASK 0x20 // slew rate 161 162 #define ULP_DDS_MASK_SET_1_AND_3 0xC0 // driver disabled state 163 #define ULP_DDS_MASK_SET_2_AND_4 0xC000 // driver disabled state 164 #define ULP_DSS_MASK_SET_1_AND_3 0x3 // driver strength select 165 #define ULP_DSS_MASK_SET_2_AND_4 0x300 // driver strength select 166 #define ULP_POS_MASK_SET_1_AND_3 0x4 // power on start 167 #define ULP_POS_MASK_SET_2_AND_4 0x400 // power on start 168 #define ULP_ST_MASK_SET_1_AND_3 0x8 // active high schmitt trigger 169 #define ULP_ST_MASK_SET_2_AND_4 0x800 // active high schmitt trigger 170 #define ULP_SR_MASK_SET_1_AND_3 0x20 // slew rate 171 #define ULP_SR_MASK_SET_2_AND_4 0x2000 // slew rate 172 173 typedef enum en_ulp_driver_disable_state { 174 ulp_HiZ = 0, // 0 for HiZ (P1=0,P2=0) 175 ulp_Pullup = 1, // 1 for Pullup (P1=0,P2=1) 176 ulp_Pulldown = 2, // 2 for Pulldown (P1=1,P2=0) 177 ulp_Repeater = 3 // 3 for Repeater (P1=1,P2=1) 178 } en_ulp_driver_disable_state_t; 179 typedef enum en_ulp_driver_strength_select { 180 ulp_two_milli_amps = 0, // 0 for two_milli_amps (E1=0,E2=0) 181 ulp_four_milli_amps = 1, // 1 for four_milli_amps (E1=0,E2=1) 182 ulp_eight_milli_amps = 2, // 2 for eight_milli_amps (E1=1,E2=0) 183 ulp_twelve_milli_amps = 3 // 3 for twelve_milli_amps(E1=1,E2=1) 184 } en_ulp_driver_strength_select_t; 185 186 void egpio_set_dir(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, boolean_t dir); 187 188 void egpio_set_pin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t val); 189 190 boolean_t egpio_get_pin(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 191 192 boolean_t egpio_get_dir(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 193 194 void egpio_pin_int_sel(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t port, uint8_t pin); 195 196 void egpio_set_int_fall_edge_enable(EGPIO_Type *pEGPIO, uint8_t intCh); 197 198 void egpio_set_int_fall_edge_disable(EGPIO_Type *pEGPIO, uint8_t intCh); 199 200 void egpio_set_int_rise_edge_enable(EGPIO_Type *pEGPIO, uint8_t intCh); 201 202 void egpio_set_int_rise_edge_disable(EGPIO_Type *pEGPIO, uint8_t intCh); 203 204 void egpio_set_int_low_level_enable(EGPIO_Type *pEGPIO, uint8_t intCh); 205 206 void egpio_int_mask(EGPIO_Type *pEGPIO, uint8_t intCh); 207 208 void egpio_int_un_mask(EGPIO_Type *pEGPIO, uint8_t intCh); 209 210 void egpio_set_int_low_level_disable(EGPIO_Type *pEGPIO, uint8_t intCh); 211 212 void egpio_set_int_high_level_enable(EGPIO_Type *pEGPIO, uint8_t intCh); 213 214 void egpio_set_int_high_level_disable(EGPIO_Type *pEGPIO, uint8_t intCh); 215 216 uint8_t egpio_get_int_stat(const EGPIO_Type *pEGPIO, uint8_t intCh); 217 218 void egpio_int_clr(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t flags); 219 220 void egpio_set_pin_mux(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t u8Mux); 221 222 void egpio_ulp_soc_gpio_mode(ULPCLK_Type *pULPCLK, uint8_t gpio, uint8_t mode); 223 224 void egpio_set_port_mask(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 225 226 void egpio_set_port_un_mask(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 227 228 void egpio_port_masked_load(EGPIO_Type *pEGPIO, uint8_t port, uint16_t u16Val); 229 230 void egpio_set_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); 231 232 void egpio_port_load(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); 233 234 void egpio_word_load(EGPIO_Type *pEGPIO, uint8_t pin, uint16_t val); 235 236 void egpio_clr_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); 237 238 void egpio_toggle_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); 239 240 uint16_t egpio_get_port(const EGPIO_Type *pEGPIO, uint8_t port); 241 242 void egpio_group_int_one_enable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 243 244 void egpio_group_int_one_disable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 245 246 void egpio_group_int_two_enable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 247 248 void egpio_group_int_mask(EGPIO_Type *pEGPIO, uint8_t grpInt); 249 250 void egpio_group_int_un_Mask(EGPIO_Type *pEGPIO, uint8_t grpInt); 251 252 void egpio_group_int_enable(EGPIO_Type *pEGPIO, uint8_t grpInt); 253 254 void egpio_group_int_disable(EGPIO_Type *pEGPIO, uint8_t grpInt); 255 256 void egpio_group_int_level(EGPIO_Type *pEGPIO, uint8_t grpInt); 257 258 void egpio_group_int_edge(EGPIO_Type *pEGPIO, uint8_t grpInt); 259 260 void egpio_group_int_and(EGPIO_Type *pEGPIO, uint8_t grpInt); 261 262 void egpio_group_int_or(EGPIO_Type *pEGPIO, uint8_t grpInt); 263 264 uint32_t egpio_group_int_stat(const EGPIO_Type *pEGPIO, uint8_t grpInt); 265 266 void egpio_group_int_wkeup_Enable(EGPIO_Type *pEGPIO, uint8_t grpInt); 267 268 void egpio_group_int_wkeup_disable(EGPIO_Type *pEGPIO, uint8_t grpInt); 269 270 void egpio_group_int_clr(EGPIO_Type *pEGPIO, uint8_t grpInt, uint8_t u8ClrFlags); 271 272 void egpio_group_int_two_disable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 273 274 void egpio_set_group_int_one_pol(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol); 275 276 void egpio_set_group_int_two_pol(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol); 277 278 void egpio_host_pads_gpio_mode_enable(uint8_t u8GpioNum); 279 280 void egpio_host_pads_gpio_mode_disable(uint8_t u8GpioNum); 281 282 void egpio_pad_selection_enable(uint8_t padNum); 283 284 void egpio_pad_selection_disable(uint8_t padNum); 285 286 void egpio_pad_receiver_enable(uint8_t u8GpioNum); 287 288 void egpio_pad_receiver_disable(uint8_t u8GpioNum); 289 290 void egpio_pad_sdio_connected(void); 291 292 void egpio_pad_driver_disable_state(uint8_t u8GpioNum, en_driver_state_t endstate); 293 294 void egpio_pad_driver_strength_select(uint8_t u8GpioNum, en_driver_strength_select_t strength); 295 296 void egpio_pad_power_on_start_enable(uint8_t u8GpioNum, uint8_t val); 297 298 void egpio_pad_active_high_schmitt_trigger(uint8_t u8GpioNum, uint8_t val); 299 300 void egpio_pad_slew_rate_controll(uint8_t u8GpioNum, uint8_t val); 301 302 void egpio_ulp_pad_receiver_enable(uint8_t gpio); 303 304 void egpio_ulp_pad_receiver_disable(uint8_t u8GpioNum); 305 306 void egpio_ulp_pad_driver_disable_state(uint8_t u8GpioNum, en_ulp_driver_disable_state_t disablestate); 307 308 void egpio_ulp_pad_driver_strength_select(uint8_t u8GpioNum, en_ulp_driver_strength_select_t strength); 309 310 void egpio_ulp_pad_power_on_start_enable(uint8_t u8GpioNum, uint8_t val); 311 312 void egpio_ulp_pad_active_high_schmitt_trigger(uint8_t u8GpioNum, uint8_t val); 313 314 void egpio_ulp_pad_slew_rate_controll(uint8_t u8GpioNum, uint8_t val); 315 316 #ifdef __cplusplus 317 } 318 #endif 319 320 #endif // RSI_EGPIO_H 321
