Searched refs:reg_read (Results 1 – 2 of 2) sorted by relevance
2730 uint32_t reg_read = 0; in clk_config_pll_ref_clk() local2731 reg_read = SPI_MEM_MAP_PLL(SOCPLLMACROREG2); in clk_config_pll_ref_clk()2732 reg_read &= ~((uint16_t)(0x3 << 14)); in clk_config_pll_ref_clk()2733 reg_read |= (ref_clk_src << 14U); in clk_config_pll_ref_clk()2734 SPI_MEM_MAP_PLL(SOCPLLMACROREG2) = (uint16_t)reg_read; in clk_config_pll_ref_clk()2752 uint32_t reg_read = 0; in clk_config_pll_lock() local2753 reg_read = SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9); in clk_config_pll_lock()2754 reg_read &= ~((0xFF << 6) | BIT(15) | BIT(14)); in clk_config_pll_lock()2755 …reg_read |= (uint32_t)((manual_lock << 15U) | (bypass_manual_lock << 14U) | (mm_count_limit << 6U)… in clk_config_pll_lock()2756 SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9) = (uint16_t)reg_read; in clk_config_pll_lock()
1479 volatile uint32_t reg_read = 0; in RSI_Clks_Trim32MHzRC() local1499 reg_read = ULP_SPI_MEM_MAP(ULPCLKS_MRC_CLK_REG_OFFSET); in RSI_Clks_Trim32MHzRC()1501 reg_read &= (uint32_t)(~(0x7F << TRIM_LSB_MHZ)); in RSI_Clks_Trim32MHzRC()1502 ULP_SPI_MEM_MAP(ULPCLKS_MRC_CLK_REG_OFFSET) = reg_read; in RSI_Clks_Trim32MHzRC()
