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/hal_silabs-latest/scripts/
Dgen_clock_control.py67 if m := re.match(r"#define (_CMU_CLKEN.*_SHIFT)\s+(\d+)", line):
75 if m := re.match(r".*uint32_t SL_BUS_(.*)_VALUE = \(([^\s]+).*(_CMU[^\s]+SHIFT)", line):
Dgen_acmp.py51 …if m := re.match(r"#define (_ACMP_INPUTCTRL_POSSEL_(?!SHIFT)(?!MASK)(?!DEFAULT).*)\s+(\dx[\dABCDEF…
60 …if m := re.match(r"#define (_ACMP_INPUTCTRL_NEGSEL_(?!SHIFT)(?!MASK)(?!DEFAULT).*)\s+(\dx[\dABCDEF…
Dgen_adc.py120 if m := re.match(r"#define _IADC_SINGLE_PORT(POS|NEG)_([^\s]+)\s+(0x[0-9A-F]*)UL", line):
Dimport_simplicity_sdk.py107 sha = re.search(r"sha256:([0-9a-f]{64})\s", lfs).group(1)
Dgen_pinctrl.py328 …if m := re.match(r"#define _GPIO_([A-Z])[A-Z]?BUSALLOC_([A-Z]+(EVEN\d|ODD\d))_([^\s]+)\s+0x(.+)UL"…
/hal_silabs-latest/simplicity_sdk/platform/security/sl_component/se_manager/src/
Dsl_se_manager_key_derivation.c472 sli_se_datatransfer_t r_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->r, 32); in sl_se_ecjpake_derive_secret()
768 sli_se_datatransfer_t r_out = SLI_SE_DATATRANSFER_DEFAULT(ctx->r, 32); in sl_se_ecjpake_write_round_one()
848 sli_se_datatransfer_t r_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->r, 32); in sl_se_ecjpake_write_round_two()
/hal_silabs-latest/simplicity_sdk/platform/security/sl_component/se_manager/inc/
Dsl_se_manager_types.h470 uint8_t r[32]; ///< Random scalar for exchange member