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Searched refs:pCLK (Results 1 – 8 of 8) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_pll.c96 rsi_error_t clk_set_soc_pll_freq(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) in clk_set_soc_pll_freq() argument
109 …if ((pCLK == NULL) || (socPllFreq < SOC_PLL_MIN_FREQUECY) || (socPllFreq > SOC_PLL_MAX_FREQUECY)) { in clk_set_soc_pll_freq()
120 clk_soc_pll_set_freq_div(pCLK, 1, 0, 39, 199, 0, 1, 1); in clk_set_soc_pll_freq()
168 clk_soc_pll_clk_set(pCLK); /* wait for lock */ in clk_set_soc_pll_freq()
181 clk_soc_pll_set_freq_div(pCLK, 1, 0, 39, 199, 0, 1, 1); in clk_set_soc_pll_freq()
267 clk_soc_pll_clk_set(pCLK); in clk_set_soc_pll_freq()
294 rsi_error_t clk_soc_pll_set_freq_div(const M4CLK_Type *pCLK, in clk_soc_pll_set_freq_div() argument
307 if (pCLK == NULL) { in clk_soc_pll_set_freq_div()
335 clk_soc_pll_clk_set(pCLK); in clk_soc_pll_set_freq_div()
375 clk_soc_pll_clk_set(pCLK); in clk_soc_pll_set_freq_div()
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Drsi_ulpss_clk.c49 rsi_error_t ulpss_clock_config(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t… in ulpss_clock_config() argument
51 if (pCLK == NULL) { in ulpss_clock_config()
55 pCLK->CLK_CONFIG_REG4_b.ULPSS_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); in ulpss_clock_config()
56 pCLK->CLK_CONFIG_REG5_b.ULPSS_ODD_DIV_SEL = (unsigned int)(oddDivFactor & 0x01); in ulpss_clock_config()
57 pCLK->CLK_ENABLE_SET_REG1 = ULPSS_CLK_ENABLE; in ulpss_clock_config()
59 pCLK->CLK_ENABLE_CLEAR_REG1 = ULPSS_CLK_ENABLE; in ulpss_clock_config()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/
Drsi_rom_clks.h135 STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32… in RSI_CLK_SetSocPllFreq() argument
153 ret = ROMAPI_M4SS_CLK_API->clk_set_soc_pll_freq(pCLK, socPllFreq, pllRefClk); in RSI_CLK_SetSocPllFreq()
156 ret = clk_set_soc_pll_freq(pCLK, socPllFreq, pllRefClk); in RSI_CLK_SetSocPllFreq()
197 STATIC INLINE rsi_error_t RSI_CLK_SocPllSetFreqDiv(const M4CLK_Type *pCLK, in RSI_CLK_SocPllSetFreqDiv() argument
208 ->clk_soc_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fCwf, dcofixsel, ldoprog); in RSI_CLK_SocPllSetFreqDiv()
210 …return clk_soc_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fCwf, dcofixsel, ldopro… in RSI_CLK_SocPllSetFreqDiv()
220 STATIC INLINE rsi_error_t RSI_CLK_SocPllClkSet(const M4CLK_Type *pCLK) in RSI_CLK_SocPllClkSet() argument
223 return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_set(pCLK); in RSI_CLK_SocPllClkSet()
225 return clk_soc_pll_clk_set(pCLK); in RSI_CLK_SocPllClkSet()
376 STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32… in RSI_CLK_SetI2sPllFreq() argument
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Drsi_rom_table_si91x.h774 …rsi_error_t (*ulpss_clock_config)(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boole…
826 …rsi_error_t (*clk_set_soc_pll_freq)(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefCl…
827 rsi_error_t (*clk_soc_pll_set_freq_div)(const M4CLK_Type *pCLK,
835 rsi_error_t (*clk_soc_pll_clk_set)(const M4CLK_Type *pCLK);
846 rsi_error_t (*clk_set_i2s_pll_freq)(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal);
847 rsi_error_t (*clk_i2s_pll_set_freq_div)(const M4CLK_Type *pCLK,
853 rsi_error_t (*clk_i2s_pll_clk_set)(const M4CLK_Type *pCLK);
858 …rsi_error_t (*clk_set_intf_pll_freq)(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRef…
859 rsi_error_t (*clk_intf_pll_set_freq_div)(const M4CLK_Type *pCLK,
870 rsi_error_t (*clk_intf_pll_clk_set)(const M4CLK_Type *pCLK);
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Drsi_rom_ulpss_clk.h99 STATIC INLINE rsi_error_t RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK, in RSI_ULPSS_ClockConfig() argument
105 return ROMAPI_ULPSS_CLK_API->ulpss_clock_config(pCLK, clkEnable, divFactor, oddDivFactor); in RSI_ULPSS_ClockConfig()
107 return ulpss_clock_config(pCLK, clkEnable, divFactor, oddDivFactor); in RSI_ULPSS_ClockConfig()
629 rsi_error_t RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolea…
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/
Drsi_pll.h660 rsi_error_t clk_i2s_pll_clk_set(const M4CLK_Type *pCLK);
666 rsi_error_t clk_soc_pll_set_freq_div(const M4CLK_Type *pCLK,
675 rsi_error_t clk_soc_pll_clk_set(const M4CLK_Type *pCLK);
697 rsi_error_t clk_i2s_pll_set_freq_div(const M4CLK_Type *pCLK,
706 rsi_error_t clk_i2s_pll_clk_set(const M4CLK_Type *pCLK);
714 rsi_error_t clk_intf_pll_set_freq_div(const M4CLK_Type *pCLK,
729 rsi_error_t clk_intf_pll_clk_set(const M4CLK_Type *pCLK);
731 rsi_error_t clk_peripheral_clk_enable1(M4CLK_Type *pCLK, uint32_t flags);
733 rsi_error_t clk_peripheral_clk_disable1(M4CLK_Type *pCLK, uint32_t flags);
735 rsi_error_t clk_peripheral_clk_enable2(M4CLK_Type *pCLK, uint32_t flags);
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Drsi_ulpss_clk.h308 rsi_error_t ulpss_clock_config(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t…
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/
Dsl_si91x_clock_manager.c76 M4CLK_Type *pCLK = M4CLK; in sl_si91x_clock_manager_init() local
104 …ROMAPI_M4SS_CLK_API->clk_qspi_clk_config(pCLK, QSPI_INTFPLLCLK, QSPI_SWALLO_EN, QSPI_ODD_DIV_EN, Q… in sl_si91x_clock_manager_init()
110 …ROMAPI_M4SS_CLK_API->clk_qspi_2_clk_config(pCLK, QSPI_INTFPLLCLK, QSPI_SWALLO_EN, QSPI_ODD_DIV_EN,… in sl_si91x_clock_manager_init()
132 M4CLK_Type *pCLK = M4CLK; in sl_si91x_clock_manager_m4_set_core_clk() local
151 error_status = RSI_CLK_M4SocClkConfig(pCLK, M4_ULPREFCLK, 0); in sl_si91x_clock_manager_m4_set_core_clk()
177 error_status = RSI_CLK_M4SocClkConfig(pCLK, clk_source, div_factor); in sl_si91x_clock_manager_m4_set_core_clk()
202 M4CLK_Type *pCLK = M4CLK; in sl_si91x_clock_manager_set_pll_freq() local
217 error_status = RSI_CLK_SetSocPllFreq(pCLK, pll_freq, pll_ref_clk); in sl_si91x_clock_manager_set_pll_freq()
222 error_status = RSI_CLK_SetIntfPllFreq(pCLK, pll_freq, pll_ref_clk); in sl_si91x_clock_manager_set_pll_freq()
227 error_status = RSI_CLK_SetI2sPllFreq(pCLK, pll_freq, pll_ref_clk); in sl_si91x_clock_manager_set_pll_freq()
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