1 /*******************************************************************************
2 * @file  rsi_reg_spi.h
3  *******************************************************************************
4  * # License
5  * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6  *******************************************************************************
7  *
8  * SPDX-License-Identifier: Zlib
9  *
10  * The licensor of this software is Silicon Laboratories Inc.
11  *
12  * This software is provided 'as-is', without any express or implied
13  * warranty. In no event will the authors be held liable for any damages
14  * arising from the use of this software.
15  *
16  * Permission is granted to anyone to use this software for any purpose,
17  * including commercial applications, and to alter it and redistribute it
18  * freely, subject to the following restrictions:
19  *
20  * 1. The origin of this software must not be misrepresented; you must not
21  *    claim that you wrote the original software. If you use this software
22  *    in a product, an acknowledgment in the product documentation would be
23  *    appreciated but is not required.
24  * 2. Altered source versions must be plainly marked as such, and must not be
25  *    misrepresented as being the original software.
26  * 3. This notice may not be removed or altered from any source distribution.
27  *
28  ******************************************************************************/
29 
30 /**
31  * Includes
32  */
33 #ifndef __RSI_REG_SPI_H__
34 #define __RSI_REG_SPI_H__
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 /**
40  * \cond HIDDEN_SYMBOLS
41  */
42 
43 #define REG_SPI_BASE_ADDR_ULP              0x24050000
44 #define REG_SPI_BASE_ADDR_PLL              0x46180000
45 #define TASS_AFE_REG_ACC_MEM_MAP_BASE_ADDR 0x41138000
46 
47 #include "rsi_ccp_common.h"
48 
49 /*Register memory mapped reg read write*/
50 
51 /*REG ADDRESS : Address of a target register ULP*/
52 #define ULP_SPI_MEM_MAP(REG_ADR) (*((uint32_t volatile *)(REG_SPI_BASE_ADDR_ULP + (0xa000 + (REG_ADR * 4)))))
53 
54 /*REG ADDRESS : Address of a target register PMU*/
55 #define PMU_SPI_MEM_MAP(REG_ADR) (*((uint32_t volatile *)(REG_SPI_BASE_ADDR_ULP + (0x00008000 + (REG_ADR * 4)))))
56 
57 /*Memory mapped SPI for M4 PLL configuration */
58 #define SPI_MEM_MAP_PLL(REG_ADR) (*((uint16_t volatile *)(REG_SPI_BASE_ADDR_PLL + 0x00008000 + (REG_ADR << 2))))
59 
60 /*Memory mapped SPI for  PLL_480 configuration */
61 #define TASS_PLL_CTRL_SET_REG(REG_ADR) (*((uint16_t volatile *)(TASS_AFE_REG_ACC_MEM_MAP_BASE_ADDR + (REG_ADR << 2))))
62 
63 /*Configuration parameters*/
64 #define GSPI_RF_N_ULP   BIT(12)
65 #define GSPI_ACTIVE     BIT(8)
66 #define GSPI_TRIG       BIT(7)
67 #define GSPI_READ       BIT(6)
68 #define GSPI_DATA_FIFO  GSPI_DATA_REG0
69 #define READ_INDICATION BIT(15)
70 #define ADDR_DATA_LEN   31
71 
72 /*GSPI Configuration*/
73 typedef struct stc_reg_spi_config {
74   uint16_t u16GspiClockRatio;
75   uint16_t u16GspiCsbSetupTime;
76   uint16_t u16GspiCsbHoldTime;
77   uint16_t u16GspiCsbHighTime;
78   boolean_t bGspiSpiMode;
79   boolean_t bGspiClockPhase;
80   boolean_t bGspiAfeIpmun;
81   boolean_t bDmaMode;
82   boolean_t bDma32_48Bitn;
83 } stc_reg_spi_config_t;
84 
85 /*Target selection*/
86 typedef enum en_select_target { PmuBlock = 0, UlpBlock = 1 } en_select_target_t;
87 
88 /*Base address assignment */
89 #define REG_SPI_ULP (*((REG_SPI_Type_T *)REG_SPI_BASE_ADDR_ULP)) /*Memory map for ULPSS Reg access SPI*/
90 #define REG_SPI_PLL (*((REG_SPI_Type_T *)REG_SPI_BASE_ADDR_PLL)) /*Memory map for ULPSS Reg access SPI*/
91 
92 /**
93  * \endcond
94  */
95 
96 #ifdef __cplusplus
97 }
98 #endif
99 
100 #endif /*__RSI_REG_SPI_H__*/
101