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Searched refs:divFactor (Results 1 – 7 of 7) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/
Drsi_rom_clks.h199 uint16_t divFactor, in RSI_CLK_SocPllSetFreqDiv() argument
208 ->clk_soc_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fCwf, dcofixsel, ldoprog); in RSI_CLK_SocPllSetFreqDiv()
210 …return clk_soc_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fCwf, dcofixsel, ldopro… in RSI_CLK_SocPllSetFreqDiv()
578 uint16_t divFactor, in RSI_CLK_IntfPllSetFreqDiv() argument
587 … ->clk_intf_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fcwF, dcoFixSel, ldoProg); in RSI_CLK_IntfPllSetFreqDiv()
589 …return clk_intf_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fcwF, dcoFixSel, ldoPr… in RSI_CLK_IntfPllSetFreqDiv()
1105 …rror_t RSI_CLK_M4SocClkConfig(M4CLK_Type *pCLK, M4_SOC_CLK_SRC_SEL_T clkSource, uint32_t divFactor) in RSI_CLK_M4SocClkConfig() argument
1107 return clk_m4_soc_clk_config(pCLK, clkSource, divFactor); in RSI_CLK_M4SocClkConfig()
1132 uint32_t divFactor) in RSI_CLK_QspiClkConfig() argument
1135 return ROMAPI_M4SS_CLK_API->clk_qspi_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor); in RSI_CLK_QspiClkConfig()
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Drsi_rom_ulpss_clk.h101 uint16_t divFactor, in RSI_ULPSS_ClockConfig() argument
105 return ROMAPI_ULPSS_CLK_API->ulpss_clock_config(pCLK, clkEnable, divFactor, oddDivFactor); in RSI_ULPSS_ClockConfig()
107 return ulpss_clock_config(pCLK, clkEnable, divFactor, oddDivFactor); in RSI_ULPSS_ClockConfig()
129 uint16_t divFactor, in RSI_ULPSS_UlpProcClkConfig() argument
132 return ulpss_ulp_proc_clk_config(pULPCLK, clkSource, divFactor, delayFn); in RSI_ULPSS_UlpProcClkConfig()
331 uint16_t divFactor) in RSI_ULPSS_UlpSsiClkConfig() argument
334 return ROMAPI_ULPSS_CLK_API->ulpss_ulp_ssi_clk_config(pULPCLK, clkType, clkSource, divFactor); in RSI_ULPSS_UlpSsiClkConfig()
336 return ulpss_ulp_ssi_clk_config(pULPCLK, clkType, clkSource, divFactor); in RSI_ULPSS_UlpSsiClkConfig()
365 uint16_t divFactor) in RSI_ULPSS_UlpI2sClkConfig() argument
368 return ROMAPI_ULPSS_CLK_API->ulpss_ulp_i2s_clk_config(pULPCLK, clkSource, divFactor); in RSI_ULPSS_UlpI2sClkConfig()
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Drsi_rom_table_si91x.h774 …rsi_error_t (*ulpss_clock_config)(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boole…
787 uint16_t divFactor);
789 …lpss_ulp_i2s_clk_config)(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor);
795 uint16_t divFactor);
809 uint16_t divFactor);
811 …lpss_touch_clk_config)(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor);
813 …or_t (*ulpss_slp_sensor_clk_config)(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor);
829 uint16_t divFactor,
861 uint16_t divFactor,
887 uint32_t divFactor);
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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_pll.c296 uint16_t divFactor, in clk_soc_pll_set_freq_div() argument
325 SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(divFactor << 9 | nFactor << 3); in clk_soc_pll_set_freq_div()
344 if ((socPllTvRead <= (M4_BBFF_STORAGE1 & 0x001F)) && (divFactor == 0)) { in clk_soc_pll_set_freq_div()
365 SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(divFactor << 9 | nFactor << 3); in clk_soc_pll_set_freq_div()
1022 uint16_t divFactor, in clk_intf_pll_set_freq_div() argument
1052 SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)((divFactor << 9) | (nFactor << 3)); in clk_intf_pll_set_freq_div()
1070 if ((intfPllTvRead <= ((M4_BBFF_STORAGE1 & 0x03E0) >> 5)) && (divFactor == 0)) { in clk_intf_pll_set_freq_div()
1091 SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)((divFactor << 9) | (nFactor << 3)); in clk_intf_pll_set_freq_div()
1375 uint32_t divFactor) in clk_qspi_clk_config() argument
1380 if ((pCLK == NULL) || (divFactor > QSPI_MAX_CLK_DIVISION_FACTOR)) { in clk_qspi_clk_config()
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Drsi_ulpss_clk.c49 rsi_error_t ulpss_clock_config(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t… in ulpss_clock_config() argument
55 pCLK->CLK_CONFIG_REG4_b.ULPSS_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); in ulpss_clock_config()
153 uint16_t divFactor) in ulpss_ulp_ssi_clk_config() argument
156 …if ((pULPCLK == NULL) || (divFactor > ULP_SSI_MAX_DIVISION_FACTOR) || (clkSource > ULP_SSI_MAX_SEL… in ulpss_ulp_ssi_clk_config()
219 pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_DIV_FACTOR = (unsigned int)(divFactor & 0x7F); in ulpss_ulp_ssi_clk_config()
236 … ulpss_ulp_i2s_clk_config(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor) in ulpss_ulp_i2s_clk_config() argument
239 …if ((pULPCLK == NULL) || (divFactor > ULP_I2S_MAX_DIVISION_FACTOR) || (clkSource > ULP_I2S_MAX_SEL… in ulpss_ulp_i2s_clk_config()
314 pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLKDIV_FACTOR = (uint8_t)divFactor; in ulpss_ulp_i2s_clk_config()
341 uint16_t divFactor) in ulpss_ulp_uar_clk_config() argument
344 …if ((pULPCLK == NULL) || (divFactor > ULP_UART_MAX_DIVISION_FACTOR) || (clkSource > ULP_UART_MAX_S… in ulpss_ulp_uar_clk_config()
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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/
Drsi_pll.h668 uint16_t divFactor,
716 uint16_t divFactor,
755 uint32_t divFactor);
761 uint32_t divFactor);
768 uint32_t divFactor);
773 uint32_t divFactor);
778 uint32_t divFactor);
780 rsi_error_t clk_ct_clk_config(M4CLK_Type *pCLK, CT_CLK_SRC_SEL_T clkSource, uint32_t divFactor, CLK…
782 rsi_error_t clk_cci_clk_config(M4CLK_Type *pCLK, CCI_CLK_SRC_SEL_T clkSource, uint32_t divFactor, C…
784 rsi_error_t clk_i2s_clk_config(M4CLK_Type *pCLK, I2S_CLK_SRC_SEL_T clkSource, uint32_t divFactor);
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Drsi_ulpss_clk.h304 uint16_t divFactor,
308 rsi_error_t ulpss_clock_config(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t…
312 uint16_t divFactor,
326 uint16_t divFactor);
328 …ulpss_ulp_i2s_clk_config(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor);
334 uint16_t divFactor);
347 uint16_t divFactor);
349 …ulpss_touch_clk_config(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor);
351 …error_t ulpss_slp_sensor_clk_config(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor);