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/hal_silabs-latest/simplicity_sdk/platform/service/device_manager/src/
Dsl_device_peripheral.c39 __WEAK const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = 0xFFFFFFFF,
44 __WEAK const sl_peripheral_val_t sl_peripheral_val_acmp1 = { .base = 0xFFFFFFFF,
49 __WEAK const sl_peripheral_val_t sl_peripheral_val_adc0 = { .base = 0xFFFFFFFF,
54 __WEAK const sl_peripheral_val_t sl_peripheral_val_aes = { .base = 0xFFFFFFFF,
59 __WEAK const sl_peripheral_val_t sl_peripheral_val_amuxcp0 = { .base = 0xFFFFFFFF,
64 __WEAK const sl_peripheral_val_t sl_peripheral_val_bufc = { .base = 0xFFFFFFFF,
69 __WEAK const sl_peripheral_val_t sl_peripheral_val_buram = { .base = 0xFFFFFFFF,
74 __WEAK const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = 0xFFFFFFFF,
79 __WEAK const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = 0xFFFFFFFF,
84 __WEAK const sl_peripheral_val_t sl_peripheral_val_cryptoacc = { .base = 0xFFFFFFFF,
[all …]
/hal_silabs-latest/simplicity_sdk/platform/service/device_manager/devices/
Dsl_device_peripheral_hal_efr32xg26.c42 const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = ACMP0_BASE,
49 const sl_peripheral_val_t sl_peripheral_val_acmp1 = { .base = ACMP1_BASE,
56 const sl_peripheral_val_t sl_peripheral_val_amuxcp0 = { .base = AMUXCP0_BASE,
63 const sl_peripheral_val_t sl_peripheral_val_buram = { .base = BURAM_BASE,
70 const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = BURTC_BASE,
77 const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = CMU_BASE,
84 const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = DCDC_BASE,
91 const sl_peripheral_val_t sl_peripheral_val_dmem0 = { .base = DMEM0_BASE,
98 const sl_peripheral_val_t sl_peripheral_val_dmem1 = { .base = DMEM1_BASE,
105 const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = DPLL0_BASE,
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Dsl_device_peripheral_hal_efr32xg25.c42 const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = ACMP0_BASE,
49 const sl_peripheral_val_t sl_peripheral_val_acmp1 = { .base = ACMP1_BASE,
56 const sl_peripheral_val_t sl_peripheral_val_bufc = { .base = BUFC_BASE,
63 const sl_peripheral_val_t sl_peripheral_val_buram = { .base = BURAM_BASE,
70 const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = BURTC_BASE,
77 const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = CMU_BASE,
84 const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = DCDC_BASE,
91 const sl_peripheral_val_t sl_peripheral_val_dmem = { .base = DMEM_BASE,
98 const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = DPLL0_BASE,
105 const sl_peripheral_val_t sl_peripheral_val_emu = { .base = EMU_BASE,
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Dsl_device_peripheral_hal_efr32xg23.c42 const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = ACMP0_BASE,
49 const sl_peripheral_val_t sl_peripheral_val_acmp1 = { .base = ACMP1_BASE,
56 const sl_peripheral_val_t sl_peripheral_val_buram = { .base = BURAM_BASE,
63 const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = BURTC_BASE,
70 const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = CMU_BASE,
77 const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = DCDC_BASE,
84 const sl_peripheral_val_t sl_peripheral_val_dmem = { .base = DMEM_BASE,
91 const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = DPLL0_BASE,
98 const sl_peripheral_val_t sl_peripheral_val_emu = { .base = EMU_BASE,
105 const sl_peripheral_val_t sl_peripheral_val_eusart0 = { .base = EUSART0_BASE,
[all …]
Dsl_device_peripheral_hal_efr32xg28.c42 const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = ACMP0_BASE,
49 const sl_peripheral_val_t sl_peripheral_val_acmp1 = { .base = ACMP1_BASE,
56 const sl_peripheral_val_t sl_peripheral_val_buram = { .base = BURAM_BASE,
63 const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = BURTC_BASE,
70 const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = CMU_BASE,
77 const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = DCDC_BASE,
84 const sl_peripheral_val_t sl_peripheral_val_dmem = { .base = DMEM_BASE,
91 const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = DPLL0_BASE,
98 const sl_peripheral_val_t sl_peripheral_val_emu = { .base = EMU_BASE,
105 const sl_peripheral_val_t sl_peripheral_val_eusart0 = { .base = EUSART0_BASE,
[all …]
Dsl_device_peripheral_hal_efr32xg24.c42 const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = ACMP0_BASE,
49 const sl_peripheral_val_t sl_peripheral_val_acmp1 = { .base = ACMP1_BASE,
56 const sl_peripheral_val_t sl_peripheral_val_buram = { .base = BURAM_BASE,
63 const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = BURTC_BASE,
70 const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = CMU_BASE,
77 const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = DCDC_BASE,
84 const sl_peripheral_val_t sl_peripheral_val_dmem = { .base = DMEM_BASE,
91 const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = DPLL0_BASE,
98 const sl_peripheral_val_t sl_peripheral_val_emu = { .base = EMU_BASE,
105 const sl_peripheral_val_t sl_peripheral_val_eusart0 = { .base = EUSART0_BASE,
[all …]
Dsl_device_peripheral_hal_efr32xg29.c42 const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = ACMP0_BASE,
49 const sl_peripheral_val_t sl_peripheral_val_buram = { .base = BURAM_BASE,
56 const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = BURTC_BASE,
63 const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = CMU_BASE,
70 const sl_peripheral_val_t sl_peripheral_val_semailbox = { .base = SEMAILBOX_HOST_BASE,
77 const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = DCDC_BASE,
84 const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = DPLL0_BASE,
91 const sl_peripheral_val_t sl_peripheral_val_emu = { .base = EMU_BASE,
98 const sl_peripheral_val_t sl_peripheral_val_etampdet = { .base = ETAMPDET_BASE,
105 const sl_peripheral_val_t sl_peripheral_val_eusart0 = { .base = EUSART0_BASE,
[all …]
Dsl_device_peripheral_hal_efr32xg21.c42 const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = ACMP0_BASE,
49 const sl_peripheral_val_t sl_peripheral_val_acmp1 = { .base = ACMP1_BASE,
56 const sl_peripheral_val_t sl_peripheral_val_bufc = { .base = BUFC_BASE,
63 const sl_peripheral_val_t sl_peripheral_val_buram = { .base = BURAM_BASE,
70 const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = BURTC_BASE,
77 const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = CMU_BASE,
84 const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = DPLL0_BASE,
91 const sl_peripheral_val_t sl_peripheral_val_emu = { .base = EMU_BASE,
98 const sl_peripheral_val_t sl_peripheral_val_fsrco = { .base = FSRCO_BASE,
105 const sl_peripheral_val_t sl_peripheral_val_gpcrc0 = { .base = GPCRC_BASE,
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Dsl_device_peripheral_hal_efr32xg27.c42 const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = ACMP0_BASE,
49 const sl_peripheral_val_t sl_peripheral_val_buram = { .base = BURAM_BASE,
56 const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = BURTC_BASE,
63 const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = CMU_BASE,
70 const sl_peripheral_val_t sl_peripheral_val_cryptoacc = { .base = CRYPTOACC_BASE,
77 const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = DCDC_BASE,
84 const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = DPLL0_BASE,
91 const sl_peripheral_val_t sl_peripheral_val_emu = { .base = EMU_BASE,
98 const sl_peripheral_val_t sl_peripheral_val_etampdet = { .base = ETAMPDET_BASE,
105 const sl_peripheral_val_t sl_peripheral_val_eusart0 = { .base = EUSART0_BASE,
[all …]
Dsl_device_peripheral_hal_efr32xg22.c42 const sl_peripheral_val_t sl_peripheral_val_buram = { .base = BURAM_BASE,
49 const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = BURTC_BASE,
56 const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = CMU_BASE,
63 const sl_peripheral_val_t sl_peripheral_val_cryptoacc = { .base = CRYPTOACC_BASE,
70 const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = DCDC_BASE,
77 const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = DPLL0_BASE,
84 const sl_peripheral_val_t sl_peripheral_val_emu = { .base = EMU_BASE,
91 const sl_peripheral_val_t sl_peripheral_val_euart0 = { .base = EUART0_BASE,
98 const sl_peripheral_val_t sl_peripheral_val_fsrco = { .base = FSRCO_BASE,
105 const sl_peripheral_val_t sl_peripheral_val_gpcrc0 = { .base = GPCRC_BASE,
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/hal_silabs-latest/simplicity_sdk/platform/service/device_manager/inc/
Dsl_device_peripheral.h919 return (ACMP_TypeDef *)peripheral->base; in sl_device_peripheral_acmp_get_base_addr()
931 return (ADC_TypeDef *)peripheral->base; in sl_device_peripheral_adc_get_base_addr()
943 return (AES_TypeDef *)peripheral->base; in sl_device_peripheral_aes_get_base_addr()
955 return (AMUXCP_TypeDef *)peripheral->base; in sl_device_peripheral_amuxcp_get_base_addr()
967 return (BUFC_TypeDef *)peripheral->base; in sl_device_peripheral_bufc_get_base_addr()
979 return (BURAM_TypeDef *)peripheral->base; in sl_device_peripheral_buram_get_base_addr()
991 return (BURTC_TypeDef *)peripheral->base; in sl_device_peripheral_burtc_get_base_addr()
1003 return (CMU_TypeDef *)peripheral->base; in sl_device_peripheral_cmu_get_base_addr()
1015 return (CRYPTOACC_TypeDef *)peripheral->base; in sl_device_peripheral_cryptoacc_get_base_addr()
1027 return (CRYPTOACC_PKCTRL_TypeDef *)peripheral->base; in sl_device_peripheral_cryptoacc_pkctrl_get_base_addr()
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Dsl_device_peripheral_types.h51 uint32_t base; ///< Peripheral base address. member
/hal_silabs-latest/wiseconnect/components/common/src/
Dsl_utility.c51 int base; member
138 best.base = -1; in sl_inet_ntop6()
139 cur.base = -1; in sl_inet_ntop6()
144 if (cur.base == -1) { in sl_inet_ntop6()
145 cur.base = i; in sl_inet_ntop6()
150 if (cur.base != -1) { in sl_inet_ntop6()
151 if (best.base == -1 || cur.len > best.len) in sl_inet_ntop6()
153 cur.base = -1; in sl_inet_ntop6()
157 if ((cur.base != -1) && (best.base == -1 || cur.len > best.len)) in sl_inet_ntop6()
159 if (best.base != -1 && best.len < 2) in sl_inet_ntop6()
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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/
Drsi_udma.h246 RSI_UDMA_T *base; // UDMA base address member
256 uint32_t base; // Pointer to RPDMA global register instance
310 pDrv->base->DMA_CFG_b.MASTER_ENABLE = ENABLE; in RSI_UDMA_UDMAEnable()
325 pDrv->base->DMA_CFG_b.MASTER_ENABLE = DISABLE; in RSI_UDMA_UDMADisable()
351 pDrv->base->ERR_CLR_b.ERR_CLR = 0x1; in RSI_UDMA_ErrorStatusClear()
367 pDrv->base->CHNL_ENABLE_SET = SET_BIT(dmaCh); in RSI_UDMA_ChannelEnable()
387 pDrv->base->CHNL_ENABLE_CLR = SET_BIT(dmaCh); in RSI_UDMA_ChannelDisable()
405 if (((pDrv->base->CHNL_ENABLE_SET) & SET_BIT(dmaCh)) != 0) { in RSI_UDMA_ChannelIsEnabled()
425 return ((void *)pDrv->base->CTRL_BASE_PTR); in RSI_UDMA_GetControlBaseAddress()
438 return ((void *)pDrv->base->ALT_CTRL_BASE_PTR); in RSI_UDMA_GetControlAlternateBase()
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/hal_silabs-latest/gecko/emlib/src/
Dem_msc.c257 uint32_t base; member
1569 volatile uint32_t *ramptr = (volatile uint32_t *) eccBank->base; in mscEccReadWriteExistingPio()
1570 const uint32_t *endptr = (const uint32_t *) (eccBank->base + eccBank->size); in mscEccReadWriteExistingPio()
1575 if (eccBank->base == ECC_RAM0_MEM_BASE) { in mscEccReadWriteExistingPio()
1577 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccReadWriteExistingPio()
1598 if (eccBank->base == ECC_RAM0_MEM_BASE) { in mscEccReadWriteExistingPio()
1601 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccReadWriteExistingPio()
1840 mscEccReadWriteExistingDma(eccBank->base, eccBank->size, dmaChannels); in mscEccBankInit()
1846 if (eccBank->base == ECC_RAM0_MEM_BASE) { in mscEccBankInit()
1848 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccBankInit()
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Dem_timer.c142 volatile PRS_TIMERn_TypeDef * base = (PRS_TIMERn_TypeDef *) &PRS->CONSUMER_TIMER0_CC0; in timerPrsConfig() local
147 base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; in timerPrsConfig()
149 base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; in timerPrsConfig()
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_msc.c259 uint32_t base; member
1572 volatile uint32_t *ramptr = (volatile uint32_t *) eccBank->base; in mscEccReadWriteExistingPio()
1573 const uint32_t *endptr = (const uint32_t *) (eccBank->base + eccBank->size); in mscEccReadWriteExistingPio()
1578 if (eccBank->base == ECC_RAM0_MEM_BASE) { in mscEccReadWriteExistingPio()
1580 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccReadWriteExistingPio()
1603 if (eccBank->base == ECC_RAM0_MEM_BASE) { in mscEccReadWriteExistingPio()
1606 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccReadWriteExistingPio()
1846 mscEccReadWriteExistingDma(eccBank->base, eccBank->size, dmaChannels); in mscEccBankInit()
1852 if (eccBank->base == ECC_RAM0_MEM_BASE) { in mscEccBankInit()
1854 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccBankInit()
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Dem_timer.c142 volatile PRS_TIMERn_TypeDef * base = (PRS_TIMERn_TypeDef *) &PRS->CONSUMER_TIMER0_CC0; in timerPrsConfig() local
147 base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; in timerPrsConfig()
149 base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; in timerPrsConfig()
/hal_silabs-latest/scripts/
Dgen_adc.py122 port_base = int(m.group(3), base=16) * 16
Dgen_pinctrl.py335 "value": int(m.group(5), base=16),