Searched refs:__OM (Results 1 – 25 of 51) sorted by relevance
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166 #ifndef __OM /*!< Fallback for older CMSIS versions */167 #define __OM __O macro522 __OM unsigned int TMR_START : 1; /*!< [0..0] This Bit are Used to start the timer timer524 __OM unsigned int TMR_INTR_CLR : 1; /*!< [1..1] This Bit are Used to clear the532 __OM unsigned int TMR_STOP : 1; /*!< [6..6] This Bit are Used to stop the timer */556 __OM unsigned int I2S_LTHR; /*!< (@ 0x00000000) Left Receive Buffer Register */559 __OM unsigned int LTHR : 24; /*!< [23..0] The Left Stereo Data to be transmitted561 __OM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */578 __OM unsigned int I2S_RTHR; /*!< (@ 0x00000004) Right Transmit Holding Register */581 __OM unsigned int RTHR : 24; /*!< [23..0] The Right Stereo Data to be transmitted[all …]
49 __OM uint32_t DOUTSET; /**< Port Data Out Set Register */50 __OM uint32_t DOUTCLR; /**< Port Data Out Clear Register */51 __OM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
48 __OM uint32_t CONFIG; /**< DMA Configuration Register */52 __OM uint32_t CHSWREQ; /**< Channel Software Request Register */54 __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */56 __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */58 __OM uint32_t CHENC; /**< Channel Enable Clear Register */60 __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */62 __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
250 __OM uint32_t CONFIG; /**< DMA Configuration Register */254 __OM uint32_t CHSWREQ; /**< Channel Software Request Register */256 __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */258 __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */260 __OM uint32_t CHENC; /**< Channel Enable Clear Register */262 __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */264 __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
240 __OM uint32_t CONFIG; /**< DMA Configuration Register */244 __OM uint32_t CHSWREQ; /**< Channel Software Request Register */246 __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */248 __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */250 __OM uint32_t CHENC; /**< Channel Enable Clear Register */252 __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */254 __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
49 __OM uint32_t CMD; /**< Command Register */
245 __OM uint32_t CONFIG; /**< DMA Configuration Register */249 __OM uint32_t CHSWREQ; /**< Channel Software Request Register */251 __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */253 __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */255 __OM uint32_t CHENC; /**< Channel Enable Clear Register */257 __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */259 __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
77 __OM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */81 __OM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */94 __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */95 __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */96 __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
293 __OM uint32_t CONFIG; /**< DMA Configuration Register */297 __OM uint32_t CHSWREQ; /**< Channel Software Request Register */299 __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */301 __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */303 __OM uint32_t CHENC; /**< Channel Enable Clear Register */305 __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */307 __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
95 __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */96 __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */97 __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
201 #define __OM volatile ///< Defines 'write only' structure member permissions macro
