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Searched refs:__CM0PLUS_REV (Results 1 – 22 of 22) sorted by relevance

/hal_silabs-latest/simplicity_sdk/platform/common/src/
Dsl_core_cortexm.c157 #ifndef __CM0PLUS_REV in CORE_AtomicDisableIrq()
174 #ifndef __CM0PLUS_REV in CORE_AtomicEnableIrq()
188 #ifndef __CM0PLUS_REV in CORE_EnterAtomic()
220 #ifndef __CM0PLUS_REV in CORE_ExitAtomic()
247 #ifndef __CM0PLUS_REV in CORE_YieldAtomic()
278 #ifndef __CM0PLUS_REV in CORE_IrqIsDisabled()
/hal_silabs-latest/gecko/emlib/inc/
Dem_core.h83 #elif defined(__CM0_REV) || defined(__CM0PLUS_REV)
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32HG/Include/
Defm32hg309f32.h159 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg309f64.h159 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg310f32.h159 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg310f64.h159 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg322f32.h159 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg322f64.h159 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg350f32.h159 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg350f64.h159 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg210f32.h158 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg210f64.h158 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg222f32.h158 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg222f64.h158 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg110f32.h158 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg110f64.h158 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg321f32.h158 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg321f64.h158 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg108f32.h156 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg108f64.h156 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg308f32.h157 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro
Defm32hg308f64.h157 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ macro