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Searched refs:_WDOG_CFG_CLRSRC_PRSSRC0 (Results 1 – 8 of 8) sorted by relevance

/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/
Defr32fg23_wdog.h129 #define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode P… macro
132 #define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifte…
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/
Defr32bg29_wdog.h124 #define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode P… macro
127 #define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifte…
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21_wdog.h124 #define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode P… macro
127 #define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifte…
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/
Defr32mg29_wdog.h124 #define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode P… macro
127 #define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifte…
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22_wdog.h124 #define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode P… macro
127 #define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifte…
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/
Defr32zg23_wdog.h129 #define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode P… macro
132 #define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifte…
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27_wdog.h124 #define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode P… macro
127 #define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifte…
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/
Defr32mg24_wdog.h129 #define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode P… macro
132 #define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifte…