1 /* ----------------------------------------------------------------------------- 2 * 3 * SPDX-License-Identifier: Zlib 4 * Copyright (c) 2013-2014 ARM Ltd. 5 * This software is provided 'as-is', without any express or implied warranty. 6 * In no event will the authors be held liable for any damages arising from 7 * the use of this software. Permission is granted to anyone to use this 8 * software for any purpose, including commercial applications, and to alter 9 * it and redistribute it freely, subject to the following restrictions: 10 * 11 * 1. The origin of this software must not be misrepresented; you must not 12 * claim that you wrote the original software. If you use this software in 13 * a product, an acknowledgment in the product documentation would be 14 * appreciated but is not required. 15 * 16 * 2. Altered source versions must be plainly marked as such, and must not be 17 * misrepresented as being the original software. 18 * 19 * 3. This notice may not be removed or altered from any source distribution. 20 * 21 * 22 * $Date: 24. Nov 2014 23 * $Revision: V2.02 24 * 25 * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) 26 * Driver definitions 27 * -------------------------------------------------------------------------- */ 28 /* 29 * Version 1.00 30 * Initial release 31 */ 32 33 #ifndef __USART_H__ 34 #define __USART_H__ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #include "rsi_pll.h" 41 #include "rsi_ulpss_clk.h" 42 #include "Driver_USART.h" 43 #include "rsi_ccp_common.h" 44 45 #include "UDMA.h" 46 47 #define USART_INSTANCE_BIT 30 // USART Instance bit postion stored in event variable 48 #define USART_EVENT_MASK 0x3FFFFFFF // USART Event Mask 49 50 // USART Transfer Information (Run-Time) 51 typedef struct _USART_TRANSFER_INFO { 52 uint32_t rx_num; // Total number of data to be received 53 uint32_t tx_num; // Total number of data to be send 54 uint8_t *rx_buf; // Pointer to in data buffer 55 uint8_t *tx_buf; // Pointer to out data buffer 56 uint32_t rx_cnt; // Number of data received 57 uint32_t tx_cnt; // Number of data sent 58 uint8_t tx_def_val; // Transmit default value (used in USART_SYNC_MASTER_MODE_RX) 59 uint8_t rx_dump_val; // Receive dump value (used in USART_SYNC_MASTER_MODE_TX) 60 uint8_t send_active; // Send active flag 61 uint8_t sync_mode; // Synchronous mode 62 } USART_TRANSFER_INFO; 63 64 typedef struct _USART_RX_STATUS { 65 uint8_t rx_busy; // Receiver busy flag 66 uint8_t rx_overflow; // Receive data overflow detected (cleared on start of next receive operation) 67 uint8_t rx_break; // Break detected on receive (cleared on start of next receive operation) 68 uint8_t rx_framing_error; // Framing error detected on receive (cleared on start of next receive operation) 69 uint8_t rx_parity_error; // Parity error detected on receive (cleared on start of next receive operation) 70 } USART_RX_STATUS; 71 72 // USART DMA 73 typedef struct _USART0_DMA 74 { 75 RSI_UDMA_CHA_CONFIG_DATA_T control; 76 uint8_t channel; // DMA Channel number 77 UDMA_SignalEvent_t cb_event; // DMA Event callback 78 } USART_DMA; 79 80 81 // USART flags 82 #define USART_FLAG_INITIALIZED (1U << 0) 83 #define USART_FLAG_POWERED (1U << 1) 84 #define USART_FLAG_CONFIGURED (1U << 2) 85 #define USART_FLAG_TX_ENABLED (1U << 3) 86 #define USART_FLAG_RX_ENABLED (1U << 4) 87 #define USART_FLAG_SEND_ACTIVE (1U << 5) 88 89 /*!< USART Configuration control bits (Line control Register)*/ 90 #define USART_CNTL_DATALEN_5 (0x00 << 0) /*!< USART 5 bit length mode */ 91 #define USART_CNTL_DATALEN_6 (0x01 << 0) /*!< USART 6 bit length mode */ 92 #define USART_CNTL_DATALEN_7 (0x02 << 0) /*!< USART 7 bit length mode */ 93 #define USART_CNTL_DATALEN_8 (0x03 << 0) /*!< USART 8 bit length mode */ 94 #define USART_CNTL_STOPBIT_1 (0x00 << 2) /*!< USART One Stop Bit Select */ 95 #define USART_CNTL_STOPBIT_2 (0x01 << 2) /*!< USART Two Stop Bits Select */ 96 #define USART_CNTL_STOPBIT_1P5 (0x01 << 2) /*!< USART Two Stop Bits Select */ 97 #define USART_CNTL_PARITY_OFF (0x00 << 3) /*!< Parity Enabled */ 98 #define USART_CNTL_PARITY_ON (0x01 << 3) /*!< Parity Disabled */ 99 #define USART_CNTL_PARITY_ODD (0x00 << 4) /*!< Odd parity */ 100 #define USART_CNTL_PARITY_EVEN (0x01 << 4) /*!< Even parity */ 101 #define USART_PARITY_ENABLE (0x01 << 3) /*!< Set parity */ 102 #define USART_CNTL_DLAB_SET (0x01 << 7) 103 #define USART_CNTL_DLAB_RESET (0x00) 104 #define USART_CNTL_DATALEN_9 (0x01 << 0) /*!< USART 9 bit length mode */ 105 106 /*!< USART FIFO Configuration control bits (FIFO control Register)*/ 107 #define USART_FIFO_ENABLE (0x01 << 0) /*!< FIFO Enable */ 108 #define USART_FIFO_RX_RESET (0x01 << 1) /*!< Receive FIFO Reset */ 109 #define USART_FIFO_TX_RESET (0x01 << 2) /*!< Transmit FIFO Reset */ 110 #define USART_FIFO_TX_EMPTY (0x00 << 4) /*!< Transmit Empty */ 111 #define USART_FIFO_TX_AEMPTY (0x01 << 4) /*!< Transmit Almost Empty */ 112 #define USART_FIFO_TX_QUARTER_FULL (0x02 << 4) /*!< Transmit FIFO Quarter full */ 113 #define USART_FIFO_TX_HALF_FULL (0x03 << 4) /*!< Transmit FIFO Half full */ 114 #define USART_FIFO_RX_AEMPTY (0x00 << 6) /*!< Receive FIFO AEMPTY */ 115 #define USART_FIFO_RX_QUARTER_FULL (0x01 << 6) /*!< Receive FIFO Quarter full */ 116 #define USART_FIFO_RX_HALF_FULL (0x01 << 7) /*!< Receive FIFO half full */ 117 #define USART_FIFO_RX_AFULL (0x03 << 6) /*!< RX FIFO Almost Full */ 118 #define USART_DMA_MODE_EN (1UL << 3) 119 120 /*!< USART (Interrupt Enable Register)*/ 121 #define USART_INTR_RX_DATA (0x01 << 0) /*!< Enable Received Data Available Interrupt. */ 122 #define USART_INTR_THRE (0x01 << 1) /*!< Enable Transmit Holding Register Empty Interrupt.*/ 123 #define USART_INTR_RXRDY (0x01 << 2) /*!< Receive Ready Interrupt */ 124 #define USART_INTR_MODEM_STATUS (0x01 << 3) /*!< TODO */ 125 #define USART_INTR_PROGRAMMABLE_THRE (0x01 << 7) /*!< TODO THRE Interrupt */ 126 127 /*!< USART (Interrupt Identity Register)*/ 128 #define USART_MODEM_STATUS_INTR (0x00 << 0) 129 #define USART_NO_INTR_PENDING (0x01 << 0) /*!< NO Interrupt Pending */ 130 #define USART_THR_EMPTY (0x01 << 1) /*!< THR Empty */ 131 #define USART_RX_DATA_AVAILABLE (0x01 << 2) /*!< Received Data Available */ 132 #define USART_RX_LINE_STATUS (0x03 << 1) /*!< Receiver line status */ 133 #define USART_BUSY_DETECT (0x07 << 0) /*!< USART busy detect */ 134 #define USART_IIR_FIFO_ENABLE (0x03 << 6) /*!< IIR FIFO enabled */ 135 136 /*!< USART (Modem status registers)*/ 137 #define USART_MSR_DCTS (0x1 << 0) /*!<Delta Clear to Send */ 138 #define USART_MSR_DDSR (0x1 << 1) /*!<Delta Data Set Ready */ 139 #define USART_MSR_TERI (0x1 << 2) /*!<Trailing Edge of Ring Indicator */ 140 #define USART_MSR_DDCD (0x1 << 3) /*!<Delta Data Carrier Detect */ 141 142 /*< USART (Line status Register)*/ 143 #define USART_OVERRUN_ERR (0x01 << 1) /*!< This is used to indicate the occurrence of an overrun error. This occurs 144 if a new data character was received before the previous data was read. */ 145 #define USART_PARITY_ERR (0x01 << 2) /*!< This is used to indicate the occurrence of a parity error in the receiver if 146 the Parity Enable */ 147 #define USART_FRAMING_ERR (0x01 << 3) /*!< This is used to indicate the occurrence of a framing error in the receiver. 148 A framing error occurs when the receiver does not detect a valid STOP bit 149 in the received data */ 150 #define USART_BREAK_ERR (0x01 << 4) /*!< Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial 151 input data. */ 152 #define USART_RECV_FIFO_ERR (0x01 << 7) /*!< This is used to indicate if there is at least one parity error, 153 framing error, or break indication in the FIFO. */ 154 #define USART_LSR_THRE (0x1 <<5) 155 156 /*!< USART (Modem control Register)*/ 157 #define USART_MODEM_DTR_SET (0x01 << 0) /*!< Data Terminal Ready set */ 158 #define USART_MODEM_RTS_SET (0x01 << 1) /*!< Request to send set */ 159 #define USART_MODEM_RTS_RESET (0x00 << 1) /*!< Request to send set */ 160 #define USART_MODEM_LOOP_BACK_ENABLE (0x01 << 4) /*!< LoopBack Bit */ 161 #define USART_MODEM_AFCE_ENABLE (0x01 << 5) /*!< Auto Flow control Enable */ 162 #define USART_MODEM_AFCE_DISABLE (0x00 << 5) /*!< Auto Flow control Disable */ 163 164 /*!< USART (LCR Register)*/ 165 #define USART_LCR_BC (0x01 << 6) 166 167 // UART Modem status register 168 #define UART_MSR_DCTS (1U << 0) 169 #define UART_MSR_DDSR (1U << 1) 170 #define UART_MSR_TERI (1U << 2) 171 #define UART_MSR_DDCD (1U << 3) 172 #define UART_MSR_CTS (1U << 4) 173 #define UART_MSR_DSR (1U << 5) 174 #define UART_MSR_RI (1U << 6) 175 #define UART_MSR_DCD (1U << 7) 176 177 /*!< API configuration macros*/ 178 #define USART_DATA_LEN_5 5 179 #define USART_DATA_LEN_6 6 180 #define USART_DATA_LEN_7 7 181 #define USART_DATA_LEN_8 8 182 #define USART_DATA_LEN_9 9 183 184 #define USART_STOP_BIT_1 0 185 #define USART_STOP_BIT_1P5 1 186 #define USART_STOP_BIT_2 2 187 188 #define USART_TRIGGER_TX_EMPTY 0 189 190 #define USART_DMA_MODE0_EN (0 << 3) 191 #define USART_DMA_MODE1_EN (1 << 3) 192 193 #define USART_TRIGGER_RX_AEMPTY 0 194 195 #define USART_ERROR_CALLBACK_INDEX 0 196 #define USART_EVENT_CALLBACK_INDEX 1 197 198 // USART synchronos xfer modes 199 #define USART_SYNC_MODE_TX ( 1U ) 200 #define USART_SYNC_MODE_RX ( 2U ) 201 #define USART_SYNC_MODE_TX_RX (USART_SYNC_MODE_TX | \ 202 USART_SYNC_MODE_RX) 203 204 #define USART_LCR_TEMT 0x80 205 #define USART_RESET_REG 0x00 ///< USART reset register address 206 207 typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. 208 209 typedef struct _USART_CLOCK 210 { 211 USART_CLK_SRC_SEL_T uart_clock_src; 212 ULP_UART_CLK_SELECT_T ulp_uart_source; 213 uint32_t divfact; 214 uint32_t frac_div_en; 215 }USART_CLOCK; 216 217 typedef const struct _USART_PIN { 218 uint8_t port; ///< CAN GPIO port 219 uint8_t pin; ///< CAN GPIO pin 220 uint8_t mode; ///< CAN GPIO mode 221 uint8_t pad_sel; ///< CAN GPIO pad selection 222 }USART_PIN; 223 224 // USART Information (Run-Time) 225 typedef struct _USART_INFO { 226 ARM_USART_SignalEvent_t cb_event; // Event callback 227 USART_RX_STATUS rx_status; // Receive status flags 228 USART_TRANSFER_INFO xfer; // Transfer information 229 uint8_t mode; // USART mode 230 uint8_t flags; // USART driver flags 231 uint32_t baudrate; // Baudrate 232 } USART_INFO; 233 234 // USART Input/Output Configuration 235 typedef const struct _USART_IO { 236 USART_PIN *clock; 237 USART_PIN *tx; 238 USART_PIN *rx; 239 USART_PIN *cts; 240 USART_PIN *rts; 241 USART_PIN *ir_tx; 242 USART_PIN *ir_rx; 243 } USART_IO; 244 245 typedef struct _USART_MODE 246 { 247 uint8_t en_usart_mode; 248 uint8_t continuous_clock; 249 }USART_SYNC_MODE; 250 251 /*!<USART data structure */ 252 typedef struct 253 { 254 ARM_USART_CAPABILITIES capabilities; ///< Capabilities 255 USART0_Type *pREGS; 256 IRQn_Type irq_num; 257 USART_DMA *dma_tx; 258 USART_DMA *dma_rx; 259 USART_INFO *info; 260 USART_IO io; 261 USART_CLOCK clock; 262 USART_SYNC_MODE sync_mode; 263 } USART_RESOURCES; 264 ARM_USART_CAPABILITIES USART_GetCapabilities (const USART_RESOURCES *usart); 265 ARM_DRIVER_VERSION ARM_USARTx_GetVersion(void); 266 void IRQ038_Handler(void); 267 void IRQ039_Handler(void); 268 void IRQ012_Handler(void); 269 void RSI_M4SSUsart0Handler(void); 270 void RSI_M4SSUart1Handler(void); 271 void RSI_ULPUartHandler(void); 272 273 #ifdef __cplusplus 274 } 275 #endif 276 #endif // __USART_H__ 277
