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Searched refs:_SMU_PPUPATD1_USART3_DEFAULT (Results 1 – 25 of 67) sorted by relevance

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/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_smu.h296 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
297 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 11) /**< Shifted mode …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_smu.h296 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
297 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 11) /**< Shifted mode …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_smu.h296 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
297 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 11) /**< Shifted mode …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_smu.h372 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
373 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b390f1024gl112.h7812 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
7813 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b390f512gl112.h7812 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
7813 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b530f512il120.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b530f512im64.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b530f512iq100.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b530f512iq64.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b530f512gq100.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b530f512gq64.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b530f512il112.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b110f1024gm64.h8579 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8580 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b110f1024gq64.h8579 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8580 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b530f512gl112.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b530f512gl120.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b530f512gm64.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b510f1024gq100.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b510f1024gq64.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b510f1024gl112.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b510f1024gl120.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b510f1024gm64.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
Defm32gg12b510f1024il112.h8615 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
8616 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 20) /**< Shifted mode …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_smu.h397 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT … macro
398 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode …

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