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Searched refs:_SMU_PPUPATD0_ADC1_MASK (Results 1 – 25 of 64) sorted by relevance

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/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_smu.h142 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b390f1024gl112.h7587 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b390f512gl112.h7587 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b530f512il120.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b530f512im64.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b530f512iq100.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b530f512iq64.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b530f512gq100.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b530f512gq64.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b530f512il112.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b110f1024gm64.h8364 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b110f1024gq64.h8364 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b530f512gl112.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b530f512gl120.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b530f512gm64.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b510f1024gq100.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b510f1024gq64.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b510f1024gl112.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b510f1024gl120.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b510f1024gm64.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b510f1024il112.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b510f1024il120.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b510f1024im64.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
Defm32gg12b510f1024iq100.h8395 #define _SMU_PPUPATD0_ADC1_MASK 0x10UL /**< Bit mask for… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_smu.h147 #define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for… macro

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