1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG22 PRS register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG22_PRS_H 31 #define EFR32BG22_PRS_H 32 #define PRS_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG22_PRS PRS 40 * @{ 41 * @brief EFR32BG22 PRS Register Declaration. 42 *****************************************************************************/ 43 44 /** PRS ASYNC_CH Register Group Declaration. */ 45 typedef struct prs_async_ch_typedef{ 46 __IOM uint32_t CTRL; /**< Async Channel Control Register */ 47 } PRS_ASYNC_CH_TypeDef; 48 49 /** PRS SYNC_CH Register Group Declaration. */ 50 typedef struct prs_sync_ch_typedef{ 51 __IOM uint32_t CTRL; /**< Sync Channel Control Register */ 52 } PRS_SYNC_CH_TypeDef; 53 54 /** PRS Register Declaration. */ 55 typedef struct prs_typedef{ 56 __IM uint32_t IPVERSION; /**< IP version ID */ 57 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 58 __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ 59 __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ 60 __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ 61 __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ 62 PRS_ASYNC_CH_TypeDef ASYNC_CH[12U]; /**< Async Channel registers */ 63 PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ 64 __IOM uint32_t CONSUMER_CMU_CALDN; /**< CMU CALDN Consumer Selection */ 65 __IOM uint32_t CONSUMER_CMU_CALUP; /**< CMU CALUP Consumer Selection */ 66 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 67 __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< IADC0 SCANTRIGGER Consumer Selection */ 68 __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< IADC0 SINGLETRIGGER Consumer Selection */ 69 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 Consumer Selection */ 70 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer Selection */ 71 __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< LETIMER CLEAR Consumer Selection */ 72 __IOM uint32_t CONSUMER_LETIMER0_START; /**< LETIMER START Consumer Selection */ 73 __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< LETIMER STOP Consumer Selection */ 74 __IOM uint32_t CONSUMER_EUART0_RX; /**< EUART0 RX consumer register */ 75 __IOM uint32_t CONSUMER_EUART0_TRIGGER; /**< EUART0 TRIGGER Consumer register */ 76 __IOM uint32_t CONSUMER_MODEM_DIN; /**< MODEM DIN Consumer Selection */ 77 uint32_t RESERVED2[2U]; /**< Reserved for future use */ 78 uint32_t RESERVED3[11U]; /**< Reserved for future use */ 79 __IOM uint32_t CONSUMER_RAC_CLR; /**< RAC CLR Consumer Selection */ 80 __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< RAC CTIIN0 Consumer Selection */ 81 __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< RAC CTIIN1 Consumer Selection */ 82 __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< RAC CTIIN2 Consumer Selection */ 83 __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< RAC CTIIN3 Consumer Selection */ 84 __IOM uint32_t CONSUMER_RAC_FORCETX; /**< RAC FORCETX Consumer Selection */ 85 __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RAC RXDIS Consumer Selection */ 86 __IOM uint32_t CONSUMER_RAC_RXEN; /**< RAC RXEN Consumer Selection */ 87 __IOM uint32_t CONSUMER_RAC_SEQ; /**< RAC SEQ Consumer Selection */ 88 __IOM uint32_t CONSUMER_RAC_TXEN; /**< RAC TXEN Consumer Selection */ 89 __IOM uint32_t CONSUMER_RTCC_CC0; /**< RTCC CC0 Consumer Selection */ 90 __IOM uint32_t CONSUMER_RTCC_CC1; /**< RTCC CC1 Consumer Selection */ 91 __IOM uint32_t CONSUMER_RTCC_CC2; /**< RTCC CC2 Consumer Selection */ 92 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 93 __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 Consumer Selection */ 94 __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer Selection */ 95 __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer Selection */ 96 __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer Selection */ 97 __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer Selection */ 98 __IOM uint32_t CONSUMER_TIMER0_CC0; /**< TIMER0 CC0 Consumer Selection */ 99 __IOM uint32_t CONSUMER_TIMER0_CC1; /**< TIMER0 CC1 Consumer Selection */ 100 __IOM uint32_t CONSUMER_TIMER0_CC2; /**< TIMER0 CC2 Consumer Selection */ 101 __IOM uint32_t CONSUMER_TIMER0_DTI; /**< TIMER0 DTI Consumer Selection */ 102 __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< TIMER0 DTIFS1 Consumer Selection */ 103 __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< TIMER0 DTIFS2 Consumer Selection */ 104 __IOM uint32_t CONSUMER_TIMER1_CC0; /**< TIMER1 CC0 Consumer Selection */ 105 __IOM uint32_t CONSUMER_TIMER1_CC1; /**< TIMER1 CC1 Consumer Selection */ 106 __IOM uint32_t CONSUMER_TIMER1_CC2; /**< TIMER1 CC2 Consumer Selection */ 107 __IOM uint32_t CONSUMER_TIMER1_DTI; /**< TIMER1 DTI Consumer Selection */ 108 __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< TIMER1 DTIFS1 Consumer Selection */ 109 __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< TIMER1 DTIFS2 Consumer Selection */ 110 __IOM uint32_t CONSUMER_TIMER2_CC0; /**< TIMER2 CC0 Consumer Selection */ 111 __IOM uint32_t CONSUMER_TIMER2_CC1; /**< TIMER2 CC1 Consumer Selection */ 112 __IOM uint32_t CONSUMER_TIMER2_CC2; /**< TIMER2 CC2 Consumer Selection */ 113 __IOM uint32_t CONSUMER_TIMER2_DTI; /**< TIMER2 DTI Consumer Selection */ 114 __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< TIMER2 DTIFS1 Consumer Selection */ 115 __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< TIMER2 DTIFS2 Consumer Selection */ 116 __IOM uint32_t CONSUMER_TIMER3_CC0; /**< TIMER3 CC0 Consumer Selection */ 117 __IOM uint32_t CONSUMER_TIMER3_CC1; /**< TIMER3 CC1 Consumer Selection */ 118 __IOM uint32_t CONSUMER_TIMER3_CC2; /**< TIMER3 CC2 Consumer Selection */ 119 __IOM uint32_t CONSUMER_TIMER3_DTI; /**< TIMER3 DTI Consumer Selection */ 120 __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< TIMER3 DTIFS1 Consumer Selection */ 121 __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< TIMER3 DTIFS2 Consumer Selection */ 122 __IOM uint32_t CONSUMER_TIMER4_CC0; /**< TIMER4 CC0 Consumer Selection */ 123 __IOM uint32_t CONSUMER_TIMER4_CC1; /**< TIMER4 CC1 Consumer Selection */ 124 __IOM uint32_t CONSUMER_TIMER4_CC2; /**< TIMER4 CC2 Consumer Selection */ 125 __IOM uint32_t CONSUMER_TIMER4_DTI; /**< TIMER4 DTI Consumer Selection */ 126 __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< TIMER4 DTIFS1 Consumer Selection */ 127 __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< TIMER4 DTIFS2 Consumer Selection */ 128 __IOM uint32_t CONSUMER_USART0_CLK; /**< USART0 CLK Consumer Selection */ 129 __IOM uint32_t CONSUMER_USART0_IR; /**< USART0 IR Consumer Selection */ 130 __IOM uint32_t CONSUMER_USART0_RX; /**< USART0 RX Consumer Selection */ 131 __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< USART0 TRIGGER Consumer Selection */ 132 __IOM uint32_t CONSUMER_USART1_CLK; /**< USART1 CLK Consumer Selection */ 133 __IOM uint32_t CONSUMER_USART1_IR; /**< USART1 IR Consumer Selection */ 134 __IOM uint32_t CONSUMER_USART1_RX; /**< USART1 RX Consumer Selection */ 135 __IOM uint32_t CONSUMER_USART1_TRIGGER; /**< USART1 TRIGGER Consumer Selection */ 136 __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< WDOG0 SRC0 Consumer Selection */ 137 __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< WDOG0 SRC1 Consumer Selection */ 138 uint32_t RESERVED5[917U]; /**< Reserved for future use */ 139 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 140 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 141 __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ 142 __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ 143 __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ 144 __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ 145 PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[12U]; /**< Async Channel registers */ 146 PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ 147 __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CMU CALDN Consumer Selection */ 148 __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CMU CALUP Consumer Selection */ 149 uint32_t RESERVED7[1U]; /**< Reserved for future use */ 150 __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< IADC0 SCANTRIGGER Consumer Selection */ 151 __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< IADC0 SINGLETRIGGER Consumer Selection */ 152 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 Consumer Selection */ 153 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer Selection */ 154 __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< LETIMER CLEAR Consumer Selection */ 155 __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< LETIMER START Consumer Selection */ 156 __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< LETIMER STOP Consumer Selection */ 157 __IOM uint32_t CONSUMER_EUART0_RX_SET; /**< EUART0 RX consumer register */ 158 __IOM uint32_t CONSUMER_EUART0_TRIGGER_SET; /**< EUART0 TRIGGER Consumer register */ 159 __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< MODEM DIN Consumer Selection */ 160 uint32_t RESERVED8[2U]; /**< Reserved for future use */ 161 uint32_t RESERVED9[11U]; /**< Reserved for future use */ 162 __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< RAC CLR Consumer Selection */ 163 __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< RAC CTIIN0 Consumer Selection */ 164 __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< RAC CTIIN1 Consumer Selection */ 165 __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< RAC CTIIN2 Consumer Selection */ 166 __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< RAC CTIIN3 Consumer Selection */ 167 __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< RAC FORCETX Consumer Selection */ 168 __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RAC RXDIS Consumer Selection */ 169 __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RAC RXEN Consumer Selection */ 170 __IOM uint32_t CONSUMER_RAC_SEQ_SET; /**< RAC SEQ Consumer Selection */ 171 __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< RAC TXEN Consumer Selection */ 172 __IOM uint32_t CONSUMER_RTCC_CC0_SET; /**< RTCC CC0 Consumer Selection */ 173 __IOM uint32_t CONSUMER_RTCC_CC1_SET; /**< RTCC CC1 Consumer Selection */ 174 __IOM uint32_t CONSUMER_RTCC_CC2_SET; /**< RTCC CC2 Consumer Selection */ 175 uint32_t RESERVED10[1U]; /**< Reserved for future use */ 176 __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI0 Consumer Selection */ 177 __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI1 Consumer Selection */ 178 __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI2 Consumer Selection */ 179 __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI3 Consumer Selection */ 180 __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer Selection */ 181 __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< TIMER0 CC0 Consumer Selection */ 182 __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< TIMER0 CC1 Consumer Selection */ 183 __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< TIMER0 CC2 Consumer Selection */ 184 __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< TIMER0 DTI Consumer Selection */ 185 __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< TIMER0 DTIFS1 Consumer Selection */ 186 __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< TIMER0 DTIFS2 Consumer Selection */ 187 __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< TIMER1 CC0 Consumer Selection */ 188 __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< TIMER1 CC1 Consumer Selection */ 189 __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< TIMER1 CC2 Consumer Selection */ 190 __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< TIMER1 DTI Consumer Selection */ 191 __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< TIMER1 DTIFS1 Consumer Selection */ 192 __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< TIMER1 DTIFS2 Consumer Selection */ 193 __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< TIMER2 CC0 Consumer Selection */ 194 __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< TIMER2 CC1 Consumer Selection */ 195 __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< TIMER2 CC2 Consumer Selection */ 196 __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< TIMER2 DTI Consumer Selection */ 197 __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< TIMER2 DTIFS1 Consumer Selection */ 198 __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< TIMER2 DTIFS2 Consumer Selection */ 199 __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< TIMER3 CC0 Consumer Selection */ 200 __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< TIMER3 CC1 Consumer Selection */ 201 __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< TIMER3 CC2 Consumer Selection */ 202 __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< TIMER3 DTI Consumer Selection */ 203 __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< TIMER3 DTIFS1 Consumer Selection */ 204 __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< TIMER3 DTIFS2 Consumer Selection */ 205 __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< TIMER4 CC0 Consumer Selection */ 206 __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< TIMER4 CC1 Consumer Selection */ 207 __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< TIMER4 CC2 Consumer Selection */ 208 __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< TIMER4 DTI Consumer Selection */ 209 __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< TIMER4 DTIFS1 Consumer Selection */ 210 __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< TIMER4 DTIFS2 Consumer Selection */ 211 __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< USART0 CLK Consumer Selection */ 212 __IOM uint32_t CONSUMER_USART0_IR_SET; /**< USART0 IR Consumer Selection */ 213 __IOM uint32_t CONSUMER_USART0_RX_SET; /**< USART0 RX Consumer Selection */ 214 __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< USART0 TRIGGER Consumer Selection */ 215 __IOM uint32_t CONSUMER_USART1_CLK_SET; /**< USART1 CLK Consumer Selection */ 216 __IOM uint32_t CONSUMER_USART1_IR_SET; /**< USART1 IR Consumer Selection */ 217 __IOM uint32_t CONSUMER_USART1_RX_SET; /**< USART1 RX Consumer Selection */ 218 __IOM uint32_t CONSUMER_USART1_TRIGGER_SET; /**< USART1 TRIGGER Consumer Selection */ 219 __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< WDOG0 SRC0 Consumer Selection */ 220 __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< WDOG0 SRC1 Consumer Selection */ 221 uint32_t RESERVED11[917U]; /**< Reserved for future use */ 222 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 223 uint32_t RESERVED12[1U]; /**< Reserved for future use */ 224 __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ 225 __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ 226 __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ 227 __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ 228 PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[12U]; /**< Async Channel registers */ 229 PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ 230 __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CMU CALDN Consumer Selection */ 231 __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CMU CALUP Consumer Selection */ 232 uint32_t RESERVED13[1U]; /**< Reserved for future use */ 233 __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< IADC0 SCANTRIGGER Consumer Selection */ 234 __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< IADC0 SINGLETRIGGER Consumer Selection */ 235 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 Consumer Selection */ 236 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer Selection */ 237 __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< LETIMER CLEAR Consumer Selection */ 238 __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< LETIMER START Consumer Selection */ 239 __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< LETIMER STOP Consumer Selection */ 240 __IOM uint32_t CONSUMER_EUART0_RX_CLR; /**< EUART0 RX consumer register */ 241 __IOM uint32_t CONSUMER_EUART0_TRIGGER_CLR; /**< EUART0 TRIGGER Consumer register */ 242 __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< MODEM DIN Consumer Selection */ 243 uint32_t RESERVED14[2U]; /**< Reserved for future use */ 244 uint32_t RESERVED15[11U]; /**< Reserved for future use */ 245 __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< RAC CLR Consumer Selection */ 246 __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< RAC CTIIN0 Consumer Selection */ 247 __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< RAC CTIIN1 Consumer Selection */ 248 __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< RAC CTIIN2 Consumer Selection */ 249 __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< RAC CTIIN3 Consumer Selection */ 250 __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< RAC FORCETX Consumer Selection */ 251 __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RAC RXDIS Consumer Selection */ 252 __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RAC RXEN Consumer Selection */ 253 __IOM uint32_t CONSUMER_RAC_SEQ_CLR; /**< RAC SEQ Consumer Selection */ 254 __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< RAC TXEN Consumer Selection */ 255 __IOM uint32_t CONSUMER_RTCC_CC0_CLR; /**< RTCC CC0 Consumer Selection */ 256 __IOM uint32_t CONSUMER_RTCC_CC1_CLR; /**< RTCC CC1 Consumer Selection */ 257 __IOM uint32_t CONSUMER_RTCC_CC2_CLR; /**< RTCC CC2 Consumer Selection */ 258 uint32_t RESERVED16[1U]; /**< Reserved for future use */ 259 __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI0 Consumer Selection */ 260 __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI1 Consumer Selection */ 261 __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI2 Consumer Selection */ 262 __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI3 Consumer Selection */ 263 __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer Selection */ 264 __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< TIMER0 CC0 Consumer Selection */ 265 __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< TIMER0 CC1 Consumer Selection */ 266 __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< TIMER0 CC2 Consumer Selection */ 267 __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< TIMER0 DTI Consumer Selection */ 268 __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< TIMER0 DTIFS1 Consumer Selection */ 269 __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< TIMER0 DTIFS2 Consumer Selection */ 270 __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< TIMER1 CC0 Consumer Selection */ 271 __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< TIMER1 CC1 Consumer Selection */ 272 __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< TIMER1 CC2 Consumer Selection */ 273 __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< TIMER1 DTI Consumer Selection */ 274 __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< TIMER1 DTIFS1 Consumer Selection */ 275 __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< TIMER1 DTIFS2 Consumer Selection */ 276 __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< TIMER2 CC0 Consumer Selection */ 277 __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< TIMER2 CC1 Consumer Selection */ 278 __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< TIMER2 CC2 Consumer Selection */ 279 __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< TIMER2 DTI Consumer Selection */ 280 __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< TIMER2 DTIFS1 Consumer Selection */ 281 __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< TIMER2 DTIFS2 Consumer Selection */ 282 __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< TIMER3 CC0 Consumer Selection */ 283 __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< TIMER3 CC1 Consumer Selection */ 284 __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< TIMER3 CC2 Consumer Selection */ 285 __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< TIMER3 DTI Consumer Selection */ 286 __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< TIMER3 DTIFS1 Consumer Selection */ 287 __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< TIMER3 DTIFS2 Consumer Selection */ 288 __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< TIMER4 CC0 Consumer Selection */ 289 __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< TIMER4 CC1 Consumer Selection */ 290 __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< TIMER4 CC2 Consumer Selection */ 291 __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< TIMER4 DTI Consumer Selection */ 292 __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< TIMER4 DTIFS1 Consumer Selection */ 293 __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< TIMER4 DTIFS2 Consumer Selection */ 294 __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< USART0 CLK Consumer Selection */ 295 __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< USART0 IR Consumer Selection */ 296 __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< USART0 RX Consumer Selection */ 297 __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< USART0 TRIGGER Consumer Selection */ 298 __IOM uint32_t CONSUMER_USART1_CLK_CLR; /**< USART1 CLK Consumer Selection */ 299 __IOM uint32_t CONSUMER_USART1_IR_CLR; /**< USART1 IR Consumer Selection */ 300 __IOM uint32_t CONSUMER_USART1_RX_CLR; /**< USART1 RX Consumer Selection */ 301 __IOM uint32_t CONSUMER_USART1_TRIGGER_CLR; /**< USART1 TRIGGER Consumer Selection */ 302 __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< WDOG0 SRC0 Consumer Selection */ 303 __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< WDOG0 SRC1 Consumer Selection */ 304 uint32_t RESERVED17[917U]; /**< Reserved for future use */ 305 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 306 uint32_t RESERVED18[1U]; /**< Reserved for future use */ 307 __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ 308 __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ 309 __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ 310 __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ 311 PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[12U]; /**< Async Channel registers */ 312 PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ 313 __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CMU CALDN Consumer Selection */ 314 __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CMU CALUP Consumer Selection */ 315 uint32_t RESERVED19[1U]; /**< Reserved for future use */ 316 __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< IADC0 SCANTRIGGER Consumer Selection */ 317 __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< IADC0 SINGLETRIGGER Consumer Selection */ 318 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 Consumer Selection */ 319 __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer Selection */ 320 __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< LETIMER CLEAR Consumer Selection */ 321 __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< LETIMER START Consumer Selection */ 322 __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< LETIMER STOP Consumer Selection */ 323 __IOM uint32_t CONSUMER_EUART0_RX_TGL; /**< EUART0 RX consumer register */ 324 __IOM uint32_t CONSUMER_EUART0_TRIGGER_TGL; /**< EUART0 TRIGGER Consumer register */ 325 __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< MODEM DIN Consumer Selection */ 326 uint32_t RESERVED20[2U]; /**< Reserved for future use */ 327 uint32_t RESERVED21[11U]; /**< Reserved for future use */ 328 __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< RAC CLR Consumer Selection */ 329 __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< RAC CTIIN0 Consumer Selection */ 330 __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< RAC CTIIN1 Consumer Selection */ 331 __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< RAC CTIIN2 Consumer Selection */ 332 __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< RAC CTIIN3 Consumer Selection */ 333 __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< RAC FORCETX Consumer Selection */ 334 __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RAC RXDIS Consumer Selection */ 335 __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RAC RXEN Consumer Selection */ 336 __IOM uint32_t CONSUMER_RAC_SEQ_TGL; /**< RAC SEQ Consumer Selection */ 337 __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< RAC TXEN Consumer Selection */ 338 __IOM uint32_t CONSUMER_RTCC_CC0_TGL; /**< RTCC CC0 Consumer Selection */ 339 __IOM uint32_t CONSUMER_RTCC_CC1_TGL; /**< RTCC CC1 Consumer Selection */ 340 __IOM uint32_t CONSUMER_RTCC_CC2_TGL; /**< RTCC CC2 Consumer Selection */ 341 uint32_t RESERVED22[1U]; /**< Reserved for future use */ 342 __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI0 Consumer Selection */ 343 __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI1 Consumer Selection */ 344 __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI2 Consumer Selection */ 345 __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI3 Consumer Selection */ 346 __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer Selection */ 347 __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< TIMER0 CC0 Consumer Selection */ 348 __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< TIMER0 CC1 Consumer Selection */ 349 __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< TIMER0 CC2 Consumer Selection */ 350 __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< TIMER0 DTI Consumer Selection */ 351 __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< TIMER0 DTIFS1 Consumer Selection */ 352 __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< TIMER0 DTIFS2 Consumer Selection */ 353 __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< TIMER1 CC0 Consumer Selection */ 354 __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< TIMER1 CC1 Consumer Selection */ 355 __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< TIMER1 CC2 Consumer Selection */ 356 __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< TIMER1 DTI Consumer Selection */ 357 __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< TIMER1 DTIFS1 Consumer Selection */ 358 __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< TIMER1 DTIFS2 Consumer Selection */ 359 __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< TIMER2 CC0 Consumer Selection */ 360 __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< TIMER2 CC1 Consumer Selection */ 361 __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< TIMER2 CC2 Consumer Selection */ 362 __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< TIMER2 DTI Consumer Selection */ 363 __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< TIMER2 DTIFS1 Consumer Selection */ 364 __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< TIMER2 DTIFS2 Consumer Selection */ 365 __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< TIMER3 CC0 Consumer Selection */ 366 __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< TIMER3 CC1 Consumer Selection */ 367 __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< TIMER3 CC2 Consumer Selection */ 368 __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< TIMER3 DTI Consumer Selection */ 369 __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< TIMER3 DTIFS1 Consumer Selection */ 370 __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< TIMER3 DTIFS2 Consumer Selection */ 371 __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< TIMER4 CC0 Consumer Selection */ 372 __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< TIMER4 CC1 Consumer Selection */ 373 __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< TIMER4 CC2 Consumer Selection */ 374 __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< TIMER4 DTI Consumer Selection */ 375 __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< TIMER4 DTIFS1 Consumer Selection */ 376 __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< TIMER4 DTIFS2 Consumer Selection */ 377 __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< USART0 CLK Consumer Selection */ 378 __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< USART0 IR Consumer Selection */ 379 __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< USART0 RX Consumer Selection */ 380 __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< USART0 TRIGGER Consumer Selection */ 381 __IOM uint32_t CONSUMER_USART1_CLK_TGL; /**< USART1 CLK Consumer Selection */ 382 __IOM uint32_t CONSUMER_USART1_IR_TGL; /**< USART1 IR Consumer Selection */ 383 __IOM uint32_t CONSUMER_USART1_RX_TGL; /**< USART1 RX Consumer Selection */ 384 __IOM uint32_t CONSUMER_USART1_TRIGGER_TGL; /**< USART1 TRIGGER Consumer Selection */ 385 __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< WDOG0 SRC0 Consumer Selection */ 386 __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< WDOG0 SRC1 Consumer Selection */ 387 } PRS_TypeDef; 388 /** @} End of group EFR32BG22_PRS */ 389 390 /**************************************************************************//** 391 * @addtogroup EFR32BG22_PRS 392 * @{ 393 * @defgroup EFR32BG22_PRS_BitFields PRS Bit Fields 394 * @{ 395 *****************************************************************************/ 396 397 /* Bit fields for PRS IPVERSION */ 398 #define _PRS_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PRS_IPVERSION */ 399 #define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ 400 #define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ 401 #define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ 402 #define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PRS_IPVERSION */ 403 #define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ 404 405 /* Bit fields for PRS ASYNC_SWPULSE */ 406 #define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ 407 #define _PRS_ASYNC_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWPULSE */ 408 #define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ 409 #define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ 410 #define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ 411 #define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 412 #define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 413 #define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ 414 #define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ 415 #define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ 416 #define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 417 #define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 418 #define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ 419 #define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ 420 #define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ 421 #define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 422 #define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 423 #define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ 424 #define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ 425 #define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ 426 #define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 427 #define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 428 #define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ 429 #define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ 430 #define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ 431 #define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 432 #define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 433 #define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ 434 #define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ 435 #define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ 436 #define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 437 #define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 438 #define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ 439 #define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ 440 #define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ 441 #define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 442 #define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 443 #define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ 444 #define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ 445 #define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ 446 #define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 447 #define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 448 #define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ 449 #define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ 450 #define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ 451 #define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 452 #define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 453 #define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ 454 #define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ 455 #define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ 456 #define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 457 #define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 458 #define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ 459 #define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ 460 #define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ 461 #define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 462 #define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 463 #define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ 464 #define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ 465 #define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ 466 #define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ 467 #define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ 468 469 /* Bit fields for PRS ASYNC_SWLEVEL */ 470 #define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ 471 #define _PRS_ASYNC_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ 472 #define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ 473 #define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ 474 #define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ 475 #define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 476 #define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 477 #define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ 478 #define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ 479 #define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ 480 #define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 481 #define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 482 #define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ 483 #define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ 484 #define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ 485 #define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 486 #define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 487 #define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ 488 #define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ 489 #define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ 490 #define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 491 #define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 492 #define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ 493 #define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ 494 #define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ 495 #define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 496 #define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 497 #define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ 498 #define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ 499 #define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ 500 #define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 501 #define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 502 #define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ 503 #define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ 504 #define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ 505 #define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 506 #define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 507 #define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ 508 #define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ 509 #define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ 510 #define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 511 #define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 512 #define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ 513 #define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ 514 #define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ 515 #define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 516 #define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 517 #define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ 518 #define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ 519 #define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ 520 #define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 521 #define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 522 #define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ 523 #define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ 524 #define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ 525 #define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 526 #define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 527 #define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ 528 #define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ 529 #define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ 530 #define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ 531 #define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ 532 533 /* Bit fields for PRS ASYNC_PEEK */ 534 #define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ 535 #define _PRS_ASYNC_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_PEEK */ 536 #define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ 537 #define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ 538 #define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ 539 #define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 540 #define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 541 #define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ 542 #define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ 543 #define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ 544 #define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 545 #define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 546 #define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ 547 #define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ 548 #define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ 549 #define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 550 #define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 551 #define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ 552 #define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ 553 #define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ 554 #define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 555 #define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 556 #define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ 557 #define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ 558 #define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ 559 #define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 560 #define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 561 #define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ 562 #define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ 563 #define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ 564 #define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 565 #define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 566 #define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ 567 #define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ 568 #define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ 569 #define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 570 #define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 571 #define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ 572 #define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ 573 #define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ 574 #define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 575 #define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 576 #define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ 577 #define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ 578 #define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ 579 #define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 580 #define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 581 #define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ 582 #define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ 583 #define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ 584 #define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 585 #define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 586 #define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ 587 #define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ 588 #define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ 589 #define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 590 #define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 591 #define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ 592 #define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ 593 #define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ 594 #define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ 595 #define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ 596 597 /* Bit fields for PRS SYNC_PEEK */ 598 #define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ 599 #define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ 600 #define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ 601 #define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ 602 #define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ 603 #define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ 604 #define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ 605 #define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ 606 #define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ 607 #define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ 608 #define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ 609 #define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ 610 #define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ 611 #define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ 612 #define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ 613 #define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ 614 #define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ 615 #define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ 616 #define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ 617 #define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ 618 #define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ 619 #define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ 620 621 /* Bit fields for PRS ASYNC_CH_CTRL */ 622 #define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ 623 #define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ 624 #define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ 625 #define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ 626 #define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ 627 #define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ 628 #define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ 629 #define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ 630 #define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ 631 #define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ 632 #define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ 633 #define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ 634 #define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ 635 #define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ 636 #define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ 637 #define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ 638 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ 639 #define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ 640 #define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ 641 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ 642 #define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ 643 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ 644 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ 645 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ 646 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ 647 #define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ 648 #define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ 649 #define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ 650 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ 651 #define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ 652 #define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ 653 #define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ 654 #define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ 655 #define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ 656 #define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ 657 #define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ 658 #define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ 659 #define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ 660 #define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ 661 #define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ 662 #define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ 663 #define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ 664 #define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ 665 #define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ 666 #define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ 667 #define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ 668 #define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ 669 #define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ 670 #define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ 671 #define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ 672 #define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ 673 #define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ 674 675 /* Bit fields for PRS SYNC_CH_CTRL */ 676 #define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ 677 #define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ 678 #define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ 679 #define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ 680 #define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ 681 #define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ 682 #define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ 683 #define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ 684 #define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ 685 #define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ 686 687 /* Bit fields for PRS CONSUMER_CMU_CALDN */ 688 #define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ 689 #define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ 690 #define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 691 #define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 692 #define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ 693 #define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ 694 695 /* Bit fields for PRS CONSUMER_CMU_CALUP */ 696 #define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ 697 #define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ 698 #define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 699 #define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 700 #define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ 701 #define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ 702 703 /* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ 704 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ 705 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ 706 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 707 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 708 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ 709 #define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ 710 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 711 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 712 #define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ 713 #define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ 714 715 /* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ 716 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ 717 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ 718 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 719 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 720 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ 721 #define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ 722 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 723 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 724 #define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ 725 #define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ 726 727 /* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ 728 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ 729 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ 730 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 731 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 732 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ 733 #define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ 734 735 /* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ 736 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ 737 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ 738 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 739 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 740 #define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ 741 #define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ 742 743 /* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ 744 #define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ 745 #define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ 746 #define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 747 #define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 748 #define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ 749 #define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ 750 751 /* Bit fields for PRS CONSUMER_LETIMER0_START */ 752 #define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ 753 #define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ 754 #define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 755 #define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 756 #define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ 757 #define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ 758 759 /* Bit fields for PRS CONSUMER_LETIMER0_STOP */ 760 #define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ 761 #define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ 762 #define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 763 #define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 764 #define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ 765 #define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ 766 767 /* Bit fields for PRS CONSUMER_EUART0_RX */ 768 #define _PRS_CONSUMER_EUART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUART0_RX */ 769 #define _PRS_CONSUMER_EUART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUART0_RX */ 770 #define _PRS_CONSUMER_EUART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 771 #define _PRS_CONSUMER_EUART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 772 #define _PRS_CONSUMER_EUART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUART0_RX */ 773 #define PRS_CONSUMER_EUART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUART0_RX*/ 774 775 /* Bit fields for PRS CONSUMER_EUART0_TRIGGER */ 776 #define _PRS_CONSUMER_EUART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUART0_TRIGGER*/ 777 #define _PRS_CONSUMER_EUART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUART0_TRIGGER */ 778 #define _PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 779 #define _PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 780 #define _PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUART0_TRIGGER*/ 781 #define PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUART0_TRIGGER*/ 782 783 /* Bit fields for PRS CONSUMER_MODEM_DIN */ 784 #define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ 785 #define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ 786 #define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 787 #define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 788 #define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ 789 #define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ 790 791 /* Bit fields for PRS CONSUMER_RAC_CLR */ 792 #define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ 793 #define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ 794 #define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 795 #define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 796 #define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ 797 #define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ 798 799 /* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ 800 #define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ 801 #define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ 802 #define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 803 #define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 804 #define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ 805 #define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ 806 807 /* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ 808 #define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ 809 #define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ 810 #define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 811 #define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 812 #define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ 813 #define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ 814 815 /* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ 816 #define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ 817 #define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ 818 #define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 819 #define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 820 #define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ 821 #define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ 822 823 /* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ 824 #define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ 825 #define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ 826 #define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 827 #define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 828 #define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ 829 #define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ 830 831 /* Bit fields for PRS CONSUMER_RAC_FORCETX */ 832 #define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ 833 #define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ 834 #define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 835 #define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 836 #define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ 837 #define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ 838 839 /* Bit fields for PRS CONSUMER_RAC_RXDIS */ 840 #define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ 841 #define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ 842 #define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 843 #define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 844 #define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ 845 #define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ 846 847 /* Bit fields for PRS CONSUMER_RAC_RXEN */ 848 #define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ 849 #define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ 850 #define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 851 #define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 852 #define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ 853 #define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ 854 855 /* Bit fields for PRS CONSUMER_RAC_SEQ */ 856 #define _PRS_CONSUMER_RAC_SEQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_SEQ */ 857 #define _PRS_CONSUMER_RAC_SEQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_SEQ */ 858 #define _PRS_CONSUMER_RAC_SEQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 859 #define _PRS_CONSUMER_RAC_SEQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 860 #define _PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_SEQ */ 861 #define PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_SEQ*/ 862 863 /* Bit fields for PRS CONSUMER_RAC_TXEN */ 864 #define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ 865 #define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ 866 #define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 867 #define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 868 #define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ 869 #define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ 870 871 /* Bit fields for PRS CONSUMER_RTCC_CC0 */ 872 #define _PRS_CONSUMER_RTCC_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC0 */ 873 #define _PRS_CONSUMER_RTCC_CC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC0 */ 874 #define _PRS_CONSUMER_RTCC_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 875 #define _PRS_CONSUMER_RTCC_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 876 #define _PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC0 */ 877 #define PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC0*/ 878 879 /* Bit fields for PRS CONSUMER_RTCC_CC1 */ 880 #define _PRS_CONSUMER_RTCC_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC1 */ 881 #define _PRS_CONSUMER_RTCC_CC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC1 */ 882 #define _PRS_CONSUMER_RTCC_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 883 #define _PRS_CONSUMER_RTCC_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 884 #define _PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC1 */ 885 #define PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC1*/ 886 887 /* Bit fields for PRS CONSUMER_RTCC_CC2 */ 888 #define _PRS_CONSUMER_RTCC_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC2 */ 889 #define _PRS_CONSUMER_RTCC_CC2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC2 */ 890 #define _PRS_CONSUMER_RTCC_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 891 #define _PRS_CONSUMER_RTCC_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 892 #define _PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC2 */ 893 #define PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC2*/ 894 895 /* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ 896 #define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ 897 #define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ 898 #define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 899 #define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 900 #define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ 901 #define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ 902 903 /* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ 904 #define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ 905 #define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ 906 #define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 907 #define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 908 #define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ 909 #define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ 910 911 /* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ 912 #define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ 913 #define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ 914 #define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 915 #define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 916 #define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ 917 #define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ 918 919 /* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ 920 #define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ 921 #define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ 922 #define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 923 #define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 924 #define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ 925 #define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ 926 927 /* Bit fields for PRS CONSUMER_CORE_M33RXEV */ 928 #define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ 929 #define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ 930 #define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 931 #define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 932 #define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ 933 #define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ 934 935 /* Bit fields for PRS CONSUMER_TIMER0_CC0 */ 936 #define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ 937 #define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ 938 #define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 939 #define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 940 #define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ 941 #define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ 942 #define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 943 #define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 944 #define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ 945 #define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ 946 947 /* Bit fields for PRS CONSUMER_TIMER0_CC1 */ 948 #define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ 949 #define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ 950 #define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 951 #define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 952 #define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ 953 #define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ 954 #define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 955 #define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 956 #define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ 957 #define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ 958 959 /* Bit fields for PRS CONSUMER_TIMER0_CC2 */ 960 #define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ 961 #define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ 962 #define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 963 #define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 964 #define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ 965 #define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ 966 #define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 967 #define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 968 #define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ 969 #define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ 970 971 /* Bit fields for PRS CONSUMER_TIMER0_DTI */ 972 #define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ 973 #define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ 974 #define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 975 #define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 976 #define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ 977 #define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ 978 979 /* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ 980 #define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ 981 #define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ 982 #define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 983 #define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 984 #define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ 985 #define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ 986 987 /* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ 988 #define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ 989 #define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ 990 #define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 991 #define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 992 #define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ 993 #define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ 994 995 /* Bit fields for PRS CONSUMER_TIMER1_CC0 */ 996 #define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ 997 #define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ 998 #define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 999 #define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1000 #define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ 1001 #define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ 1002 #define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1003 #define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1004 #define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ 1005 #define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ 1006 1007 /* Bit fields for PRS CONSUMER_TIMER1_CC1 */ 1008 #define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ 1009 #define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ 1010 #define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1011 #define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1012 #define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ 1013 #define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ 1014 #define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1015 #define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1016 #define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ 1017 #define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ 1018 1019 /* Bit fields for PRS CONSUMER_TIMER1_CC2 */ 1020 #define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ 1021 #define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ 1022 #define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1023 #define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1024 #define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ 1025 #define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ 1026 #define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1027 #define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1028 #define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ 1029 #define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ 1030 1031 /* Bit fields for PRS CONSUMER_TIMER1_DTI */ 1032 #define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ 1033 #define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ 1034 #define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1035 #define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1036 #define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ 1037 #define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ 1038 1039 /* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ 1040 #define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ 1041 #define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ 1042 #define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1043 #define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1044 #define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ 1045 #define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ 1046 1047 /* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ 1048 #define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ 1049 #define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ 1050 #define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1051 #define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1052 #define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ 1053 #define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ 1054 1055 /* Bit fields for PRS CONSUMER_TIMER2_CC0 */ 1056 #define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ 1057 #define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ 1058 #define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1059 #define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1060 #define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ 1061 #define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ 1062 #define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1063 #define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1064 #define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ 1065 #define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ 1066 1067 /* Bit fields for PRS CONSUMER_TIMER2_CC1 */ 1068 #define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ 1069 #define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ 1070 #define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1071 #define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1072 #define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ 1073 #define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ 1074 #define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1075 #define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1076 #define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ 1077 #define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ 1078 1079 /* Bit fields for PRS CONSUMER_TIMER2_CC2 */ 1080 #define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ 1081 #define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ 1082 #define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1083 #define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1084 #define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ 1085 #define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ 1086 #define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1087 #define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1088 #define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ 1089 #define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ 1090 1091 /* Bit fields for PRS CONSUMER_TIMER2_DTI */ 1092 #define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ 1093 #define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ 1094 #define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1095 #define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1096 #define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ 1097 #define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ 1098 1099 /* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ 1100 #define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ 1101 #define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ 1102 #define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1103 #define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1104 #define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ 1105 #define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ 1106 1107 /* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ 1108 #define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ 1109 #define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ 1110 #define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1111 #define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1112 #define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ 1113 #define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ 1114 1115 /* Bit fields for PRS CONSUMER_TIMER3_CC0 */ 1116 #define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ 1117 #define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ 1118 #define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1119 #define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1120 #define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ 1121 #define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ 1122 #define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1123 #define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1124 #define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ 1125 #define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ 1126 1127 /* Bit fields for PRS CONSUMER_TIMER3_CC1 */ 1128 #define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ 1129 #define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ 1130 #define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1131 #define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1132 #define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ 1133 #define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ 1134 #define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1135 #define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1136 #define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ 1137 #define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ 1138 1139 /* Bit fields for PRS CONSUMER_TIMER3_CC2 */ 1140 #define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ 1141 #define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ 1142 #define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1143 #define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1144 #define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ 1145 #define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ 1146 #define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1147 #define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1148 #define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ 1149 #define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ 1150 1151 /* Bit fields for PRS CONSUMER_TIMER3_DTI */ 1152 #define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ 1153 #define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ 1154 #define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1155 #define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1156 #define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ 1157 #define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ 1158 1159 /* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ 1160 #define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ 1161 #define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ 1162 #define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1163 #define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1164 #define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ 1165 #define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ 1166 1167 /* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ 1168 #define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ 1169 #define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ 1170 #define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1171 #define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1172 #define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ 1173 #define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ 1174 1175 /* Bit fields for PRS CONSUMER_TIMER4_CC0 */ 1176 #define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ 1177 #define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ 1178 #define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1179 #define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1180 #define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ 1181 #define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ 1182 #define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1183 #define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1184 #define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ 1185 #define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ 1186 1187 /* Bit fields for PRS CONSUMER_TIMER4_CC1 */ 1188 #define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ 1189 #define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ 1190 #define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1191 #define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1192 #define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ 1193 #define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ 1194 #define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1195 #define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1196 #define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ 1197 #define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ 1198 1199 /* Bit fields for PRS CONSUMER_TIMER4_CC2 */ 1200 #define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ 1201 #define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ 1202 #define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1203 #define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1204 #define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ 1205 #define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ 1206 #define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ 1207 #define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ 1208 #define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ 1209 #define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ 1210 1211 /* Bit fields for PRS CONSUMER_TIMER4_DTI */ 1212 #define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ 1213 #define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ 1214 #define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1215 #define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1216 #define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ 1217 #define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ 1218 1219 /* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ 1220 #define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ 1221 #define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ 1222 #define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1223 #define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1224 #define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ 1225 #define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ 1226 1227 /* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ 1228 #define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ 1229 #define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ 1230 #define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1231 #define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1232 #define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ 1233 #define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ 1234 1235 /* Bit fields for PRS CONSUMER_USART0_CLK */ 1236 #define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ 1237 #define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ 1238 #define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1239 #define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1240 #define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ 1241 #define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ 1242 1243 /* Bit fields for PRS CONSUMER_USART0_IR */ 1244 #define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ 1245 #define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ 1246 #define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1247 #define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1248 #define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ 1249 #define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ 1250 1251 /* Bit fields for PRS CONSUMER_USART0_RX */ 1252 #define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ 1253 #define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ 1254 #define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1255 #define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1256 #define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ 1257 #define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ 1258 1259 /* Bit fields for PRS CONSUMER_USART0_TRIGGER */ 1260 #define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ 1261 #define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ 1262 #define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1263 #define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1264 #define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ 1265 #define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ 1266 1267 /* Bit fields for PRS CONSUMER_USART1_CLK */ 1268 #define _PRS_CONSUMER_USART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_CLK */ 1269 #define _PRS_CONSUMER_USART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_CLK */ 1270 #define _PRS_CONSUMER_USART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1271 #define _PRS_CONSUMER_USART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1272 #define _PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_CLK */ 1273 #define PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_CLK*/ 1274 1275 /* Bit fields for PRS CONSUMER_USART1_IR */ 1276 #define _PRS_CONSUMER_USART1_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_IR */ 1277 #define _PRS_CONSUMER_USART1_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_IR */ 1278 #define _PRS_CONSUMER_USART1_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1279 #define _PRS_CONSUMER_USART1_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1280 #define _PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_IR */ 1281 #define PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_IR*/ 1282 1283 /* Bit fields for PRS CONSUMER_USART1_RX */ 1284 #define _PRS_CONSUMER_USART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_RX */ 1285 #define _PRS_CONSUMER_USART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_RX */ 1286 #define _PRS_CONSUMER_USART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1287 #define _PRS_CONSUMER_USART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1288 #define _PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_RX */ 1289 #define PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_RX*/ 1290 1291 /* Bit fields for PRS CONSUMER_USART1_TRIGGER */ 1292 #define _PRS_CONSUMER_USART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_TRIGGER*/ 1293 #define _PRS_CONSUMER_USART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_TRIGGER */ 1294 #define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1295 #define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1296 #define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ 1297 #define PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ 1298 1299 /* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ 1300 #define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ 1301 #define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ 1302 #define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1303 #define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1304 #define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ 1305 #define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ 1306 1307 /* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ 1308 #define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ 1309 #define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ 1310 #define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ 1311 #define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ 1312 #define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ 1313 #define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ 1314 1315 /** @} End of group EFR32BG22_PRS_BitFields */ 1316 /** @} End of group EFR32BG22_PRS */ 1317 /** @} End of group Parts */ 1318 1319 #endif // EFR32BG22_PRS_H 1320
