1 /***************************************************************************//** 2 * @file 3 * @brief EFM32HG_MTB register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32HG_MTB 43 * @{ 44 * @brief EFM32HG_MTB Register Declaration 45 ******************************************************************************/ 46 typedef struct { 47 __IOM uint32_t POSITION; /**< MTB Trace Position Register. */ 48 __IOM uint32_t MASTER; /**< MTB Trace Control Register */ 49 __IOM uint32_t FLOW; /**< MTB Trace Flow Register */ 50 __IOM uint32_t BASE; /**< MTB Trace Base Register */ 51 } MTB_TypeDef; /**< MTB Register Declaration *//** @} */ 52 53 /***************************************************************************//** 54 * @defgroup EFM32HG_MTB_BitFields 55 * @{ 56 ******************************************************************************/ 57 58 /* Bit fields for MTB POSITION */ 59 #define _MTB_POSITION_RESETVALUE 0x00000000UL /**< Default value for MTB_POSITION */ 60 #define _MTB_POSITION_MASK 0xFFFFFFFCUL /**< Mask for MTB_POSITION */ 61 #define MTB_POSITION_WRAP (0x1UL << 2) /**< Trace wrap bit. */ 62 #define _MTB_POSITION_WRAP_SHIFT 2 /**< Shift value for MTB_WRAP */ 63 #define _MTB_POSITION_WRAP_MASK 0x4UL /**< Bit mask for MTB_WRAP */ 64 #define _MTB_POSITION_WRAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_POSITION */ 65 #define MTB_POSITION_WRAP_DEFAULT (_MTB_POSITION_WRAP_DEFAULT << 2) /**< Shifted mode DEFAULT for MTB_POSITION */ 66 #define _MTB_POSITION_POINTER_SHIFT 3 /**< Shift value for MTB_POINTER */ 67 #define _MTB_POSITION_POINTER_MASK 0xFFFFFFF8UL /**< Bit mask for MTB_POINTER */ 68 #define _MTB_POSITION_POINTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_POSITION */ 69 #define MTB_POSITION_POINTER_DEFAULT (_MTB_POSITION_POINTER_DEFAULT << 3) /**< Shifted mode DEFAULT for MTB_POSITION */ 70 71 /* Bit fields for MTB MASTER */ 72 #define _MTB_MASTER_RESETVALUE 0x00000000UL /**< Default value for MTB_MASTER */ 73 #define _MTB_MASTER_MASK 0x8000027FUL /**< Mask for MTB_MASTER */ 74 #define _MTB_MASTER_MASK_SHIFT 0 /**< Shift value for MTB_MASK */ 75 #define _MTB_MASTER_MASK_MASK 0x1FUL /**< Bit mask for MTB_MASK */ 76 #define _MTB_MASTER_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_MASTER */ 77 #define MTB_MASTER_MASK_DEFAULT (_MTB_MASTER_MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for MTB_MASTER */ 78 #define MTB_MASTER_TSTARTEN (0x1UL << 5) /**< Trace start input enable. */ 79 #define _MTB_MASTER_TSTARTEN_SHIFT 5 /**< Shift value for MTB_TSTARTEN */ 80 #define _MTB_MASTER_TSTARTEN_MASK 0x20UL /**< Bit mask for MTB_TSTARTEN */ 81 #define _MTB_MASTER_TSTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_MASTER */ 82 #define MTB_MASTER_TSTARTEN_DEFAULT (_MTB_MASTER_TSTARTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MTB_MASTER */ 83 #define MTB_MASTER_TSTOPEN (0x1UL << 6) /**< Trace stop input enable. */ 84 #define _MTB_MASTER_TSTOPEN_SHIFT 6 /**< Shift value for MTB_TSTOPEN */ 85 #define _MTB_MASTER_TSTOPEN_MASK 0x40UL /**< Bit mask for MTB_TSTOPEN */ 86 #define _MTB_MASTER_TSTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_MASTER */ 87 #define MTB_MASTER_TSTOPEN_DEFAULT (_MTB_MASTER_TSTOPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MTB_MASTER */ 88 #define MTB_MASTER_HALTREQ (0x1UL << 9) /**< Halt request bit. */ 89 #define _MTB_MASTER_HALTREQ_SHIFT 9 /**< Shift value for MTB_HALTREQ */ 90 #define _MTB_MASTER_HALTREQ_MASK 0x200UL /**< Bit mask for MTB_HALTREQ */ 91 #define _MTB_MASTER_HALTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_MASTER */ 92 #define MTB_MASTER_HALTREQ_DEFAULT (_MTB_MASTER_HALTREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for MTB_MASTER */ 93 #define MTB_MASTER_EN (0x1UL << 31) /**< Main trace enable bit. */ 94 #define _MTB_MASTER_EN_SHIFT 31 /**< Shift value for MTB_EN */ 95 #define _MTB_MASTER_EN_MASK 0x80000000UL /**< Bit mask for MTB_EN */ 96 #define _MTB_MASTER_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_MASTER */ 97 #define MTB_MASTER_EN_DEFAULT (_MTB_MASTER_EN_DEFAULT << 31) /**< Shifted mode DEFAULT for MTB_MASTER */ 98 99 /* Bit fields for MTB FLOW */ 100 #define _MTB_FLOW_RESETVALUE 0x00000000UL /**< Default value for MTB_FLOW */ 101 #define _MTB_FLOW_MASK 0xFFFFFFFBUL /**< Mask for MTB_FLOW */ 102 #define MTB_FLOW_AUTOSTOP (0x1UL << 0) /**< AUTOSTOP enable. */ 103 #define _MTB_FLOW_AUTOSTOP_SHIFT 0 /**< Shift value for MTB_AUTOSTOP */ 104 #define _MTB_FLOW_AUTOSTOP_MASK 0x1UL /**< Bit mask for MTB_AUTOSTOP */ 105 #define _MTB_FLOW_AUTOSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_FLOW */ 106 #define MTB_FLOW_AUTOSTOP_DEFAULT (_MTB_FLOW_AUTOSTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for MTB_FLOW */ 107 #define MTB_FLOW_AUTOHALT (0x1UL << 1) /**< AUTOHALT enable. */ 108 #define _MTB_FLOW_AUTOHALT_SHIFT 1 /**< Shift value for MTB_AUTOHALT */ 109 #define _MTB_FLOW_AUTOHALT_MASK 0x2UL /**< Bit mask for MTB_AUTOHALT */ 110 #define _MTB_FLOW_AUTOHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_FLOW */ 111 #define MTB_FLOW_AUTOHALT_DEFAULT (_MTB_FLOW_AUTOHALT_DEFAULT << 1) /**< Shifted mode DEFAULT for MTB_FLOW */ 112 #define _MTB_FLOW_WATERMARK_SHIFT 3 /**< Shift value for MTB_WATERMARK */ 113 #define _MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8UL /**< Bit mask for MTB_WATERMARK */ 114 #define _MTB_FLOW_WATERMARK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_FLOW */ 115 #define MTB_FLOW_WATERMARK_DEFAULT (_MTB_FLOW_WATERMARK_DEFAULT << 3) /**< Shifted mode DEFAULT for MTB_FLOW */ 116 117 /* Bit fields for MTB BASE */ 118 #define _MTB_BASE_RESETVALUE 0x20000000UL /**< Default value for MTB_BASE */ 119 #define _MTB_BASE_MASK 0xFFFFFFFFUL /**< Mask for MTB_BASE */ 120 #define _MTB_BASE_BASE_SHIFT 0 /**< Shift value for MTB_BASE */ 121 #define _MTB_BASE_BASE_MASK 0xFFFFFFFFUL /**< Bit mask for MTB_BASE */ 122 #define _MTB_BASE_BASE_DEFAULT 0x20000000UL /**< Mode DEFAULT for MTB_BASE */ 123 #define MTB_BASE_BASE_DEFAULT (_MTB_BASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MTB_BASE */ 124 125 /** @} End of group EFM32HG_MTB */ 126 /** @} End of group Parts */ 127
