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Searched refs:_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (Results 1 – 25 of 62) sorted by relevance

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/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_msc.h793 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
794 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_msc.h829 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
830 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b530f512il120.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b530f512im64.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b530f512iq100.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b530f512iq64.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b530f512gq100.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b530f512gq64.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b530f512il112.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b110f1024gm64.h2961 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2962 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b110f1024gq64.h2961 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2962 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b530f512gl112.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b530f512gl120.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b530f512gm64.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b510f1024gq100.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b510f1024gq64.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b510f1024gl112.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b510f1024gl120.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b510f1024gm64.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b510f1024il112.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b510f1024il120.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b510f1024im64.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b510f1024iq100.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b510f1024iq64.h2969 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2970 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…
Defm32gg12b110f1024im64.h2961 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL … macro
2962 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 1…

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