1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG11B_ETH register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG11B_ETH ETH 43 * @{ 44 * @brief EFM32GG11B_ETH Register Declaration 45 ******************************************************************************/ 46 /** ETH Register Declaration */ 47 typedef struct { 48 __IOM uint32_t NETWORKCTRL; /**< Network control register */ 49 __IOM uint32_t NETWORKCFG; /**< Network configuration register */ 50 __IM uint32_t NETWORKSTATUS; /**< Network status register */ 51 52 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 53 __IOM uint32_t DMACFG; /**< DMA Configuration Register */ 54 __IOM uint32_t TXSTATUS; /**< Transmit status register */ 55 __IOM uint32_t RXQPTR; /**< Start address of the receive buffer queue */ 56 __IOM uint32_t TXQPTR; /**< Start address of the transmit buffer queue */ 57 __IOM uint32_t RXSTATUS; /**< Receive status register */ 58 __IOM uint32_t IFCR; /**< Interrupt status register */ 59 __IOM uint32_t IENS; /**< Interrupt Enable Register */ 60 __IOM uint32_t IENC; /**< Interrupt Disable Register */ 61 __IOM uint32_t IENRO; /**< Interrupt mask register */ 62 __IOM uint32_t PHYMNGMNT; /**< PHY management register */ 63 __IM uint32_t RXPAUSEQUANT; /**< Received Pause Quantum Register */ 64 __IOM uint32_t TXPAUSEQUANT; /**< Transmit Pause Quantum Register */ 65 __IOM uint32_t PBUFTXCUTTHRU; /**< TX Partial Store and Forward */ 66 __IOM uint32_t PBUFRXCUTTHRU; /**< RX Partial Store and Forward */ 67 __IOM uint32_t JUMBOMAXLEN; /**< Maximum Jumbo Frame Size. */ 68 69 uint32_t RESERVED1[4U]; /**< Reserved for future use **/ 70 __IOM uint32_t IMOD; /**< Interrupt moderation register */ 71 __IOM uint32_t SYSWAKETIME; /**< System wake time */ 72 uint32_t RESERVED2[7U]; /**< Reserved for future use **/ 73 __IOM uint32_t HASHBOTTOM; /**< Hash Register Bottom [31:0] */ 74 __IOM uint32_t HASHTOP; /**< Hash Register Top [63:32] */ 75 __IOM uint32_t SPECADDR1BOTTOM; /**< Specific Address 1 Bottom */ 76 __IOM uint32_t SPECADDR1TOP; /**< Specific Address 1 Top */ 77 __IOM uint32_t SPECADDR2BOTTOM; /**< Specific Address 2 Bottom */ 78 __IOM uint32_t SPECADDR2TOP; /**< Specific Address 2 Top */ 79 __IOM uint32_t SPECADDR3BOTTOM; /**< Specific Address 3 Bottom */ 80 __IOM uint32_t SPECADDR3TOP; /**< Specific Address 3 Top */ 81 __IOM uint32_t SPECADDR4BOTTOM; /**< Specific Address 4 Bottom */ 82 __IOM uint32_t SPECADDR4TOP; /**< Specific Address 4 Top */ 83 __IOM uint32_t SPECTYPE1; /**< Type ID Match 1 */ 84 __IOM uint32_t SPECTYPE2; /**< Type ID Match 2 */ 85 __IOM uint32_t SPECTYPE3; /**< Type ID Match 3 */ 86 __IOM uint32_t SPECTYPE4; /**< Type ID Match 4 */ 87 __IOM uint32_t WOLREG; /**< Wake on LAN Register */ 88 __IOM uint32_t STRETCHRATIO; /**< IPG stretch register */ 89 __IOM uint32_t STACKEDVLAN; /**< Stacked VLAN Register */ 90 __IOM uint32_t TXPFCPAUSE; /**< Transmit PFC Pause Register */ 91 __IOM uint32_t MASKADD1BOTTOM; /**< Specific Address Mask 1 Bottom 31:0 */ 92 __IOM uint32_t MASKADD1TOP; /**< Specific Address Mask 1 Top 47:32 */ 93 94 uint32_t RESERVED3[1U]; /**< Reserved for future use **/ 95 __IOM uint32_t RXPTPUNICAST; /**< PTP RX unicast IP destination address */ 96 __IOM uint32_t TXPTPUNICAST; /**< PTP TX unicast IP destination address */ 97 __IOM uint32_t TSUNSECCMP; /**< TSU timer comparison value nanoseconds */ 98 __IOM uint32_t TSUSECCMP; /**< TSU timer comparison value seconds [31:0] */ 99 __IOM uint32_t TSUMSBSECCMP; /**< TSU timer comparison value seconds [47:32] */ 100 __IM uint32_t TSUPTPTXMSBSEC; /**< PTP Event Frame Transmitted Seconds Register 47:32 */ 101 __IM uint32_t TSUPTPRXMSBSEC; /**< PTP Event Frame Received Seconds Register 47:32 */ 102 __IM uint32_t TSUPEERTXMSBSEC; /**< PTP Peer Event Frame Transmitted Seconds Register 47:32 */ 103 __IM uint32_t TSUPEERRXMSBSEC; /**< PTP Peer Event Frame Received Seconds Register 47:32 */ 104 105 uint32_t RESERVED4[2U]; /**< Reserved for future use **/ 106 __IOM uint32_t OCTETSTXEDBOTTOM; /**< Octets transmitted 31:0 */ 107 __IOM uint32_t OCTETSTXEDTOP; /**< Octets Transmitted 47:32 */ 108 __IOM uint32_t FRAMESTXEDOK; /**< Frames Transmitted */ 109 __IOM uint32_t BROADCASTTXED; /**< Broadcast Frames Transmitted */ 110 __IOM uint32_t MULTICASTTXED; /**< Multicast Frames Transmitted */ 111 __IOM uint32_t PFRAMESTXED; /**< Pause Frames Transmitted */ 112 __IOM uint32_t FRAMESTXED64; /**< 64 Byte Frames Transmitted */ 113 __IOM uint32_t FRAMESTXED65; /**< 65 to 127 Byte Frames Transmitted */ 114 __IOM uint32_t FRAMESTXED128; /**< 128 to 255 Byte Frames Transmitted */ 115 __IOM uint32_t FRAMESTXED256; /**< 256 to 511 Byte Frames Transmitted */ 116 __IOM uint32_t FRAMESTXED512; /**< 512 to 1023 Byte Frames Transmitted */ 117 __IOM uint32_t FRAMESTXED1024; /**< 1024 to 1518 Byte Frames Transmitted */ 118 __IOM uint32_t FRAMESTXED1519; /**< Greater Than 1518 Byte Frames Transmitted */ 119 __IOM uint32_t TXUNDERRUNS; /**< Transmit Under Runs */ 120 __IOM uint32_t SINGLECOLS; /**< Single Collision Frames */ 121 __IOM uint32_t MULTICOLS; /**< Multiple Collision Frames */ 122 __IOM uint32_t EXCESSCOLS; /**< Excessive Collisions */ 123 __IOM uint32_t LATECOLS; /**< Late Collisions */ 124 __IOM uint32_t DEFERREDFRAMES; /**< Deferred Transmission Frames */ 125 __IOM uint32_t CRSERRS; /**< Carrier Sense Errors */ 126 __IOM uint32_t OCTETSRXEDBOTTOM; /**< Octets Received 31:0 */ 127 __IOM uint32_t OCTETSRXEDTOP; /**< Octets Received 47:32 */ 128 __IOM uint32_t FRAMESRXEDOK; /**< Frames Received */ 129 __IOM uint32_t BROADCASTRXED; /**< Broadcast Frames Received */ 130 __IOM uint32_t MULTICASTRXED; /**< Multicast Frames Received */ 131 __IOM uint32_t PFRAMESRXED; /**< Pause Frames Received */ 132 __IOM uint32_t FRAMESRXED64; /**< 64 Byte Frames Received */ 133 __IOM uint32_t FRAMESRXED65; /**< 65 to 127 Byte Frames Received */ 134 __IOM uint32_t FRAMESRXED128; /**< 128 to 255 Byte Frames Received */ 135 __IOM uint32_t FRAMESRXED256; /**< 256 to 511 Byte Frames Received */ 136 __IOM uint32_t FRAMESRXED512; /**< 512 to 1023 Byte Frames Received */ 137 __IOM uint32_t FRAMESRXED1024; /**< 1024 to 1518 Byte Frames Received */ 138 __IOM uint32_t FRAMESRXED1519; /**< 1519 to maximum Byte Frames Received */ 139 __IOM uint32_t UNDERSIZEFRAMES; /**< Undersized Frames Received */ 140 __IOM uint32_t EXCESSIVERXLEN; /**< Oversize Frames Received */ 141 __IOM uint32_t RXJABBERS; /**< Jabbers Received */ 142 __IOM uint32_t FCSERRS; /**< Frame Check Sequence Errors */ 143 __IOM uint32_t RXLENERRS; /**< Length Field Frame Errors */ 144 __IOM uint32_t RXSYMBOLERRS; /**< Receive Symbol Errors */ 145 __IOM uint32_t ALIGNERRS; /**< Alignment Errors */ 146 __IOM uint32_t RXRESOURCEERRS; /**< Receive Resource Errors */ 147 __IOM uint32_t RXOVERRUNS; /**< Receive Overruns */ 148 __IOM uint32_t RXIPCKERRS; /**< IP Header Checksum Errors */ 149 __IOM uint32_t RXTCPCKERRS; /**< TCP Checksum Errors */ 150 __IOM uint32_t RXUDPCKERRS; /**< UDP Checksum Errors */ 151 __IOM uint32_t AUTOFLUSHEDPKTS; /**< Receive DMA Flushed Packets */ 152 uint32_t RESERVED5[1U]; /**< Reserved for future use **/ 153 __IOM uint32_t TSUTIMERINCRSUBNSEC; /**< 1588 Timer Increment Register subscript nsec */ 154 __IOM uint32_t TSUTIMERMSBSEC; /**< 1588 Timer Seconds Register 47:32 */ 155 156 uint32_t RESERVED6[3U]; /**< Reserved for future use **/ 157 __IOM uint32_t TSUTIMERSEC; /**< 1588 Timer Seconds Register 31:0 */ 158 __IOM uint32_t TSUTIMERNSEC; /**< 1588 Timer Nanoseconds Register */ 159 __IOM uint32_t TSUTIMERADJUST; /**< This register returns all zeroes when read. */ 160 __IOM uint32_t TSUTIMERINCR; /**< 1588 Timer Increment Register */ 161 __IM uint32_t TSUPTPTXSEC; /**< PTP Event Frame Transmitted Seconds Register 31:0 */ 162 __IM uint32_t TSUPTPTXNSEC; /**< PTP Event Frame Transmitted Nanoseconds Register */ 163 __IM uint32_t TSUPTPRXSEC; /**< PTP Event Frame Received Seconds Register 31:0 */ 164 __IM uint32_t TSUPTPRXNSEC; /**< PTP Event Frame Received Nanoseconds Register */ 165 __IM uint32_t TSUPEERTXSEC; /**< PTP Peer Event Frame Transmitted Seconds Register 31:0 */ 166 __IM uint32_t TSUPEERTXNSEC; /**< PTP Peer Event Frame Transmitted Nanoseconds Register */ 167 __IM uint32_t TSUPEERRXSEC; /**< PTP Peer Event Frame Received Seconds Register 31:0 */ 168 __IM uint32_t TSUPEERRXNSEC; /**< PTP Peer Event Frame Received Nanoseconds Register */ 169 170 uint32_t RESERVED7[24U]; /**< Reserved for future use **/ 171 __IOM uint32_t TXPAUSEQUANT1; /**< Transmit Pause Quantum Register 1 */ 172 __IOM uint32_t TXPAUSEQUANT2; /**< Transmit Pause Quantum Register 2 */ 173 __IOM uint32_t TXPAUSEQUANT3; /**< Transmit Pause Quantum Register 3 */ 174 uint32_t RESERVED8[1U]; /**< Reserved for future use **/ 175 __IOM uint32_t RXLPI; /**< Received LPI transitions */ 176 __IOM uint32_t RXLPITIME; /**< Received LPI time */ 177 __IOM uint32_t TXLPI; /**< Transmit LPI transitions */ 178 __IOM uint32_t TXLPITIME; /**< Transmit LPI time */ 179 180 uint32_t RESERVED9[147U]; /**< Reserved for future use **/ 181 __IOM uint32_t TXBDCTRL; /**< TX BD control register */ 182 __IOM uint32_t RXBDCTRL; /**< RX BD control register */ 183 184 uint32_t RESERVED10[459U]; /**< Reserved for future use **/ 185 __IOM uint32_t ROUTEPEN; /**< I/O Route Enable Register */ 186 __IOM uint32_t ROUTELOC0; /**< I/O Route Location Register 0 */ 187 uint32_t RESERVED11[1U]; /**< Reserved for future use **/ 188 __IOM uint32_t ROUTELOC1; /**< I/O Route Location Register 1 */ 189 __IOM uint32_t CTRL; /**< Ethernet control register */ 190 } ETH_TypeDef; /** @} */ 191 192 /***************************************************************************//** 193 * @addtogroup EFM32GG11B_ETH 194 * @{ 195 * @defgroup EFM32GG11B_ETH_BitFields ETH Bit Fields 196 * @{ 197 ******************************************************************************/ 198 199 /* Bit fields for ETH NETWORKCTRL */ 200 #define _ETH_NETWORKCTRL_RESETVALUE 0x00000000UL /**< Default value for ETH_NETWORKCTRL */ 201 #define _ETH_NETWORKCTRL_MASK 0x035F9FFEUL /**< Mask for ETH_NETWORKCTRL */ 202 #define ETH_NETWORKCTRL_LOOPBACKLOCAL (0x1UL << 1) /**< Loopback local */ 203 #define _ETH_NETWORKCTRL_LOOPBACKLOCAL_SHIFT 1 /**< Shift value for ETH_LOOPBACKLOCAL */ 204 #define _ETH_NETWORKCTRL_LOOPBACKLOCAL_MASK 0x2UL /**< Bit mask for ETH_LOOPBACKLOCAL */ 205 #define _ETH_NETWORKCTRL_LOOPBACKLOCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 206 #define ETH_NETWORKCTRL_LOOPBACKLOCAL_DEFAULT (_ETH_NETWORKCTRL_LOOPBACKLOCAL_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 207 #define ETH_NETWORKCTRL_ENBRX (0x1UL << 2) /**< Receive enable */ 208 #define _ETH_NETWORKCTRL_ENBRX_SHIFT 2 /**< Shift value for ETH_ENBRX */ 209 #define _ETH_NETWORKCTRL_ENBRX_MASK 0x4UL /**< Bit mask for ETH_ENBRX */ 210 #define _ETH_NETWORKCTRL_ENBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 211 #define ETH_NETWORKCTRL_ENBRX_DEFAULT (_ETH_NETWORKCTRL_ENBRX_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 212 #define ETH_NETWORKCTRL_ENBTX (0x1UL << 3) /**< Transmit enable */ 213 #define _ETH_NETWORKCTRL_ENBTX_SHIFT 3 /**< Shift value for ETH_ENBTX */ 214 #define _ETH_NETWORKCTRL_ENBTX_MASK 0x8UL /**< Bit mask for ETH_ENBTX */ 215 #define _ETH_NETWORKCTRL_ENBTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 216 #define ETH_NETWORKCTRL_ENBTX_DEFAULT (_ETH_NETWORKCTRL_ENBTX_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 217 #define ETH_NETWORKCTRL_MANPORTEN (0x1UL << 4) /**< Management port enable */ 218 #define _ETH_NETWORKCTRL_MANPORTEN_SHIFT 4 /**< Shift value for ETH_MANPORTEN */ 219 #define _ETH_NETWORKCTRL_MANPORTEN_MASK 0x10UL /**< Bit mask for ETH_MANPORTEN */ 220 #define _ETH_NETWORKCTRL_MANPORTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 221 #define ETH_NETWORKCTRL_MANPORTEN_DEFAULT (_ETH_NETWORKCTRL_MANPORTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 222 #define ETH_NETWORKCTRL_CLRALLSTATSREGS (0x1UL << 5) /**< Clear statistics registers */ 223 #define _ETH_NETWORKCTRL_CLRALLSTATSREGS_SHIFT 5 /**< Shift value for ETH_CLRALLSTATSREGS */ 224 #define _ETH_NETWORKCTRL_CLRALLSTATSREGS_MASK 0x20UL /**< Bit mask for ETH_CLRALLSTATSREGS */ 225 #define _ETH_NETWORKCTRL_CLRALLSTATSREGS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 226 #define ETH_NETWORKCTRL_CLRALLSTATSREGS_DEFAULT (_ETH_NETWORKCTRL_CLRALLSTATSREGS_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 227 #define ETH_NETWORKCTRL_INCALLSTATSREGS (0x1UL << 6) /**< Incremental statistics registers */ 228 #define _ETH_NETWORKCTRL_INCALLSTATSREGS_SHIFT 6 /**< Shift value for ETH_INCALLSTATSREGS */ 229 #define _ETH_NETWORKCTRL_INCALLSTATSREGS_MASK 0x40UL /**< Bit mask for ETH_INCALLSTATSREGS */ 230 #define _ETH_NETWORKCTRL_INCALLSTATSREGS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 231 #define ETH_NETWORKCTRL_INCALLSTATSREGS_DEFAULT (_ETH_NETWORKCTRL_INCALLSTATSREGS_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 232 #define ETH_NETWORKCTRL_STATSWREN (0x1UL << 7) /**< Write enable for statistics registers */ 233 #define _ETH_NETWORKCTRL_STATSWREN_SHIFT 7 /**< Shift value for ETH_STATSWREN */ 234 #define _ETH_NETWORKCTRL_STATSWREN_MASK 0x80UL /**< Bit mask for ETH_STATSWREN */ 235 #define _ETH_NETWORKCTRL_STATSWREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 236 #define ETH_NETWORKCTRL_STATSWREN_DEFAULT (_ETH_NETWORKCTRL_STATSWREN_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 237 #define ETH_NETWORKCTRL_BACKPRESSURE (0x1UL << 8) /**< Back pressure will force collisions on all received frames */ 238 #define _ETH_NETWORKCTRL_BACKPRESSURE_SHIFT 8 /**< Shift value for ETH_BACKPRESSURE */ 239 #define _ETH_NETWORKCTRL_BACKPRESSURE_MASK 0x100UL /**< Bit mask for ETH_BACKPRESSURE */ 240 #define _ETH_NETWORKCTRL_BACKPRESSURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 241 #define ETH_NETWORKCTRL_BACKPRESSURE_DEFAULT (_ETH_NETWORKCTRL_BACKPRESSURE_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 242 #define ETH_NETWORKCTRL_TXSTRT (0x1UL << 9) /**< Start transmission */ 243 #define _ETH_NETWORKCTRL_TXSTRT_SHIFT 9 /**< Shift value for ETH_TXSTRT */ 244 #define _ETH_NETWORKCTRL_TXSTRT_MASK 0x200UL /**< Bit mask for ETH_TXSTRT */ 245 #define _ETH_NETWORKCTRL_TXSTRT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 246 #define ETH_NETWORKCTRL_TXSTRT_DEFAULT (_ETH_NETWORKCTRL_TXSTRT_DEFAULT << 9) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 247 #define ETH_NETWORKCTRL_TXHALT (0x1UL << 10) /**< Transmit halt */ 248 #define _ETH_NETWORKCTRL_TXHALT_SHIFT 10 /**< Shift value for ETH_TXHALT */ 249 #define _ETH_NETWORKCTRL_TXHALT_MASK 0x400UL /**< Bit mask for ETH_TXHALT */ 250 #define _ETH_NETWORKCTRL_TXHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 251 #define ETH_NETWORKCTRL_TXHALT_DEFAULT (_ETH_NETWORKCTRL_TXHALT_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 252 #define ETH_NETWORKCTRL_TXPFRMREQ (0x1UL << 11) /**< Transmit pause frame */ 253 #define _ETH_NETWORKCTRL_TXPFRMREQ_SHIFT 11 /**< Shift value for ETH_TXPFRMREQ */ 254 #define _ETH_NETWORKCTRL_TXPFRMREQ_MASK 0x800UL /**< Bit mask for ETH_TXPFRMREQ */ 255 #define _ETH_NETWORKCTRL_TXPFRMREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 256 #define ETH_NETWORKCTRL_TXPFRMREQ_DEFAULT (_ETH_NETWORKCTRL_TXPFRMREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 257 #define ETH_NETWORKCTRL_TXPFRMZERO (0x1UL << 12) /**< Transmit zero quantum pause frame */ 258 #define _ETH_NETWORKCTRL_TXPFRMZERO_SHIFT 12 /**< Shift value for ETH_TXPFRMZERO */ 259 #define _ETH_NETWORKCTRL_TXPFRMZERO_MASK 0x1000UL /**< Bit mask for ETH_TXPFRMZERO */ 260 #define _ETH_NETWORKCTRL_TXPFRMZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 261 #define ETH_NETWORKCTRL_TXPFRMZERO_DEFAULT (_ETH_NETWORKCTRL_TXPFRMZERO_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 262 #define ETH_NETWORKCTRL_STORERXTS (0x1UL << 15) /**< Store receive time stamp to memory. */ 263 #define _ETH_NETWORKCTRL_STORERXTS_SHIFT 15 /**< Shift value for ETH_STORERXTS */ 264 #define _ETH_NETWORKCTRL_STORERXTS_MASK 0x8000UL /**< Bit mask for ETH_STORERXTS */ 265 #define _ETH_NETWORKCTRL_STORERXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 266 #define ETH_NETWORKCTRL_STORERXTS_DEFAULT (_ETH_NETWORKCTRL_STORERXTS_DEFAULT << 15) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 267 #define ETH_NETWORKCTRL_PFCENB (0x1UL << 16) /**< Enable PFC Priority Based Pause Reception capabilities. */ 268 #define _ETH_NETWORKCTRL_PFCENB_SHIFT 16 /**< Shift value for ETH_PFCENB */ 269 #define _ETH_NETWORKCTRL_PFCENB_MASK 0x10000UL /**< Bit mask for ETH_PFCENB */ 270 #define _ETH_NETWORKCTRL_PFCENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 271 #define ETH_NETWORKCTRL_PFCENB_DEFAULT (_ETH_NETWORKCTRL_PFCENB_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 272 #define ETH_NETWORKCTRL_TXPFCPRIORPFRM (0x1UL << 17) /**< Write a one to transmit PFC priority based pause frame. */ 273 #define _ETH_NETWORKCTRL_TXPFCPRIORPFRM_SHIFT 17 /**< Shift value for ETH_TXPFCPRIORPFRM */ 274 #define _ETH_NETWORKCTRL_TXPFCPRIORPFRM_MASK 0x20000UL /**< Bit mask for ETH_TXPFCPRIORPFRM */ 275 #define _ETH_NETWORKCTRL_TXPFCPRIORPFRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 276 #define ETH_NETWORKCTRL_TXPFCPRIORPFRM_DEFAULT (_ETH_NETWORKCTRL_TXPFCPRIORPFRM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 277 #define ETH_NETWORKCTRL_FLUSHRXPKT (0x1UL << 18) /**< Flush the next packet from the external RX DPRAM. */ 278 #define _ETH_NETWORKCTRL_FLUSHRXPKT_SHIFT 18 /**< Shift value for ETH_FLUSHRXPKT */ 279 #define _ETH_NETWORKCTRL_FLUSHRXPKT_MASK 0x40000UL /**< Bit mask for ETH_FLUSHRXPKT */ 280 #define _ETH_NETWORKCTRL_FLUSHRXPKT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 281 #define ETH_NETWORKCTRL_FLUSHRXPKT_DEFAULT (_ETH_NETWORKCTRL_FLUSHRXPKT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 282 #define ETH_NETWORKCTRL_TXLPIEN (0x1UL << 19) /**< Enable LPI transmission when set LPI (low power idle) is immediately transmitted. */ 283 #define _ETH_NETWORKCTRL_TXLPIEN_SHIFT 19 /**< Shift value for ETH_TXLPIEN */ 284 #define _ETH_NETWORKCTRL_TXLPIEN_MASK 0x80000UL /**< Bit mask for ETH_TXLPIEN */ 285 #define _ETH_NETWORKCTRL_TXLPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 286 #define ETH_NETWORKCTRL_TXLPIEN_DEFAULT (_ETH_NETWORKCTRL_TXLPIEN_DEFAULT << 19) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 287 #define ETH_NETWORKCTRL_PTPUNICASTEN (0x1UL << 20) /**< Enable detection of unicast PTP unicast frames. */ 288 #define _ETH_NETWORKCTRL_PTPUNICASTEN_SHIFT 20 /**< Shift value for ETH_PTPUNICASTEN */ 289 #define _ETH_NETWORKCTRL_PTPUNICASTEN_MASK 0x100000UL /**< Bit mask for ETH_PTPUNICASTEN */ 290 #define _ETH_NETWORKCTRL_PTPUNICASTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 291 #define ETH_NETWORKCTRL_PTPUNICASTEN_DEFAULT (_ETH_NETWORKCTRL_PTPUNICASTEN_DEFAULT << 20) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 292 #define ETH_NETWORKCTRL_STOREUDPOFFSET (0x1UL << 22) /**< Store UDP / TCP offset to memory. */ 293 #define _ETH_NETWORKCTRL_STOREUDPOFFSET_SHIFT 22 /**< Shift value for ETH_STOREUDPOFFSET */ 294 #define _ETH_NETWORKCTRL_STOREUDPOFFSET_MASK 0x400000UL /**< Bit mask for ETH_STOREUDPOFFSET */ 295 #define _ETH_NETWORKCTRL_STOREUDPOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 296 #define ETH_NETWORKCTRL_STOREUDPOFFSET_DEFAULT (_ETH_NETWORKCTRL_STOREUDPOFFSET_DEFAULT << 22) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 297 #define ETH_NETWORKCTRL_ONESTEPSYNCMODE (0x1UL << 24) /**< 1588 One Step Sync Mode. */ 298 #define _ETH_NETWORKCTRL_ONESTEPSYNCMODE_SHIFT 24 /**< Shift value for ETH_ONESTEPSYNCMODE */ 299 #define _ETH_NETWORKCTRL_ONESTEPSYNCMODE_MASK 0x1000000UL /**< Bit mask for ETH_ONESTEPSYNCMODE */ 300 #define _ETH_NETWORKCTRL_ONESTEPSYNCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 301 #define ETH_NETWORKCTRL_ONESTEPSYNCMODE_DEFAULT (_ETH_NETWORKCTRL_ONESTEPSYNCMODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 302 #define ETH_NETWORKCTRL_PFCCTRL (0x1UL << 25) /**< Enable multiple PFC pause quantums, one per pause priority */ 303 #define _ETH_NETWORKCTRL_PFCCTRL_SHIFT 25 /**< Shift value for ETH_PFCCTRL */ 304 #define _ETH_NETWORKCTRL_PFCCTRL_MASK 0x2000000UL /**< Bit mask for ETH_PFCCTRL */ 305 #define _ETH_NETWORKCTRL_PFCCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCTRL */ 306 #define ETH_NETWORKCTRL_PFCCTRL_DEFAULT (_ETH_NETWORKCTRL_PFCCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_NETWORKCTRL */ 307 308 /* Bit fields for ETH NETWORKCFG */ 309 #define _ETH_NETWORKCFG_RESETVALUE 0x00080000UL /**< Default value for ETH_NETWORKCFG */ 310 #define _ETH_NETWORKCFG_MASK 0x779FF1FFUL /**< Mask for ETH_NETWORKCFG */ 311 #define ETH_NETWORKCFG_SPEED (0x1UL << 0) /**< Speed */ 312 #define _ETH_NETWORKCFG_SPEED_SHIFT 0 /**< Shift value for ETH_SPEED */ 313 #define _ETH_NETWORKCFG_SPEED_MASK 0x1UL /**< Bit mask for ETH_SPEED */ 314 #define _ETH_NETWORKCFG_SPEED_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 315 #define ETH_NETWORKCFG_SPEED_DEFAULT (_ETH_NETWORKCFG_SPEED_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 316 #define ETH_NETWORKCFG_FULLDUPLEX (0x1UL << 1) /**< Full duplex */ 317 #define _ETH_NETWORKCFG_FULLDUPLEX_SHIFT 1 /**< Shift value for ETH_FULLDUPLEX */ 318 #define _ETH_NETWORKCFG_FULLDUPLEX_MASK 0x2UL /**< Bit mask for ETH_FULLDUPLEX */ 319 #define _ETH_NETWORKCFG_FULLDUPLEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 320 #define ETH_NETWORKCFG_FULLDUPLEX_DEFAULT (_ETH_NETWORKCFG_FULLDUPLEX_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 321 #define ETH_NETWORKCFG_DISCRDNONVLANFRAMES (0x1UL << 2) /**< Discard non-VLAN frames */ 322 #define _ETH_NETWORKCFG_DISCRDNONVLANFRAMES_SHIFT 2 /**< Shift value for ETH_DISCRDNONVLANFRAMES */ 323 #define _ETH_NETWORKCFG_DISCRDNONVLANFRAMES_MASK 0x4UL /**< Bit mask for ETH_DISCRDNONVLANFRAMES */ 324 #define _ETH_NETWORKCFG_DISCRDNONVLANFRAMES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 325 #define ETH_NETWORKCFG_DISCRDNONVLANFRAMES_DEFAULT (_ETH_NETWORKCFG_DISCRDNONVLANFRAMES_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 326 #define ETH_NETWORKCFG_JUMBOFRAMES (0x1UL << 3) /**< Jumbo frames enable */ 327 #define _ETH_NETWORKCFG_JUMBOFRAMES_SHIFT 3 /**< Shift value for ETH_JUMBOFRAMES */ 328 #define _ETH_NETWORKCFG_JUMBOFRAMES_MASK 0x8UL /**< Bit mask for ETH_JUMBOFRAMES */ 329 #define _ETH_NETWORKCFG_JUMBOFRAMES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 330 #define ETH_NETWORKCFG_JUMBOFRAMES_DEFAULT (_ETH_NETWORKCFG_JUMBOFRAMES_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 331 #define ETH_NETWORKCFG_COPYALLFRAMES (0x1UL << 4) /**< Copy all frames */ 332 #define _ETH_NETWORKCFG_COPYALLFRAMES_SHIFT 4 /**< Shift value for ETH_COPYALLFRAMES */ 333 #define _ETH_NETWORKCFG_COPYALLFRAMES_MASK 0x10UL /**< Bit mask for ETH_COPYALLFRAMES */ 334 #define _ETH_NETWORKCFG_COPYALLFRAMES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 335 #define ETH_NETWORKCFG_COPYALLFRAMES_DEFAULT (_ETH_NETWORKCFG_COPYALLFRAMES_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 336 #define ETH_NETWORKCFG_NOBROADCAST (0x1UL << 5) /**< No broadcast */ 337 #define _ETH_NETWORKCFG_NOBROADCAST_SHIFT 5 /**< Shift value for ETH_NOBROADCAST */ 338 #define _ETH_NETWORKCFG_NOBROADCAST_MASK 0x20UL /**< Bit mask for ETH_NOBROADCAST */ 339 #define _ETH_NETWORKCFG_NOBROADCAST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 340 #define ETH_NETWORKCFG_NOBROADCAST_DEFAULT (_ETH_NETWORKCFG_NOBROADCAST_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 341 #define ETH_NETWORKCFG_MULTICASTHASHEN (0x1UL << 6) /**< Multicast hash enable */ 342 #define _ETH_NETWORKCFG_MULTICASTHASHEN_SHIFT 6 /**< Shift value for ETH_MULTICASTHASHEN */ 343 #define _ETH_NETWORKCFG_MULTICASTHASHEN_MASK 0x40UL /**< Bit mask for ETH_MULTICASTHASHEN */ 344 #define _ETH_NETWORKCFG_MULTICASTHASHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 345 #define ETH_NETWORKCFG_MULTICASTHASHEN_DEFAULT (_ETH_NETWORKCFG_MULTICASTHASHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 346 #define ETH_NETWORKCFG_UNICASTHASHEN (0x1UL << 7) /**< Unicast hash enable */ 347 #define _ETH_NETWORKCFG_UNICASTHASHEN_SHIFT 7 /**< Shift value for ETH_UNICASTHASHEN */ 348 #define _ETH_NETWORKCFG_UNICASTHASHEN_MASK 0x80UL /**< Bit mask for ETH_UNICASTHASHEN */ 349 #define _ETH_NETWORKCFG_UNICASTHASHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 350 #define ETH_NETWORKCFG_UNICASTHASHEN_DEFAULT (_ETH_NETWORKCFG_UNICASTHASHEN_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 351 #define ETH_NETWORKCFG_RX1536BYTEFRAMES (0x1UL << 8) /**< Receive 1536 byte frames */ 352 #define _ETH_NETWORKCFG_RX1536BYTEFRAMES_SHIFT 8 /**< Shift value for ETH_RX1536BYTEFRAMES */ 353 #define _ETH_NETWORKCFG_RX1536BYTEFRAMES_MASK 0x100UL /**< Bit mask for ETH_RX1536BYTEFRAMES */ 354 #define _ETH_NETWORKCFG_RX1536BYTEFRAMES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 355 #define ETH_NETWORKCFG_RX1536BYTEFRAMES_DEFAULT (_ETH_NETWORKCFG_RX1536BYTEFRAMES_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 356 #define ETH_NETWORKCFG_RETRYTEST (0x1UL << 12) /**< Retry test */ 357 #define _ETH_NETWORKCFG_RETRYTEST_SHIFT 12 /**< Shift value for ETH_RETRYTEST */ 358 #define _ETH_NETWORKCFG_RETRYTEST_MASK 0x1000UL /**< Bit mask for ETH_RETRYTEST */ 359 #define _ETH_NETWORKCFG_RETRYTEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 360 #define ETH_NETWORKCFG_RETRYTEST_DEFAULT (_ETH_NETWORKCFG_RETRYTEST_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 361 #define ETH_NETWORKCFG_PAUSEEN (0x1UL << 13) /**< Pause enable */ 362 #define _ETH_NETWORKCFG_PAUSEEN_SHIFT 13 /**< Shift value for ETH_PAUSEEN */ 363 #define _ETH_NETWORKCFG_PAUSEEN_MASK 0x2000UL /**< Bit mask for ETH_PAUSEEN */ 364 #define _ETH_NETWORKCFG_PAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 365 #define ETH_NETWORKCFG_PAUSEEN_DEFAULT (_ETH_NETWORKCFG_PAUSEEN_DEFAULT << 13) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 366 #define _ETH_NETWORKCFG_RXBUFFOFFSET_SHIFT 14 /**< Shift value for ETH_RXBUFFOFFSET */ 367 #define _ETH_NETWORKCFG_RXBUFFOFFSET_MASK 0xC000UL /**< Bit mask for ETH_RXBUFFOFFSET */ 368 #define _ETH_NETWORKCFG_RXBUFFOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 369 #define ETH_NETWORKCFG_RXBUFFOFFSET_DEFAULT (_ETH_NETWORKCFG_RXBUFFOFFSET_DEFAULT << 14) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 370 #define ETH_NETWORKCFG_LENFIELDERRFRMDISCRD (0x1UL << 16) /**< Length field error frame discard */ 371 #define _ETH_NETWORKCFG_LENFIELDERRFRMDISCRD_SHIFT 16 /**< Shift value for ETH_LENFIELDERRFRMDISCRD */ 372 #define _ETH_NETWORKCFG_LENFIELDERRFRMDISCRD_MASK 0x10000UL /**< Bit mask for ETH_LENFIELDERRFRMDISCRD */ 373 #define _ETH_NETWORKCFG_LENFIELDERRFRMDISCRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 374 #define ETH_NETWORKCFG_LENFIELDERRFRMDISCRD_DEFAULT (_ETH_NETWORKCFG_LENFIELDERRFRMDISCRD_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 375 #define ETH_NETWORKCFG_FCSREMOVE (0x1UL << 17) /**< FCS remove */ 376 #define _ETH_NETWORKCFG_FCSREMOVE_SHIFT 17 /**< Shift value for ETH_FCSREMOVE */ 377 #define _ETH_NETWORKCFG_FCSREMOVE_MASK 0x20000UL /**< Bit mask for ETH_FCSREMOVE */ 378 #define _ETH_NETWORKCFG_FCSREMOVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 379 #define ETH_NETWORKCFG_FCSREMOVE_DEFAULT (_ETH_NETWORKCFG_FCSREMOVE_DEFAULT << 17) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 380 #define _ETH_NETWORKCFG_MDCCLKDIV_SHIFT 18 /**< Shift value for ETH_MDCCLKDIV */ 381 #define _ETH_NETWORKCFG_MDCCLKDIV_MASK 0x1C0000UL /**< Bit mask for ETH_MDCCLKDIV */ 382 #define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY8 0x00000000UL /**< Mode DIVBY8 for ETH_NETWORKCFG */ 383 #define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY16 0x00000001UL /**< Mode DIVBY16 for ETH_NETWORKCFG */ 384 #define _ETH_NETWORKCFG_MDCCLKDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 385 #define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY32 0x00000002UL /**< Mode DIVBY32 for ETH_NETWORKCFG */ 386 #define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY48 0x00000003UL /**< Mode DIVBY48 for ETH_NETWORKCFG */ 387 #define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY64 0x00000004UL /**< Mode DIVBY64 for ETH_NETWORKCFG */ 388 #define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY96 0x00000005UL /**< Mode DIVBY96 for ETH_NETWORKCFG */ 389 #define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY128 0x00000006UL /**< Mode DIVBY128 for ETH_NETWORKCFG */ 390 #define _ETH_NETWORKCFG_MDCCLKDIV_DIVBY224 0x00000007UL /**< Mode DIVBY224 for ETH_NETWORKCFG */ 391 #define ETH_NETWORKCFG_MDCCLKDIV_DIVBY8 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY8 << 18) /**< Shifted mode DIVBY8 for ETH_NETWORKCFG */ 392 #define ETH_NETWORKCFG_MDCCLKDIV_DIVBY16 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY16 << 18) /**< Shifted mode DIVBY16 for ETH_NETWORKCFG */ 393 #define ETH_NETWORKCFG_MDCCLKDIV_DEFAULT (_ETH_NETWORKCFG_MDCCLKDIV_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 394 #define ETH_NETWORKCFG_MDCCLKDIV_DIVBY32 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY32 << 18) /**< Shifted mode DIVBY32 for ETH_NETWORKCFG */ 395 #define ETH_NETWORKCFG_MDCCLKDIV_DIVBY48 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY48 << 18) /**< Shifted mode DIVBY48 for ETH_NETWORKCFG */ 396 #define ETH_NETWORKCFG_MDCCLKDIV_DIVBY64 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY64 << 18) /**< Shifted mode DIVBY64 for ETH_NETWORKCFG */ 397 #define ETH_NETWORKCFG_MDCCLKDIV_DIVBY96 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY96 << 18) /**< Shifted mode DIVBY96 for ETH_NETWORKCFG */ 398 #define ETH_NETWORKCFG_MDCCLKDIV_DIVBY128 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY128 << 18) /**< Shifted mode DIVBY128 for ETH_NETWORKCFG */ 399 #define ETH_NETWORKCFG_MDCCLKDIV_DIVBY224 (_ETH_NETWORKCFG_MDCCLKDIV_DIVBY224 << 18) /**< Shifted mode DIVBY224 for ETH_NETWORKCFG */ 400 #define ETH_NETWORKCFG_DISCOPYOFPFRAMES (0x1UL << 23) /**< Disable copy of pause frames */ 401 #define _ETH_NETWORKCFG_DISCOPYOFPFRAMES_SHIFT 23 /**< Shift value for ETH_DISCOPYOFPFRAMES */ 402 #define _ETH_NETWORKCFG_DISCOPYOFPFRAMES_MASK 0x800000UL /**< Bit mask for ETH_DISCOPYOFPFRAMES */ 403 #define _ETH_NETWORKCFG_DISCOPYOFPFRAMES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 404 #define ETH_NETWORKCFG_DISCOPYOFPFRAMES_DEFAULT (_ETH_NETWORKCFG_DISCOPYOFPFRAMES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 405 #define ETH_NETWORKCFG_RXCHKSUMOFFLOADEN (0x1UL << 24) /**< Receive checksum offload enable */ 406 #define _ETH_NETWORKCFG_RXCHKSUMOFFLOADEN_SHIFT 24 /**< Shift value for ETH_RXCHKSUMOFFLOADEN */ 407 #define _ETH_NETWORKCFG_RXCHKSUMOFFLOADEN_MASK 0x1000000UL /**< Bit mask for ETH_RXCHKSUMOFFLOADEN */ 408 #define _ETH_NETWORKCFG_RXCHKSUMOFFLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 409 #define ETH_NETWORKCFG_RXCHKSUMOFFLOADEN_DEFAULT (_ETH_NETWORKCFG_RXCHKSUMOFFLOADEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 410 #define ETH_NETWORKCFG_ENHALFDUPLEXRX (0x1UL << 25) /**< Enable frames to be received in half-duplex mode while transmitting. */ 411 #define _ETH_NETWORKCFG_ENHALFDUPLEXRX_SHIFT 25 /**< Shift value for ETH_ENHALFDUPLEXRX */ 412 #define _ETH_NETWORKCFG_ENHALFDUPLEXRX_MASK 0x2000000UL /**< Bit mask for ETH_ENHALFDUPLEXRX */ 413 #define _ETH_NETWORKCFG_ENHALFDUPLEXRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 414 #define ETH_NETWORKCFG_ENHALFDUPLEXRX_DEFAULT (_ETH_NETWORKCFG_ENHALFDUPLEXRX_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 415 #define ETH_NETWORKCFG_IGNORERXFCS (0x1UL << 26) /**< Ignore RX FCS */ 416 #define _ETH_NETWORKCFG_IGNORERXFCS_SHIFT 26 /**< Shift value for ETH_IGNORERXFCS */ 417 #define _ETH_NETWORKCFG_IGNORERXFCS_MASK 0x4000000UL /**< Bit mask for ETH_IGNORERXFCS */ 418 #define _ETH_NETWORKCFG_IGNORERXFCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 419 #define ETH_NETWORKCFG_IGNORERXFCS_DEFAULT (_ETH_NETWORKCFG_IGNORERXFCS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 420 #define ETH_NETWORKCFG_IPGSTRTCHEN (0x1UL << 28) /**< IPG stretch enable */ 421 #define _ETH_NETWORKCFG_IPGSTRTCHEN_SHIFT 28 /**< Shift value for ETH_IPGSTRTCHEN */ 422 #define _ETH_NETWORKCFG_IPGSTRTCHEN_MASK 0x10000000UL /**< Bit mask for ETH_IPGSTRTCHEN */ 423 #define _ETH_NETWORKCFG_IPGSTRTCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 424 #define ETH_NETWORKCFG_IPGSTRTCHEN_DEFAULT (_ETH_NETWORKCFG_IPGSTRTCHEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 425 #define ETH_NETWORKCFG_NSPCHANGE (0x1UL << 29) /**< Receive bad preamble. */ 426 #define _ETH_NETWORKCFG_NSPCHANGE_SHIFT 29 /**< Shift value for ETH_NSPCHANGE */ 427 #define _ETH_NETWORKCFG_NSPCHANGE_MASK 0x20000000UL /**< Bit mask for ETH_NSPCHANGE */ 428 #define _ETH_NETWORKCFG_NSPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 429 #define ETH_NETWORKCFG_NSPCHANGE_DEFAULT (_ETH_NETWORKCFG_NSPCHANGE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 430 #define ETH_NETWORKCFG_IGNOREIPGRXER (0x1UL << 30) /**< Ignore IPG rx_er. */ 431 #define _ETH_NETWORKCFG_IGNOREIPGRXER_SHIFT 30 /**< Shift value for ETH_IGNOREIPGRXER */ 432 #define _ETH_NETWORKCFG_IGNOREIPGRXER_MASK 0x40000000UL /**< Bit mask for ETH_IGNOREIPGRXER */ 433 #define _ETH_NETWORKCFG_IGNOREIPGRXER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKCFG */ 434 #define ETH_NETWORKCFG_IGNOREIPGRXER_DEFAULT (_ETH_NETWORKCFG_IGNOREIPGRXER_DEFAULT << 30) /**< Shifted mode DEFAULT for ETH_NETWORKCFG */ 435 436 /* Bit fields for ETH NETWORKSTATUS */ 437 #define _ETH_NETWORKSTATUS_RESETVALUE 0x00000004UL /**< Default value for ETH_NETWORKSTATUS */ 438 #define _ETH_NETWORKSTATUS_MASK 0x000000C6UL /**< Mask for ETH_NETWORKSTATUS */ 439 #define ETH_NETWORKSTATUS_MDIOIN (0x1UL << 1) /**< Returns status of the mdio_in pin. */ 440 #define _ETH_NETWORKSTATUS_MDIOIN_SHIFT 1 /**< Shift value for ETH_MDIOIN */ 441 #define _ETH_NETWORKSTATUS_MDIOIN_MASK 0x2UL /**< Bit mask for ETH_MDIOIN */ 442 #define _ETH_NETWORKSTATUS_MDIOIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKSTATUS */ 443 #define ETH_NETWORKSTATUS_MDIOIN_DEFAULT (_ETH_NETWORKSTATUS_MDIOIN_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_NETWORKSTATUS */ 444 #define ETH_NETWORKSTATUS_MANDONE (0x1UL << 2) /**< The PHY management logic is idle (i.e. has completed). */ 445 #define _ETH_NETWORKSTATUS_MANDONE_SHIFT 2 /**< Shift value for ETH_MANDONE */ 446 #define _ETH_NETWORKSTATUS_MANDONE_MASK 0x4UL /**< Bit mask for ETH_MANDONE */ 447 #define _ETH_NETWORKSTATUS_MANDONE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_NETWORKSTATUS */ 448 #define ETH_NETWORKSTATUS_MANDONE_DEFAULT (_ETH_NETWORKSTATUS_MANDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_NETWORKSTATUS */ 449 #define ETH_NETWORKSTATUS_PFCNEGOTIATE (0x1UL << 6) /**< Set when PFC Priority Based Pause has been negotiated. */ 450 #define _ETH_NETWORKSTATUS_PFCNEGOTIATE_SHIFT 6 /**< Shift value for ETH_PFCNEGOTIATE */ 451 #define _ETH_NETWORKSTATUS_PFCNEGOTIATE_MASK 0x40UL /**< Bit mask for ETH_PFCNEGOTIATE */ 452 #define _ETH_NETWORKSTATUS_PFCNEGOTIATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKSTATUS */ 453 #define ETH_NETWORKSTATUS_PFCNEGOTIATE_DEFAULT (_ETH_NETWORKSTATUS_PFCNEGOTIATE_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_NETWORKSTATUS */ 454 #define ETH_NETWORKSTATUS_LPIINDICATE (0x1UL << 7) /**< LPI Indication */ 455 #define _ETH_NETWORKSTATUS_LPIINDICATE_SHIFT 7 /**< Shift value for ETH_LPIINDICATE */ 456 #define _ETH_NETWORKSTATUS_LPIINDICATE_MASK 0x80UL /**< Bit mask for ETH_LPIINDICATE */ 457 #define _ETH_NETWORKSTATUS_LPIINDICATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_NETWORKSTATUS */ 458 #define ETH_NETWORKSTATUS_LPIINDICATE_DEFAULT (_ETH_NETWORKSTATUS_LPIINDICATE_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_NETWORKSTATUS */ 459 460 /* Bit fields for ETH DMACFG */ 461 #define _ETH_DMACFG_RESETVALUE 0x00020704UL /**< Default value for ETH_DMACFG */ 462 #define _ETH_DMACFG_MASK 0x37FF1F3FUL /**< Mask for ETH_DMACFG */ 463 #define _ETH_DMACFG_AMBABRSTLEN_SHIFT 0 /**< Shift value for ETH_AMBABRSTLEN */ 464 #define _ETH_DMACFG_AMBABRSTLEN_MASK 0x1FUL /**< Bit mask for ETH_AMBABRSTLEN */ 465 #define _ETH_DMACFG_AMBABRSTLEN_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETH_DMACFG */ 466 #define ETH_DMACFG_AMBABRSTLEN_DEFAULT (_ETH_DMACFG_AMBABRSTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_DMACFG */ 467 #define ETH_DMACFG_HDRDATASPLITEN (0x1UL << 5) /**< Enable header data Splitting. */ 468 #define _ETH_DMACFG_HDRDATASPLITEN_SHIFT 5 /**< Shift value for ETH_HDRDATASPLITEN */ 469 #define _ETH_DMACFG_HDRDATASPLITEN_MASK 0x20UL /**< Bit mask for ETH_HDRDATASPLITEN */ 470 #define _ETH_DMACFG_HDRDATASPLITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ 471 #define ETH_DMACFG_HDRDATASPLITEN_DEFAULT (_ETH_DMACFG_HDRDATASPLITEN_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_DMACFG */ 472 #define _ETH_DMACFG_RXPBUFSIZE_SHIFT 8 /**< Shift value for ETH_RXPBUFSIZE */ 473 #define _ETH_DMACFG_RXPBUFSIZE_MASK 0x300UL /**< Bit mask for ETH_RXPBUFSIZE */ 474 #define _ETH_DMACFG_RXPBUFSIZE_SIZE0 0x00000000UL /**< Mode SIZE0 for ETH_DMACFG */ 475 #define _ETH_DMACFG_RXPBUFSIZE_SIZE1 0x00000001UL /**< Mode SIZE1 for ETH_DMACFG */ 476 #define _ETH_DMACFG_RXPBUFSIZE_SIZE2 0x00000002UL /**< Mode SIZE2 for ETH_DMACFG */ 477 #define _ETH_DMACFG_RXPBUFSIZE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETH_DMACFG */ 478 #define _ETH_DMACFG_RXPBUFSIZE_SIZE3 0x00000003UL /**< Mode SIZE3 for ETH_DMACFG */ 479 #define ETH_DMACFG_RXPBUFSIZE_SIZE0 (_ETH_DMACFG_RXPBUFSIZE_SIZE0 << 8) /**< Shifted mode SIZE0 for ETH_DMACFG */ 480 #define ETH_DMACFG_RXPBUFSIZE_SIZE1 (_ETH_DMACFG_RXPBUFSIZE_SIZE1 << 8) /**< Shifted mode SIZE1 for ETH_DMACFG */ 481 #define ETH_DMACFG_RXPBUFSIZE_SIZE2 (_ETH_DMACFG_RXPBUFSIZE_SIZE2 << 8) /**< Shifted mode SIZE2 for ETH_DMACFG */ 482 #define ETH_DMACFG_RXPBUFSIZE_DEFAULT (_ETH_DMACFG_RXPBUFSIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_DMACFG */ 483 #define ETH_DMACFG_RXPBUFSIZE_SIZE3 (_ETH_DMACFG_RXPBUFSIZE_SIZE3 << 8) /**< Shifted mode SIZE3 for ETH_DMACFG */ 484 #define ETH_DMACFG_TXPBUFSIZE (0x1UL << 10) /**< Transmitter packet buffer memory size select. */ 485 #define _ETH_DMACFG_TXPBUFSIZE_SHIFT 10 /**< Shift value for ETH_TXPBUFSIZE */ 486 #define _ETH_DMACFG_TXPBUFSIZE_MASK 0x400UL /**< Bit mask for ETH_TXPBUFSIZE */ 487 #define _ETH_DMACFG_TXPBUFSIZE_SIZE0 0x00000000UL /**< Mode SIZE0 for ETH_DMACFG */ 488 #define _ETH_DMACFG_TXPBUFSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_DMACFG */ 489 #define _ETH_DMACFG_TXPBUFSIZE_SIZE1 0x00000001UL /**< Mode SIZE1 for ETH_DMACFG */ 490 #define ETH_DMACFG_TXPBUFSIZE_SIZE0 (_ETH_DMACFG_TXPBUFSIZE_SIZE0 << 10) /**< Shifted mode SIZE0 for ETH_DMACFG */ 491 #define ETH_DMACFG_TXPBUFSIZE_DEFAULT (_ETH_DMACFG_TXPBUFSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_DMACFG */ 492 #define ETH_DMACFG_TXPBUFSIZE_SIZE1 (_ETH_DMACFG_TXPBUFSIZE_SIZE1 << 10) /**< Shifted mode SIZE1 for ETH_DMACFG */ 493 #define ETH_DMACFG_TXPBUFTCPEN (0x1UL << 11) /**< Transmitter IP, TCP and UDP checksum generation offload enable */ 494 #define _ETH_DMACFG_TXPBUFTCPEN_SHIFT 11 /**< Shift value for ETH_TXPBUFTCPEN */ 495 #define _ETH_DMACFG_TXPBUFTCPEN_MASK 0x800UL /**< Bit mask for ETH_TXPBUFTCPEN */ 496 #define _ETH_DMACFG_TXPBUFTCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ 497 #define ETH_DMACFG_TXPBUFTCPEN_DEFAULT (_ETH_DMACFG_TXPBUFTCPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for ETH_DMACFG */ 498 #define ETH_DMACFG_INFLASTDBUFSIZEEN (0x1UL << 12) /**< Forces the DMA */ 499 #define _ETH_DMACFG_INFLASTDBUFSIZEEN_SHIFT 12 /**< Shift value for ETH_INFLASTDBUFSIZEEN */ 500 #define _ETH_DMACFG_INFLASTDBUFSIZEEN_MASK 0x1000UL /**< Bit mask for ETH_INFLASTDBUFSIZEEN */ 501 #define _ETH_DMACFG_INFLASTDBUFSIZEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ 502 #define ETH_DMACFG_INFLASTDBUFSIZEEN_DEFAULT (_ETH_DMACFG_INFLASTDBUFSIZEEN_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_DMACFG */ 503 #define _ETH_DMACFG_RXBUFSIZE_SHIFT 16 /**< Shift value for ETH_RXBUFSIZE */ 504 #define _ETH_DMACFG_RXBUFSIZE_MASK 0xFF0000UL /**< Bit mask for ETH_RXBUFSIZE */ 505 #define _ETH_DMACFG_RXBUFSIZE_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETH_DMACFG */ 506 #define ETH_DMACFG_RXBUFSIZE_DEFAULT (_ETH_DMACFG_RXBUFSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_DMACFG */ 507 #define ETH_DMACFG_FRCDISCARDONERR (0x1UL << 24) /**< Auto Discard RX pkts during lack of resource. */ 508 #define _ETH_DMACFG_FRCDISCARDONERR_SHIFT 24 /**< Shift value for ETH_FRCDISCARDONERR */ 509 #define _ETH_DMACFG_FRCDISCARDONERR_MASK 0x1000000UL /**< Bit mask for ETH_FRCDISCARDONERR */ 510 #define _ETH_DMACFG_FRCDISCARDONERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ 511 #define ETH_DMACFG_FRCDISCARDONERR_DEFAULT (_ETH_DMACFG_FRCDISCARDONERR_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_DMACFG */ 512 #define ETH_DMACFG_FRCMAXAMBABRSTRX (0x1UL << 25) /**< Force max length bursts on RX. */ 513 #define _ETH_DMACFG_FRCMAXAMBABRSTRX_SHIFT 25 /**< Shift value for ETH_FRCMAXAMBABRSTRX */ 514 #define _ETH_DMACFG_FRCMAXAMBABRSTRX_MASK 0x2000000UL /**< Bit mask for ETH_FRCMAXAMBABRSTRX */ 515 #define _ETH_DMACFG_FRCMAXAMBABRSTRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ 516 #define ETH_DMACFG_FRCMAXAMBABRSTRX_DEFAULT (_ETH_DMACFG_FRCMAXAMBABRSTRX_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_DMACFG */ 517 #define ETH_DMACFG_FRCMAXAMBABRSTTX (0x1UL << 26) /**< Force max length bursts on TX. */ 518 #define _ETH_DMACFG_FRCMAXAMBABRSTTX_SHIFT 26 /**< Shift value for ETH_FRCMAXAMBABRSTTX */ 519 #define _ETH_DMACFG_FRCMAXAMBABRSTTX_MASK 0x4000000UL /**< Bit mask for ETH_FRCMAXAMBABRSTTX */ 520 #define _ETH_DMACFG_FRCMAXAMBABRSTTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ 521 #define ETH_DMACFG_FRCMAXAMBABRSTTX_DEFAULT (_ETH_DMACFG_FRCMAXAMBABRSTTX_DEFAULT << 26) /**< Shifted mode DEFAULT for ETH_DMACFG */ 522 #define ETH_DMACFG_RXBDEXTNDMODEEN (0x1UL << 28) /**< Enable RX extended BD mode. */ 523 #define _ETH_DMACFG_RXBDEXTNDMODEEN_SHIFT 28 /**< Shift value for ETH_RXBDEXTNDMODEEN */ 524 #define _ETH_DMACFG_RXBDEXTNDMODEEN_MASK 0x10000000UL /**< Bit mask for ETH_RXBDEXTNDMODEEN */ 525 #define _ETH_DMACFG_RXBDEXTNDMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ 526 #define ETH_DMACFG_RXBDEXTNDMODEEN_DEFAULT (_ETH_DMACFG_RXBDEXTNDMODEEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_DMACFG */ 527 #define ETH_DMACFG_TXBDEXTENDMODEEN (0x1UL << 29) /**< Enable TX extended BD mode. */ 528 #define _ETH_DMACFG_TXBDEXTENDMODEEN_SHIFT 29 /**< Shift value for ETH_TXBDEXTENDMODEEN */ 529 #define _ETH_DMACFG_TXBDEXTENDMODEEN_MASK 0x20000000UL /**< Bit mask for ETH_TXBDEXTENDMODEEN */ 530 #define _ETH_DMACFG_TXBDEXTENDMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DMACFG */ 531 #define ETH_DMACFG_TXBDEXTENDMODEEN_DEFAULT (_ETH_DMACFG_TXBDEXTENDMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ETH_DMACFG */ 532 533 /* Bit fields for ETH TXSTATUS */ 534 #define _ETH_TXSTATUS_RESETVALUE 0x00000000UL /**< Default value for ETH_TXSTATUS */ 535 #define _ETH_TXSTATUS_MASK 0x000001FFUL /**< Mask for ETH_TXSTATUS */ 536 #define ETH_TXSTATUS_USEDBITREAD (0x1UL << 0) /**< Used bit read */ 537 #define _ETH_TXSTATUS_USEDBITREAD_SHIFT 0 /**< Shift value for ETH_USEDBITREAD */ 538 #define _ETH_TXSTATUS_USEDBITREAD_MASK 0x1UL /**< Bit mask for ETH_USEDBITREAD */ 539 #define _ETH_TXSTATUS_USEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ 540 #define ETH_TXSTATUS_USEDBITREAD_DEFAULT (_ETH_TXSTATUS_USEDBITREAD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ 541 #define ETH_TXSTATUS_COLOCCRD (0x1UL << 1) /**< Collision occurred */ 542 #define _ETH_TXSTATUS_COLOCCRD_SHIFT 1 /**< Shift value for ETH_COLOCCRD */ 543 #define _ETH_TXSTATUS_COLOCCRD_MASK 0x2UL /**< Bit mask for ETH_COLOCCRD */ 544 #define _ETH_TXSTATUS_COLOCCRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ 545 #define ETH_TXSTATUS_COLOCCRD_DEFAULT (_ETH_TXSTATUS_COLOCCRD_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ 546 #define ETH_TXSTATUS_RETRYLMTEXCD (0x1UL << 2) /**< Retry limit exceeded */ 547 #define _ETH_TXSTATUS_RETRYLMTEXCD_SHIFT 2 /**< Shift value for ETH_RETRYLMTEXCD */ 548 #define _ETH_TXSTATUS_RETRYLMTEXCD_MASK 0x4UL /**< Bit mask for ETH_RETRYLMTEXCD */ 549 #define _ETH_TXSTATUS_RETRYLMTEXCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ 550 #define ETH_TXSTATUS_RETRYLMTEXCD_DEFAULT (_ETH_TXSTATUS_RETRYLMTEXCD_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ 551 #define ETH_TXSTATUS_TXGO (0x1UL << 3) /**< Transmit go */ 552 #define _ETH_TXSTATUS_TXGO_SHIFT 3 /**< Shift value for ETH_TXGO */ 553 #define _ETH_TXSTATUS_TXGO_MASK 0x8UL /**< Bit mask for ETH_TXGO */ 554 #define _ETH_TXSTATUS_TXGO_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ 555 #define ETH_TXSTATUS_TXGO_DEFAULT (_ETH_TXSTATUS_TXGO_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ 556 #define ETH_TXSTATUS_AMBAERR (0x1UL << 4) /**< Transmit frame corruption due to AMBA (AHB) errors. */ 557 #define _ETH_TXSTATUS_AMBAERR_SHIFT 4 /**< Shift value for ETH_AMBAERR */ 558 #define _ETH_TXSTATUS_AMBAERR_MASK 0x10UL /**< Bit mask for ETH_AMBAERR */ 559 #define _ETH_TXSTATUS_AMBAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ 560 #define ETH_TXSTATUS_AMBAERR_DEFAULT (_ETH_TXSTATUS_AMBAERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ 561 #define ETH_TXSTATUS_TXCMPLT (0x1UL << 5) /**< Transmit complete */ 562 #define _ETH_TXSTATUS_TXCMPLT_SHIFT 5 /**< Shift value for ETH_TXCMPLT */ 563 #define _ETH_TXSTATUS_TXCMPLT_MASK 0x20UL /**< Bit mask for ETH_TXCMPLT */ 564 #define _ETH_TXSTATUS_TXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ 565 #define ETH_TXSTATUS_TXCMPLT_DEFAULT (_ETH_TXSTATUS_TXCMPLT_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ 566 #define ETH_TXSTATUS_TXUNDERRUN (0x1UL << 6) /**< Transmit under run */ 567 #define _ETH_TXSTATUS_TXUNDERRUN_SHIFT 6 /**< Shift value for ETH_TXUNDERRUN */ 568 #define _ETH_TXSTATUS_TXUNDERRUN_MASK 0x40UL /**< Bit mask for ETH_TXUNDERRUN */ 569 #define _ETH_TXSTATUS_TXUNDERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ 570 #define ETH_TXSTATUS_TXUNDERRUN_DEFAULT (_ETH_TXSTATUS_TXUNDERRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ 571 #define ETH_TXSTATUS_LATECOLOCCRD (0x1UL << 7) /**< Late collision occurred */ 572 #define _ETH_TXSTATUS_LATECOLOCCRD_SHIFT 7 /**< Shift value for ETH_LATECOLOCCRD */ 573 #define _ETH_TXSTATUS_LATECOLOCCRD_MASK 0x80UL /**< Bit mask for ETH_LATECOLOCCRD */ 574 #define _ETH_TXSTATUS_LATECOLOCCRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ 575 #define ETH_TXSTATUS_LATECOLOCCRD_DEFAULT (_ETH_TXSTATUS_LATECOLOCCRD_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ 576 #define ETH_TXSTATUS_RESPNOTOK (0x1UL << 8) /**< bresp/hresp not OK */ 577 #define _ETH_TXSTATUS_RESPNOTOK_SHIFT 8 /**< Shift value for ETH_RESPNOTOK */ 578 #define _ETH_TXSTATUS_RESPNOTOK_MASK 0x100UL /**< Bit mask for ETH_RESPNOTOK */ 579 #define _ETH_TXSTATUS_RESPNOTOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXSTATUS */ 580 #define ETH_TXSTATUS_RESPNOTOK_DEFAULT (_ETH_TXSTATUS_RESPNOTOK_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_TXSTATUS */ 581 582 /* Bit fields for ETH RXQPTR */ 583 #define _ETH_RXQPTR_RESETVALUE 0x00000000UL /**< Default value for ETH_RXQPTR */ 584 #define _ETH_RXQPTR_MASK 0xFFFFFFFCUL /**< Mask for ETH_RXQPTR */ 585 #define _ETH_RXQPTR_DMARXQPTR_SHIFT 2 /**< Shift value for ETH_DMARXQPTR */ 586 #define _ETH_RXQPTR_DMARXQPTR_MASK 0xFFFFFFFCUL /**< Bit mask for ETH_DMARXQPTR */ 587 #define _ETH_RXQPTR_DMARXQPTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXQPTR */ 588 #define ETH_RXQPTR_DMARXQPTR_DEFAULT (_ETH_RXQPTR_DMARXQPTR_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_RXQPTR */ 589 590 /* Bit fields for ETH TXQPTR */ 591 #define _ETH_TXQPTR_RESETVALUE 0x00000000UL /**< Default value for ETH_TXQPTR */ 592 #define _ETH_TXQPTR_MASK 0xFFFFFFFCUL /**< Mask for ETH_TXQPTR */ 593 #define _ETH_TXQPTR_DMATXQPTR_SHIFT 2 /**< Shift value for ETH_DMATXQPTR */ 594 #define _ETH_TXQPTR_DMATXQPTR_MASK 0xFFFFFFFCUL /**< Bit mask for ETH_DMATXQPTR */ 595 #define _ETH_TXQPTR_DMATXQPTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXQPTR */ 596 #define ETH_TXQPTR_DMATXQPTR_DEFAULT (_ETH_TXQPTR_DMATXQPTR_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_TXQPTR */ 597 598 /* Bit fields for ETH RXSTATUS */ 599 #define _ETH_RXSTATUS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXSTATUS */ 600 #define _ETH_RXSTATUS_MASK 0x0000000FUL /**< Mask for ETH_RXSTATUS */ 601 #define ETH_RXSTATUS_BUFFNOTAVAIL (0x1UL << 0) /**< Buffer not available */ 602 #define _ETH_RXSTATUS_BUFFNOTAVAIL_SHIFT 0 /**< Shift value for ETH_BUFFNOTAVAIL */ 603 #define _ETH_RXSTATUS_BUFFNOTAVAIL_MASK 0x1UL /**< Bit mask for ETH_BUFFNOTAVAIL */ 604 #define _ETH_RXSTATUS_BUFFNOTAVAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXSTATUS */ 605 #define ETH_RXSTATUS_BUFFNOTAVAIL_DEFAULT (_ETH_RXSTATUS_BUFFNOTAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXSTATUS */ 606 #define ETH_RXSTATUS_FRMRX (0x1UL << 1) /**< Frame received */ 607 #define _ETH_RXSTATUS_FRMRX_SHIFT 1 /**< Shift value for ETH_FRMRX */ 608 #define _ETH_RXSTATUS_FRMRX_MASK 0x2UL /**< Bit mask for ETH_FRMRX */ 609 #define _ETH_RXSTATUS_FRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXSTATUS */ 610 #define ETH_RXSTATUS_FRMRX_DEFAULT (_ETH_RXSTATUS_FRMRX_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_RXSTATUS */ 611 #define ETH_RXSTATUS_RXOVERRUN (0x1UL << 2) /**< Receive overrun */ 612 #define _ETH_RXSTATUS_RXOVERRUN_SHIFT 2 /**< Shift value for ETH_RXOVERRUN */ 613 #define _ETH_RXSTATUS_RXOVERRUN_MASK 0x4UL /**< Bit mask for ETH_RXOVERRUN */ 614 #define _ETH_RXSTATUS_RXOVERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXSTATUS */ 615 #define ETH_RXSTATUS_RXOVERRUN_DEFAULT (_ETH_RXSTATUS_RXOVERRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_RXSTATUS */ 616 #define ETH_RXSTATUS_RESPNOTOK (0x1UL << 3) /**< bresp/hresp not OK */ 617 #define _ETH_RXSTATUS_RESPNOTOK_SHIFT 3 /**< Shift value for ETH_RESPNOTOK */ 618 #define _ETH_RXSTATUS_RESPNOTOK_MASK 0x8UL /**< Bit mask for ETH_RESPNOTOK */ 619 #define _ETH_RXSTATUS_RESPNOTOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXSTATUS */ 620 #define ETH_RXSTATUS_RESPNOTOK_DEFAULT (_ETH_RXSTATUS_RESPNOTOK_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_RXSTATUS */ 621 622 /* Bit fields for ETH IFCR */ 623 #define _ETH_IFCR_RESETVALUE 0x00000000UL /**< Default value for ETH_IFCR */ 624 #define _ETH_IFCR_MASK 0x3FFC7CFFUL /**< Mask for ETH_IFCR */ 625 #define ETH_IFCR_MNGMNTDONE (0x1UL << 0) /**< Management frame sent */ 626 #define _ETH_IFCR_MNGMNTDONE_SHIFT 0 /**< Shift value for ETH_MNGMNTDONE */ 627 #define _ETH_IFCR_MNGMNTDONE_MASK 0x1UL /**< Bit mask for ETH_MNGMNTDONE */ 628 #define _ETH_IFCR_MNGMNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 629 #define ETH_IFCR_MNGMNTDONE_DEFAULT (_ETH_IFCR_MNGMNTDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_IFCR */ 630 #define ETH_IFCR_RXCMPLT (0x1UL << 1) /**< Receive complete */ 631 #define _ETH_IFCR_RXCMPLT_SHIFT 1 /**< Shift value for ETH_RXCMPLT */ 632 #define _ETH_IFCR_RXCMPLT_MASK 0x2UL /**< Bit mask for ETH_RXCMPLT */ 633 #define _ETH_IFCR_RXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 634 #define ETH_IFCR_RXCMPLT_DEFAULT (_ETH_IFCR_RXCMPLT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_IFCR */ 635 #define ETH_IFCR_RXUSEDBITREAD (0x1UL << 2) /**< RX used bit read */ 636 #define _ETH_IFCR_RXUSEDBITREAD_SHIFT 2 /**< Shift value for ETH_RXUSEDBITREAD */ 637 #define _ETH_IFCR_RXUSEDBITREAD_MASK 0x4UL /**< Bit mask for ETH_RXUSEDBITREAD */ 638 #define _ETH_IFCR_RXUSEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 639 #define ETH_IFCR_RXUSEDBITREAD_DEFAULT (_ETH_IFCR_RXUSEDBITREAD_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_IFCR */ 640 #define ETH_IFCR_TXUSEDBITREAD (0x1UL << 3) /**< TX used bit read */ 641 #define _ETH_IFCR_TXUSEDBITREAD_SHIFT 3 /**< Shift value for ETH_TXUSEDBITREAD */ 642 #define _ETH_IFCR_TXUSEDBITREAD_MASK 0x8UL /**< Bit mask for ETH_TXUSEDBITREAD */ 643 #define _ETH_IFCR_TXUSEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 644 #define ETH_IFCR_TXUSEDBITREAD_DEFAULT (_ETH_IFCR_TXUSEDBITREAD_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_IFCR */ 645 #define ETH_IFCR_TXUNDERRUN (0x1UL << 4) /**< Transmit under run */ 646 #define _ETH_IFCR_TXUNDERRUN_SHIFT 4 /**< Shift value for ETH_TXUNDERRUN */ 647 #define _ETH_IFCR_TXUNDERRUN_MASK 0x10UL /**< Bit mask for ETH_TXUNDERRUN */ 648 #define _ETH_IFCR_TXUNDERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 649 #define ETH_IFCR_TXUNDERRUN_DEFAULT (_ETH_IFCR_TXUNDERRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_IFCR */ 650 #define ETH_IFCR_RTRYLMTORLATECOL (0x1UL << 5) /**< Retry limit exceeded or late collision */ 651 #define _ETH_IFCR_RTRYLMTORLATECOL_SHIFT 5 /**< Shift value for ETH_RTRYLMTORLATECOL */ 652 #define _ETH_IFCR_RTRYLMTORLATECOL_MASK 0x20UL /**< Bit mask for ETH_RTRYLMTORLATECOL */ 653 #define _ETH_IFCR_RTRYLMTORLATECOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 654 #define ETH_IFCR_RTRYLMTORLATECOL_DEFAULT (_ETH_IFCR_RTRYLMTORLATECOL_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_IFCR */ 655 #define ETH_IFCR_AMBAERR (0x1UL << 6) /**< Transmit frame corruption due to AMBA (AHB) error. */ 656 #define _ETH_IFCR_AMBAERR_SHIFT 6 /**< Shift value for ETH_AMBAERR */ 657 #define _ETH_IFCR_AMBAERR_MASK 0x40UL /**< Bit mask for ETH_AMBAERR */ 658 #define _ETH_IFCR_AMBAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 659 #define ETH_IFCR_AMBAERR_DEFAULT (_ETH_IFCR_AMBAERR_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_IFCR */ 660 #define ETH_IFCR_TXCMPLT (0x1UL << 7) /**< Transmit complete */ 661 #define _ETH_IFCR_TXCMPLT_SHIFT 7 /**< Shift value for ETH_TXCMPLT */ 662 #define _ETH_IFCR_TXCMPLT_MASK 0x80UL /**< Bit mask for ETH_TXCMPLT */ 663 #define _ETH_IFCR_TXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 664 #define ETH_IFCR_TXCMPLT_DEFAULT (_ETH_IFCR_TXCMPLT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_IFCR */ 665 #define ETH_IFCR_RXOVERRUN (0x1UL << 10) /**< Receive overrun */ 666 #define _ETH_IFCR_RXOVERRUN_SHIFT 10 /**< Shift value for ETH_RXOVERRUN */ 667 #define _ETH_IFCR_RXOVERRUN_MASK 0x400UL /**< Bit mask for ETH_RXOVERRUN */ 668 #define _ETH_IFCR_RXOVERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 669 #define ETH_IFCR_RXOVERRUN_DEFAULT (_ETH_IFCR_RXOVERRUN_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_IFCR */ 670 #define ETH_IFCR_RESPNOTOK (0x1UL << 11) /**< Hresp not OK */ 671 #define _ETH_IFCR_RESPNOTOK_SHIFT 11 /**< Shift value for ETH_RESPNOTOK */ 672 #define _ETH_IFCR_RESPNOTOK_MASK 0x800UL /**< Bit mask for ETH_RESPNOTOK */ 673 #define _ETH_IFCR_RESPNOTOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 674 #define ETH_IFCR_RESPNOTOK_DEFAULT (_ETH_IFCR_RESPNOTOK_DEFAULT << 11) /**< Shifted mode DEFAULT for ETH_IFCR */ 675 #define ETH_IFCR_NONZEROPFRMQUANT (0x1UL << 12) /**< Pause frame with non-zero pause quantum received */ 676 #define _ETH_IFCR_NONZEROPFRMQUANT_SHIFT 12 /**< Shift value for ETH_NONZEROPFRMQUANT */ 677 #define _ETH_IFCR_NONZEROPFRMQUANT_MASK 0x1000UL /**< Bit mask for ETH_NONZEROPFRMQUANT */ 678 #define _ETH_IFCR_NONZEROPFRMQUANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 679 #define ETH_IFCR_NONZEROPFRMQUANT_DEFAULT (_ETH_IFCR_NONZEROPFRMQUANT_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_IFCR */ 680 #define ETH_IFCR_PAUSETIMEZERO (0x1UL << 13) /**< Pause Time zero */ 681 #define _ETH_IFCR_PAUSETIMEZERO_SHIFT 13 /**< Shift value for ETH_PAUSETIMEZERO */ 682 #define _ETH_IFCR_PAUSETIMEZERO_MASK 0x2000UL /**< Bit mask for ETH_PAUSETIMEZERO */ 683 #define _ETH_IFCR_PAUSETIMEZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 684 #define ETH_IFCR_PAUSETIMEZERO_DEFAULT (_ETH_IFCR_PAUSETIMEZERO_DEFAULT << 13) /**< Shifted mode DEFAULT for ETH_IFCR */ 685 #define ETH_IFCR_PFRMTX (0x1UL << 14) /**< Pause frame transmitted */ 686 #define _ETH_IFCR_PFRMTX_SHIFT 14 /**< Shift value for ETH_PFRMTX */ 687 #define _ETH_IFCR_PFRMTX_MASK 0x4000UL /**< Bit mask for ETH_PFRMTX */ 688 #define _ETH_IFCR_PFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 689 #define ETH_IFCR_PFRMTX_DEFAULT (_ETH_IFCR_PFRMTX_DEFAULT << 14) /**< Shifted mode DEFAULT for ETH_IFCR */ 690 #define ETH_IFCR_PTPDLYREQFRMRX (0x1UL << 18) /**< PTP delay_req frame received */ 691 #define _ETH_IFCR_PTPDLYREQFRMRX_SHIFT 18 /**< Shift value for ETH_PTPDLYREQFRMRX */ 692 #define _ETH_IFCR_PTPDLYREQFRMRX_MASK 0x40000UL /**< Bit mask for ETH_PTPDLYREQFRMRX */ 693 #define _ETH_IFCR_PTPDLYREQFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 694 #define ETH_IFCR_PTPDLYREQFRMRX_DEFAULT (_ETH_IFCR_PTPDLYREQFRMRX_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_IFCR */ 695 #define ETH_IFCR_PTPSYNCFRMRX (0x1UL << 19) /**< PTP sync frame received */ 696 #define _ETH_IFCR_PTPSYNCFRMRX_SHIFT 19 /**< Shift value for ETH_PTPSYNCFRMRX */ 697 #define _ETH_IFCR_PTPSYNCFRMRX_MASK 0x80000UL /**< Bit mask for ETH_PTPSYNCFRMRX */ 698 #define _ETH_IFCR_PTPSYNCFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 699 #define ETH_IFCR_PTPSYNCFRMRX_DEFAULT (_ETH_IFCR_PTPSYNCFRMRX_DEFAULT << 19) /**< Shifted mode DEFAULT for ETH_IFCR */ 700 #define ETH_IFCR_PTPDLYREQFRMTX (0x1UL << 20) /**< PTP delay_req frame transmitted */ 701 #define _ETH_IFCR_PTPDLYREQFRMTX_SHIFT 20 /**< Shift value for ETH_PTPDLYREQFRMTX */ 702 #define _ETH_IFCR_PTPDLYREQFRMTX_MASK 0x100000UL /**< Bit mask for ETH_PTPDLYREQFRMTX */ 703 #define _ETH_IFCR_PTPDLYREQFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 704 #define ETH_IFCR_PTPDLYREQFRMTX_DEFAULT (_ETH_IFCR_PTPDLYREQFRMTX_DEFAULT << 20) /**< Shifted mode DEFAULT for ETH_IFCR */ 705 #define ETH_IFCR_PTPSYNCFRMTX (0x1UL << 21) /**< PTP sync frame transmitted */ 706 #define _ETH_IFCR_PTPSYNCFRMTX_SHIFT 21 /**< Shift value for ETH_PTPSYNCFRMTX */ 707 #define _ETH_IFCR_PTPSYNCFRMTX_MASK 0x200000UL /**< Bit mask for ETH_PTPSYNCFRMTX */ 708 #define _ETH_IFCR_PTPSYNCFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 709 #define ETH_IFCR_PTPSYNCFRMTX_DEFAULT (_ETH_IFCR_PTPSYNCFRMTX_DEFAULT << 21) /**< Shifted mode DEFAULT for ETH_IFCR */ 710 #define ETH_IFCR_PTPPDLYREQFRMRX (0x1UL << 22) /**< PTP pdelay_req frame received */ 711 #define _ETH_IFCR_PTPPDLYREQFRMRX_SHIFT 22 /**< Shift value for ETH_PTPPDLYREQFRMRX */ 712 #define _ETH_IFCR_PTPPDLYREQFRMRX_MASK 0x400000UL /**< Bit mask for ETH_PTPPDLYREQFRMRX */ 713 #define _ETH_IFCR_PTPPDLYREQFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 714 #define ETH_IFCR_PTPPDLYREQFRMRX_DEFAULT (_ETH_IFCR_PTPPDLYREQFRMRX_DEFAULT << 22) /**< Shifted mode DEFAULT for ETH_IFCR */ 715 #define ETH_IFCR_PTPPDLYRESPFRMRX (0x1UL << 23) /**< PTP pdelay_resp frame received */ 716 #define _ETH_IFCR_PTPPDLYRESPFRMRX_SHIFT 23 /**< Shift value for ETH_PTPPDLYRESPFRMRX */ 717 #define _ETH_IFCR_PTPPDLYRESPFRMRX_MASK 0x800000UL /**< Bit mask for ETH_PTPPDLYRESPFRMRX */ 718 #define _ETH_IFCR_PTPPDLYRESPFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 719 #define ETH_IFCR_PTPPDLYRESPFRMRX_DEFAULT (_ETH_IFCR_PTPPDLYRESPFRMRX_DEFAULT << 23) /**< Shifted mode DEFAULT for ETH_IFCR */ 720 #define ETH_IFCR_PTPPDLYREQFRMTX (0x1UL << 24) /**< PTP pdelay_req frame transmitted */ 721 #define _ETH_IFCR_PTPPDLYREQFRMTX_SHIFT 24 /**< Shift value for ETH_PTPPDLYREQFRMTX */ 722 #define _ETH_IFCR_PTPPDLYREQFRMTX_MASK 0x1000000UL /**< Bit mask for ETH_PTPPDLYREQFRMTX */ 723 #define _ETH_IFCR_PTPPDLYREQFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 724 #define ETH_IFCR_PTPPDLYREQFRMTX_DEFAULT (_ETH_IFCR_PTPPDLYREQFRMTX_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_IFCR */ 725 #define ETH_IFCR_PTPPDLYRESPFRMTX (0x1UL << 25) /**< PTP pdelay_resp frame transmitted */ 726 #define _ETH_IFCR_PTPPDLYRESPFRMTX_SHIFT 25 /**< Shift value for ETH_PTPPDLYRESPFRMTX */ 727 #define _ETH_IFCR_PTPPDLYRESPFRMTX_MASK 0x2000000UL /**< Bit mask for ETH_PTPPDLYRESPFRMTX */ 728 #define _ETH_IFCR_PTPPDLYRESPFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 729 #define ETH_IFCR_PTPPDLYRESPFRMTX_DEFAULT (_ETH_IFCR_PTPPDLYRESPFRMTX_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_IFCR */ 730 #define ETH_IFCR_TSUSECREGINCR (0x1UL << 26) /**< TSU seconds register increment */ 731 #define _ETH_IFCR_TSUSECREGINCR_SHIFT 26 /**< Shift value for ETH_TSUSECREGINCR */ 732 #define _ETH_IFCR_TSUSECREGINCR_MASK 0x4000000UL /**< Bit mask for ETH_TSUSECREGINCR */ 733 #define _ETH_IFCR_TSUSECREGINCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 734 #define ETH_IFCR_TSUSECREGINCR_DEFAULT (_ETH_IFCR_TSUSECREGINCR_DEFAULT << 26) /**< Shifted mode DEFAULT for ETH_IFCR */ 735 #define ETH_IFCR_RXLPIINDC (0x1UL << 27) /**< Receive LPI indication status bit change */ 736 #define _ETH_IFCR_RXLPIINDC_SHIFT 27 /**< Shift value for ETH_RXLPIINDC */ 737 #define _ETH_IFCR_RXLPIINDC_MASK 0x8000000UL /**< Bit mask for ETH_RXLPIINDC */ 738 #define _ETH_IFCR_RXLPIINDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 739 #define ETH_IFCR_RXLPIINDC_DEFAULT (_ETH_IFCR_RXLPIINDC_DEFAULT << 27) /**< Shifted mode DEFAULT for ETH_IFCR */ 740 #define ETH_IFCR_WOLEVNTRX (0x1UL << 28) /**< WOL event received interrupt. */ 741 #define _ETH_IFCR_WOLEVNTRX_SHIFT 28 /**< Shift value for ETH_WOLEVNTRX */ 742 #define _ETH_IFCR_WOLEVNTRX_MASK 0x10000000UL /**< Bit mask for ETH_WOLEVNTRX */ 743 #define _ETH_IFCR_WOLEVNTRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 744 #define ETH_IFCR_WOLEVNTRX_DEFAULT (_ETH_IFCR_WOLEVNTRX_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_IFCR */ 745 #define ETH_IFCR_TSUTIMERCOMP (0x1UL << 29) /**< TSU timer comparison interrupt. */ 746 #define _ETH_IFCR_TSUTIMERCOMP_SHIFT 29 /**< Shift value for ETH_TSUTIMERCOMP */ 747 #define _ETH_IFCR_TSUTIMERCOMP_MASK 0x20000000UL /**< Bit mask for ETH_TSUTIMERCOMP */ 748 #define _ETH_IFCR_TSUTIMERCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IFCR */ 749 #define ETH_IFCR_TSUTIMERCOMP_DEFAULT (_ETH_IFCR_TSUTIMERCOMP_DEFAULT << 29) /**< Shifted mode DEFAULT for ETH_IFCR */ 750 751 /* Bit fields for ETH IENS */ 752 #define _ETH_IENS_RESETVALUE 0x00000000UL /**< Default value for ETH_IENS */ 753 #define _ETH_IENS_MASK 0x3FFC7CFFUL /**< Mask for ETH_IENS */ 754 #define ETH_IENS_MNGMNTDONE (0x1UL << 0) /**< Enable management done interrupt */ 755 #define _ETH_IENS_MNGMNTDONE_SHIFT 0 /**< Shift value for ETH_MNGMNTDONE */ 756 #define _ETH_IENS_MNGMNTDONE_MASK 0x1UL /**< Bit mask for ETH_MNGMNTDONE */ 757 #define _ETH_IENS_MNGMNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 758 #define ETH_IENS_MNGMNTDONE_DEFAULT (_ETH_IENS_MNGMNTDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_IENS */ 759 #define ETH_IENS_RXCMPLT (0x1UL << 1) /**< Enable receive complete interrupt */ 760 #define _ETH_IENS_RXCMPLT_SHIFT 1 /**< Shift value for ETH_RXCMPLT */ 761 #define _ETH_IENS_RXCMPLT_MASK 0x2UL /**< Bit mask for ETH_RXCMPLT */ 762 #define _ETH_IENS_RXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 763 #define ETH_IENS_RXCMPLT_DEFAULT (_ETH_IENS_RXCMPLT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_IENS */ 764 #define ETH_IENS_RXUSEDBITREAD (0x1UL << 2) /**< Enable receive used bit read interrupt */ 765 #define _ETH_IENS_RXUSEDBITREAD_SHIFT 2 /**< Shift value for ETH_RXUSEDBITREAD */ 766 #define _ETH_IENS_RXUSEDBITREAD_MASK 0x4UL /**< Bit mask for ETH_RXUSEDBITREAD */ 767 #define _ETH_IENS_RXUSEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 768 #define ETH_IENS_RXUSEDBITREAD_DEFAULT (_ETH_IENS_RXUSEDBITREAD_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_IENS */ 769 #define ETH_IENS_TXUSEDBITREAD (0x1UL << 3) /**< Enable transmit used bit read interrupt */ 770 #define _ETH_IENS_TXUSEDBITREAD_SHIFT 3 /**< Shift value for ETH_TXUSEDBITREAD */ 771 #define _ETH_IENS_TXUSEDBITREAD_MASK 0x8UL /**< Bit mask for ETH_TXUSEDBITREAD */ 772 #define _ETH_IENS_TXUSEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 773 #define ETH_IENS_TXUSEDBITREAD_DEFAULT (_ETH_IENS_TXUSEDBITREAD_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_IENS */ 774 #define ETH_IENS_TXUNDERRUN (0x1UL << 4) /**< Enable transmit buffer under run interrupt */ 775 #define _ETH_IENS_TXUNDERRUN_SHIFT 4 /**< Shift value for ETH_TXUNDERRUN */ 776 #define _ETH_IENS_TXUNDERRUN_MASK 0x10UL /**< Bit mask for ETH_TXUNDERRUN */ 777 #define _ETH_IENS_TXUNDERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 778 #define ETH_IENS_TXUNDERRUN_DEFAULT (_ETH_IENS_TXUNDERRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_IENS */ 779 #define ETH_IENS_RTRYLMTORLATECOL (0x1UL << 5) /**< Enable retry limit exceeded or late collision interrupt */ 780 #define _ETH_IENS_RTRYLMTORLATECOL_SHIFT 5 /**< Shift value for ETH_RTRYLMTORLATECOL */ 781 #define _ETH_IENS_RTRYLMTORLATECOL_MASK 0x20UL /**< Bit mask for ETH_RTRYLMTORLATECOL */ 782 #define _ETH_IENS_RTRYLMTORLATECOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 783 #define ETH_IENS_RTRYLMTORLATECOL_DEFAULT (_ETH_IENS_RTRYLMTORLATECOL_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_IENS */ 784 #define ETH_IENS_AMBAERR (0x1UL << 6) /**< Enable transmit frame corruption due to AMBA (AHB) error interrupt */ 785 #define _ETH_IENS_AMBAERR_SHIFT 6 /**< Shift value for ETH_AMBAERR */ 786 #define _ETH_IENS_AMBAERR_MASK 0x40UL /**< Bit mask for ETH_AMBAERR */ 787 #define _ETH_IENS_AMBAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 788 #define ETH_IENS_AMBAERR_DEFAULT (_ETH_IENS_AMBAERR_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_IENS */ 789 #define ETH_IENS_TXCMPLT (0x1UL << 7) /**< Enable transmit complete interrupt */ 790 #define _ETH_IENS_TXCMPLT_SHIFT 7 /**< Shift value for ETH_TXCMPLT */ 791 #define _ETH_IENS_TXCMPLT_MASK 0x80UL /**< Bit mask for ETH_TXCMPLT */ 792 #define _ETH_IENS_TXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 793 #define ETH_IENS_TXCMPLT_DEFAULT (_ETH_IENS_TXCMPLT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_IENS */ 794 #define ETH_IENS_RXOVERRUN (0x1UL << 10) /**< Enable receive overrun interrupt */ 795 #define _ETH_IENS_RXOVERRUN_SHIFT 10 /**< Shift value for ETH_RXOVERRUN */ 796 #define _ETH_IENS_RXOVERRUN_MASK 0x400UL /**< Bit mask for ETH_RXOVERRUN */ 797 #define _ETH_IENS_RXOVERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 798 #define ETH_IENS_RXOVERRUN_DEFAULT (_ETH_IENS_RXOVERRUN_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_IENS */ 799 #define ETH_IENS_RESPNOTOK (0x1UL << 11) /**< Enable bresp/hresp not OK interrupt */ 800 #define _ETH_IENS_RESPNOTOK_SHIFT 11 /**< Shift value for ETH_RESPNOTOK */ 801 #define _ETH_IENS_RESPNOTOK_MASK 0x800UL /**< Bit mask for ETH_RESPNOTOK */ 802 #define _ETH_IENS_RESPNOTOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 803 #define ETH_IENS_RESPNOTOK_DEFAULT (_ETH_IENS_RESPNOTOK_DEFAULT << 11) /**< Shifted mode DEFAULT for ETH_IENS */ 804 #define ETH_IENS_NONZEROPFRMQUANT (0x1UL << 12) /**< Enable pause frame with non-zero pause quantum interrupt */ 805 #define _ETH_IENS_NONZEROPFRMQUANT_SHIFT 12 /**< Shift value for ETH_NONZEROPFRMQUANT */ 806 #define _ETH_IENS_NONZEROPFRMQUANT_MASK 0x1000UL /**< Bit mask for ETH_NONZEROPFRMQUANT */ 807 #define _ETH_IENS_NONZEROPFRMQUANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 808 #define ETH_IENS_NONZEROPFRMQUANT_DEFAULT (_ETH_IENS_NONZEROPFRMQUANT_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_IENS */ 809 #define ETH_IENS_PAUSETIMEZERO (0x1UL << 13) /**< Enable pause time zero interrupt */ 810 #define _ETH_IENS_PAUSETIMEZERO_SHIFT 13 /**< Shift value for ETH_PAUSETIMEZERO */ 811 #define _ETH_IENS_PAUSETIMEZERO_MASK 0x2000UL /**< Bit mask for ETH_PAUSETIMEZERO */ 812 #define _ETH_IENS_PAUSETIMEZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 813 #define ETH_IENS_PAUSETIMEZERO_DEFAULT (_ETH_IENS_PAUSETIMEZERO_DEFAULT << 13) /**< Shifted mode DEFAULT for ETH_IENS */ 814 #define ETH_IENS_PFRMTX (0x1UL << 14) /**< Enable pause frame transmitted interrupt */ 815 #define _ETH_IENS_PFRMTX_SHIFT 14 /**< Shift value for ETH_PFRMTX */ 816 #define _ETH_IENS_PFRMTX_MASK 0x4000UL /**< Bit mask for ETH_PFRMTX */ 817 #define _ETH_IENS_PFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 818 #define ETH_IENS_PFRMTX_DEFAULT (_ETH_IENS_PFRMTX_DEFAULT << 14) /**< Shifted mode DEFAULT for ETH_IENS */ 819 #define ETH_IENS_PTPDLYREQFRMRX (0x1UL << 18) /**< Enable PTP delay_req frame received interrupt */ 820 #define _ETH_IENS_PTPDLYREQFRMRX_SHIFT 18 /**< Shift value for ETH_PTPDLYREQFRMRX */ 821 #define _ETH_IENS_PTPDLYREQFRMRX_MASK 0x40000UL /**< Bit mask for ETH_PTPDLYREQFRMRX */ 822 #define _ETH_IENS_PTPDLYREQFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 823 #define ETH_IENS_PTPDLYREQFRMRX_DEFAULT (_ETH_IENS_PTPDLYREQFRMRX_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_IENS */ 824 #define ETH_IENS_PTPSYNCFRMRX (0x1UL << 19) /**< Enable PTP sync frame received interrupt */ 825 #define _ETH_IENS_PTPSYNCFRMRX_SHIFT 19 /**< Shift value for ETH_PTPSYNCFRMRX */ 826 #define _ETH_IENS_PTPSYNCFRMRX_MASK 0x80000UL /**< Bit mask for ETH_PTPSYNCFRMRX */ 827 #define _ETH_IENS_PTPSYNCFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 828 #define ETH_IENS_PTPSYNCFRMRX_DEFAULT (_ETH_IENS_PTPSYNCFRMRX_DEFAULT << 19) /**< Shifted mode DEFAULT for ETH_IENS */ 829 #define ETH_IENS_PTPDLYREQFRMTX (0x1UL << 20) /**< Enable PTP delay_req frame transmitted interrupt */ 830 #define _ETH_IENS_PTPDLYREQFRMTX_SHIFT 20 /**< Shift value for ETH_PTPDLYREQFRMTX */ 831 #define _ETH_IENS_PTPDLYREQFRMTX_MASK 0x100000UL /**< Bit mask for ETH_PTPDLYREQFRMTX */ 832 #define _ETH_IENS_PTPDLYREQFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 833 #define ETH_IENS_PTPDLYREQFRMTX_DEFAULT (_ETH_IENS_PTPDLYREQFRMTX_DEFAULT << 20) /**< Shifted mode DEFAULT for ETH_IENS */ 834 #define ETH_IENS_PTPSYNCFRMTX (0x1UL << 21) /**< Enable PTP sync frame transmitted interrupt */ 835 #define _ETH_IENS_PTPSYNCFRMTX_SHIFT 21 /**< Shift value for ETH_PTPSYNCFRMTX */ 836 #define _ETH_IENS_PTPSYNCFRMTX_MASK 0x200000UL /**< Bit mask for ETH_PTPSYNCFRMTX */ 837 #define _ETH_IENS_PTPSYNCFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 838 #define ETH_IENS_PTPSYNCFRMTX_DEFAULT (_ETH_IENS_PTPSYNCFRMTX_DEFAULT << 21) /**< Shifted mode DEFAULT for ETH_IENS */ 839 #define ETH_IENS_PTPPDLYREQFRMRX (0x1UL << 22) /**< Enable PTP pdelay_req frame received interrupt */ 840 #define _ETH_IENS_PTPPDLYREQFRMRX_SHIFT 22 /**< Shift value for ETH_PTPPDLYREQFRMRX */ 841 #define _ETH_IENS_PTPPDLYREQFRMRX_MASK 0x400000UL /**< Bit mask for ETH_PTPPDLYREQFRMRX */ 842 #define _ETH_IENS_PTPPDLYREQFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 843 #define ETH_IENS_PTPPDLYREQFRMRX_DEFAULT (_ETH_IENS_PTPPDLYREQFRMRX_DEFAULT << 22) /**< Shifted mode DEFAULT for ETH_IENS */ 844 #define ETH_IENS_PTPPDLYRESPFRMRX (0x1UL << 23) /**< Enable PTP pdelay_resp frame received interrupt */ 845 #define _ETH_IENS_PTPPDLYRESPFRMRX_SHIFT 23 /**< Shift value for ETH_PTPPDLYRESPFRMRX */ 846 #define _ETH_IENS_PTPPDLYRESPFRMRX_MASK 0x800000UL /**< Bit mask for ETH_PTPPDLYRESPFRMRX */ 847 #define _ETH_IENS_PTPPDLYRESPFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 848 #define ETH_IENS_PTPPDLYRESPFRMRX_DEFAULT (_ETH_IENS_PTPPDLYRESPFRMRX_DEFAULT << 23) /**< Shifted mode DEFAULT for ETH_IENS */ 849 #define ETH_IENS_PTPPDLYREQFRMTX (0x1UL << 24) /**< Enable PTP pdelay_req frame transmitted interrupt */ 850 #define _ETH_IENS_PTPPDLYREQFRMTX_SHIFT 24 /**< Shift value for ETH_PTPPDLYREQFRMTX */ 851 #define _ETH_IENS_PTPPDLYREQFRMTX_MASK 0x1000000UL /**< Bit mask for ETH_PTPPDLYREQFRMTX */ 852 #define _ETH_IENS_PTPPDLYREQFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 853 #define ETH_IENS_PTPPDLYREQFRMTX_DEFAULT (_ETH_IENS_PTPPDLYREQFRMTX_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_IENS */ 854 #define ETH_IENS_PTPPDLYRESPFRMTX (0x1UL << 25) /**< Enable PTP pdelay_resp frame transmitted interrupt */ 855 #define _ETH_IENS_PTPPDLYRESPFRMTX_SHIFT 25 /**< Shift value for ETH_PTPPDLYRESPFRMTX */ 856 #define _ETH_IENS_PTPPDLYRESPFRMTX_MASK 0x2000000UL /**< Bit mask for ETH_PTPPDLYRESPFRMTX */ 857 #define _ETH_IENS_PTPPDLYRESPFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 858 #define ETH_IENS_PTPPDLYRESPFRMTX_DEFAULT (_ETH_IENS_PTPPDLYRESPFRMTX_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_IENS */ 859 #define ETH_IENS_TSUSECREGINCR (0x1UL << 26) /**< Enable TSU seconds register increment interrupt */ 860 #define _ETH_IENS_TSUSECREGINCR_SHIFT 26 /**< Shift value for ETH_TSUSECREGINCR */ 861 #define _ETH_IENS_TSUSECREGINCR_MASK 0x4000000UL /**< Bit mask for ETH_TSUSECREGINCR */ 862 #define _ETH_IENS_TSUSECREGINCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 863 #define ETH_IENS_TSUSECREGINCR_DEFAULT (_ETH_IENS_TSUSECREGINCR_DEFAULT << 26) /**< Shifted mode DEFAULT for ETH_IENS */ 864 #define ETH_IENS_RXLPIINDC (0x1UL << 27) /**< Enable RX LPI indication interrupt */ 865 #define _ETH_IENS_RXLPIINDC_SHIFT 27 /**< Shift value for ETH_RXLPIINDC */ 866 #define _ETH_IENS_RXLPIINDC_MASK 0x8000000UL /**< Bit mask for ETH_RXLPIINDC */ 867 #define _ETH_IENS_RXLPIINDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 868 #define ETH_IENS_RXLPIINDC_DEFAULT (_ETH_IENS_RXLPIINDC_DEFAULT << 27) /**< Shifted mode DEFAULT for ETH_IENS */ 869 #define ETH_IENS_WOLEVNTRX (0x1UL << 28) /**< Enable WOL event received interrupt */ 870 #define _ETH_IENS_WOLEVNTRX_SHIFT 28 /**< Shift value for ETH_WOLEVNTRX */ 871 #define _ETH_IENS_WOLEVNTRX_MASK 0x10000000UL /**< Bit mask for ETH_WOLEVNTRX */ 872 #define _ETH_IENS_WOLEVNTRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 873 #define ETH_IENS_WOLEVNTRX_DEFAULT (_ETH_IENS_WOLEVNTRX_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_IENS */ 874 #define ETH_IENS_TSUTIMERCOMP (0x1UL << 29) /**< Enable TSU timer comparison interrupt. */ 875 #define _ETH_IENS_TSUTIMERCOMP_SHIFT 29 /**< Shift value for ETH_TSUTIMERCOMP */ 876 #define _ETH_IENS_TSUTIMERCOMP_MASK 0x20000000UL /**< Bit mask for ETH_TSUTIMERCOMP */ 877 #define _ETH_IENS_TSUTIMERCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENS */ 878 #define ETH_IENS_TSUTIMERCOMP_DEFAULT (_ETH_IENS_TSUTIMERCOMP_DEFAULT << 29) /**< Shifted mode DEFAULT for ETH_IENS */ 879 880 /* Bit fields for ETH IENC */ 881 #define _ETH_IENC_RESETVALUE 0x00000000UL /**< Default value for ETH_IENC */ 882 #define _ETH_IENC_MASK 0x3FFC7CFFUL /**< Mask for ETH_IENC */ 883 #define ETH_IENC_MNGMNTDONE (0x1UL << 0) /**< Disable management done interrupt */ 884 #define _ETH_IENC_MNGMNTDONE_SHIFT 0 /**< Shift value for ETH_MNGMNTDONE */ 885 #define _ETH_IENC_MNGMNTDONE_MASK 0x1UL /**< Bit mask for ETH_MNGMNTDONE */ 886 #define _ETH_IENC_MNGMNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 887 #define ETH_IENC_MNGMNTDONE_DEFAULT (_ETH_IENC_MNGMNTDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_IENC */ 888 #define ETH_IENC_RXCMPLT (0x1UL << 1) /**< Disable receive complete interrupt */ 889 #define _ETH_IENC_RXCMPLT_SHIFT 1 /**< Shift value for ETH_RXCMPLT */ 890 #define _ETH_IENC_RXCMPLT_MASK 0x2UL /**< Bit mask for ETH_RXCMPLT */ 891 #define _ETH_IENC_RXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 892 #define ETH_IENC_RXCMPLT_DEFAULT (_ETH_IENC_RXCMPLT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_IENC */ 893 #define ETH_IENC_RXUSEDBITREAD (0x1UL << 2) /**< Disable receive used bit read interrupt */ 894 #define _ETH_IENC_RXUSEDBITREAD_SHIFT 2 /**< Shift value for ETH_RXUSEDBITREAD */ 895 #define _ETH_IENC_RXUSEDBITREAD_MASK 0x4UL /**< Bit mask for ETH_RXUSEDBITREAD */ 896 #define _ETH_IENC_RXUSEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 897 #define ETH_IENC_RXUSEDBITREAD_DEFAULT (_ETH_IENC_RXUSEDBITREAD_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_IENC */ 898 #define ETH_IENC_TXUSEDBITREAD (0x1UL << 3) /**< Disable transmit used bit read interrupt */ 899 #define _ETH_IENC_TXUSEDBITREAD_SHIFT 3 /**< Shift value for ETH_TXUSEDBITREAD */ 900 #define _ETH_IENC_TXUSEDBITREAD_MASK 0x8UL /**< Bit mask for ETH_TXUSEDBITREAD */ 901 #define _ETH_IENC_TXUSEDBITREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 902 #define ETH_IENC_TXUSEDBITREAD_DEFAULT (_ETH_IENC_TXUSEDBITREAD_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_IENC */ 903 #define ETH_IENC_TXUNDERRUN (0x1UL << 4) /**< Disable transmit buffer under run interrupt */ 904 #define _ETH_IENC_TXUNDERRUN_SHIFT 4 /**< Shift value for ETH_TXUNDERRUN */ 905 #define _ETH_IENC_TXUNDERRUN_MASK 0x10UL /**< Bit mask for ETH_TXUNDERRUN */ 906 #define _ETH_IENC_TXUNDERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 907 #define ETH_IENC_TXUNDERRUN_DEFAULT (_ETH_IENC_TXUNDERRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_IENC */ 908 #define ETH_IENC_RTRYLMTORLATECOL (0x1UL << 5) /**< Disable retry limit exceeded or late collision interrupt */ 909 #define _ETH_IENC_RTRYLMTORLATECOL_SHIFT 5 /**< Shift value for ETH_RTRYLMTORLATECOL */ 910 #define _ETH_IENC_RTRYLMTORLATECOL_MASK 0x20UL /**< Bit mask for ETH_RTRYLMTORLATECOL */ 911 #define _ETH_IENC_RTRYLMTORLATECOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 912 #define ETH_IENC_RTRYLMTORLATECOL_DEFAULT (_ETH_IENC_RTRYLMTORLATECOL_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_IENC */ 913 #define ETH_IENC_AMBAERR (0x1UL << 6) /**< Disable transmit frame corruption due to AMBA (AHB) error interrupt */ 914 #define _ETH_IENC_AMBAERR_SHIFT 6 /**< Shift value for ETH_AMBAERR */ 915 #define _ETH_IENC_AMBAERR_MASK 0x40UL /**< Bit mask for ETH_AMBAERR */ 916 #define _ETH_IENC_AMBAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 917 #define ETH_IENC_AMBAERR_DEFAULT (_ETH_IENC_AMBAERR_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_IENC */ 918 #define ETH_IENC_TXCMPLT (0x1UL << 7) /**< Disable transmit complete interrupt */ 919 #define _ETH_IENC_TXCMPLT_SHIFT 7 /**< Shift value for ETH_TXCMPLT */ 920 #define _ETH_IENC_TXCMPLT_MASK 0x80UL /**< Bit mask for ETH_TXCMPLT */ 921 #define _ETH_IENC_TXCMPLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 922 #define ETH_IENC_TXCMPLT_DEFAULT (_ETH_IENC_TXCMPLT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_IENC */ 923 #define ETH_IENC_RXOVERRUN (0x1UL << 10) /**< Disable receive overrun interrupt */ 924 #define _ETH_IENC_RXOVERRUN_SHIFT 10 /**< Shift value for ETH_RXOVERRUN */ 925 #define _ETH_IENC_RXOVERRUN_MASK 0x400UL /**< Bit mask for ETH_RXOVERRUN */ 926 #define _ETH_IENC_RXOVERRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 927 #define ETH_IENC_RXOVERRUN_DEFAULT (_ETH_IENC_RXOVERRUN_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_IENC */ 928 #define ETH_IENC_RESPNOTOK (0x1UL << 11) /**< Disable bresp/hresp not OK interrupt */ 929 #define _ETH_IENC_RESPNOTOK_SHIFT 11 /**< Shift value for ETH_RESPNOTOK */ 930 #define _ETH_IENC_RESPNOTOK_MASK 0x800UL /**< Bit mask for ETH_RESPNOTOK */ 931 #define _ETH_IENC_RESPNOTOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 932 #define ETH_IENC_RESPNOTOK_DEFAULT (_ETH_IENC_RESPNOTOK_DEFAULT << 11) /**< Shifted mode DEFAULT for ETH_IENC */ 933 #define ETH_IENC_NONZEROPFRMQUANT (0x1UL << 12) /**< Disable pause frame with non-zero pause quantum interrupt */ 934 #define _ETH_IENC_NONZEROPFRMQUANT_SHIFT 12 /**< Shift value for ETH_NONZEROPFRMQUANT */ 935 #define _ETH_IENC_NONZEROPFRMQUANT_MASK 0x1000UL /**< Bit mask for ETH_NONZEROPFRMQUANT */ 936 #define _ETH_IENC_NONZEROPFRMQUANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 937 #define ETH_IENC_NONZEROPFRMQUANT_DEFAULT (_ETH_IENC_NONZEROPFRMQUANT_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_IENC */ 938 #define ETH_IENC_PAUSETIMEZERO (0x1UL << 13) /**< Disable pause time zero interrupt */ 939 #define _ETH_IENC_PAUSETIMEZERO_SHIFT 13 /**< Shift value for ETH_PAUSETIMEZERO */ 940 #define _ETH_IENC_PAUSETIMEZERO_MASK 0x2000UL /**< Bit mask for ETH_PAUSETIMEZERO */ 941 #define _ETH_IENC_PAUSETIMEZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 942 #define ETH_IENC_PAUSETIMEZERO_DEFAULT (_ETH_IENC_PAUSETIMEZERO_DEFAULT << 13) /**< Shifted mode DEFAULT for ETH_IENC */ 943 #define ETH_IENC_PFRMTX (0x1UL << 14) /**< Disable pause frame transmitted interrupt */ 944 #define _ETH_IENC_PFRMTX_SHIFT 14 /**< Shift value for ETH_PFRMTX */ 945 #define _ETH_IENC_PFRMTX_MASK 0x4000UL /**< Bit mask for ETH_PFRMTX */ 946 #define _ETH_IENC_PFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 947 #define ETH_IENC_PFRMTX_DEFAULT (_ETH_IENC_PFRMTX_DEFAULT << 14) /**< Shifted mode DEFAULT for ETH_IENC */ 948 #define ETH_IENC_PTPDLYREQFRMRX (0x1UL << 18) /**< Disable PTP delay_req frame received interrupt */ 949 #define _ETH_IENC_PTPDLYREQFRMRX_SHIFT 18 /**< Shift value for ETH_PTPDLYREQFRMRX */ 950 #define _ETH_IENC_PTPDLYREQFRMRX_MASK 0x40000UL /**< Bit mask for ETH_PTPDLYREQFRMRX */ 951 #define _ETH_IENC_PTPDLYREQFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 952 #define ETH_IENC_PTPDLYREQFRMRX_DEFAULT (_ETH_IENC_PTPDLYREQFRMRX_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_IENC */ 953 #define ETH_IENC_PTPSYNCFRMRX (0x1UL << 19) /**< Disable PTP sync frame received interrupt */ 954 #define _ETH_IENC_PTPSYNCFRMRX_SHIFT 19 /**< Shift value for ETH_PTPSYNCFRMRX */ 955 #define _ETH_IENC_PTPSYNCFRMRX_MASK 0x80000UL /**< Bit mask for ETH_PTPSYNCFRMRX */ 956 #define _ETH_IENC_PTPSYNCFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 957 #define ETH_IENC_PTPSYNCFRMRX_DEFAULT (_ETH_IENC_PTPSYNCFRMRX_DEFAULT << 19) /**< Shifted mode DEFAULT for ETH_IENC */ 958 #define ETH_IENC_PTPDLYREQFRMTX (0x1UL << 20) /**< Disable PTP delay_req frame transmitted interrupt */ 959 #define _ETH_IENC_PTPDLYREQFRMTX_SHIFT 20 /**< Shift value for ETH_PTPDLYREQFRMTX */ 960 #define _ETH_IENC_PTPDLYREQFRMTX_MASK 0x100000UL /**< Bit mask for ETH_PTPDLYREQFRMTX */ 961 #define _ETH_IENC_PTPDLYREQFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 962 #define ETH_IENC_PTPDLYREQFRMTX_DEFAULT (_ETH_IENC_PTPDLYREQFRMTX_DEFAULT << 20) /**< Shifted mode DEFAULT for ETH_IENC */ 963 #define ETH_IENC_PTPSYNCFRMTX (0x1UL << 21) /**< Disable PTP sync frame transmitted interrupt */ 964 #define _ETH_IENC_PTPSYNCFRMTX_SHIFT 21 /**< Shift value for ETH_PTPSYNCFRMTX */ 965 #define _ETH_IENC_PTPSYNCFRMTX_MASK 0x200000UL /**< Bit mask for ETH_PTPSYNCFRMTX */ 966 #define _ETH_IENC_PTPSYNCFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 967 #define ETH_IENC_PTPSYNCFRMTX_DEFAULT (_ETH_IENC_PTPSYNCFRMTX_DEFAULT << 21) /**< Shifted mode DEFAULT for ETH_IENC */ 968 #define ETH_IENC_PTPPDLYREQFRMRX (0x1UL << 22) /**< Disable PTP pdelay_req frame received interrupt */ 969 #define _ETH_IENC_PTPPDLYREQFRMRX_SHIFT 22 /**< Shift value for ETH_PTPPDLYREQFRMRX */ 970 #define _ETH_IENC_PTPPDLYREQFRMRX_MASK 0x400000UL /**< Bit mask for ETH_PTPPDLYREQFRMRX */ 971 #define _ETH_IENC_PTPPDLYREQFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 972 #define ETH_IENC_PTPPDLYREQFRMRX_DEFAULT (_ETH_IENC_PTPPDLYREQFRMRX_DEFAULT << 22) /**< Shifted mode DEFAULT for ETH_IENC */ 973 #define ETH_IENC_PTPPDLYRESPFRMRX (0x1UL << 23) /**< Disable PTP pdelay_resp frame received interrupt */ 974 #define _ETH_IENC_PTPPDLYRESPFRMRX_SHIFT 23 /**< Shift value for ETH_PTPPDLYRESPFRMRX */ 975 #define _ETH_IENC_PTPPDLYRESPFRMRX_MASK 0x800000UL /**< Bit mask for ETH_PTPPDLYRESPFRMRX */ 976 #define _ETH_IENC_PTPPDLYRESPFRMRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 977 #define ETH_IENC_PTPPDLYRESPFRMRX_DEFAULT (_ETH_IENC_PTPPDLYRESPFRMRX_DEFAULT << 23) /**< Shifted mode DEFAULT for ETH_IENC */ 978 #define ETH_IENC_PTPPDLYREQFRMTX (0x1UL << 24) /**< Disable PTP pdelay_req frame transmitted interrupt */ 979 #define _ETH_IENC_PTPPDLYREQFRMTX_SHIFT 24 /**< Shift value for ETH_PTPPDLYREQFRMTX */ 980 #define _ETH_IENC_PTPPDLYREQFRMTX_MASK 0x1000000UL /**< Bit mask for ETH_PTPPDLYREQFRMTX */ 981 #define _ETH_IENC_PTPPDLYREQFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 982 #define ETH_IENC_PTPPDLYREQFRMTX_DEFAULT (_ETH_IENC_PTPPDLYREQFRMTX_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_IENC */ 983 #define ETH_IENC_PTPPDLYRESPFRMTX (0x1UL << 25) /**< Disable PTP pdelay_resp frame transmitted interrupt */ 984 #define _ETH_IENC_PTPPDLYRESPFRMTX_SHIFT 25 /**< Shift value for ETH_PTPPDLYRESPFRMTX */ 985 #define _ETH_IENC_PTPPDLYRESPFRMTX_MASK 0x2000000UL /**< Bit mask for ETH_PTPPDLYRESPFRMTX */ 986 #define _ETH_IENC_PTPPDLYRESPFRMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 987 #define ETH_IENC_PTPPDLYRESPFRMTX_DEFAULT (_ETH_IENC_PTPPDLYRESPFRMTX_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_IENC */ 988 #define ETH_IENC_TSUSECREGINCR (0x1UL << 26) /**< Disable TSU seconds register increment interrupt */ 989 #define _ETH_IENC_TSUSECREGINCR_SHIFT 26 /**< Shift value for ETH_TSUSECREGINCR */ 990 #define _ETH_IENC_TSUSECREGINCR_MASK 0x4000000UL /**< Bit mask for ETH_TSUSECREGINCR */ 991 #define _ETH_IENC_TSUSECREGINCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 992 #define ETH_IENC_TSUSECREGINCR_DEFAULT (_ETH_IENC_TSUSECREGINCR_DEFAULT << 26) /**< Shifted mode DEFAULT for ETH_IENC */ 993 #define ETH_IENC_RXLPIINDC (0x1UL << 27) /**< Disable RX LPI indication interrupt */ 994 #define _ETH_IENC_RXLPIINDC_SHIFT 27 /**< Shift value for ETH_RXLPIINDC */ 995 #define _ETH_IENC_RXLPIINDC_MASK 0x8000000UL /**< Bit mask for ETH_RXLPIINDC */ 996 #define _ETH_IENC_RXLPIINDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 997 #define ETH_IENC_RXLPIINDC_DEFAULT (_ETH_IENC_RXLPIINDC_DEFAULT << 27) /**< Shifted mode DEFAULT for ETH_IENC */ 998 #define ETH_IENC_WOLEVNTRX (0x1UL << 28) /**< Disable WOL event received interrupt */ 999 #define _ETH_IENC_WOLEVNTRX_SHIFT 28 /**< Shift value for ETH_WOLEVNTRX */ 1000 #define _ETH_IENC_WOLEVNTRX_MASK 0x10000000UL /**< Bit mask for ETH_WOLEVNTRX */ 1001 #define _ETH_IENC_WOLEVNTRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 1002 #define ETH_IENC_WOLEVNTRX_DEFAULT (_ETH_IENC_WOLEVNTRX_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_IENC */ 1003 #define ETH_IENC_TSUTIMERCOMP (0x1UL << 29) /**< Disable TSU timer comparison interrupt. */ 1004 #define _ETH_IENC_TSUTIMERCOMP_SHIFT 29 /**< Shift value for ETH_TSUTIMERCOMP */ 1005 #define _ETH_IENC_TSUTIMERCOMP_MASK 0x20000000UL /**< Bit mask for ETH_TSUTIMERCOMP */ 1006 #define _ETH_IENC_TSUTIMERCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IENC */ 1007 #define ETH_IENC_TSUTIMERCOMP_DEFAULT (_ETH_IENC_TSUTIMERCOMP_DEFAULT << 29) /**< Shifted mode DEFAULT for ETH_IENC */ 1008 1009 /* Bit fields for ETH IENRO */ 1010 #define _ETH_IENRO_RESETVALUE 0x3FFC7DFFUL /**< Default value for ETH_IENRO */ 1011 #define _ETH_IENRO_MASK 0x3FFC7DFFUL /**< Mask for ETH_IENRO */ 1012 #define ETH_IENRO_MNGMNTDONE (0x1UL << 0) /**< management done interrupt mask */ 1013 #define _ETH_IENRO_MNGMNTDONE_SHIFT 0 /**< Shift value for ETH_MNGMNTDONE */ 1014 #define _ETH_IENRO_MNGMNTDONE_MASK 0x1UL /**< Bit mask for ETH_MNGMNTDONE */ 1015 #define _ETH_IENRO_MNGMNTDONE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1016 #define ETH_IENRO_MNGMNTDONE_DEFAULT (_ETH_IENRO_MNGMNTDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_IENRO */ 1017 #define ETH_IENRO_RXCMPLT (0x1UL << 1) /**< receive complete interrupt mask */ 1018 #define _ETH_IENRO_RXCMPLT_SHIFT 1 /**< Shift value for ETH_RXCMPLT */ 1019 #define _ETH_IENRO_RXCMPLT_MASK 0x2UL /**< Bit mask for ETH_RXCMPLT */ 1020 #define _ETH_IENRO_RXCMPLT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1021 #define ETH_IENRO_RXCMPLT_DEFAULT (_ETH_IENRO_RXCMPLT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_IENRO */ 1022 #define ETH_IENRO_RXUSEDBITREAD (0x1UL << 2) /**< receive used bit read interrupt mask */ 1023 #define _ETH_IENRO_RXUSEDBITREAD_SHIFT 2 /**< Shift value for ETH_RXUSEDBITREAD */ 1024 #define _ETH_IENRO_RXUSEDBITREAD_MASK 0x4UL /**< Bit mask for ETH_RXUSEDBITREAD */ 1025 #define _ETH_IENRO_RXUSEDBITREAD_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1026 #define ETH_IENRO_RXUSEDBITREAD_DEFAULT (_ETH_IENRO_RXUSEDBITREAD_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_IENRO */ 1027 #define ETH_IENRO_TXUSEDBITREAD (0x1UL << 3) /**< transmit used bit read interrupt mask */ 1028 #define _ETH_IENRO_TXUSEDBITREAD_SHIFT 3 /**< Shift value for ETH_TXUSEDBITREAD */ 1029 #define _ETH_IENRO_TXUSEDBITREAD_MASK 0x8UL /**< Bit mask for ETH_TXUSEDBITREAD */ 1030 #define _ETH_IENRO_TXUSEDBITREAD_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1031 #define ETH_IENRO_TXUSEDBITREAD_DEFAULT (_ETH_IENRO_TXUSEDBITREAD_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_IENRO */ 1032 #define ETH_IENRO_TXUNDERRUN (0x1UL << 4) /**< transmit buffer under run interrupt mask */ 1033 #define _ETH_IENRO_TXUNDERRUN_SHIFT 4 /**< Shift value for ETH_TXUNDERRUN */ 1034 #define _ETH_IENRO_TXUNDERRUN_MASK 0x10UL /**< Bit mask for ETH_TXUNDERRUN */ 1035 #define _ETH_IENRO_TXUNDERRUN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1036 #define ETH_IENRO_TXUNDERRUN_DEFAULT (_ETH_IENRO_TXUNDERRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_IENRO */ 1037 #define ETH_IENRO_RTRYLMTORLATECOL (0x1UL << 5) /**< Retry limit exceeded or late collision (gigabit mode only) interrupt mask */ 1038 #define _ETH_IENRO_RTRYLMTORLATECOL_SHIFT 5 /**< Shift value for ETH_RTRYLMTORLATECOL */ 1039 #define _ETH_IENRO_RTRYLMTORLATECOL_MASK 0x20UL /**< Bit mask for ETH_RTRYLMTORLATECOL */ 1040 #define _ETH_IENRO_RTRYLMTORLATECOL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1041 #define ETH_IENRO_RTRYLMTORLATECOL_DEFAULT (_ETH_IENRO_RTRYLMTORLATECOL_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_IENRO */ 1042 #define ETH_IENRO_AMBAERR (0x1UL << 6) /**< Transmit frame corruption due to AMBA (AHB) error interrupt mask */ 1043 #define _ETH_IENRO_AMBAERR_SHIFT 6 /**< Shift value for ETH_AMBAERR */ 1044 #define _ETH_IENRO_AMBAERR_MASK 0x40UL /**< Bit mask for ETH_AMBAERR */ 1045 #define _ETH_IENRO_AMBAERR_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1046 #define ETH_IENRO_AMBAERR_DEFAULT (_ETH_IENRO_AMBAERR_DEFAULT << 6) /**< Shifted mode DEFAULT for ETH_IENRO */ 1047 #define ETH_IENRO_TXCMPLT (0x1UL << 7) /**< Transmit complete interrupt mask */ 1048 #define _ETH_IENRO_TXCMPLT_SHIFT 7 /**< Shift value for ETH_TXCMPLT */ 1049 #define _ETH_IENRO_TXCMPLT_MASK 0x80UL /**< Bit mask for ETH_TXCMPLT */ 1050 #define _ETH_IENRO_TXCMPLT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1051 #define ETH_IENRO_TXCMPLT_DEFAULT (_ETH_IENRO_TXCMPLT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETH_IENRO */ 1052 #define ETH_IENRO_UNUSED (0x1UL << 8) /**< Unused */ 1053 #define _ETH_IENRO_UNUSED_SHIFT 8 /**< Shift value for ETH_UNUSED */ 1054 #define _ETH_IENRO_UNUSED_MASK 0x100UL /**< Bit mask for ETH_UNUSED */ 1055 #define _ETH_IENRO_UNUSED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1056 #define ETH_IENRO_UNUSED_DEFAULT (_ETH_IENRO_UNUSED_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_IENRO */ 1057 #define ETH_IENRO_RXOVERRUN (0x1UL << 10) /**< Receive overrun interrupt mask */ 1058 #define _ETH_IENRO_RXOVERRUN_SHIFT 10 /**< Shift value for ETH_RXOVERRUN */ 1059 #define _ETH_IENRO_RXOVERRUN_MASK 0x400UL /**< Bit mask for ETH_RXOVERRUN */ 1060 #define _ETH_IENRO_RXOVERRUN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1061 #define ETH_IENRO_RXOVERRUN_DEFAULT (_ETH_IENRO_RXOVERRUN_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_IENRO */ 1062 #define ETH_IENRO_RESPNOTOK (0x1UL << 11) /**< bresp/hresp not OK interrupt mask */ 1063 #define _ETH_IENRO_RESPNOTOK_SHIFT 11 /**< Shift value for ETH_RESPNOTOK */ 1064 #define _ETH_IENRO_RESPNOTOK_MASK 0x800UL /**< Bit mask for ETH_RESPNOTOK */ 1065 #define _ETH_IENRO_RESPNOTOK_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1066 #define ETH_IENRO_RESPNOTOK_DEFAULT (_ETH_IENRO_RESPNOTOK_DEFAULT << 11) /**< Shifted mode DEFAULT for ETH_IENRO */ 1067 #define ETH_IENRO_NONZEROPFRMQUANT (0x1UL << 12) /**< Pause frame with non-zero pause quantum interrupt mask */ 1068 #define _ETH_IENRO_NONZEROPFRMQUANT_SHIFT 12 /**< Shift value for ETH_NONZEROPFRMQUANT */ 1069 #define _ETH_IENRO_NONZEROPFRMQUANT_MASK 0x1000UL /**< Bit mask for ETH_NONZEROPFRMQUANT */ 1070 #define _ETH_IENRO_NONZEROPFRMQUANT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1071 #define ETH_IENRO_NONZEROPFRMQUANT_DEFAULT (_ETH_IENRO_NONZEROPFRMQUANT_DEFAULT << 12) /**< Shifted mode DEFAULT for ETH_IENRO */ 1072 #define ETH_IENRO_PAUSETIMEZERO (0x1UL << 13) /**< pause time zero interrupt mask */ 1073 #define _ETH_IENRO_PAUSETIMEZERO_SHIFT 13 /**< Shift value for ETH_PAUSETIMEZERO */ 1074 #define _ETH_IENRO_PAUSETIMEZERO_MASK 0x2000UL /**< Bit mask for ETH_PAUSETIMEZERO */ 1075 #define _ETH_IENRO_PAUSETIMEZERO_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1076 #define ETH_IENRO_PAUSETIMEZERO_DEFAULT (_ETH_IENRO_PAUSETIMEZERO_DEFAULT << 13) /**< Shifted mode DEFAULT for ETH_IENRO */ 1077 #define ETH_IENRO_PFRMTX (0x1UL << 14) /**< pause frame transmitted interrupt mask */ 1078 #define _ETH_IENRO_PFRMTX_SHIFT 14 /**< Shift value for ETH_PFRMTX */ 1079 #define _ETH_IENRO_PFRMTX_MASK 0x4000UL /**< Bit mask for ETH_PFRMTX */ 1080 #define _ETH_IENRO_PFRMTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1081 #define ETH_IENRO_PFRMTX_DEFAULT (_ETH_IENRO_PFRMTX_DEFAULT << 14) /**< Shifted mode DEFAULT for ETH_IENRO */ 1082 #define ETH_IENRO_PTPDLYREQFRMRX (0x1UL << 18) /**< PTP delay_req frame received mask */ 1083 #define _ETH_IENRO_PTPDLYREQFRMRX_SHIFT 18 /**< Shift value for ETH_PTPDLYREQFRMRX */ 1084 #define _ETH_IENRO_PTPDLYREQFRMRX_MASK 0x40000UL /**< Bit mask for ETH_PTPDLYREQFRMRX */ 1085 #define _ETH_IENRO_PTPDLYREQFRMRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1086 #define ETH_IENRO_PTPDLYREQFRMRX_DEFAULT (_ETH_IENRO_PTPDLYREQFRMRX_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_IENRO */ 1087 #define ETH_IENRO_PTPSYNCFRMRX (0x1UL << 19) /**< PTP sync frame received mask */ 1088 #define _ETH_IENRO_PTPSYNCFRMRX_SHIFT 19 /**< Shift value for ETH_PTPSYNCFRMRX */ 1089 #define _ETH_IENRO_PTPSYNCFRMRX_MASK 0x80000UL /**< Bit mask for ETH_PTPSYNCFRMRX */ 1090 #define _ETH_IENRO_PTPSYNCFRMRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1091 #define ETH_IENRO_PTPSYNCFRMRX_DEFAULT (_ETH_IENRO_PTPSYNCFRMRX_DEFAULT << 19) /**< Shifted mode DEFAULT for ETH_IENRO */ 1092 #define ETH_IENRO_PTPDLYREQFRMTX (0x1UL << 20) /**< PTP delay_req frame transmitted mask */ 1093 #define _ETH_IENRO_PTPDLYREQFRMTX_SHIFT 20 /**< Shift value for ETH_PTPDLYREQFRMTX */ 1094 #define _ETH_IENRO_PTPDLYREQFRMTX_MASK 0x100000UL /**< Bit mask for ETH_PTPDLYREQFRMTX */ 1095 #define _ETH_IENRO_PTPDLYREQFRMTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1096 #define ETH_IENRO_PTPDLYREQFRMTX_DEFAULT (_ETH_IENRO_PTPDLYREQFRMTX_DEFAULT << 20) /**< Shifted mode DEFAULT for ETH_IENRO */ 1097 #define ETH_IENRO_PTPSYNCFRMTX (0x1UL << 21) /**< PTP sync frame transmitted mask */ 1098 #define _ETH_IENRO_PTPSYNCFRMTX_SHIFT 21 /**< Shift value for ETH_PTPSYNCFRMTX */ 1099 #define _ETH_IENRO_PTPSYNCFRMTX_MASK 0x200000UL /**< Bit mask for ETH_PTPSYNCFRMTX */ 1100 #define _ETH_IENRO_PTPSYNCFRMTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1101 #define ETH_IENRO_PTPSYNCFRMTX_DEFAULT (_ETH_IENRO_PTPSYNCFRMTX_DEFAULT << 21) /**< Shifted mode DEFAULT for ETH_IENRO */ 1102 #define ETH_IENRO_PTPPDLYREQFRMRX (0x1UL << 22) /**< PTP pdelay_req frame received mask */ 1103 #define _ETH_IENRO_PTPPDLYREQFRMRX_SHIFT 22 /**< Shift value for ETH_PTPPDLYREQFRMRX */ 1104 #define _ETH_IENRO_PTPPDLYREQFRMRX_MASK 0x400000UL /**< Bit mask for ETH_PTPPDLYREQFRMRX */ 1105 #define _ETH_IENRO_PTPPDLYREQFRMRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1106 #define ETH_IENRO_PTPPDLYREQFRMRX_DEFAULT (_ETH_IENRO_PTPPDLYREQFRMRX_DEFAULT << 22) /**< Shifted mode DEFAULT for ETH_IENRO */ 1107 #define ETH_IENRO_PTPPDLYRESPFRMRX (0x1UL << 23) /**< PTP pdelay_resp frame received mask */ 1108 #define _ETH_IENRO_PTPPDLYRESPFRMRX_SHIFT 23 /**< Shift value for ETH_PTPPDLYRESPFRMRX */ 1109 #define _ETH_IENRO_PTPPDLYRESPFRMRX_MASK 0x800000UL /**< Bit mask for ETH_PTPPDLYRESPFRMRX */ 1110 #define _ETH_IENRO_PTPPDLYRESPFRMRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1111 #define ETH_IENRO_PTPPDLYRESPFRMRX_DEFAULT (_ETH_IENRO_PTPPDLYRESPFRMRX_DEFAULT << 23) /**< Shifted mode DEFAULT for ETH_IENRO */ 1112 #define ETH_IENRO_PTPPDLYREQFRMTX (0x1UL << 24) /**< PTP pdelay_req frame transmitted mask */ 1113 #define _ETH_IENRO_PTPPDLYREQFRMTX_SHIFT 24 /**< Shift value for ETH_PTPPDLYREQFRMTX */ 1114 #define _ETH_IENRO_PTPPDLYREQFRMTX_MASK 0x1000000UL /**< Bit mask for ETH_PTPPDLYREQFRMTX */ 1115 #define _ETH_IENRO_PTPPDLYREQFRMTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1116 #define ETH_IENRO_PTPPDLYREQFRMTX_DEFAULT (_ETH_IENRO_PTPPDLYREQFRMTX_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_IENRO */ 1117 #define ETH_IENRO_PTPPDLYRESPFRMTX (0x1UL << 25) /**< PTP pdelay_resp frame transmitted mask */ 1118 #define _ETH_IENRO_PTPPDLYRESPFRMTX_SHIFT 25 /**< Shift value for ETH_PTPPDLYRESPFRMTX */ 1119 #define _ETH_IENRO_PTPPDLYRESPFRMTX_MASK 0x2000000UL /**< Bit mask for ETH_PTPPDLYRESPFRMTX */ 1120 #define _ETH_IENRO_PTPPDLYRESPFRMTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1121 #define ETH_IENRO_PTPPDLYRESPFRMTX_DEFAULT (_ETH_IENRO_PTPPDLYRESPFRMTX_DEFAULT << 25) /**< Shifted mode DEFAULT for ETH_IENRO */ 1122 #define ETH_IENRO_TSUSECREGINCR (0x1UL << 26) /**< TSU seconds register increment mask */ 1123 #define _ETH_IENRO_TSUSECREGINCR_SHIFT 26 /**< Shift value for ETH_TSUSECREGINCR */ 1124 #define _ETH_IENRO_TSUSECREGINCR_MASK 0x4000000UL /**< Bit mask for ETH_TSUSECREGINCR */ 1125 #define _ETH_IENRO_TSUSECREGINCR_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1126 #define ETH_IENRO_TSUSECREGINCR_DEFAULT (_ETH_IENRO_TSUSECREGINCR_DEFAULT << 26) /**< Shifted mode DEFAULT for ETH_IENRO */ 1127 #define ETH_IENRO_RXLPIINDC (0x1UL << 27) /**< RX LPI indication mask */ 1128 #define _ETH_IENRO_RXLPIINDC_SHIFT 27 /**< Shift value for ETH_RXLPIINDC */ 1129 #define _ETH_IENRO_RXLPIINDC_MASK 0x8000000UL /**< Bit mask for ETH_RXLPIINDC */ 1130 #define _ETH_IENRO_RXLPIINDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1131 #define ETH_IENRO_RXLPIINDC_DEFAULT (_ETH_IENRO_RXLPIINDC_DEFAULT << 27) /**< Shifted mode DEFAULT for ETH_IENRO */ 1132 #define ETH_IENRO_WOLEVNTRX (0x1UL << 28) /**< WOL event received mask */ 1133 #define _ETH_IENRO_WOLEVNTRX_SHIFT 28 /**< Shift value for ETH_WOLEVNTRX */ 1134 #define _ETH_IENRO_WOLEVNTRX_MASK 0x10000000UL /**< Bit mask for ETH_WOLEVNTRX */ 1135 #define _ETH_IENRO_WOLEVNTRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1136 #define ETH_IENRO_WOLEVNTRX_DEFAULT (_ETH_IENRO_WOLEVNTRX_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_IENRO */ 1137 #define ETH_IENRO_TSUTIMERCOMP (0x1UL << 29) /**< TSU timer comparison interrupt mask. */ 1138 #define _ETH_IENRO_TSUTIMERCOMP_SHIFT 29 /**< Shift value for ETH_TSUTIMERCOMP */ 1139 #define _ETH_IENRO_TSUTIMERCOMP_MASK 0x20000000UL /**< Bit mask for ETH_TSUTIMERCOMP */ 1140 #define _ETH_IENRO_TSUTIMERCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETH_IENRO */ 1141 #define ETH_IENRO_TSUTIMERCOMP_DEFAULT (_ETH_IENRO_TSUTIMERCOMP_DEFAULT << 29) /**< Shifted mode DEFAULT for ETH_IENRO */ 1142 1143 /* Bit fields for ETH PHYMNGMNT */ 1144 #define _ETH_PHYMNGMNT_RESETVALUE 0x00000000UL /**< Default value for ETH_PHYMNGMNT */ 1145 #define _ETH_PHYMNGMNT_MASK 0xFFFFFFFFUL /**< Mask for ETH_PHYMNGMNT */ 1146 #define _ETH_PHYMNGMNT_PHYRWDATA_SHIFT 0 /**< Shift value for ETH_PHYRWDATA */ 1147 #define _ETH_PHYMNGMNT_PHYRWDATA_MASK 0xFFFFUL /**< Bit mask for ETH_PHYRWDATA */ 1148 #define _ETH_PHYMNGMNT_PHYRWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ 1149 #define ETH_PHYMNGMNT_PHYRWDATA_DEFAULT (_ETH_PHYMNGMNT_PHYRWDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ 1150 #define _ETH_PHYMNGMNT_WRITE10_SHIFT 16 /**< Shift value for ETH_WRITE10 */ 1151 #define _ETH_PHYMNGMNT_WRITE10_MASK 0x30000UL /**< Bit mask for ETH_WRITE10 */ 1152 #define _ETH_PHYMNGMNT_WRITE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ 1153 #define ETH_PHYMNGMNT_WRITE10_DEFAULT (_ETH_PHYMNGMNT_WRITE10_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ 1154 #define _ETH_PHYMNGMNT_REGADDR_SHIFT 18 /**< Shift value for ETH_REGADDR */ 1155 #define _ETH_PHYMNGMNT_REGADDR_MASK 0x7C0000UL /**< Bit mask for ETH_REGADDR */ 1156 #define _ETH_PHYMNGMNT_REGADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ 1157 #define ETH_PHYMNGMNT_REGADDR_DEFAULT (_ETH_PHYMNGMNT_REGADDR_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ 1158 #define _ETH_PHYMNGMNT_PHYADDR_SHIFT 23 /**< Shift value for ETH_PHYADDR */ 1159 #define _ETH_PHYMNGMNT_PHYADDR_MASK 0xF800000UL /**< Bit mask for ETH_PHYADDR */ 1160 #define _ETH_PHYMNGMNT_PHYADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ 1161 #define ETH_PHYMNGMNT_PHYADDR_DEFAULT (_ETH_PHYMNGMNT_PHYADDR_DEFAULT << 23) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ 1162 #define _ETH_PHYMNGMNT_OPERATION_SHIFT 28 /**< Shift value for ETH_OPERATION */ 1163 #define _ETH_PHYMNGMNT_OPERATION_MASK 0x30000000UL /**< Bit mask for ETH_OPERATION */ 1164 #define _ETH_PHYMNGMNT_OPERATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ 1165 #define ETH_PHYMNGMNT_OPERATION_DEFAULT (_ETH_PHYMNGMNT_OPERATION_DEFAULT << 28) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ 1166 #define ETH_PHYMNGMNT_WRITE1 (0x1UL << 30) /**< Must be written to 1 for a valid Clause 22 frame and to 0 for a valid Clause 45 frame. */ 1167 #define _ETH_PHYMNGMNT_WRITE1_SHIFT 30 /**< Shift value for ETH_WRITE1 */ 1168 #define _ETH_PHYMNGMNT_WRITE1_MASK 0x40000000UL /**< Bit mask for ETH_WRITE1 */ 1169 #define _ETH_PHYMNGMNT_WRITE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ 1170 #define ETH_PHYMNGMNT_WRITE1_DEFAULT (_ETH_PHYMNGMNT_WRITE1_DEFAULT << 30) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ 1171 #define ETH_PHYMNGMNT_WRITE0 (0x1UL << 31) /**< Must be written with 0. */ 1172 #define _ETH_PHYMNGMNT_WRITE0_SHIFT 31 /**< Shift value for ETH_WRITE0 */ 1173 #define _ETH_PHYMNGMNT_WRITE0_MASK 0x80000000UL /**< Bit mask for ETH_WRITE0 */ 1174 #define _ETH_PHYMNGMNT_WRITE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PHYMNGMNT */ 1175 #define ETH_PHYMNGMNT_WRITE0_DEFAULT (_ETH_PHYMNGMNT_WRITE0_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_PHYMNGMNT */ 1176 1177 /* Bit fields for ETH RXPAUSEQUANT */ 1178 #define _ETH_RXPAUSEQUANT_RESETVALUE 0x00000000UL /**< Default value for ETH_RXPAUSEQUANT */ 1179 #define _ETH_RXPAUSEQUANT_MASK 0x0000FFFFUL /**< Mask for ETH_RXPAUSEQUANT */ 1180 #define _ETH_RXPAUSEQUANT_QUANT_SHIFT 0 /**< Shift value for ETH_QUANT */ 1181 #define _ETH_RXPAUSEQUANT_QUANT_MASK 0xFFFFUL /**< Bit mask for ETH_QUANT */ 1182 #define _ETH_RXPAUSEQUANT_QUANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXPAUSEQUANT */ 1183 #define ETH_RXPAUSEQUANT_QUANT_DEFAULT (_ETH_RXPAUSEQUANT_QUANT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXPAUSEQUANT */ 1184 1185 /* Bit fields for ETH TXPAUSEQUANT */ 1186 #define _ETH_TXPAUSEQUANT_RESETVALUE 0xFFFFFFFFUL /**< Default value for ETH_TXPAUSEQUANT */ 1187 #define _ETH_TXPAUSEQUANT_MASK 0xFFFFFFFFUL /**< Mask for ETH_TXPAUSEQUANT */ 1188 #define _ETH_TXPAUSEQUANT_QUANT_SHIFT 0 /**< Shift value for ETH_QUANT */ 1189 #define _ETH_TXPAUSEQUANT_QUANT_MASK 0xFFFFUL /**< Bit mask for ETH_QUANT */ 1190 #define _ETH_TXPAUSEQUANT_QUANT_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT */ 1191 #define ETH_TXPAUSEQUANT_QUANT_DEFAULT (_ETH_TXPAUSEQUANT_QUANT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT */ 1192 #define _ETH_TXPAUSEQUANT_QUANTP1_SHIFT 16 /**< Shift value for ETH_QUANTP1 */ 1193 #define _ETH_TXPAUSEQUANT_QUANTP1_MASK 0xFFFF0000UL /**< Bit mask for ETH_QUANTP1 */ 1194 #define _ETH_TXPAUSEQUANT_QUANTP1_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT */ 1195 #define ETH_TXPAUSEQUANT_QUANTP1_DEFAULT (_ETH_TXPAUSEQUANT_QUANTP1_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT */ 1196 1197 /* Bit fields for ETH PBUFTXCUTTHRU */ 1198 #define _ETH_PBUFTXCUTTHRU_RESETVALUE 0x000003FFUL /**< Default value for ETH_PBUFTXCUTTHRU */ 1199 #define _ETH_PBUFTXCUTTHRU_MASK 0x800003FFUL /**< Mask for ETH_PBUFTXCUTTHRU */ 1200 #define _ETH_PBUFTXCUTTHRU_DMATXCUTTHRUTHR_SHIFT 0 /**< Shift value for ETH_DMATXCUTTHRUTHR */ 1201 #define _ETH_PBUFTXCUTTHRU_DMATXCUTTHRUTHR_MASK 0x3FFUL /**< Bit mask for ETH_DMATXCUTTHRUTHR */ 1202 #define _ETH_PBUFTXCUTTHRU_DMATXCUTTHRUTHR_DEFAULT 0x000003FFUL /**< Mode DEFAULT for ETH_PBUFTXCUTTHRU */ 1203 #define ETH_PBUFTXCUTTHRU_DMATXCUTTHRUTHR_DEFAULT (_ETH_PBUFTXCUTTHRU_DMATXCUTTHRUTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_PBUFTXCUTTHRU */ 1204 #define ETH_PBUFTXCUTTHRU_DMATXCUTTHRU (0x1UL << 31) /**< Enable TX partial store and forward operation */ 1205 #define _ETH_PBUFTXCUTTHRU_DMATXCUTTHRU_SHIFT 31 /**< Shift value for ETH_DMATXCUTTHRU */ 1206 #define _ETH_PBUFTXCUTTHRU_DMATXCUTTHRU_MASK 0x80000000UL /**< Bit mask for ETH_DMATXCUTTHRU */ 1207 #define _ETH_PBUFTXCUTTHRU_DMATXCUTTHRU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PBUFTXCUTTHRU */ 1208 #define ETH_PBUFTXCUTTHRU_DMATXCUTTHRU_DEFAULT (_ETH_PBUFTXCUTTHRU_DMATXCUTTHRU_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_PBUFTXCUTTHRU */ 1209 1210 /* Bit fields for ETH PBUFRXCUTTHRU */ 1211 #define _ETH_PBUFRXCUTTHRU_RESETVALUE 0x000003FFUL /**< Default value for ETH_PBUFRXCUTTHRU */ 1212 #define _ETH_PBUFRXCUTTHRU_MASK 0x800003FFUL /**< Mask for ETH_PBUFRXCUTTHRU */ 1213 #define _ETH_PBUFRXCUTTHRU_DMARXCUTTHRUTHR_SHIFT 0 /**< Shift value for ETH_DMARXCUTTHRUTHR */ 1214 #define _ETH_PBUFRXCUTTHRU_DMARXCUTTHRUTHR_MASK 0x3FFUL /**< Bit mask for ETH_DMARXCUTTHRUTHR */ 1215 #define _ETH_PBUFRXCUTTHRU_DMARXCUTTHRUTHR_DEFAULT 0x000003FFUL /**< Mode DEFAULT for ETH_PBUFRXCUTTHRU */ 1216 #define ETH_PBUFRXCUTTHRU_DMARXCUTTHRUTHR_DEFAULT (_ETH_PBUFRXCUTTHRU_DMARXCUTTHRUTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_PBUFRXCUTTHRU */ 1217 #define ETH_PBUFRXCUTTHRU_DMARXCUTTHRU (0x1UL << 31) /**< Enable RX partial store and forward operation */ 1218 #define _ETH_PBUFRXCUTTHRU_DMARXCUTTHRU_SHIFT 31 /**< Shift value for ETH_DMARXCUTTHRU */ 1219 #define _ETH_PBUFRXCUTTHRU_DMARXCUTTHRU_MASK 0x80000000UL /**< Bit mask for ETH_DMARXCUTTHRU */ 1220 #define _ETH_PBUFRXCUTTHRU_DMARXCUTTHRU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PBUFRXCUTTHRU */ 1221 #define ETH_PBUFRXCUTTHRU_DMARXCUTTHRU_DEFAULT (_ETH_PBUFRXCUTTHRU_DMARXCUTTHRU_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_PBUFRXCUTTHRU */ 1222 1223 /* Bit fields for ETH JUMBOMAXLEN */ 1224 #define _ETH_JUMBOMAXLEN_RESETVALUE 0x00002800UL /**< Default value for ETH_JUMBOMAXLEN */ 1225 #define _ETH_JUMBOMAXLEN_MASK 0x00003FFFUL /**< Mask for ETH_JUMBOMAXLEN */ 1226 #define _ETH_JUMBOMAXLEN_JUMBOMAXLEN_SHIFT 0 /**< Shift value for ETH_JUMBOMAXLEN */ 1227 #define _ETH_JUMBOMAXLEN_JUMBOMAXLEN_MASK 0x3FFFUL /**< Bit mask for ETH_JUMBOMAXLEN */ 1228 #define _ETH_JUMBOMAXLEN_JUMBOMAXLEN_DEFAULT 0x00002800UL /**< Mode DEFAULT for ETH_JUMBOMAXLEN */ 1229 #define ETH_JUMBOMAXLEN_JUMBOMAXLEN_DEFAULT (_ETH_JUMBOMAXLEN_JUMBOMAXLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_JUMBOMAXLEN */ 1230 1231 /* Bit fields for ETH IMOD */ 1232 #define _ETH_IMOD_RESETVALUE 0x00000000UL /**< Default value for ETH_IMOD */ 1233 #define _ETH_IMOD_MASK 0x00FF00FFUL /**< Mask for ETH_IMOD */ 1234 #define _ETH_IMOD_RXINTMOD_SHIFT 0 /**< Shift value for ETH_RXINTMOD */ 1235 #define _ETH_IMOD_RXINTMOD_MASK 0xFFUL /**< Bit mask for ETH_RXINTMOD */ 1236 #define _ETH_IMOD_RXINTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IMOD */ 1237 #define ETH_IMOD_RXINTMOD_DEFAULT (_ETH_IMOD_RXINTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_IMOD */ 1238 #define _ETH_IMOD_TXINTMOD_SHIFT 16 /**< Shift value for ETH_TXINTMOD */ 1239 #define _ETH_IMOD_TXINTMOD_MASK 0xFF0000UL /**< Bit mask for ETH_TXINTMOD */ 1240 #define _ETH_IMOD_TXINTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_IMOD */ 1241 #define ETH_IMOD_TXINTMOD_DEFAULT (_ETH_IMOD_TXINTMOD_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_IMOD */ 1242 1243 /* Bit fields for ETH SYSWAKETIME */ 1244 #define _ETH_SYSWAKETIME_RESETVALUE 0x00000000UL /**< Default value for ETH_SYSWAKETIME */ 1245 #define _ETH_SYSWAKETIME_MASK 0x0000FFFFUL /**< Mask for ETH_SYSWAKETIME */ 1246 #define _ETH_SYSWAKETIME_SYSWAKETIME_SHIFT 0 /**< Shift value for ETH_SYSWAKETIME */ 1247 #define _ETH_SYSWAKETIME_SYSWAKETIME_MASK 0xFFFFUL /**< Bit mask for ETH_SYSWAKETIME */ 1248 #define _ETH_SYSWAKETIME_SYSWAKETIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SYSWAKETIME */ 1249 #define ETH_SYSWAKETIME_SYSWAKETIME_DEFAULT (_ETH_SYSWAKETIME_SYSWAKETIME_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SYSWAKETIME */ 1250 1251 /* Bit fields for ETH HASHBOTTOM */ 1252 #define _ETH_HASHBOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_HASHBOTTOM */ 1253 #define _ETH_HASHBOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_HASHBOTTOM */ 1254 #define _ETH_HASHBOTTOM_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1255 #define _ETH_HASHBOTTOM_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ 1256 #define _ETH_HASHBOTTOM_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_HASHBOTTOM */ 1257 #define ETH_HASHBOTTOM_ADDR_DEFAULT (_ETH_HASHBOTTOM_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_HASHBOTTOM */ 1258 1259 /* Bit fields for ETH HASHTOP */ 1260 #define _ETH_HASHTOP_RESETVALUE 0x00000000UL /**< Default value for ETH_HASHTOP */ 1261 #define _ETH_HASHTOP_MASK 0xFFFFFFFFUL /**< Mask for ETH_HASHTOP */ 1262 #define _ETH_HASHTOP_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1263 #define _ETH_HASHTOP_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ 1264 #define _ETH_HASHTOP_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_HASHTOP */ 1265 #define ETH_HASHTOP_ADDR_DEFAULT (_ETH_HASHTOP_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_HASHTOP */ 1266 1267 /* Bit fields for ETH SPECADDR1BOTTOM */ 1268 #define _ETH_SPECADDR1BOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR1BOTTOM */ 1269 #define _ETH_SPECADDR1BOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_SPECADDR1BOTTOM */ 1270 #define _ETH_SPECADDR1BOTTOM_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1271 #define _ETH_SPECADDR1BOTTOM_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ 1272 #define _ETH_SPECADDR1BOTTOM_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR1BOTTOM */ 1273 #define ETH_SPECADDR1BOTTOM_ADDR_DEFAULT (_ETH_SPECADDR1BOTTOM_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR1BOTTOM */ 1274 1275 /* Bit fields for ETH SPECADDR1TOP */ 1276 #define _ETH_SPECADDR1TOP_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR1TOP */ 1277 #define _ETH_SPECADDR1TOP_MASK 0x0001FFFFUL /**< Mask for ETH_SPECADDR1TOP */ 1278 #define _ETH_SPECADDR1TOP_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1279 #define _ETH_SPECADDR1TOP_ADDR_MASK 0xFFFFUL /**< Bit mask for ETH_ADDR */ 1280 #define _ETH_SPECADDR1TOP_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR1TOP */ 1281 #define ETH_SPECADDR1TOP_ADDR_DEFAULT (_ETH_SPECADDR1TOP_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR1TOP */ 1282 #define ETH_SPECADDR1TOP_FILTERTYPE (0x1UL << 16) /**< MAC SA or DA selection */ 1283 #define _ETH_SPECADDR1TOP_FILTERTYPE_SHIFT 16 /**< Shift value for ETH_FILTERTYPE */ 1284 #define _ETH_SPECADDR1TOP_FILTERTYPE_MASK 0x10000UL /**< Bit mask for ETH_FILTERTYPE */ 1285 #define _ETH_SPECADDR1TOP_FILTERTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR1TOP */ 1286 #define _ETH_SPECADDR1TOP_FILTERTYPE_DA 0x00000000UL /**< Mode DA for ETH_SPECADDR1TOP */ 1287 #define _ETH_SPECADDR1TOP_FILTERTYPE_SA 0x00000001UL /**< Mode SA for ETH_SPECADDR1TOP */ 1288 #define ETH_SPECADDR1TOP_FILTERTYPE_DEFAULT (_ETH_SPECADDR1TOP_FILTERTYPE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_SPECADDR1TOP */ 1289 #define ETH_SPECADDR1TOP_FILTERTYPE_DA (_ETH_SPECADDR1TOP_FILTERTYPE_DA << 16) /**< Shifted mode DA for ETH_SPECADDR1TOP */ 1290 #define ETH_SPECADDR1TOP_FILTERTYPE_SA (_ETH_SPECADDR1TOP_FILTERTYPE_SA << 16) /**< Shifted mode SA for ETH_SPECADDR1TOP */ 1291 1292 /* Bit fields for ETH SPECADDR2BOTTOM */ 1293 #define _ETH_SPECADDR2BOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR2BOTTOM */ 1294 #define _ETH_SPECADDR2BOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_SPECADDR2BOTTOM */ 1295 #define _ETH_SPECADDR2BOTTOM_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1296 #define _ETH_SPECADDR2BOTTOM_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ 1297 #define _ETH_SPECADDR2BOTTOM_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR2BOTTOM */ 1298 #define ETH_SPECADDR2BOTTOM_ADDR_DEFAULT (_ETH_SPECADDR2BOTTOM_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR2BOTTOM */ 1299 1300 /* Bit fields for ETH SPECADDR2TOP */ 1301 #define _ETH_SPECADDR2TOP_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR2TOP */ 1302 #define _ETH_SPECADDR2TOP_MASK 0x3F01FFFFUL /**< Mask for ETH_SPECADDR2TOP */ 1303 #define _ETH_SPECADDR2TOP_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1304 #define _ETH_SPECADDR2TOP_ADDR_MASK 0xFFFFUL /**< Bit mask for ETH_ADDR */ 1305 #define _ETH_SPECADDR2TOP_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR2TOP */ 1306 #define ETH_SPECADDR2TOP_ADDR_DEFAULT (_ETH_SPECADDR2TOP_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR2TOP */ 1307 #define ETH_SPECADDR2TOP_FILTERTYPE (0x1UL << 16) /**< MAC SA or DA selection */ 1308 #define _ETH_SPECADDR2TOP_FILTERTYPE_SHIFT 16 /**< Shift value for ETH_FILTERTYPE */ 1309 #define _ETH_SPECADDR2TOP_FILTERTYPE_MASK 0x10000UL /**< Bit mask for ETH_FILTERTYPE */ 1310 #define _ETH_SPECADDR2TOP_FILTERTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR2TOP */ 1311 #define _ETH_SPECADDR2TOP_FILTERTYPE_DA 0x00000000UL /**< Mode DA for ETH_SPECADDR2TOP */ 1312 #define _ETH_SPECADDR2TOP_FILTERTYPE_SA 0x00000001UL /**< Mode SA for ETH_SPECADDR2TOP */ 1313 #define ETH_SPECADDR2TOP_FILTERTYPE_DEFAULT (_ETH_SPECADDR2TOP_FILTERTYPE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_SPECADDR2TOP */ 1314 #define ETH_SPECADDR2TOP_FILTERTYPE_DA (_ETH_SPECADDR2TOP_FILTERTYPE_DA << 16) /**< Shifted mode DA for ETH_SPECADDR2TOP */ 1315 #define ETH_SPECADDR2TOP_FILTERTYPE_SA (_ETH_SPECADDR2TOP_FILTERTYPE_SA << 16) /**< Shifted mode SA for ETH_SPECADDR2TOP */ 1316 #define _ETH_SPECADDR2TOP_FILTERBYTEMASK_SHIFT 24 /**< Shift value for ETH_FILTERBYTEMASK */ 1317 #define _ETH_SPECADDR2TOP_FILTERBYTEMASK_MASK 0x3F000000UL /**< Bit mask for ETH_FILTERBYTEMASK */ 1318 #define _ETH_SPECADDR2TOP_FILTERBYTEMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR2TOP */ 1319 #define ETH_SPECADDR2TOP_FILTERBYTEMASK_DEFAULT (_ETH_SPECADDR2TOP_FILTERBYTEMASK_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_SPECADDR2TOP */ 1320 1321 /* Bit fields for ETH SPECADDR3BOTTOM */ 1322 #define _ETH_SPECADDR3BOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR3BOTTOM */ 1323 #define _ETH_SPECADDR3BOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_SPECADDR3BOTTOM */ 1324 #define _ETH_SPECADDR3BOTTOM_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1325 #define _ETH_SPECADDR3BOTTOM_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ 1326 #define _ETH_SPECADDR3BOTTOM_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR3BOTTOM */ 1327 #define ETH_SPECADDR3BOTTOM_ADDR_DEFAULT (_ETH_SPECADDR3BOTTOM_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR3BOTTOM */ 1328 1329 /* Bit fields for ETH SPECADDR3TOP */ 1330 #define _ETH_SPECADDR3TOP_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR3TOP */ 1331 #define _ETH_SPECADDR3TOP_MASK 0x3F01FFFFUL /**< Mask for ETH_SPECADDR3TOP */ 1332 #define _ETH_SPECADDR3TOP_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1333 #define _ETH_SPECADDR3TOP_ADDR_MASK 0xFFFFUL /**< Bit mask for ETH_ADDR */ 1334 #define _ETH_SPECADDR3TOP_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR3TOP */ 1335 #define ETH_SPECADDR3TOP_ADDR_DEFAULT (_ETH_SPECADDR3TOP_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR3TOP */ 1336 #define ETH_SPECADDR3TOP_FILTERTYPE (0x1UL << 16) /**< MAC SA or DA selection */ 1337 #define _ETH_SPECADDR3TOP_FILTERTYPE_SHIFT 16 /**< Shift value for ETH_FILTERTYPE */ 1338 #define _ETH_SPECADDR3TOP_FILTERTYPE_MASK 0x10000UL /**< Bit mask for ETH_FILTERTYPE */ 1339 #define _ETH_SPECADDR3TOP_FILTERTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR3TOP */ 1340 #define _ETH_SPECADDR3TOP_FILTERTYPE_DA 0x00000000UL /**< Mode DA for ETH_SPECADDR3TOP */ 1341 #define _ETH_SPECADDR3TOP_FILTERTYPE_SA 0x00000001UL /**< Mode SA for ETH_SPECADDR3TOP */ 1342 #define ETH_SPECADDR3TOP_FILTERTYPE_DEFAULT (_ETH_SPECADDR3TOP_FILTERTYPE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_SPECADDR3TOP */ 1343 #define ETH_SPECADDR3TOP_FILTERTYPE_DA (_ETH_SPECADDR3TOP_FILTERTYPE_DA << 16) /**< Shifted mode DA for ETH_SPECADDR3TOP */ 1344 #define ETH_SPECADDR3TOP_FILTERTYPE_SA (_ETH_SPECADDR3TOP_FILTERTYPE_SA << 16) /**< Shifted mode SA for ETH_SPECADDR3TOP */ 1345 #define _ETH_SPECADDR3TOP_FILTERBYTEMASK_SHIFT 24 /**< Shift value for ETH_FILTERBYTEMASK */ 1346 #define _ETH_SPECADDR3TOP_FILTERBYTEMASK_MASK 0x3F000000UL /**< Bit mask for ETH_FILTERBYTEMASK */ 1347 #define _ETH_SPECADDR3TOP_FILTERBYTEMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR3TOP */ 1348 #define ETH_SPECADDR3TOP_FILTERBYTEMASK_DEFAULT (_ETH_SPECADDR3TOP_FILTERBYTEMASK_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_SPECADDR3TOP */ 1349 1350 /* Bit fields for ETH SPECADDR4BOTTOM */ 1351 #define _ETH_SPECADDR4BOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR4BOTTOM */ 1352 #define _ETH_SPECADDR4BOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_SPECADDR4BOTTOM */ 1353 #define _ETH_SPECADDR4BOTTOM_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1354 #define _ETH_SPECADDR4BOTTOM_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ 1355 #define _ETH_SPECADDR4BOTTOM_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR4BOTTOM */ 1356 #define ETH_SPECADDR4BOTTOM_ADDR_DEFAULT (_ETH_SPECADDR4BOTTOM_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR4BOTTOM */ 1357 1358 /* Bit fields for ETH SPECADDR4TOP */ 1359 #define _ETH_SPECADDR4TOP_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECADDR4TOP */ 1360 #define _ETH_SPECADDR4TOP_MASK 0x3F01FFFFUL /**< Mask for ETH_SPECADDR4TOP */ 1361 #define _ETH_SPECADDR4TOP_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1362 #define _ETH_SPECADDR4TOP_ADDR_MASK 0xFFFFUL /**< Bit mask for ETH_ADDR */ 1363 #define _ETH_SPECADDR4TOP_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR4TOP */ 1364 #define ETH_SPECADDR4TOP_ADDR_DEFAULT (_ETH_SPECADDR4TOP_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECADDR4TOP */ 1365 #define ETH_SPECADDR4TOP_FILTERTYPE (0x1UL << 16) /**< MAC SA or DA selection */ 1366 #define _ETH_SPECADDR4TOP_FILTERTYPE_SHIFT 16 /**< Shift value for ETH_FILTERTYPE */ 1367 #define _ETH_SPECADDR4TOP_FILTERTYPE_MASK 0x10000UL /**< Bit mask for ETH_FILTERTYPE */ 1368 #define _ETH_SPECADDR4TOP_FILTERTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR4TOP */ 1369 #define _ETH_SPECADDR4TOP_FILTERTYPE_DA 0x00000000UL /**< Mode DA for ETH_SPECADDR4TOP */ 1370 #define _ETH_SPECADDR4TOP_FILTERTYPE_SA 0x00000001UL /**< Mode SA for ETH_SPECADDR4TOP */ 1371 #define ETH_SPECADDR4TOP_FILTERTYPE_DEFAULT (_ETH_SPECADDR4TOP_FILTERTYPE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_SPECADDR4TOP */ 1372 #define ETH_SPECADDR4TOP_FILTERTYPE_DA (_ETH_SPECADDR4TOP_FILTERTYPE_DA << 16) /**< Shifted mode DA for ETH_SPECADDR4TOP */ 1373 #define ETH_SPECADDR4TOP_FILTERTYPE_SA (_ETH_SPECADDR4TOP_FILTERTYPE_SA << 16) /**< Shifted mode SA for ETH_SPECADDR4TOP */ 1374 #define _ETH_SPECADDR4TOP_FILTERBYTEMASK_SHIFT 24 /**< Shift value for ETH_FILTERBYTEMASK */ 1375 #define _ETH_SPECADDR4TOP_FILTERBYTEMASK_MASK 0x3F000000UL /**< Bit mask for ETH_FILTERBYTEMASK */ 1376 #define _ETH_SPECADDR4TOP_FILTERBYTEMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECADDR4TOP */ 1377 #define ETH_SPECADDR4TOP_FILTERBYTEMASK_DEFAULT (_ETH_SPECADDR4TOP_FILTERBYTEMASK_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_SPECADDR4TOP */ 1378 1379 /* Bit fields for ETH SPECTYPE1 */ 1380 #define _ETH_SPECTYPE1_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECTYPE1 */ 1381 #define _ETH_SPECTYPE1_MASK 0x8000FFFFUL /**< Mask for ETH_SPECTYPE1 */ 1382 #define _ETH_SPECTYPE1_MATCH_SHIFT 0 /**< Shift value for ETH_MATCH */ 1383 #define _ETH_SPECTYPE1_MATCH_MASK 0xFFFFUL /**< Bit mask for ETH_MATCH */ 1384 #define _ETH_SPECTYPE1_MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE1 */ 1385 #define ETH_SPECTYPE1_MATCH_DEFAULT (_ETH_SPECTYPE1_MATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECTYPE1 */ 1386 #define ETH_SPECTYPE1_ENBCOPY (0x1UL << 31) /**< Enable copying of type ID match 1 matched frames. */ 1387 #define _ETH_SPECTYPE1_ENBCOPY_SHIFT 31 /**< Shift value for ETH_ENBCOPY */ 1388 #define _ETH_SPECTYPE1_ENBCOPY_MASK 0x80000000UL /**< Bit mask for ETH_ENBCOPY */ 1389 #define _ETH_SPECTYPE1_ENBCOPY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE1 */ 1390 #define ETH_SPECTYPE1_ENBCOPY_DEFAULT (_ETH_SPECTYPE1_ENBCOPY_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_SPECTYPE1 */ 1391 1392 /* Bit fields for ETH SPECTYPE2 */ 1393 #define _ETH_SPECTYPE2_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECTYPE2 */ 1394 #define _ETH_SPECTYPE2_MASK 0x8000FFFFUL /**< Mask for ETH_SPECTYPE2 */ 1395 #define _ETH_SPECTYPE2_MATCH_SHIFT 0 /**< Shift value for ETH_MATCH */ 1396 #define _ETH_SPECTYPE2_MATCH_MASK 0xFFFFUL /**< Bit mask for ETH_MATCH */ 1397 #define _ETH_SPECTYPE2_MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE2 */ 1398 #define ETH_SPECTYPE2_MATCH_DEFAULT (_ETH_SPECTYPE2_MATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECTYPE2 */ 1399 #define ETH_SPECTYPE2_ENBCOPY (0x1UL << 31) /**< Enable copying of type ID match 2 matched frames. */ 1400 #define _ETH_SPECTYPE2_ENBCOPY_SHIFT 31 /**< Shift value for ETH_ENBCOPY */ 1401 #define _ETH_SPECTYPE2_ENBCOPY_MASK 0x80000000UL /**< Bit mask for ETH_ENBCOPY */ 1402 #define _ETH_SPECTYPE2_ENBCOPY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE2 */ 1403 #define ETH_SPECTYPE2_ENBCOPY_DEFAULT (_ETH_SPECTYPE2_ENBCOPY_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_SPECTYPE2 */ 1404 1405 /* Bit fields for ETH SPECTYPE3 */ 1406 #define _ETH_SPECTYPE3_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECTYPE3 */ 1407 #define _ETH_SPECTYPE3_MASK 0x8000FFFFUL /**< Mask for ETH_SPECTYPE3 */ 1408 #define _ETH_SPECTYPE3_MATCH_SHIFT 0 /**< Shift value for ETH_MATCH */ 1409 #define _ETH_SPECTYPE3_MATCH_MASK 0xFFFFUL /**< Bit mask for ETH_MATCH */ 1410 #define _ETH_SPECTYPE3_MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE3 */ 1411 #define ETH_SPECTYPE3_MATCH_DEFAULT (_ETH_SPECTYPE3_MATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECTYPE3 */ 1412 #define ETH_SPECTYPE3_ENBCOPY (0x1UL << 31) /**< Enable copying of type ID match 3 matched frames. */ 1413 #define _ETH_SPECTYPE3_ENBCOPY_SHIFT 31 /**< Shift value for ETH_ENBCOPY */ 1414 #define _ETH_SPECTYPE3_ENBCOPY_MASK 0x80000000UL /**< Bit mask for ETH_ENBCOPY */ 1415 #define _ETH_SPECTYPE3_ENBCOPY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE3 */ 1416 #define ETH_SPECTYPE3_ENBCOPY_DEFAULT (_ETH_SPECTYPE3_ENBCOPY_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_SPECTYPE3 */ 1417 1418 /* Bit fields for ETH SPECTYPE4 */ 1419 #define _ETH_SPECTYPE4_RESETVALUE 0x00000000UL /**< Default value for ETH_SPECTYPE4 */ 1420 #define _ETH_SPECTYPE4_MASK 0x8000FFFFUL /**< Mask for ETH_SPECTYPE4 */ 1421 #define _ETH_SPECTYPE4_MATCH_SHIFT 0 /**< Shift value for ETH_MATCH */ 1422 #define _ETH_SPECTYPE4_MATCH_MASK 0xFFFFUL /**< Bit mask for ETH_MATCH */ 1423 #define _ETH_SPECTYPE4_MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE4 */ 1424 #define ETH_SPECTYPE4_MATCH_DEFAULT (_ETH_SPECTYPE4_MATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SPECTYPE4 */ 1425 #define ETH_SPECTYPE4_ENBCOPY (0x1UL << 31) /**< Enable copying of type ID match 4 matched frames. */ 1426 #define _ETH_SPECTYPE4_ENBCOPY_SHIFT 31 /**< Shift value for ETH_ENBCOPY */ 1427 #define _ETH_SPECTYPE4_ENBCOPY_MASK 0x80000000UL /**< Bit mask for ETH_ENBCOPY */ 1428 #define _ETH_SPECTYPE4_ENBCOPY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SPECTYPE4 */ 1429 #define ETH_SPECTYPE4_ENBCOPY_DEFAULT (_ETH_SPECTYPE4_ENBCOPY_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_SPECTYPE4 */ 1430 1431 /* Bit fields for ETH WOLREG */ 1432 #define _ETH_WOLREG_RESETVALUE 0x00000000UL /**< Default value for ETH_WOLREG */ 1433 #define _ETH_WOLREG_MASK 0x000FFFFFUL /**< Mask for ETH_WOLREG */ 1434 #define _ETH_WOLREG_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1435 #define _ETH_WOLREG_ADDR_MASK 0xFFFFUL /**< Bit mask for ETH_ADDR */ 1436 #define _ETH_WOLREG_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_WOLREG */ 1437 #define ETH_WOLREG_ADDR_DEFAULT (_ETH_WOLREG_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_WOLREG */ 1438 #define ETH_WOLREG_WOLMASK0 (0x1UL << 16) /**< Wake on LAN magic packet event enable */ 1439 #define _ETH_WOLREG_WOLMASK0_SHIFT 16 /**< Shift value for ETH_WOLMASK0 */ 1440 #define _ETH_WOLREG_WOLMASK0_MASK 0x10000UL /**< Bit mask for ETH_WOLMASK0 */ 1441 #define _ETH_WOLREG_WOLMASK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_WOLREG */ 1442 #define ETH_WOLREG_WOLMASK0_DEFAULT (_ETH_WOLREG_WOLMASK0_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_WOLREG */ 1443 #define ETH_WOLREG_WOLMASK1 (0x1UL << 17) /**< Wake on LAN ARP request event enable */ 1444 #define _ETH_WOLREG_WOLMASK1_SHIFT 17 /**< Shift value for ETH_WOLMASK1 */ 1445 #define _ETH_WOLREG_WOLMASK1_MASK 0x20000UL /**< Bit mask for ETH_WOLMASK1 */ 1446 #define _ETH_WOLREG_WOLMASK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_WOLREG */ 1447 #define ETH_WOLREG_WOLMASK1_DEFAULT (_ETH_WOLREG_WOLMASK1_DEFAULT << 17) /**< Shifted mode DEFAULT for ETH_WOLREG */ 1448 #define ETH_WOLREG_WOLMASK2 (0x1UL << 18) /**< Wake on LAN specific address register 1 event enable */ 1449 #define _ETH_WOLREG_WOLMASK2_SHIFT 18 /**< Shift value for ETH_WOLMASK2 */ 1450 #define _ETH_WOLREG_WOLMASK2_MASK 0x40000UL /**< Bit mask for ETH_WOLMASK2 */ 1451 #define _ETH_WOLREG_WOLMASK2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_WOLREG */ 1452 #define ETH_WOLREG_WOLMASK2_DEFAULT (_ETH_WOLREG_WOLMASK2_DEFAULT << 18) /**< Shifted mode DEFAULT for ETH_WOLREG */ 1453 #define ETH_WOLREG_WOLMASK3 (0x1UL << 19) /**< Wake on LAN multicast hash event enable */ 1454 #define _ETH_WOLREG_WOLMASK3_SHIFT 19 /**< Shift value for ETH_WOLMASK3 */ 1455 #define _ETH_WOLREG_WOLMASK3_MASK 0x80000UL /**< Bit mask for ETH_WOLMASK3 */ 1456 #define _ETH_WOLREG_WOLMASK3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_WOLREG */ 1457 #define ETH_WOLREG_WOLMASK3_DEFAULT (_ETH_WOLREG_WOLMASK3_DEFAULT << 19) /**< Shifted mode DEFAULT for ETH_WOLREG */ 1458 1459 /* Bit fields for ETH STRETCHRATIO */ 1460 #define _ETH_STRETCHRATIO_RESETVALUE 0x00000000UL /**< Default value for ETH_STRETCHRATIO */ 1461 #define _ETH_STRETCHRATIO_MASK 0x0000FFFFUL /**< Mask for ETH_STRETCHRATIO */ 1462 #define _ETH_STRETCHRATIO_IPGSTRETCH_SHIFT 0 /**< Shift value for ETH_IPGSTRETCH */ 1463 #define _ETH_STRETCHRATIO_IPGSTRETCH_MASK 0xFFFFUL /**< Bit mask for ETH_IPGSTRETCH */ 1464 #define _ETH_STRETCHRATIO_IPGSTRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_STRETCHRATIO */ 1465 #define ETH_STRETCHRATIO_IPGSTRETCH_DEFAULT (_ETH_STRETCHRATIO_IPGSTRETCH_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_STRETCHRATIO */ 1466 1467 /* Bit fields for ETH STACKEDVLAN */ 1468 #define _ETH_STACKEDVLAN_RESETVALUE 0x00000000UL /**< Default value for ETH_STACKEDVLAN */ 1469 #define _ETH_STACKEDVLAN_MASK 0x8000FFFFUL /**< Mask for ETH_STACKEDVLAN */ 1470 #define _ETH_STACKEDVLAN_MATCH_SHIFT 0 /**< Shift value for ETH_MATCH */ 1471 #define _ETH_STACKEDVLAN_MATCH_MASK 0xFFFFUL /**< Bit mask for ETH_MATCH */ 1472 #define _ETH_STACKEDVLAN_MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_STACKEDVLAN */ 1473 #define ETH_STACKEDVLAN_MATCH_DEFAULT (_ETH_STACKEDVLAN_MATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_STACKEDVLAN */ 1474 #define ETH_STACKEDVLAN_ENBPROCESSING (0x1UL << 31) /**< Enable stacked VLAN processing mode */ 1475 #define _ETH_STACKEDVLAN_ENBPROCESSING_SHIFT 31 /**< Shift value for ETH_ENBPROCESSING */ 1476 #define _ETH_STACKEDVLAN_ENBPROCESSING_MASK 0x80000000UL /**< Bit mask for ETH_ENBPROCESSING */ 1477 #define _ETH_STACKEDVLAN_ENBPROCESSING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_STACKEDVLAN */ 1478 #define ETH_STACKEDVLAN_ENBPROCESSING_DEFAULT (_ETH_STACKEDVLAN_ENBPROCESSING_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_STACKEDVLAN */ 1479 1480 /* Bit fields for ETH TXPFCPAUSE */ 1481 #define _ETH_TXPFCPAUSE_RESETVALUE 0x00000000UL /**< Default value for ETH_TXPFCPAUSE */ 1482 #define _ETH_TXPFCPAUSE_MASK 0x0000FFFFUL /**< Mask for ETH_TXPFCPAUSE */ 1483 #define _ETH_TXPFCPAUSE_VECTORENB_SHIFT 0 /**< Shift value for ETH_VECTORENB */ 1484 #define _ETH_TXPFCPAUSE_VECTORENB_MASK 0xFFUL /**< Bit mask for ETH_VECTORENB */ 1485 #define _ETH_TXPFCPAUSE_VECTORENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXPFCPAUSE */ 1486 #define ETH_TXPFCPAUSE_VECTORENB_DEFAULT (_ETH_TXPFCPAUSE_VECTORENB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXPFCPAUSE */ 1487 #define _ETH_TXPFCPAUSE_VECTOR_SHIFT 8 /**< Shift value for ETH_VECTOR */ 1488 #define _ETH_TXPFCPAUSE_VECTOR_MASK 0xFF00UL /**< Bit mask for ETH_VECTOR */ 1489 #define _ETH_TXPFCPAUSE_VECTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXPFCPAUSE */ 1490 #define ETH_TXPFCPAUSE_VECTOR_DEFAULT (_ETH_TXPFCPAUSE_VECTOR_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_TXPFCPAUSE */ 1491 1492 /* Bit fields for ETH MASKADD1BOTTOM */ 1493 #define _ETH_MASKADD1BOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_MASKADD1BOTTOM */ 1494 #define _ETH_MASKADD1BOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_MASKADD1BOTTOM */ 1495 #define _ETH_MASKADD1BOTTOM_ADDRMASK_SHIFT 0 /**< Shift value for ETH_ADDRMASK */ 1496 #define _ETH_MASKADD1BOTTOM_ADDRMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDRMASK */ 1497 #define _ETH_MASKADD1BOTTOM_ADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_MASKADD1BOTTOM */ 1498 #define ETH_MASKADD1BOTTOM_ADDRMASK_DEFAULT (_ETH_MASKADD1BOTTOM_ADDRMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_MASKADD1BOTTOM */ 1499 1500 /* Bit fields for ETH MASKADD1TOP */ 1501 #define _ETH_MASKADD1TOP_RESETVALUE 0x00000000UL /**< Default value for ETH_MASKADD1TOP */ 1502 #define _ETH_MASKADD1TOP_MASK 0x0000FFFFUL /**< Mask for ETH_MASKADD1TOP */ 1503 #define _ETH_MASKADD1TOP_ADDRMASK_SHIFT 0 /**< Shift value for ETH_ADDRMASK */ 1504 #define _ETH_MASKADD1TOP_ADDRMASK_MASK 0xFFFFUL /**< Bit mask for ETH_ADDRMASK */ 1505 #define _ETH_MASKADD1TOP_ADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_MASKADD1TOP */ 1506 #define ETH_MASKADD1TOP_ADDRMASK_DEFAULT (_ETH_MASKADD1TOP_ADDRMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_MASKADD1TOP */ 1507 1508 /* Bit fields for ETH RXPTPUNICAST */ 1509 #define _ETH_RXPTPUNICAST_RESETVALUE 0x00000000UL /**< Default value for ETH_RXPTPUNICAST */ 1510 #define _ETH_RXPTPUNICAST_MASK 0xFFFFFFFFUL /**< Mask for ETH_RXPTPUNICAST */ 1511 #define _ETH_RXPTPUNICAST_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1512 #define _ETH_RXPTPUNICAST_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ 1513 #define _ETH_RXPTPUNICAST_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXPTPUNICAST */ 1514 #define ETH_RXPTPUNICAST_ADDR_DEFAULT (_ETH_RXPTPUNICAST_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXPTPUNICAST */ 1515 1516 /* Bit fields for ETH TXPTPUNICAST */ 1517 #define _ETH_TXPTPUNICAST_RESETVALUE 0x00000000UL /**< Default value for ETH_TXPTPUNICAST */ 1518 #define _ETH_TXPTPUNICAST_MASK 0xFFFFFFFFUL /**< Mask for ETH_TXPTPUNICAST */ 1519 #define _ETH_TXPTPUNICAST_ADDR_SHIFT 0 /**< Shift value for ETH_ADDR */ 1520 #define _ETH_TXPTPUNICAST_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_ADDR */ 1521 #define _ETH_TXPTPUNICAST_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXPTPUNICAST */ 1522 #define ETH_TXPTPUNICAST_ADDR_DEFAULT (_ETH_TXPTPUNICAST_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXPTPUNICAST */ 1523 1524 /* Bit fields for ETH TSUNSECCMP */ 1525 #define _ETH_TSUNSECCMP_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUNSECCMP */ 1526 #define _ETH_TSUNSECCMP_MASK 0x003FFFFFUL /**< Mask for ETH_TSUNSECCMP */ 1527 #define _ETH_TSUNSECCMP_COMPVAL_SHIFT 0 /**< Shift value for ETH_COMPVAL */ 1528 #define _ETH_TSUNSECCMP_COMPVAL_MASK 0x3FFFFFUL /**< Bit mask for ETH_COMPVAL */ 1529 #define _ETH_TSUNSECCMP_COMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUNSECCMP */ 1530 #define ETH_TSUNSECCMP_COMPVAL_DEFAULT (_ETH_TSUNSECCMP_COMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUNSECCMP */ 1531 1532 /* Bit fields for ETH TSUSECCMP */ 1533 #define _ETH_TSUSECCMP_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUSECCMP */ 1534 #define _ETH_TSUSECCMP_MASK 0xFFFFFFFFUL /**< Mask for ETH_TSUSECCMP */ 1535 #define _ETH_TSUSECCMP_COMPVAL_SHIFT 0 /**< Shift value for ETH_COMPVAL */ 1536 #define _ETH_TSUSECCMP_COMPVAL_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COMPVAL */ 1537 #define _ETH_TSUSECCMP_COMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUSECCMP */ 1538 #define ETH_TSUSECCMP_COMPVAL_DEFAULT (_ETH_TSUSECCMP_COMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUSECCMP */ 1539 1540 /* Bit fields for ETH TSUMSBSECCMP */ 1541 #define _ETH_TSUMSBSECCMP_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUMSBSECCMP */ 1542 #define _ETH_TSUMSBSECCMP_MASK 0x0000FFFFUL /**< Mask for ETH_TSUMSBSECCMP */ 1543 #define _ETH_TSUMSBSECCMP_COMPVAL_SHIFT 0 /**< Shift value for ETH_COMPVAL */ 1544 #define _ETH_TSUMSBSECCMP_COMPVAL_MASK 0xFFFFUL /**< Bit mask for ETH_COMPVAL */ 1545 #define _ETH_TSUMSBSECCMP_COMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUMSBSECCMP */ 1546 #define ETH_TSUMSBSECCMP_COMPVAL_DEFAULT (_ETH_TSUMSBSECCMP_COMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUMSBSECCMP */ 1547 1548 /* Bit fields for ETH TSUPTPTXMSBSEC */ 1549 #define _ETH_TSUPTPTXMSBSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPTPTXMSBSEC */ 1550 #define _ETH_TSUPTPTXMSBSEC_MASK 0x0000FFFFUL /**< Mask for ETH_TSUPTPTXMSBSEC */ 1551 #define _ETH_TSUPTPTXMSBSEC_TIMERSEC_SHIFT 0 /**< Shift value for ETH_TIMERSEC */ 1552 #define _ETH_TSUPTPTXMSBSEC_TIMERSEC_MASK 0xFFFFUL /**< Bit mask for ETH_TIMERSEC */ 1553 #define _ETH_TSUPTPTXMSBSEC_TIMERSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPTPTXMSBSEC */ 1554 #define ETH_TSUPTPTXMSBSEC_TIMERSEC_DEFAULT (_ETH_TSUPTPTXMSBSEC_TIMERSEC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPTPTXMSBSEC */ 1555 1556 /* Bit fields for ETH TSUPTPRXMSBSEC */ 1557 #define _ETH_TSUPTPRXMSBSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPTPRXMSBSEC */ 1558 #define _ETH_TSUPTPRXMSBSEC_MASK 0x0000FFFFUL /**< Mask for ETH_TSUPTPRXMSBSEC */ 1559 #define _ETH_TSUPTPRXMSBSEC_TIMERSEC_SHIFT 0 /**< Shift value for ETH_TIMERSEC */ 1560 #define _ETH_TSUPTPRXMSBSEC_TIMERSEC_MASK 0xFFFFUL /**< Bit mask for ETH_TIMERSEC */ 1561 #define _ETH_TSUPTPRXMSBSEC_TIMERSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPTPRXMSBSEC */ 1562 #define ETH_TSUPTPRXMSBSEC_TIMERSEC_DEFAULT (_ETH_TSUPTPRXMSBSEC_TIMERSEC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPTPRXMSBSEC */ 1563 1564 /* Bit fields for ETH TSUPEERTXMSBSEC */ 1565 #define _ETH_TSUPEERTXMSBSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPEERTXMSBSEC */ 1566 #define _ETH_TSUPEERTXMSBSEC_MASK 0x0000FFFFUL /**< Mask for ETH_TSUPEERTXMSBSEC */ 1567 #define _ETH_TSUPEERTXMSBSEC_TIMERSEC_SHIFT 0 /**< Shift value for ETH_TIMERSEC */ 1568 #define _ETH_TSUPEERTXMSBSEC_TIMERSEC_MASK 0xFFFFUL /**< Bit mask for ETH_TIMERSEC */ 1569 #define _ETH_TSUPEERTXMSBSEC_TIMERSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPEERTXMSBSEC */ 1570 #define ETH_TSUPEERTXMSBSEC_TIMERSEC_DEFAULT (_ETH_TSUPEERTXMSBSEC_TIMERSEC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPEERTXMSBSEC */ 1571 1572 /* Bit fields for ETH TSUPEERRXMSBSEC */ 1573 #define _ETH_TSUPEERRXMSBSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPEERRXMSBSEC */ 1574 #define _ETH_TSUPEERRXMSBSEC_MASK 0x0000FFFFUL /**< Mask for ETH_TSUPEERRXMSBSEC */ 1575 #define _ETH_TSUPEERRXMSBSEC_TIMERSEC_SHIFT 0 /**< Shift value for ETH_TIMERSEC */ 1576 #define _ETH_TSUPEERRXMSBSEC_TIMERSEC_MASK 0xFFFFUL /**< Bit mask for ETH_TIMERSEC */ 1577 #define _ETH_TSUPEERRXMSBSEC_TIMERSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPEERRXMSBSEC */ 1578 #define ETH_TSUPEERRXMSBSEC_TIMERSEC_DEFAULT (_ETH_TSUPEERRXMSBSEC_TIMERSEC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPEERRXMSBSEC */ 1579 1580 /* Bit fields for ETH OCTETSTXEDBOTTOM */ 1581 #define _ETH_OCTETSTXEDBOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_OCTETSTXEDBOTTOM */ 1582 #define _ETH_OCTETSTXEDBOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_OCTETSTXEDBOTTOM */ 1583 #define _ETH_OCTETSTXEDBOTTOM_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1584 #define _ETH_OCTETSTXEDBOTTOM_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1585 #define _ETH_OCTETSTXEDBOTTOM_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_OCTETSTXEDBOTTOM */ 1586 #define ETH_OCTETSTXEDBOTTOM_COUNT_DEFAULT (_ETH_OCTETSTXEDBOTTOM_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_OCTETSTXEDBOTTOM */ 1587 1588 /* Bit fields for ETH OCTETSTXEDTOP */ 1589 #define _ETH_OCTETSTXEDTOP_RESETVALUE 0x00000000UL /**< Default value for ETH_OCTETSTXEDTOP */ 1590 #define _ETH_OCTETSTXEDTOP_MASK 0x0000FFFFUL /**< Mask for ETH_OCTETSTXEDTOP */ 1591 #define _ETH_OCTETSTXEDTOP_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1592 #define _ETH_OCTETSTXEDTOP_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ 1593 #define _ETH_OCTETSTXEDTOP_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_OCTETSTXEDTOP */ 1594 #define ETH_OCTETSTXEDTOP_COUNT_DEFAULT (_ETH_OCTETSTXEDTOP_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_OCTETSTXEDTOP */ 1595 1596 /* Bit fields for ETH FRAMESTXEDOK */ 1597 #define _ETH_FRAMESTXEDOK_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXEDOK */ 1598 #define _ETH_FRAMESTXEDOK_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXEDOK */ 1599 #define _ETH_FRAMESTXEDOK_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1600 #define _ETH_FRAMESTXEDOK_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1601 #define _ETH_FRAMESTXEDOK_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXEDOK */ 1602 #define ETH_FRAMESTXEDOK_COUNT_DEFAULT (_ETH_FRAMESTXEDOK_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXEDOK */ 1603 1604 /* Bit fields for ETH BROADCASTTXED */ 1605 #define _ETH_BROADCASTTXED_RESETVALUE 0x00000000UL /**< Default value for ETH_BROADCASTTXED */ 1606 #define _ETH_BROADCASTTXED_MASK 0xFFFFFFFFUL /**< Mask for ETH_BROADCASTTXED */ 1607 #define _ETH_BROADCASTTXED_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1608 #define _ETH_BROADCASTTXED_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1609 #define _ETH_BROADCASTTXED_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_BROADCASTTXED */ 1610 #define ETH_BROADCASTTXED_COUNT_DEFAULT (_ETH_BROADCASTTXED_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_BROADCASTTXED */ 1611 1612 /* Bit fields for ETH MULTICASTTXED */ 1613 #define _ETH_MULTICASTTXED_RESETVALUE 0x00000000UL /**< Default value for ETH_MULTICASTTXED */ 1614 #define _ETH_MULTICASTTXED_MASK 0xFFFFFFFFUL /**< Mask for ETH_MULTICASTTXED */ 1615 #define _ETH_MULTICASTTXED_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1616 #define _ETH_MULTICASTTXED_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1617 #define _ETH_MULTICASTTXED_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_MULTICASTTXED */ 1618 #define ETH_MULTICASTTXED_COUNT_DEFAULT (_ETH_MULTICASTTXED_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_MULTICASTTXED */ 1619 1620 /* Bit fields for ETH PFRAMESTXED */ 1621 #define _ETH_PFRAMESTXED_RESETVALUE 0x00000000UL /**< Default value for ETH_PFRAMESTXED */ 1622 #define _ETH_PFRAMESTXED_MASK 0x0000FFFFUL /**< Mask for ETH_PFRAMESTXED */ 1623 #define _ETH_PFRAMESTXED_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1624 #define _ETH_PFRAMESTXED_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ 1625 #define _ETH_PFRAMESTXED_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PFRAMESTXED */ 1626 #define ETH_PFRAMESTXED_COUNT_DEFAULT (_ETH_PFRAMESTXED_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_PFRAMESTXED */ 1627 1628 /* Bit fields for ETH FRAMESTXED64 */ 1629 #define _ETH_FRAMESTXED64_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED64 */ 1630 #define _ETH_FRAMESTXED64_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED64 */ 1631 #define _ETH_FRAMESTXED64_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1632 #define _ETH_FRAMESTXED64_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1633 #define _ETH_FRAMESTXED64_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED64 */ 1634 #define ETH_FRAMESTXED64_COUNT_DEFAULT (_ETH_FRAMESTXED64_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED64 */ 1635 1636 /* Bit fields for ETH FRAMESTXED65 */ 1637 #define _ETH_FRAMESTXED65_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED65 */ 1638 #define _ETH_FRAMESTXED65_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED65 */ 1639 #define _ETH_FRAMESTXED65_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1640 #define _ETH_FRAMESTXED65_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1641 #define _ETH_FRAMESTXED65_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED65 */ 1642 #define ETH_FRAMESTXED65_COUNT_DEFAULT (_ETH_FRAMESTXED65_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED65 */ 1643 1644 /* Bit fields for ETH FRAMESTXED128 */ 1645 #define _ETH_FRAMESTXED128_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED128 */ 1646 #define _ETH_FRAMESTXED128_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED128 */ 1647 #define _ETH_FRAMESTXED128_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1648 #define _ETH_FRAMESTXED128_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1649 #define _ETH_FRAMESTXED128_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED128 */ 1650 #define ETH_FRAMESTXED128_COUNT_DEFAULT (_ETH_FRAMESTXED128_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED128 */ 1651 1652 /* Bit fields for ETH FRAMESTXED256 */ 1653 #define _ETH_FRAMESTXED256_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED256 */ 1654 #define _ETH_FRAMESTXED256_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED256 */ 1655 #define _ETH_FRAMESTXED256_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1656 #define _ETH_FRAMESTXED256_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1657 #define _ETH_FRAMESTXED256_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED256 */ 1658 #define ETH_FRAMESTXED256_COUNT_DEFAULT (_ETH_FRAMESTXED256_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED256 */ 1659 1660 /* Bit fields for ETH FRAMESTXED512 */ 1661 #define _ETH_FRAMESTXED512_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED512 */ 1662 #define _ETH_FRAMESTXED512_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED512 */ 1663 #define _ETH_FRAMESTXED512_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1664 #define _ETH_FRAMESTXED512_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1665 #define _ETH_FRAMESTXED512_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED512 */ 1666 #define ETH_FRAMESTXED512_COUNT_DEFAULT (_ETH_FRAMESTXED512_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED512 */ 1667 1668 /* Bit fields for ETH FRAMESTXED1024 */ 1669 #define _ETH_FRAMESTXED1024_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED1024 */ 1670 #define _ETH_FRAMESTXED1024_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED1024 */ 1671 #define _ETH_FRAMESTXED1024_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1672 #define _ETH_FRAMESTXED1024_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1673 #define _ETH_FRAMESTXED1024_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED1024 */ 1674 #define ETH_FRAMESTXED1024_COUNT_DEFAULT (_ETH_FRAMESTXED1024_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED1024 */ 1675 1676 /* Bit fields for ETH FRAMESTXED1519 */ 1677 #define _ETH_FRAMESTXED1519_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESTXED1519 */ 1678 #define _ETH_FRAMESTXED1519_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESTXED1519 */ 1679 #define _ETH_FRAMESTXED1519_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1680 #define _ETH_FRAMESTXED1519_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1681 #define _ETH_FRAMESTXED1519_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESTXED1519 */ 1682 #define ETH_FRAMESTXED1519_COUNT_DEFAULT (_ETH_FRAMESTXED1519_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESTXED1519 */ 1683 1684 /* Bit fields for ETH TXUNDERRUNS */ 1685 #define _ETH_TXUNDERRUNS_RESETVALUE 0x00000000UL /**< Default value for ETH_TXUNDERRUNS */ 1686 #define _ETH_TXUNDERRUNS_MASK 0x000003FFUL /**< Mask for ETH_TXUNDERRUNS */ 1687 #define _ETH_TXUNDERRUNS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1688 #define _ETH_TXUNDERRUNS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ 1689 #define _ETH_TXUNDERRUNS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXUNDERRUNS */ 1690 #define ETH_TXUNDERRUNS_COUNT_DEFAULT (_ETH_TXUNDERRUNS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXUNDERRUNS */ 1691 1692 /* Bit fields for ETH SINGLECOLS */ 1693 #define _ETH_SINGLECOLS_RESETVALUE 0x00000000UL /**< Default value for ETH_SINGLECOLS */ 1694 #define _ETH_SINGLECOLS_MASK 0x0003FFFFUL /**< Mask for ETH_SINGLECOLS */ 1695 #define _ETH_SINGLECOLS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1696 #define _ETH_SINGLECOLS_COUNT_MASK 0x3FFFFUL /**< Bit mask for ETH_COUNT */ 1697 #define _ETH_SINGLECOLS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_SINGLECOLS */ 1698 #define ETH_SINGLECOLS_COUNT_DEFAULT (_ETH_SINGLECOLS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_SINGLECOLS */ 1699 1700 /* Bit fields for ETH MULTICOLS */ 1701 #define _ETH_MULTICOLS_RESETVALUE 0x00000000UL /**< Default value for ETH_MULTICOLS */ 1702 #define _ETH_MULTICOLS_MASK 0x0003FFFFUL /**< Mask for ETH_MULTICOLS */ 1703 #define _ETH_MULTICOLS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1704 #define _ETH_MULTICOLS_COUNT_MASK 0x3FFFFUL /**< Bit mask for ETH_COUNT */ 1705 #define _ETH_MULTICOLS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_MULTICOLS */ 1706 #define ETH_MULTICOLS_COUNT_DEFAULT (_ETH_MULTICOLS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_MULTICOLS */ 1707 1708 /* Bit fields for ETH EXCESSCOLS */ 1709 #define _ETH_EXCESSCOLS_RESETVALUE 0x00000000UL /**< Default value for ETH_EXCESSCOLS */ 1710 #define _ETH_EXCESSCOLS_MASK 0x000003FFUL /**< Mask for ETH_EXCESSCOLS */ 1711 #define _ETH_EXCESSCOLS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1712 #define _ETH_EXCESSCOLS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ 1713 #define _ETH_EXCESSCOLS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_EXCESSCOLS */ 1714 #define ETH_EXCESSCOLS_COUNT_DEFAULT (_ETH_EXCESSCOLS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_EXCESSCOLS */ 1715 1716 /* Bit fields for ETH LATECOLS */ 1717 #define _ETH_LATECOLS_RESETVALUE 0x00000000UL /**< Default value for ETH_LATECOLS */ 1718 #define _ETH_LATECOLS_MASK 0x000003FFUL /**< Mask for ETH_LATECOLS */ 1719 #define _ETH_LATECOLS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1720 #define _ETH_LATECOLS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ 1721 #define _ETH_LATECOLS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_LATECOLS */ 1722 #define ETH_LATECOLS_COUNT_DEFAULT (_ETH_LATECOLS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_LATECOLS */ 1723 1724 /* Bit fields for ETH DEFERREDFRAMES */ 1725 #define _ETH_DEFERREDFRAMES_RESETVALUE 0x00000000UL /**< Default value for ETH_DEFERREDFRAMES */ 1726 #define _ETH_DEFERREDFRAMES_MASK 0x0003FFFFUL /**< Mask for ETH_DEFERREDFRAMES */ 1727 #define _ETH_DEFERREDFRAMES_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1728 #define _ETH_DEFERREDFRAMES_COUNT_MASK 0x3FFFFUL /**< Bit mask for ETH_COUNT */ 1729 #define _ETH_DEFERREDFRAMES_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_DEFERREDFRAMES */ 1730 #define ETH_DEFERREDFRAMES_COUNT_DEFAULT (_ETH_DEFERREDFRAMES_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_DEFERREDFRAMES */ 1731 1732 /* Bit fields for ETH CRSERRS */ 1733 #define _ETH_CRSERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_CRSERRS */ 1734 #define _ETH_CRSERRS_MASK 0x000003FFUL /**< Mask for ETH_CRSERRS */ 1735 #define _ETH_CRSERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1736 #define _ETH_CRSERRS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ 1737 #define _ETH_CRSERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_CRSERRS */ 1738 #define ETH_CRSERRS_COUNT_DEFAULT (_ETH_CRSERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_CRSERRS */ 1739 1740 /* Bit fields for ETH OCTETSRXEDBOTTOM */ 1741 #define _ETH_OCTETSRXEDBOTTOM_RESETVALUE 0x00000000UL /**< Default value for ETH_OCTETSRXEDBOTTOM */ 1742 #define _ETH_OCTETSRXEDBOTTOM_MASK 0xFFFFFFFFUL /**< Mask for ETH_OCTETSRXEDBOTTOM */ 1743 #define _ETH_OCTETSRXEDBOTTOM_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1744 #define _ETH_OCTETSRXEDBOTTOM_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1745 #define _ETH_OCTETSRXEDBOTTOM_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_OCTETSRXEDBOTTOM */ 1746 #define ETH_OCTETSRXEDBOTTOM_COUNT_DEFAULT (_ETH_OCTETSRXEDBOTTOM_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_OCTETSRXEDBOTTOM */ 1747 1748 /* Bit fields for ETH OCTETSRXEDTOP */ 1749 #define _ETH_OCTETSRXEDTOP_RESETVALUE 0x00000000UL /**< Default value for ETH_OCTETSRXEDTOP */ 1750 #define _ETH_OCTETSRXEDTOP_MASK 0x0000FFFFUL /**< Mask for ETH_OCTETSRXEDTOP */ 1751 #define _ETH_OCTETSRXEDTOP_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1752 #define _ETH_OCTETSRXEDTOP_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ 1753 #define _ETH_OCTETSRXEDTOP_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_OCTETSRXEDTOP */ 1754 #define ETH_OCTETSRXEDTOP_COUNT_DEFAULT (_ETH_OCTETSRXEDTOP_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_OCTETSRXEDTOP */ 1755 1756 /* Bit fields for ETH FRAMESRXEDOK */ 1757 #define _ETH_FRAMESRXEDOK_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXEDOK */ 1758 #define _ETH_FRAMESRXEDOK_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXEDOK */ 1759 #define _ETH_FRAMESRXEDOK_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1760 #define _ETH_FRAMESRXEDOK_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1761 #define _ETH_FRAMESRXEDOK_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXEDOK */ 1762 #define ETH_FRAMESRXEDOK_COUNT_DEFAULT (_ETH_FRAMESRXEDOK_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXEDOK */ 1763 1764 /* Bit fields for ETH BROADCASTRXED */ 1765 #define _ETH_BROADCASTRXED_RESETVALUE 0x00000000UL /**< Default value for ETH_BROADCASTRXED */ 1766 #define _ETH_BROADCASTRXED_MASK 0xFFFFFFFFUL /**< Mask for ETH_BROADCASTRXED */ 1767 #define _ETH_BROADCASTRXED_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1768 #define _ETH_BROADCASTRXED_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1769 #define _ETH_BROADCASTRXED_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_BROADCASTRXED */ 1770 #define ETH_BROADCASTRXED_COUNT_DEFAULT (_ETH_BROADCASTRXED_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_BROADCASTRXED */ 1771 1772 /* Bit fields for ETH MULTICASTRXED */ 1773 #define _ETH_MULTICASTRXED_RESETVALUE 0x00000000UL /**< Default value for ETH_MULTICASTRXED */ 1774 #define _ETH_MULTICASTRXED_MASK 0xFFFFFFFFUL /**< Mask for ETH_MULTICASTRXED */ 1775 #define _ETH_MULTICASTRXED_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1776 #define _ETH_MULTICASTRXED_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1777 #define _ETH_MULTICASTRXED_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_MULTICASTRXED */ 1778 #define ETH_MULTICASTRXED_COUNT_DEFAULT (_ETH_MULTICASTRXED_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_MULTICASTRXED */ 1779 1780 /* Bit fields for ETH PFRAMESRXED */ 1781 #define _ETH_PFRAMESRXED_RESETVALUE 0x00000000UL /**< Default value for ETH_PFRAMESRXED */ 1782 #define _ETH_PFRAMESRXED_MASK 0x0000FFFFUL /**< Mask for ETH_PFRAMESRXED */ 1783 #define _ETH_PFRAMESRXED_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1784 #define _ETH_PFRAMESRXED_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ 1785 #define _ETH_PFRAMESRXED_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_PFRAMESRXED */ 1786 #define ETH_PFRAMESRXED_COUNT_DEFAULT (_ETH_PFRAMESRXED_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_PFRAMESRXED */ 1787 1788 /* Bit fields for ETH FRAMESRXED64 */ 1789 #define _ETH_FRAMESRXED64_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED64 */ 1790 #define _ETH_FRAMESRXED64_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED64 */ 1791 #define _ETH_FRAMESRXED64_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1792 #define _ETH_FRAMESRXED64_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1793 #define _ETH_FRAMESRXED64_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED64 */ 1794 #define ETH_FRAMESRXED64_COUNT_DEFAULT (_ETH_FRAMESRXED64_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED64 */ 1795 1796 /* Bit fields for ETH FRAMESRXED65 */ 1797 #define _ETH_FRAMESRXED65_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED65 */ 1798 #define _ETH_FRAMESRXED65_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED65 */ 1799 #define _ETH_FRAMESRXED65_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1800 #define _ETH_FRAMESRXED65_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1801 #define _ETH_FRAMESRXED65_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED65 */ 1802 #define ETH_FRAMESRXED65_COUNT_DEFAULT (_ETH_FRAMESRXED65_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED65 */ 1803 1804 /* Bit fields for ETH FRAMESRXED128 */ 1805 #define _ETH_FRAMESRXED128_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED128 */ 1806 #define _ETH_FRAMESRXED128_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED128 */ 1807 #define _ETH_FRAMESRXED128_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1808 #define _ETH_FRAMESRXED128_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1809 #define _ETH_FRAMESRXED128_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED128 */ 1810 #define ETH_FRAMESRXED128_COUNT_DEFAULT (_ETH_FRAMESRXED128_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED128 */ 1811 1812 /* Bit fields for ETH FRAMESRXED256 */ 1813 #define _ETH_FRAMESRXED256_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED256 */ 1814 #define _ETH_FRAMESRXED256_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED256 */ 1815 #define _ETH_FRAMESRXED256_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1816 #define _ETH_FRAMESRXED256_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1817 #define _ETH_FRAMESRXED256_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED256 */ 1818 #define ETH_FRAMESRXED256_COUNT_DEFAULT (_ETH_FRAMESRXED256_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED256 */ 1819 1820 /* Bit fields for ETH FRAMESRXED512 */ 1821 #define _ETH_FRAMESRXED512_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED512 */ 1822 #define _ETH_FRAMESRXED512_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED512 */ 1823 #define _ETH_FRAMESRXED512_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1824 #define _ETH_FRAMESRXED512_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1825 #define _ETH_FRAMESRXED512_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED512 */ 1826 #define ETH_FRAMESRXED512_COUNT_DEFAULT (_ETH_FRAMESRXED512_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED512 */ 1827 1828 /* Bit fields for ETH FRAMESRXED1024 */ 1829 #define _ETH_FRAMESRXED1024_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED1024 */ 1830 #define _ETH_FRAMESRXED1024_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED1024 */ 1831 #define _ETH_FRAMESRXED1024_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1832 #define _ETH_FRAMESRXED1024_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1833 #define _ETH_FRAMESRXED1024_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED1024 */ 1834 #define ETH_FRAMESRXED1024_COUNT_DEFAULT (_ETH_FRAMESRXED1024_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED1024 */ 1835 1836 /* Bit fields for ETH FRAMESRXED1519 */ 1837 #define _ETH_FRAMESRXED1519_RESETVALUE 0x00000000UL /**< Default value for ETH_FRAMESRXED1519 */ 1838 #define _ETH_FRAMESRXED1519_MASK 0xFFFFFFFFUL /**< Mask for ETH_FRAMESRXED1519 */ 1839 #define _ETH_FRAMESRXED1519_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1840 #define _ETH_FRAMESRXED1519_COUNT_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_COUNT */ 1841 #define _ETH_FRAMESRXED1519_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FRAMESRXED1519 */ 1842 #define ETH_FRAMESRXED1519_COUNT_DEFAULT (_ETH_FRAMESRXED1519_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FRAMESRXED1519 */ 1843 1844 /* Bit fields for ETH UNDERSIZEFRAMES */ 1845 #define _ETH_UNDERSIZEFRAMES_RESETVALUE 0x00000000UL /**< Default value for ETH_UNDERSIZEFRAMES */ 1846 #define _ETH_UNDERSIZEFRAMES_MASK 0x000003FFUL /**< Mask for ETH_UNDERSIZEFRAMES */ 1847 #define _ETH_UNDERSIZEFRAMES_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1848 #define _ETH_UNDERSIZEFRAMES_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ 1849 #define _ETH_UNDERSIZEFRAMES_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_UNDERSIZEFRAMES */ 1850 #define ETH_UNDERSIZEFRAMES_COUNT_DEFAULT (_ETH_UNDERSIZEFRAMES_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_UNDERSIZEFRAMES */ 1851 1852 /* Bit fields for ETH EXCESSIVERXLEN */ 1853 #define _ETH_EXCESSIVERXLEN_RESETVALUE 0x00000000UL /**< Default value for ETH_EXCESSIVERXLEN */ 1854 #define _ETH_EXCESSIVERXLEN_MASK 0x000003FFUL /**< Mask for ETH_EXCESSIVERXLEN */ 1855 #define _ETH_EXCESSIVERXLEN_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1856 #define _ETH_EXCESSIVERXLEN_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ 1857 #define _ETH_EXCESSIVERXLEN_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_EXCESSIVERXLEN */ 1858 #define ETH_EXCESSIVERXLEN_COUNT_DEFAULT (_ETH_EXCESSIVERXLEN_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_EXCESSIVERXLEN */ 1859 1860 /* Bit fields for ETH RXJABBERS */ 1861 #define _ETH_RXJABBERS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXJABBERS */ 1862 #define _ETH_RXJABBERS_MASK 0x000003FFUL /**< Mask for ETH_RXJABBERS */ 1863 #define _ETH_RXJABBERS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1864 #define _ETH_RXJABBERS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ 1865 #define _ETH_RXJABBERS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXJABBERS */ 1866 #define ETH_RXJABBERS_COUNT_DEFAULT (_ETH_RXJABBERS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXJABBERS */ 1867 1868 /* Bit fields for ETH FCSERRS */ 1869 #define _ETH_FCSERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_FCSERRS */ 1870 #define _ETH_FCSERRS_MASK 0x000003FFUL /**< Mask for ETH_FCSERRS */ 1871 #define _ETH_FCSERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1872 #define _ETH_FCSERRS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ 1873 #define _ETH_FCSERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_FCSERRS */ 1874 #define ETH_FCSERRS_COUNT_DEFAULT (_ETH_FCSERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_FCSERRS */ 1875 1876 /* Bit fields for ETH RXLENERRS */ 1877 #define _ETH_RXLENERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXLENERRS */ 1878 #define _ETH_RXLENERRS_MASK 0x000003FFUL /**< Mask for ETH_RXLENERRS */ 1879 #define _ETH_RXLENERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1880 #define _ETH_RXLENERRS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ 1881 #define _ETH_RXLENERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXLENERRS */ 1882 #define ETH_RXLENERRS_COUNT_DEFAULT (_ETH_RXLENERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXLENERRS */ 1883 1884 /* Bit fields for ETH RXSYMBOLERRS */ 1885 #define _ETH_RXSYMBOLERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXSYMBOLERRS */ 1886 #define _ETH_RXSYMBOLERRS_MASK 0x000003FFUL /**< Mask for ETH_RXSYMBOLERRS */ 1887 #define _ETH_RXSYMBOLERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1888 #define _ETH_RXSYMBOLERRS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ 1889 #define _ETH_RXSYMBOLERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXSYMBOLERRS */ 1890 #define ETH_RXSYMBOLERRS_COUNT_DEFAULT (_ETH_RXSYMBOLERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXSYMBOLERRS */ 1891 1892 /* Bit fields for ETH ALIGNERRS */ 1893 #define _ETH_ALIGNERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_ALIGNERRS */ 1894 #define _ETH_ALIGNERRS_MASK 0x000003FFUL /**< Mask for ETH_ALIGNERRS */ 1895 #define _ETH_ALIGNERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1896 #define _ETH_ALIGNERRS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ 1897 #define _ETH_ALIGNERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ALIGNERRS */ 1898 #define ETH_ALIGNERRS_COUNT_DEFAULT (_ETH_ALIGNERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_ALIGNERRS */ 1899 1900 /* Bit fields for ETH RXRESOURCEERRS */ 1901 #define _ETH_RXRESOURCEERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXRESOURCEERRS */ 1902 #define _ETH_RXRESOURCEERRS_MASK 0x0003FFFFUL /**< Mask for ETH_RXRESOURCEERRS */ 1903 #define _ETH_RXRESOURCEERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1904 #define _ETH_RXRESOURCEERRS_COUNT_MASK 0x3FFFFUL /**< Bit mask for ETH_COUNT */ 1905 #define _ETH_RXRESOURCEERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXRESOURCEERRS */ 1906 #define ETH_RXRESOURCEERRS_COUNT_DEFAULT (_ETH_RXRESOURCEERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXRESOURCEERRS */ 1907 1908 /* Bit fields for ETH RXOVERRUNS */ 1909 #define _ETH_RXOVERRUNS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXOVERRUNS */ 1910 #define _ETH_RXOVERRUNS_MASK 0x000003FFUL /**< Mask for ETH_RXOVERRUNS */ 1911 #define _ETH_RXOVERRUNS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1912 #define _ETH_RXOVERRUNS_COUNT_MASK 0x3FFUL /**< Bit mask for ETH_COUNT */ 1913 #define _ETH_RXOVERRUNS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXOVERRUNS */ 1914 #define ETH_RXOVERRUNS_COUNT_DEFAULT (_ETH_RXOVERRUNS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXOVERRUNS */ 1915 1916 /* Bit fields for ETH RXIPCKERRS */ 1917 #define _ETH_RXIPCKERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXIPCKERRS */ 1918 #define _ETH_RXIPCKERRS_MASK 0x000000FFUL /**< Mask for ETH_RXIPCKERRS */ 1919 #define _ETH_RXIPCKERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1920 #define _ETH_RXIPCKERRS_COUNT_MASK 0xFFUL /**< Bit mask for ETH_COUNT */ 1921 #define _ETH_RXIPCKERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXIPCKERRS */ 1922 #define ETH_RXIPCKERRS_COUNT_DEFAULT (_ETH_RXIPCKERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXIPCKERRS */ 1923 1924 /* Bit fields for ETH RXTCPCKERRS */ 1925 #define _ETH_RXTCPCKERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXTCPCKERRS */ 1926 #define _ETH_RXTCPCKERRS_MASK 0x000000FFUL /**< Mask for ETH_RXTCPCKERRS */ 1927 #define _ETH_RXTCPCKERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1928 #define _ETH_RXTCPCKERRS_COUNT_MASK 0xFFUL /**< Bit mask for ETH_COUNT */ 1929 #define _ETH_RXTCPCKERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXTCPCKERRS */ 1930 #define ETH_RXTCPCKERRS_COUNT_DEFAULT (_ETH_RXTCPCKERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXTCPCKERRS */ 1931 1932 /* Bit fields for ETH RXUDPCKERRS */ 1933 #define _ETH_RXUDPCKERRS_RESETVALUE 0x00000000UL /**< Default value for ETH_RXUDPCKERRS */ 1934 #define _ETH_RXUDPCKERRS_MASK 0x000000FFUL /**< Mask for ETH_RXUDPCKERRS */ 1935 #define _ETH_RXUDPCKERRS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1936 #define _ETH_RXUDPCKERRS_COUNT_MASK 0xFFUL /**< Bit mask for ETH_COUNT */ 1937 #define _ETH_RXUDPCKERRS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXUDPCKERRS */ 1938 #define ETH_RXUDPCKERRS_COUNT_DEFAULT (_ETH_RXUDPCKERRS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXUDPCKERRS */ 1939 1940 /* Bit fields for ETH AUTOFLUSHEDPKTS */ 1941 #define _ETH_AUTOFLUSHEDPKTS_RESETVALUE 0x00000000UL /**< Default value for ETH_AUTOFLUSHEDPKTS */ 1942 #define _ETH_AUTOFLUSHEDPKTS_MASK 0x0000FFFFUL /**< Mask for ETH_AUTOFLUSHEDPKTS */ 1943 #define _ETH_AUTOFLUSHEDPKTS_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 1944 #define _ETH_AUTOFLUSHEDPKTS_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ 1945 #define _ETH_AUTOFLUSHEDPKTS_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_AUTOFLUSHEDPKTS */ 1946 #define ETH_AUTOFLUSHEDPKTS_COUNT_DEFAULT (_ETH_AUTOFLUSHEDPKTS_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_AUTOFLUSHEDPKTS */ 1947 1948 /* Bit fields for ETH TSUTIMERINCRSUBNSEC */ 1949 #define _ETH_TSUTIMERINCRSUBNSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUTIMERINCRSUBNSEC */ 1950 #define _ETH_TSUTIMERINCRSUBNSEC_MASK 0xFF00FFFFUL /**< Mask for ETH_TSUTIMERINCRSUBNSEC */ 1951 #define _ETH_TSUTIMERINCRSUBNSEC_SUBNSINCR_SHIFT 0 /**< Shift value for ETH_SUBNSINCR */ 1952 #define _ETH_TSUTIMERINCRSUBNSEC_SUBNSINCR_MASK 0xFFFFUL /**< Bit mask for ETH_SUBNSINCR */ 1953 #define _ETH_TSUTIMERINCRSUBNSEC_SUBNSINCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERINCRSUBNSEC */ 1954 #define ETH_TSUTIMERINCRSUBNSEC_SUBNSINCR_DEFAULT (_ETH_TSUTIMERINCRSUBNSEC_SUBNSINCR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUTIMERINCRSUBNSEC */ 1955 #define _ETH_TSUTIMERINCRSUBNSEC_SUBNSINCRLSB_SHIFT 24 /**< Shift value for ETH_SUBNSINCRLSB */ 1956 #define _ETH_TSUTIMERINCRSUBNSEC_SUBNSINCRLSB_MASK 0xFF000000UL /**< Bit mask for ETH_SUBNSINCRLSB */ 1957 #define _ETH_TSUTIMERINCRSUBNSEC_SUBNSINCRLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERINCRSUBNSEC */ 1958 #define ETH_TSUTIMERINCRSUBNSEC_SUBNSINCRLSB_DEFAULT (_ETH_TSUTIMERINCRSUBNSEC_SUBNSINCRLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_TSUTIMERINCRSUBNSEC */ 1959 1960 /* Bit fields for ETH TSUTIMERMSBSEC */ 1961 #define _ETH_TSUTIMERMSBSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUTIMERMSBSEC */ 1962 #define _ETH_TSUTIMERMSBSEC_MASK 0x0000FFFFUL /**< Mask for ETH_TSUTIMERMSBSEC */ 1963 #define _ETH_TSUTIMERMSBSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ 1964 #define _ETH_TSUTIMERMSBSEC_TIMER_MASK 0xFFFFUL /**< Bit mask for ETH_TIMER */ 1965 #define _ETH_TSUTIMERMSBSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERMSBSEC */ 1966 #define ETH_TSUTIMERMSBSEC_TIMER_DEFAULT (_ETH_TSUTIMERMSBSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUTIMERMSBSEC */ 1967 1968 /* Bit fields for ETH TSUTIMERSEC */ 1969 #define _ETH_TSUTIMERSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUTIMERSEC */ 1970 #define _ETH_TSUTIMERSEC_MASK 0xFFFFFFFFUL /**< Mask for ETH_TSUTIMERSEC */ 1971 #define _ETH_TSUTIMERSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ 1972 #define _ETH_TSUTIMERSEC_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_TIMER */ 1973 #define _ETH_TSUTIMERSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERSEC */ 1974 #define ETH_TSUTIMERSEC_TIMER_DEFAULT (_ETH_TSUTIMERSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUTIMERSEC */ 1975 1976 /* Bit fields for ETH TSUTIMERNSEC */ 1977 #define _ETH_TSUTIMERNSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUTIMERNSEC */ 1978 #define _ETH_TSUTIMERNSEC_MASK 0x3FFFFFFFUL /**< Mask for ETH_TSUTIMERNSEC */ 1979 #define _ETH_TSUTIMERNSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ 1980 #define _ETH_TSUTIMERNSEC_TIMER_MASK 0x3FFFFFFFUL /**< Bit mask for ETH_TIMER */ 1981 #define _ETH_TSUTIMERNSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERNSEC */ 1982 #define ETH_TSUTIMERNSEC_TIMER_DEFAULT (_ETH_TSUTIMERNSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUTIMERNSEC */ 1983 1984 /* Bit fields for ETH TSUTIMERADJUST */ 1985 #define _ETH_TSUTIMERADJUST_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUTIMERADJUST */ 1986 #define _ETH_TSUTIMERADJUST_MASK 0xBFFFFFFFUL /**< Mask for ETH_TSUTIMERADJUST */ 1987 #define _ETH_TSUTIMERADJUST_INCREMENTVAL_SHIFT 0 /**< Shift value for ETH_INCREMENTVAL */ 1988 #define _ETH_TSUTIMERADJUST_INCREMENTVAL_MASK 0x3FFFFFFFUL /**< Bit mask for ETH_INCREMENTVAL */ 1989 #define _ETH_TSUTIMERADJUST_INCREMENTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERADJUST */ 1990 #define ETH_TSUTIMERADJUST_INCREMENTVAL_DEFAULT (_ETH_TSUTIMERADJUST_INCREMENTVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUTIMERADJUST */ 1991 #define ETH_TSUTIMERADJUST_ADDSUBTRACT (0x1UL << 31) /**< Write as one to subtract from the 1588 timer */ 1992 #define _ETH_TSUTIMERADJUST_ADDSUBTRACT_SHIFT 31 /**< Shift value for ETH_ADDSUBTRACT */ 1993 #define _ETH_TSUTIMERADJUST_ADDSUBTRACT_MASK 0x80000000UL /**< Bit mask for ETH_ADDSUBTRACT */ 1994 #define _ETH_TSUTIMERADJUST_ADDSUBTRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERADJUST */ 1995 #define ETH_TSUTIMERADJUST_ADDSUBTRACT_DEFAULT (_ETH_TSUTIMERADJUST_ADDSUBTRACT_DEFAULT << 31) /**< Shifted mode DEFAULT for ETH_TSUTIMERADJUST */ 1996 1997 /* Bit fields for ETH TSUTIMERINCR */ 1998 #define _ETH_TSUTIMERINCR_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUTIMERINCR */ 1999 #define _ETH_TSUTIMERINCR_MASK 0x00FFFFFFUL /**< Mask for ETH_TSUTIMERINCR */ 2000 #define _ETH_TSUTIMERINCR_NSINCREMENT_SHIFT 0 /**< Shift value for ETH_NSINCREMENT */ 2001 #define _ETH_TSUTIMERINCR_NSINCREMENT_MASK 0xFFUL /**< Bit mask for ETH_NSINCREMENT */ 2002 #define _ETH_TSUTIMERINCR_NSINCREMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERINCR */ 2003 #define ETH_TSUTIMERINCR_NSINCREMENT_DEFAULT (_ETH_TSUTIMERINCR_NSINCREMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUTIMERINCR */ 2004 #define _ETH_TSUTIMERINCR_ALTNSINCR_SHIFT 8 /**< Shift value for ETH_ALTNSINCR */ 2005 #define _ETH_TSUTIMERINCR_ALTNSINCR_MASK 0xFF00UL /**< Bit mask for ETH_ALTNSINCR */ 2006 #define _ETH_TSUTIMERINCR_ALTNSINCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERINCR */ 2007 #define ETH_TSUTIMERINCR_ALTNSINCR_DEFAULT (_ETH_TSUTIMERINCR_ALTNSINCR_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_TSUTIMERINCR */ 2008 #define _ETH_TSUTIMERINCR_NUMINCS_SHIFT 16 /**< Shift value for ETH_NUMINCS */ 2009 #define _ETH_TSUTIMERINCR_NUMINCS_MASK 0xFF0000UL /**< Bit mask for ETH_NUMINCS */ 2010 #define _ETH_TSUTIMERINCR_NUMINCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUTIMERINCR */ 2011 #define ETH_TSUTIMERINCR_NUMINCS_DEFAULT (_ETH_TSUTIMERINCR_NUMINCS_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_TSUTIMERINCR */ 2012 2013 /* Bit fields for ETH TSUPTPTXSEC */ 2014 #define _ETH_TSUPTPTXSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPTPTXSEC */ 2015 #define _ETH_TSUPTPTXSEC_MASK 0xFFFFFFFFUL /**< Mask for ETH_TSUPTPTXSEC */ 2016 #define _ETH_TSUPTPTXSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ 2017 #define _ETH_TSUPTPTXSEC_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_TIMER */ 2018 #define _ETH_TSUPTPTXSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPTPTXSEC */ 2019 #define ETH_TSUPTPTXSEC_TIMER_DEFAULT (_ETH_TSUPTPTXSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPTPTXSEC */ 2020 2021 /* Bit fields for ETH TSUPTPTXNSEC */ 2022 #define _ETH_TSUPTPTXNSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPTPTXNSEC */ 2023 #define _ETH_TSUPTPTXNSEC_MASK 0x3FFFFFFFUL /**< Mask for ETH_TSUPTPTXNSEC */ 2024 #define _ETH_TSUPTPTXNSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ 2025 #define _ETH_TSUPTPTXNSEC_TIMER_MASK 0x3FFFFFFFUL /**< Bit mask for ETH_TIMER */ 2026 #define _ETH_TSUPTPTXNSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPTPTXNSEC */ 2027 #define ETH_TSUPTPTXNSEC_TIMER_DEFAULT (_ETH_TSUPTPTXNSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPTPTXNSEC */ 2028 2029 /* Bit fields for ETH TSUPTPRXSEC */ 2030 #define _ETH_TSUPTPRXSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPTPRXSEC */ 2031 #define _ETH_TSUPTPRXSEC_MASK 0xFFFFFFFFUL /**< Mask for ETH_TSUPTPRXSEC */ 2032 #define _ETH_TSUPTPRXSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ 2033 #define _ETH_TSUPTPRXSEC_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_TIMER */ 2034 #define _ETH_TSUPTPRXSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPTPRXSEC */ 2035 #define ETH_TSUPTPRXSEC_TIMER_DEFAULT (_ETH_TSUPTPRXSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPTPRXSEC */ 2036 2037 /* Bit fields for ETH TSUPTPRXNSEC */ 2038 #define _ETH_TSUPTPRXNSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPTPRXNSEC */ 2039 #define _ETH_TSUPTPRXNSEC_MASK 0x3FFFFFFFUL /**< Mask for ETH_TSUPTPRXNSEC */ 2040 #define _ETH_TSUPTPRXNSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ 2041 #define _ETH_TSUPTPRXNSEC_TIMER_MASK 0x3FFFFFFFUL /**< Bit mask for ETH_TIMER */ 2042 #define _ETH_TSUPTPRXNSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPTPRXNSEC */ 2043 #define ETH_TSUPTPRXNSEC_TIMER_DEFAULT (_ETH_TSUPTPRXNSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPTPRXNSEC */ 2044 2045 /* Bit fields for ETH TSUPEERTXSEC */ 2046 #define _ETH_TSUPEERTXSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPEERTXSEC */ 2047 #define _ETH_TSUPEERTXSEC_MASK 0xFFFFFFFFUL /**< Mask for ETH_TSUPEERTXSEC */ 2048 #define _ETH_TSUPEERTXSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ 2049 #define _ETH_TSUPEERTXSEC_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_TIMER */ 2050 #define _ETH_TSUPEERTXSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPEERTXSEC */ 2051 #define ETH_TSUPEERTXSEC_TIMER_DEFAULT (_ETH_TSUPEERTXSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPEERTXSEC */ 2052 2053 /* Bit fields for ETH TSUPEERTXNSEC */ 2054 #define _ETH_TSUPEERTXNSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPEERTXNSEC */ 2055 #define _ETH_TSUPEERTXNSEC_MASK 0x3FFFFFFFUL /**< Mask for ETH_TSUPEERTXNSEC */ 2056 #define _ETH_TSUPEERTXNSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ 2057 #define _ETH_TSUPEERTXNSEC_TIMER_MASK 0x3FFFFFFFUL /**< Bit mask for ETH_TIMER */ 2058 #define _ETH_TSUPEERTXNSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPEERTXNSEC */ 2059 #define ETH_TSUPEERTXNSEC_TIMER_DEFAULT (_ETH_TSUPEERTXNSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPEERTXNSEC */ 2060 2061 /* Bit fields for ETH TSUPEERRXSEC */ 2062 #define _ETH_TSUPEERRXSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPEERRXSEC */ 2063 #define _ETH_TSUPEERRXSEC_MASK 0xFFFFFFFFUL /**< Mask for ETH_TSUPEERRXSEC */ 2064 #define _ETH_TSUPEERRXSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ 2065 #define _ETH_TSUPEERRXSEC_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for ETH_TIMER */ 2066 #define _ETH_TSUPEERRXSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPEERRXSEC */ 2067 #define ETH_TSUPEERRXSEC_TIMER_DEFAULT (_ETH_TSUPEERRXSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPEERRXSEC */ 2068 2069 /* Bit fields for ETH TSUPEERRXNSEC */ 2070 #define _ETH_TSUPEERRXNSEC_RESETVALUE 0x00000000UL /**< Default value for ETH_TSUPEERRXNSEC */ 2071 #define _ETH_TSUPEERRXNSEC_MASK 0x3FFFFFFFUL /**< Mask for ETH_TSUPEERRXNSEC */ 2072 #define _ETH_TSUPEERRXNSEC_TIMER_SHIFT 0 /**< Shift value for ETH_TIMER */ 2073 #define _ETH_TSUPEERRXNSEC_TIMER_MASK 0x3FFFFFFFUL /**< Bit mask for ETH_TIMER */ 2074 #define _ETH_TSUPEERRXNSEC_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TSUPEERRXNSEC */ 2075 #define ETH_TSUPEERRXNSEC_TIMER_DEFAULT (_ETH_TSUPEERRXNSEC_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TSUPEERRXNSEC */ 2076 2077 /* Bit fields for ETH TXPAUSEQUANT1 */ 2078 #define _ETH_TXPAUSEQUANT1_RESETVALUE 0xFFFFFFFFUL /**< Default value for ETH_TXPAUSEQUANT1 */ 2079 #define _ETH_TXPAUSEQUANT1_MASK 0xFFFFFFFFUL /**< Mask for ETH_TXPAUSEQUANT1 */ 2080 #define _ETH_TXPAUSEQUANT1_QUANTP2_SHIFT 0 /**< Shift value for ETH_QUANTP2 */ 2081 #define _ETH_TXPAUSEQUANT1_QUANTP2_MASK 0xFFFFUL /**< Bit mask for ETH_QUANTP2 */ 2082 #define _ETH_TXPAUSEQUANT1_QUANTP2_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT1 */ 2083 #define ETH_TXPAUSEQUANT1_QUANTP2_DEFAULT (_ETH_TXPAUSEQUANT1_QUANTP2_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT1 */ 2084 #define _ETH_TXPAUSEQUANT1_QUANTP3_SHIFT 16 /**< Shift value for ETH_QUANTP3 */ 2085 #define _ETH_TXPAUSEQUANT1_QUANTP3_MASK 0xFFFF0000UL /**< Bit mask for ETH_QUANTP3 */ 2086 #define _ETH_TXPAUSEQUANT1_QUANTP3_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT1 */ 2087 #define ETH_TXPAUSEQUANT1_QUANTP3_DEFAULT (_ETH_TXPAUSEQUANT1_QUANTP3_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT1 */ 2088 2089 /* Bit fields for ETH TXPAUSEQUANT2 */ 2090 #define _ETH_TXPAUSEQUANT2_RESETVALUE 0xFFFFFFFFUL /**< Default value for ETH_TXPAUSEQUANT2 */ 2091 #define _ETH_TXPAUSEQUANT2_MASK 0xFFFFFFFFUL /**< Mask for ETH_TXPAUSEQUANT2 */ 2092 #define _ETH_TXPAUSEQUANT2_QUANTP4_SHIFT 0 /**< Shift value for ETH_QUANTP4 */ 2093 #define _ETH_TXPAUSEQUANT2_QUANTP4_MASK 0xFFFFUL /**< Bit mask for ETH_QUANTP4 */ 2094 #define _ETH_TXPAUSEQUANT2_QUANTP4_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT2 */ 2095 #define ETH_TXPAUSEQUANT2_QUANTP4_DEFAULT (_ETH_TXPAUSEQUANT2_QUANTP4_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT2 */ 2096 #define _ETH_TXPAUSEQUANT2_QUANTP5_SHIFT 16 /**< Shift value for ETH_QUANTP5 */ 2097 #define _ETH_TXPAUSEQUANT2_QUANTP5_MASK 0xFFFF0000UL /**< Bit mask for ETH_QUANTP5 */ 2098 #define _ETH_TXPAUSEQUANT2_QUANTP5_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT2 */ 2099 #define ETH_TXPAUSEQUANT2_QUANTP5_DEFAULT (_ETH_TXPAUSEQUANT2_QUANTP5_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT2 */ 2100 2101 /* Bit fields for ETH TXPAUSEQUANT3 */ 2102 #define _ETH_TXPAUSEQUANT3_RESETVALUE 0xFFFFFFFFUL /**< Default value for ETH_TXPAUSEQUANT3 */ 2103 #define _ETH_TXPAUSEQUANT3_MASK 0xFFFFFFFFUL /**< Mask for ETH_TXPAUSEQUANT3 */ 2104 #define _ETH_TXPAUSEQUANT3_QUANTP6_SHIFT 0 /**< Shift value for ETH_QUANTP6 */ 2105 #define _ETH_TXPAUSEQUANT3_QUANTP6_MASK 0xFFFFUL /**< Bit mask for ETH_QUANTP6 */ 2106 #define _ETH_TXPAUSEQUANT3_QUANTP6_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT3 */ 2107 #define ETH_TXPAUSEQUANT3_QUANTP6_DEFAULT (_ETH_TXPAUSEQUANT3_QUANTP6_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT3 */ 2108 #define _ETH_TXPAUSEQUANT3_QUANTP7_SHIFT 16 /**< Shift value for ETH_QUANTP7 */ 2109 #define _ETH_TXPAUSEQUANT3_QUANTP7_MASK 0xFFFF0000UL /**< Bit mask for ETH_QUANTP7 */ 2110 #define _ETH_TXPAUSEQUANT3_QUANTP7_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for ETH_TXPAUSEQUANT3 */ 2111 #define ETH_TXPAUSEQUANT3_QUANTP7_DEFAULT (_ETH_TXPAUSEQUANT3_QUANTP7_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_TXPAUSEQUANT3 */ 2112 2113 /* Bit fields for ETH RXLPI */ 2114 #define _ETH_RXLPI_RESETVALUE 0x00000000UL /**< Default value for ETH_RXLPI */ 2115 #define _ETH_RXLPI_MASK 0x0000FFFFUL /**< Mask for ETH_RXLPI */ 2116 #define _ETH_RXLPI_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 2117 #define _ETH_RXLPI_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ 2118 #define _ETH_RXLPI_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXLPI */ 2119 #define ETH_RXLPI_COUNT_DEFAULT (_ETH_RXLPI_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXLPI */ 2120 2121 /* Bit fields for ETH RXLPITIME */ 2122 #define _ETH_RXLPITIME_RESETVALUE 0x00000000UL /**< Default value for ETH_RXLPITIME */ 2123 #define _ETH_RXLPITIME_MASK 0x00FFFFFFUL /**< Mask for ETH_RXLPITIME */ 2124 #define _ETH_RXLPITIME_LPITIME_SHIFT 0 /**< Shift value for ETH_LPITIME */ 2125 #define _ETH_RXLPITIME_LPITIME_MASK 0xFFFFFFUL /**< Bit mask for ETH_LPITIME */ 2126 #define _ETH_RXLPITIME_LPITIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXLPITIME */ 2127 #define ETH_RXLPITIME_LPITIME_DEFAULT (_ETH_RXLPITIME_LPITIME_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_RXLPITIME */ 2128 2129 /* Bit fields for ETH TXLPI */ 2130 #define _ETH_TXLPI_RESETVALUE 0x00000000UL /**< Default value for ETH_TXLPI */ 2131 #define _ETH_TXLPI_MASK 0x0000FFFFUL /**< Mask for ETH_TXLPI */ 2132 #define _ETH_TXLPI_COUNT_SHIFT 0 /**< Shift value for ETH_COUNT */ 2133 #define _ETH_TXLPI_COUNT_MASK 0xFFFFUL /**< Bit mask for ETH_COUNT */ 2134 #define _ETH_TXLPI_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXLPI */ 2135 #define ETH_TXLPI_COUNT_DEFAULT (_ETH_TXLPI_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXLPI */ 2136 2137 /* Bit fields for ETH TXLPITIME */ 2138 #define _ETH_TXLPITIME_RESETVALUE 0x00000000UL /**< Default value for ETH_TXLPITIME */ 2139 #define _ETH_TXLPITIME_MASK 0x00FFFFFFUL /**< Mask for ETH_TXLPITIME */ 2140 #define _ETH_TXLPITIME_LPITIME_SHIFT 0 /**< Shift value for ETH_LPITIME */ 2141 #define _ETH_TXLPITIME_LPITIME_MASK 0xFFFFFFUL /**< Bit mask for ETH_LPITIME */ 2142 #define _ETH_TXLPITIME_LPITIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXLPITIME */ 2143 #define ETH_TXLPITIME_LPITIME_DEFAULT (_ETH_TXLPITIME_LPITIME_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_TXLPITIME */ 2144 2145 /* Bit fields for ETH TXBDCTRL */ 2146 #define _ETH_TXBDCTRL_RESETVALUE 0x00000000UL /**< Default value for ETH_TXBDCTRL */ 2147 #define _ETH_TXBDCTRL_MASK 0x00000030UL /**< Mask for ETH_TXBDCTRL */ 2148 #define _ETH_TXBDCTRL_TXBDTSMODE_SHIFT 4 /**< Shift value for ETH_TXBDTSMODE */ 2149 #define _ETH_TXBDCTRL_TXBDTSMODE_MASK 0x30UL /**< Bit mask for ETH_TXBDTSMODE */ 2150 #define _ETH_TXBDCTRL_TXBDTSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_TXBDCTRL */ 2151 #define ETH_TXBDCTRL_TXBDTSMODE_DEFAULT (_ETH_TXBDCTRL_TXBDTSMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_TXBDCTRL */ 2152 2153 /* Bit fields for ETH RXBDCTRL */ 2154 #define _ETH_RXBDCTRL_RESETVALUE 0x00000000UL /**< Default value for ETH_RXBDCTRL */ 2155 #define _ETH_RXBDCTRL_MASK 0x00000030UL /**< Mask for ETH_RXBDCTRL */ 2156 #define _ETH_RXBDCTRL_RXBDTSMODE_SHIFT 4 /**< Shift value for ETH_RXBDTSMODE */ 2157 #define _ETH_RXBDCTRL_RXBDTSMODE_MASK 0x30UL /**< Bit mask for ETH_RXBDTSMODE */ 2158 #define _ETH_RXBDCTRL_RXBDTSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_RXBDCTRL */ 2159 #define ETH_RXBDCTRL_RXBDTSMODE_DEFAULT (_ETH_RXBDCTRL_RXBDTSMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_RXBDCTRL */ 2160 2161 /* Bit fields for ETH ROUTEPEN */ 2162 #define _ETH_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for ETH_ROUTEPEN */ 2163 #define _ETH_ROUTEPEN_MASK 0x0000003FUL /**< Mask for ETH_ROUTEPEN */ 2164 #define ETH_ROUTEPEN_MDIOPEN (0x1UL << 0) /**< MDIO I/O Enable */ 2165 #define _ETH_ROUTEPEN_MDIOPEN_SHIFT 0 /**< Shift value for ETH_MDIOPEN */ 2166 #define _ETH_ROUTEPEN_MDIOPEN_MASK 0x1UL /**< Bit mask for ETH_MDIOPEN */ 2167 #define _ETH_ROUTEPEN_MDIOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTEPEN */ 2168 #define _ETH_ROUTEPEN_MDIOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for ETH_ROUTEPEN */ 2169 #define _ETH_ROUTEPEN_MDIOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for ETH_ROUTEPEN */ 2170 #define ETH_ROUTEPEN_MDIOPEN_DEFAULT (_ETH_ROUTEPEN_MDIOPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_ROUTEPEN */ 2171 #define ETH_ROUTEPEN_MDIOPEN_DISABLE (_ETH_ROUTEPEN_MDIOPEN_DISABLE << 0) /**< Shifted mode DISABLE for ETH_ROUTEPEN */ 2172 #define ETH_ROUTEPEN_MDIOPEN_ENABLE (_ETH_ROUTEPEN_MDIOPEN_ENABLE << 0) /**< Shifted mode ENABLE for ETH_ROUTEPEN */ 2173 #define ETH_ROUTEPEN_MIITXERPEN (0x1UL << 1) /**< MII TX ER I/O Enable */ 2174 #define _ETH_ROUTEPEN_MIITXERPEN_SHIFT 1 /**< Shift value for ETH_MIITXERPEN */ 2175 #define _ETH_ROUTEPEN_MIITXERPEN_MASK 0x2UL /**< Bit mask for ETH_MIITXERPEN */ 2176 #define _ETH_ROUTEPEN_MIITXERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTEPEN */ 2177 #define _ETH_ROUTEPEN_MIITXERPEN_DISABLE 0x00000000UL /**< Mode DISABLE for ETH_ROUTEPEN */ 2178 #define _ETH_ROUTEPEN_MIITXERPEN_ENABLE 0x00000001UL /**< Mode ENABLE for ETH_ROUTEPEN */ 2179 #define ETH_ROUTEPEN_MIITXERPEN_DEFAULT (_ETH_ROUTEPEN_MIITXERPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for ETH_ROUTEPEN */ 2180 #define ETH_ROUTEPEN_MIITXERPEN_DISABLE (_ETH_ROUTEPEN_MIITXERPEN_DISABLE << 1) /**< Shifted mode DISABLE for ETH_ROUTEPEN */ 2181 #define ETH_ROUTEPEN_MIITXERPEN_ENABLE (_ETH_ROUTEPEN_MIITXERPEN_ENABLE << 1) /**< Shifted mode ENABLE for ETH_ROUTEPEN */ 2182 #define ETH_ROUTEPEN_MIIRXERPEN (0x1UL << 2) /**< MII TX ER I/O Enable */ 2183 #define _ETH_ROUTEPEN_MIIRXERPEN_SHIFT 2 /**< Shift value for ETH_MIIRXERPEN */ 2184 #define _ETH_ROUTEPEN_MIIRXERPEN_MASK 0x4UL /**< Bit mask for ETH_MIIRXERPEN */ 2185 #define _ETH_ROUTEPEN_MIIRXERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTEPEN */ 2186 #define _ETH_ROUTEPEN_MIIRXERPEN_DISABLE 0x00000000UL /**< Mode DISABLE for ETH_ROUTEPEN */ 2187 #define _ETH_ROUTEPEN_MIIRXERPEN_ENABLE 0x00000001UL /**< Mode ENABLE for ETH_ROUTEPEN */ 2188 #define ETH_ROUTEPEN_MIIRXERPEN_DEFAULT (_ETH_ROUTEPEN_MIIRXERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for ETH_ROUTEPEN */ 2189 #define ETH_ROUTEPEN_MIIRXERPEN_DISABLE (_ETH_ROUTEPEN_MIIRXERPEN_DISABLE << 2) /**< Shifted mode DISABLE for ETH_ROUTEPEN */ 2190 #define ETH_ROUTEPEN_MIIRXERPEN_ENABLE (_ETH_ROUTEPEN_MIIRXERPEN_ENABLE << 2) /**< Shifted mode ENABLE for ETH_ROUTEPEN */ 2191 #define ETH_ROUTEPEN_MIIPEN (0x1UL << 3) /**< MII I/O Enable */ 2192 #define _ETH_ROUTEPEN_MIIPEN_SHIFT 3 /**< Shift value for ETH_MIIPEN */ 2193 #define _ETH_ROUTEPEN_MIIPEN_MASK 0x8UL /**< Bit mask for ETH_MIIPEN */ 2194 #define _ETH_ROUTEPEN_MIIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTEPEN */ 2195 #define _ETH_ROUTEPEN_MIIPEN_DISABLE 0x00000000UL /**< Mode DISABLE for ETH_ROUTEPEN */ 2196 #define _ETH_ROUTEPEN_MIIPEN_ENABLE 0x00000001UL /**< Mode ENABLE for ETH_ROUTEPEN */ 2197 #define ETH_ROUTEPEN_MIIPEN_DEFAULT (_ETH_ROUTEPEN_MIIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for ETH_ROUTEPEN */ 2198 #define ETH_ROUTEPEN_MIIPEN_DISABLE (_ETH_ROUTEPEN_MIIPEN_DISABLE << 3) /**< Shifted mode DISABLE for ETH_ROUTEPEN */ 2199 #define ETH_ROUTEPEN_MIIPEN_ENABLE (_ETH_ROUTEPEN_MIIPEN_ENABLE << 3) /**< Shifted mode ENABLE for ETH_ROUTEPEN */ 2200 #define ETH_ROUTEPEN_RMIIPEN (0x1UL << 4) /**< RMII I/O Enable */ 2201 #define _ETH_ROUTEPEN_RMIIPEN_SHIFT 4 /**< Shift value for ETH_RMIIPEN */ 2202 #define _ETH_ROUTEPEN_RMIIPEN_MASK 0x10UL /**< Bit mask for ETH_RMIIPEN */ 2203 #define _ETH_ROUTEPEN_RMIIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTEPEN */ 2204 #define _ETH_ROUTEPEN_RMIIPEN_DISABLE 0x00000000UL /**< Mode DISABLE for ETH_ROUTEPEN */ 2205 #define _ETH_ROUTEPEN_RMIIPEN_ENABLE 0x00000001UL /**< Mode ENABLE for ETH_ROUTEPEN */ 2206 #define ETH_ROUTEPEN_RMIIPEN_DEFAULT (_ETH_ROUTEPEN_RMIIPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_ROUTEPEN */ 2207 #define ETH_ROUTEPEN_RMIIPEN_DISABLE (_ETH_ROUTEPEN_RMIIPEN_DISABLE << 4) /**< Shifted mode DISABLE for ETH_ROUTEPEN */ 2208 #define ETH_ROUTEPEN_RMIIPEN_ENABLE (_ETH_ROUTEPEN_RMIIPEN_ENABLE << 4) /**< Shifted mode ENABLE for ETH_ROUTEPEN */ 2209 #define ETH_ROUTEPEN_TSUTMRTOGPEN (0x1UL << 5) /**< TSU_TMR_CNT_SEC Output Enable */ 2210 #define _ETH_ROUTEPEN_TSUTMRTOGPEN_SHIFT 5 /**< Shift value for ETH_TSUTMRTOGPEN */ 2211 #define _ETH_ROUTEPEN_TSUTMRTOGPEN_MASK 0x20UL /**< Bit mask for ETH_TSUTMRTOGPEN */ 2212 #define _ETH_ROUTEPEN_TSUTMRTOGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTEPEN */ 2213 #define _ETH_ROUTEPEN_TSUTMRTOGPEN_DISABLE 0x00000000UL /**< Mode DISABLE for ETH_ROUTEPEN */ 2214 #define _ETH_ROUTEPEN_TSUTMRTOGPEN_ENABLE 0x00000001UL /**< Mode ENABLE for ETH_ROUTEPEN */ 2215 #define ETH_ROUTEPEN_TSUTMRTOGPEN_DEFAULT (_ETH_ROUTEPEN_TSUTMRTOGPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for ETH_ROUTEPEN */ 2216 #define ETH_ROUTEPEN_TSUTMRTOGPEN_DISABLE (_ETH_ROUTEPEN_TSUTMRTOGPEN_DISABLE << 5) /**< Shifted mode DISABLE for ETH_ROUTEPEN */ 2217 #define ETH_ROUTEPEN_TSUTMRTOGPEN_ENABLE (_ETH_ROUTEPEN_TSUTMRTOGPEN_ENABLE << 5) /**< Shifted mode ENABLE for ETH_ROUTEPEN */ 2218 2219 /* Bit fields for ETH ROUTELOC0 */ 2220 #define _ETH_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for ETH_ROUTELOC0 */ 2221 #define _ETH_ROUTELOC0_MASK 0x03030301UL /**< Mask for ETH_ROUTELOC0 */ 2222 #define _ETH_ROUTELOC0_MIITXLOC_SHIFT 0 /**< Shift value for ETH_MIITXLOC */ 2223 #define _ETH_ROUTELOC0_MIITXLOC_MASK 0x1UL /**< Bit mask for ETH_MIITXLOC */ 2224 #define _ETH_ROUTELOC0_MIITXLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC0 */ 2225 #define _ETH_ROUTELOC0_MIITXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC0 */ 2226 #define _ETH_ROUTELOC0_MIITXLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC0 */ 2227 #define ETH_ROUTELOC0_MIITXLOC_LOC0 (_ETH_ROUTELOC0_MIITXLOC_LOC0 << 0) /**< Shifted mode LOC0 for ETH_ROUTELOC0 */ 2228 #define ETH_ROUTELOC0_MIITXLOC_DEFAULT (_ETH_ROUTELOC0_MIITXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_ROUTELOC0 */ 2229 #define ETH_ROUTELOC0_MIITXLOC_LOC1 (_ETH_ROUTELOC0_MIITXLOC_LOC1 << 0) /**< Shifted mode LOC1 for ETH_ROUTELOC0 */ 2230 #define _ETH_ROUTELOC0_MIIRXLOC_SHIFT 8 /**< Shift value for ETH_MIIRXLOC */ 2231 #define _ETH_ROUTELOC0_MIIRXLOC_MASK 0x300UL /**< Bit mask for ETH_MIIRXLOC */ 2232 #define _ETH_ROUTELOC0_MIIRXLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC0 */ 2233 #define _ETH_ROUTELOC0_MIIRXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC0 */ 2234 #define _ETH_ROUTELOC0_MIIRXLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC0 */ 2235 #define _ETH_ROUTELOC0_MIIRXLOC_LOC2 0x00000002UL /**< Mode LOC2 for ETH_ROUTELOC0 */ 2236 #define ETH_ROUTELOC0_MIIRXLOC_LOC0 (_ETH_ROUTELOC0_MIIRXLOC_LOC0 << 8) /**< Shifted mode LOC0 for ETH_ROUTELOC0 */ 2237 #define ETH_ROUTELOC0_MIIRXLOC_DEFAULT (_ETH_ROUTELOC0_MIIRXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_ROUTELOC0 */ 2238 #define ETH_ROUTELOC0_MIIRXLOC_LOC1 (_ETH_ROUTELOC0_MIIRXLOC_LOC1 << 8) /**< Shifted mode LOC1 for ETH_ROUTELOC0 */ 2239 #define ETH_ROUTELOC0_MIIRXLOC_LOC2 (_ETH_ROUTELOC0_MIIRXLOC_LOC2 << 8) /**< Shifted mode LOC2 for ETH_ROUTELOC0 */ 2240 #define _ETH_ROUTELOC0_MIICRSLOC_SHIFT 16 /**< Shift value for ETH_MIICRSLOC */ 2241 #define _ETH_ROUTELOC0_MIICRSLOC_MASK 0x30000UL /**< Bit mask for ETH_MIICRSLOC */ 2242 #define _ETH_ROUTELOC0_MIICRSLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC0 */ 2243 #define _ETH_ROUTELOC0_MIICRSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC0 */ 2244 #define _ETH_ROUTELOC0_MIICRSLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC0 */ 2245 #define _ETH_ROUTELOC0_MIICRSLOC_LOC2 0x00000002UL /**< Mode LOC2 for ETH_ROUTELOC0 */ 2246 #define ETH_ROUTELOC0_MIICRSLOC_LOC0 (_ETH_ROUTELOC0_MIICRSLOC_LOC0 << 16) /**< Shifted mode LOC0 for ETH_ROUTELOC0 */ 2247 #define ETH_ROUTELOC0_MIICRSLOC_DEFAULT (_ETH_ROUTELOC0_MIICRSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_ROUTELOC0 */ 2248 #define ETH_ROUTELOC0_MIICRSLOC_LOC1 (_ETH_ROUTELOC0_MIICRSLOC_LOC1 << 16) /**< Shifted mode LOC1 for ETH_ROUTELOC0 */ 2249 #define ETH_ROUTELOC0_MIICRSLOC_LOC2 (_ETH_ROUTELOC0_MIICRSLOC_LOC2 << 16) /**< Shifted mode LOC2 for ETH_ROUTELOC0 */ 2250 #define _ETH_ROUTELOC0_MIICOLLOC_SHIFT 24 /**< Shift value for ETH_MIICOLLOC */ 2251 #define _ETH_ROUTELOC0_MIICOLLOC_MASK 0x3000000UL /**< Bit mask for ETH_MIICOLLOC */ 2252 #define _ETH_ROUTELOC0_MIICOLLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC0 */ 2253 #define _ETH_ROUTELOC0_MIICOLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC0 */ 2254 #define _ETH_ROUTELOC0_MIICOLLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC0 */ 2255 #define _ETH_ROUTELOC0_MIICOLLOC_LOC2 0x00000002UL /**< Mode LOC2 for ETH_ROUTELOC0 */ 2256 #define ETH_ROUTELOC0_MIICOLLOC_LOC0 (_ETH_ROUTELOC0_MIICOLLOC_LOC0 << 24) /**< Shifted mode LOC0 for ETH_ROUTELOC0 */ 2257 #define ETH_ROUTELOC0_MIICOLLOC_DEFAULT (_ETH_ROUTELOC0_MIICOLLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_ROUTELOC0 */ 2258 #define ETH_ROUTELOC0_MIICOLLOC_LOC1 (_ETH_ROUTELOC0_MIICOLLOC_LOC1 << 24) /**< Shifted mode LOC1 for ETH_ROUTELOC0 */ 2259 #define ETH_ROUTELOC0_MIICOLLOC_LOC2 (_ETH_ROUTELOC0_MIICOLLOC_LOC2 << 24) /**< Shifted mode LOC2 for ETH_ROUTELOC0 */ 2260 2261 /* Bit fields for ETH ROUTELOC1 */ 2262 #define _ETH_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for ETH_ROUTELOC1 */ 2263 #define _ETH_ROUTELOC1_MASK 0x01030303UL /**< Mask for ETH_ROUTELOC1 */ 2264 #define _ETH_ROUTELOC1_TSUEXTCLKLOC_SHIFT 0 /**< Shift value for ETH_TSUEXTCLKLOC */ 2265 #define _ETH_ROUTELOC1_TSUEXTCLKLOC_MASK 0x3UL /**< Bit mask for ETH_TSUEXTCLKLOC */ 2266 #define _ETH_ROUTELOC1_TSUEXTCLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC1 */ 2267 #define _ETH_ROUTELOC1_TSUEXTCLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC1 */ 2268 #define _ETH_ROUTELOC1_TSUEXTCLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC1 */ 2269 #define _ETH_ROUTELOC1_TSUEXTCLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for ETH_ROUTELOC1 */ 2270 #define _ETH_ROUTELOC1_TSUEXTCLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for ETH_ROUTELOC1 */ 2271 #define ETH_ROUTELOC1_TSUEXTCLKLOC_LOC0 (_ETH_ROUTELOC1_TSUEXTCLKLOC_LOC0 << 0) /**< Shifted mode LOC0 for ETH_ROUTELOC1 */ 2272 #define ETH_ROUTELOC1_TSUEXTCLKLOC_DEFAULT (_ETH_ROUTELOC1_TSUEXTCLKLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_ROUTELOC1 */ 2273 #define ETH_ROUTELOC1_TSUEXTCLKLOC_LOC1 (_ETH_ROUTELOC1_TSUEXTCLKLOC_LOC1 << 0) /**< Shifted mode LOC1 for ETH_ROUTELOC1 */ 2274 #define ETH_ROUTELOC1_TSUEXTCLKLOC_LOC2 (_ETH_ROUTELOC1_TSUEXTCLKLOC_LOC2 << 0) /**< Shifted mode LOC2 for ETH_ROUTELOC1 */ 2275 #define ETH_ROUTELOC1_TSUEXTCLKLOC_LOC3 (_ETH_ROUTELOC1_TSUEXTCLKLOC_LOC3 << 0) /**< Shifted mode LOC3 for ETH_ROUTELOC1 */ 2276 #define _ETH_ROUTELOC1_TSUTMRTOGLOC_SHIFT 8 /**< Shift value for ETH_TSUTMRTOGLOC */ 2277 #define _ETH_ROUTELOC1_TSUTMRTOGLOC_MASK 0x300UL /**< Bit mask for ETH_TSUTMRTOGLOC */ 2278 #define _ETH_ROUTELOC1_TSUTMRTOGLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC1 */ 2279 #define _ETH_ROUTELOC1_TSUTMRTOGLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC1 */ 2280 #define _ETH_ROUTELOC1_TSUTMRTOGLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC1 */ 2281 #define _ETH_ROUTELOC1_TSUTMRTOGLOC_LOC2 0x00000002UL /**< Mode LOC2 for ETH_ROUTELOC1 */ 2282 #define _ETH_ROUTELOC1_TSUTMRTOGLOC_LOC3 0x00000003UL /**< Mode LOC3 for ETH_ROUTELOC1 */ 2283 #define ETH_ROUTELOC1_TSUTMRTOGLOC_LOC0 (_ETH_ROUTELOC1_TSUTMRTOGLOC_LOC0 << 8) /**< Shifted mode LOC0 for ETH_ROUTELOC1 */ 2284 #define ETH_ROUTELOC1_TSUTMRTOGLOC_DEFAULT (_ETH_ROUTELOC1_TSUTMRTOGLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_ROUTELOC1 */ 2285 #define ETH_ROUTELOC1_TSUTMRTOGLOC_LOC1 (_ETH_ROUTELOC1_TSUTMRTOGLOC_LOC1 << 8) /**< Shifted mode LOC1 for ETH_ROUTELOC1 */ 2286 #define ETH_ROUTELOC1_TSUTMRTOGLOC_LOC2 (_ETH_ROUTELOC1_TSUTMRTOGLOC_LOC2 << 8) /**< Shifted mode LOC2 for ETH_ROUTELOC1 */ 2287 #define ETH_ROUTELOC1_TSUTMRTOGLOC_LOC3 (_ETH_ROUTELOC1_TSUTMRTOGLOC_LOC3 << 8) /**< Shifted mode LOC3 for ETH_ROUTELOC1 */ 2288 #define _ETH_ROUTELOC1_MDIOLOC_SHIFT 16 /**< Shift value for ETH_MDIOLOC */ 2289 #define _ETH_ROUTELOC1_MDIOLOC_MASK 0x30000UL /**< Bit mask for ETH_MDIOLOC */ 2290 #define _ETH_ROUTELOC1_MDIOLOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC1 */ 2291 #define _ETH_ROUTELOC1_MDIOLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC1 */ 2292 #define _ETH_ROUTELOC1_MDIOLOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC1 */ 2293 #define _ETH_ROUTELOC1_MDIOLOC_LOC2 0x00000002UL /**< Mode LOC2 for ETH_ROUTELOC1 */ 2294 #define _ETH_ROUTELOC1_MDIOLOC_LOC3 0x00000003UL /**< Mode LOC3 for ETH_ROUTELOC1 */ 2295 #define ETH_ROUTELOC1_MDIOLOC_LOC0 (_ETH_ROUTELOC1_MDIOLOC_LOC0 << 16) /**< Shifted mode LOC0 for ETH_ROUTELOC1 */ 2296 #define ETH_ROUTELOC1_MDIOLOC_DEFAULT (_ETH_ROUTELOC1_MDIOLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for ETH_ROUTELOC1 */ 2297 #define ETH_ROUTELOC1_MDIOLOC_LOC1 (_ETH_ROUTELOC1_MDIOLOC_LOC1 << 16) /**< Shifted mode LOC1 for ETH_ROUTELOC1 */ 2298 #define ETH_ROUTELOC1_MDIOLOC_LOC2 (_ETH_ROUTELOC1_MDIOLOC_LOC2 << 16) /**< Shifted mode LOC2 for ETH_ROUTELOC1 */ 2299 #define ETH_ROUTELOC1_MDIOLOC_LOC3 (_ETH_ROUTELOC1_MDIOLOC_LOC3 << 16) /**< Shifted mode LOC3 for ETH_ROUTELOC1 */ 2300 #define _ETH_ROUTELOC1_RMIILOC_SHIFT 24 /**< Shift value for ETH_RMIILOC */ 2301 #define _ETH_ROUTELOC1_RMIILOC_MASK 0x1000000UL /**< Bit mask for ETH_RMIILOC */ 2302 #define _ETH_ROUTELOC1_RMIILOC_LOC0 0x00000000UL /**< Mode LOC0 for ETH_ROUTELOC1 */ 2303 #define _ETH_ROUTELOC1_RMIILOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_ROUTELOC1 */ 2304 #define _ETH_ROUTELOC1_RMIILOC_LOC1 0x00000001UL /**< Mode LOC1 for ETH_ROUTELOC1 */ 2305 #define ETH_ROUTELOC1_RMIILOC_LOC0 (_ETH_ROUTELOC1_RMIILOC_LOC0 << 24) /**< Shifted mode LOC0 for ETH_ROUTELOC1 */ 2306 #define ETH_ROUTELOC1_RMIILOC_DEFAULT (_ETH_ROUTELOC1_RMIILOC_DEFAULT << 24) /**< Shifted mode DEFAULT for ETH_ROUTELOC1 */ 2307 #define ETH_ROUTELOC1_RMIILOC_LOC1 (_ETH_ROUTELOC1_RMIILOC_LOC1 << 24) /**< Shifted mode LOC1 for ETH_ROUTELOC1 */ 2308 2309 /* Bit fields for ETH CTRL */ 2310 #define _ETH_CTRL_RESETVALUE 0x00000000UL /**< Default value for ETH_CTRL */ 2311 #define _ETH_CTRL_MASK 0x000007F7UL /**< Mask for ETH_CTRL */ 2312 #define _ETH_CTRL_TSUCLKSEL_SHIFT 0 /**< Shift value for ETH_TSUCLKSEL */ 2313 #define _ETH_CTRL_TSUCLKSEL_MASK 0x7UL /**< Bit mask for ETH_TSUCLKSEL */ 2314 #define _ETH_CTRL_TSUCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_CTRL */ 2315 #define _ETH_CTRL_TSUCLKSEL_NOCLOCK 0x00000000UL /**< Mode NOCLOCK for ETH_CTRL */ 2316 #define _ETH_CTRL_TSUCLKSEL_PLL 0x00000001UL /**< Mode PLL for ETH_CTRL */ 2317 #define _ETH_CTRL_TSUCLKSEL_RXCLK 0x00000002UL /**< Mode RXCLK for ETH_CTRL */ 2318 #define _ETH_CTRL_TSUCLKSEL_REFCLK 0x00000003UL /**< Mode REFCLK for ETH_CTRL */ 2319 #define _ETH_CTRL_TSUCLKSEL_TSUEXTCLK 0x00000004UL /**< Mode TSUEXTCLK for ETH_CTRL */ 2320 #define ETH_CTRL_TSUCLKSEL_DEFAULT (_ETH_CTRL_TSUCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETH_CTRL */ 2321 #define ETH_CTRL_TSUCLKSEL_NOCLOCK (_ETH_CTRL_TSUCLKSEL_NOCLOCK << 0) /**< Shifted mode NOCLOCK for ETH_CTRL */ 2322 #define ETH_CTRL_TSUCLKSEL_PLL (_ETH_CTRL_TSUCLKSEL_PLL << 0) /**< Shifted mode PLL for ETH_CTRL */ 2323 #define ETH_CTRL_TSUCLKSEL_RXCLK (_ETH_CTRL_TSUCLKSEL_RXCLK << 0) /**< Shifted mode RXCLK for ETH_CTRL */ 2324 #define ETH_CTRL_TSUCLKSEL_REFCLK (_ETH_CTRL_TSUCLKSEL_REFCLK << 0) /**< Shifted mode REFCLK for ETH_CTRL */ 2325 #define ETH_CTRL_TSUCLKSEL_TSUEXTCLK (_ETH_CTRL_TSUCLKSEL_TSUEXTCLK << 0) /**< Shifted mode TSUEXTCLK for ETH_CTRL */ 2326 #define _ETH_CTRL_TSUPRESC_SHIFT 4 /**< Shift value for ETH_TSUPRESC */ 2327 #define _ETH_CTRL_TSUPRESC_MASK 0xF0UL /**< Bit mask for ETH_TSUPRESC */ 2328 #define _ETH_CTRL_TSUPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_CTRL */ 2329 #define ETH_CTRL_TSUPRESC_DEFAULT (_ETH_CTRL_TSUPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for ETH_CTRL */ 2330 #define ETH_CTRL_MIISEL (0x1UL << 8) /**< MII select signal */ 2331 #define _ETH_CTRL_MIISEL_SHIFT 8 /**< Shift value for ETH_MIISEL */ 2332 #define _ETH_CTRL_MIISEL_MASK 0x100UL /**< Bit mask for ETH_MIISEL */ 2333 #define _ETH_CTRL_MIISEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_CTRL */ 2334 #define _ETH_CTRL_MIISEL_RMII 0x00000000UL /**< Mode RMII for ETH_CTRL */ 2335 #define _ETH_CTRL_MIISEL_MII 0x00000001UL /**< Mode MII for ETH_CTRL */ 2336 #define ETH_CTRL_MIISEL_DEFAULT (_ETH_CTRL_MIISEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETH_CTRL */ 2337 #define ETH_CTRL_MIISEL_RMII (_ETH_CTRL_MIISEL_RMII << 8) /**< Shifted mode RMII for ETH_CTRL */ 2338 #define ETH_CTRL_MIISEL_MII (_ETH_CTRL_MIISEL_MII << 8) /**< Shifted mode MII for ETH_CTRL */ 2339 #define ETH_CTRL_GBLCLKEN (0x1UL << 9) /**< Global Clock Enable signal for Ethernet clocks tsu_clk, tx_clk, rx_clk and ref_clk */ 2340 #define _ETH_CTRL_GBLCLKEN_SHIFT 9 /**< Shift value for ETH_GBLCLKEN */ 2341 #define _ETH_CTRL_GBLCLKEN_MASK 0x200UL /**< Bit mask for ETH_GBLCLKEN */ 2342 #define _ETH_CTRL_GBLCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_CTRL */ 2343 #define ETH_CTRL_GBLCLKEN_DEFAULT (_ETH_CTRL_GBLCLKEN_DEFAULT << 9) /**< Shifted mode DEFAULT for ETH_CTRL */ 2344 #define ETH_CTRL_TXREFCLKSEL (0x1UL << 10) /**< REFCLK source select for RMII_TXD and RMII_TX_EN */ 2345 #define _ETH_CTRL_TXREFCLKSEL_SHIFT 10 /**< Shift value for ETH_TXREFCLKSEL */ 2346 #define _ETH_CTRL_TXREFCLKSEL_MASK 0x400UL /**< Bit mask for ETH_TXREFCLKSEL */ 2347 #define _ETH_CTRL_TXREFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETH_CTRL */ 2348 #define _ETH_CTRL_TXREFCLKSEL_REFCLKINT 0x00000000UL /**< Mode REFCLKINT for ETH_CTRL */ 2349 #define _ETH_CTRL_TXREFCLKSEL_REFCLKPIN 0x00000001UL /**< Mode REFCLKPIN for ETH_CTRL */ 2350 #define ETH_CTRL_TXREFCLKSEL_DEFAULT (_ETH_CTRL_TXREFCLKSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ETH_CTRL */ 2351 #define ETH_CTRL_TXREFCLKSEL_REFCLKINT (_ETH_CTRL_TXREFCLKSEL_REFCLKINT << 10) /**< Shifted mode REFCLKINT for ETH_CTRL */ 2352 #define ETH_CTRL_TXREFCLKSEL_REFCLKPIN (_ETH_CTRL_TXREFCLKSEL_REFCLKPIN << 10) /**< Shifted mode REFCLKPIN for ETH_CTRL */ 2353 2354 /** @} */ 2355 /** @} End of group EFM32GG11B_ETH */ 2356 /** @} End of group Parts */ 2357
